UNIT - 5 THE INPUT-OUTPUT ORGANIZATION STRUCTURE

5.0 5.1 5.2 5.3 Introduction Objectives Addressing of I/O devices Data transfer mode 5.3.1 Programmed I/O 5.3.2 Interrupt I/O 5.3.3 Direct 5." 5.5 5.& 5.' I/O c#anne$s %tandard I/O interfaces %ummar! (uestions emor! Access

5.0 INTRODUCTION
)#is unit discusses t#e various *a!s in *#ic# input/output devices. *#ic# operates at e$ectro/mec#anica$ can ta+e p$ace bet*een t#e ,P-. *#ic# operates at t#e e$ectronic speed and t#e perip#era$ speeds. )#e ver! nature of emor! Access. speed difference bet*een t#e ,P- and I/O devices $ead to a rea$ bott$enec+ in performance. )#e I/O met#ods $i+e Programmed I/O . Direct Interrupt I/O . I/O c#anne$s and I/O processors are used to so$ve t#is prob$em. %o. in order to ma+e a computer *or+ efficient$!. *e need to +no* about t#e I/O organi0ation. )#e I/O organi0ation inc$udes various t!pes of input/output devices. device contro$$ers and different I/O modes.

5.1 OBJECTIVES
A t t#e end of t#is session !ou s#ou$d be ab$e to -nderstand t#e ro$e of ,P- in contro$$ing t#e perip#era$ devices -nderstand t#e *a! t#e I/O devices are addressed -nderstand t#e Programmed I/O mode Appreciate t#e *a! of #and$ing interrupts -nderstand t#e importance of Direct emor! Access mode of data transfer

-nderstand t#e concepts of I/O c#anne$s and its usage 1ive some e2amp$es of standard I/O interfaces

5.2

ADDRESSING OF I/O DEVICES

Addressing or se$ection of individua$ I/O devices for a given data transfer operation. is an important function t#at need to be performed b! a computer to #and$e I/O operation. If severa$ devices are connected to t#e computer and if it is necessar! to se$ect an! one of t#em to participate in t#e I/O operation. t#en t#is is done b! addressing t#e I/O devices using an I/O Bus arran !"!n# in case of t*o/bus mac#ines and using $!"%r&-"a''!( I/O or I/O-"a''!( I/O in case of sing$e/bus mac#ines.

I/O BUS ARRANGE$ENT

Memory
Memory bus

I/O bus

CPU Device 1 3igure 5.1 Device 2 Device N

,onsider an I/O bus arrangement . as s#o*n in figure 5.1. *#ere more t#an one device is connected to t#e computer. )#e I/O 4us is used for communication bet*een t#e I/O devices and t#e ,P-. It consists of t#ree sets of *ires for transmission of address. data and contro$ signa$s. 5ere. eac# device is given an address or identification code. )#e ,Pse$ects an I/O device b! p$acing t#e address on t#e address $ines. t#e corresponding I/O device recogni0es its address and responds to t#e ,P-6s command. 7it# t#is arrangement. *#ere memor! bus is different from I/O bus. specia$ instructions are re8uired to perform I/O transfers. %uc# as OUT (a#a) (!*+,! IN (a#a) (!*+,!

$E$OR-- $APPED I/O

In case of sing$e/bus mac#ines. t#e same bus serves as bot# t#e memor! and I/O bus. 5ence. t#e address of I/O devices are not distinguis#ed from t#e address of t#e memor! $ocation. )#erefore. to se$ect I/O devices. a portion of memor! address space is used and in t#em uni8ue address codes are p$aced. In t#is *a!. it is possib$e to access an! I/O device just $i+e t#at of an! memor! $ocation. )#is is +no*n as memor!/mapped I/O and is s#o*n in figure 5.2

Data Address Read Read Write

Main memory

CPU

I/O device 1

I/O device 2

....

3igure 5.2

I/O- $APPED I/O

5ere. t#e memor! and I/O address space are +ept separate b! 9ead/7rite contro$ $ines as s#o*n in figure 5.3 3igure 5.3 data address
Read M
Write M Read I/O Write I/O

Main memory

CPU

I/O device 1

I/O device 2 or 7rite

....
$ine and does

A memor! reference instruction activates t#e 9ead

not affect t#e I/O devices. )#e I/O instruction suc# as for e2amp$e I: or O-) activates t#e 9ead I/O and *rite I/O $ine and causes a *ord to be transferred bet*een t#e addressed I/O and t#e ,P-. )#erefore. t#e memor! $ocation and t#e I/O device ma! #ave t#e same address. )#is is +no*n as I/O mapped I/O.

5..

DATA TRANSFER $ODE

In t!pica$ computer. data transfer ta+es p$ace bet*een t#e main memor! and t#e ,P- or t#e main memor! and I/O devices or t#e ,P- and t#e I/O devices. )#e data transfer bet*een t#e ,P- and t#e I/O devices can be of t*o t!pes; 1. Programmed I/O 2. Direct emor! Access < D A =

5...1

PROGRA$$ED I/O

It is a mode of data transfer bet*een t#e ,P- and t#e $ogic *it#in t#e perip#era$s. )#e transfer is initiated using an I/O transfer instruction < IO) = and contro$$ed entire$! b! t#e ,P-. During transfers. t#e s!stem a$*a!s fo$$o* a pre/ estab$is#ed se8uence of events ca$$ed Pr%#%,%/.

)#is t!pe of transfer is used *#en sma$$ amounts of data are to be transferred. Programmed I/O can be; %!nc#ronous < Or -nconditiona$ = transfer As!nc#ronous < Or ,onditiona$ = transfer

S-NCHRONOUS TRANSFER
It is simp$est and straig#t for*ard transfer initiated b! an IO) instruction. 5ere no c#ec+ is made b! t#e ,P- to determine t#e state of t#e perip#era$s $i+e 9ead! or 4us!. )#e transfer ta+es p$ace *#en ever t#e ,P- directs it i.e. t#e I/O device must be read! to receive t#e output data from t#e ,P- or to input data into t#e ,P- *#en ever ,P- initiates suc# a transfer. 5ence t#e transfer is -nconditiona$. 7#! is it s!nc#ronous> )#e data transfers are contro$$ed b! a c$oc+ of fi2ed fre8uenc!. independent of t#e ,P-.

AS-NCHRONOUS TRANSFER
It is a$so +no*n as 5and/s#a+ing I/O. 5ere. t#e perip#era$ is 8ueried about its status to see if it is read! to perform t#e transfer. )#e actua$ transfer ta+es p$ace on$! *#en t#e perip#era$ s#o*s 9ead! state. be fi2ed. )#is met#od accomp$is#es s!nc#roni0ation bet*een t#e ,P- and s$o*er perip#era$s *#ose timing ma! not

ADVANTAGES AND DISADVANTAGES

)#e programmed I/O mode is ver! $o* cost interface and can meet speeds of most of t#e perip#era$s. )#is is t#e main advantage. )#e main disadvantage is t#at during t#e I/O operation. t#e ,P- spends most of its time *aiting for t#e device to become read! and #ence performs no productive *or+. In ot#er *ords.

t#e ,P- speed is broug#t do*n to t#at of t#e s$o* perip#era$ device. )#is disadvantage #as given raise to anot#er I/O mode +no*n as Interrupt /I/O mode.

5...0

INTERRUPT I/O

An interrupt is a signa$ t#at refers to t#e transfer of program contro$ from a current$! running program to anot#er service program as a resu$t of an e2terna$ or interna$ generated re8uest. )#e contro$ returns to t#e origina$ program after t#e service program is e2ecuted. Interrupts are used to coordinate s$o* e2terna$ devices *it# fast computer. 5ere. t#e ,P- does not *ait for t#e perip#era$ device to become read! for t#e data transfer instead. It initiates t#e device and t#en goes a*a! to #and$e ot#er tas+s.. )#e perip#era$ sends t#e 9ead! signa$ to t#e ,P- *#en ever it is read!.

T1! !n!ra/ s!2u!n,! %3 !*!n#s +n +n#!rru'# I/O4

1. Interrupt re8uest / )#e I/O re8uesting perip#era$ sends an interrupt re8uest signa$ < I:) 9?(= to t#e ,P- to indicate t#at it is read! for an I/O operation 2. Interrupt ac+no*$edge / On receiving t#e interrupt re8uest signa$. t#e ,Pcomp$etes t#e e2ecution of t#e current instruction and sends an Interrupt ac+no*$edgement signa$ <I:) A,@= to t#e interrupt re8uesting perip#era$

3. %tatus saving / 4efore servicing t#e interrupt re8uest. t#e return address of t#e main program is stored in some pre/assigned memor! $ocations. so t#at t#e ,P- can resume its norma$ operation on comp$etion of t#e subroutine. ". Device identification / )#e interrupt re8uest to t#e ,P- is on$! t#roug# a sing$e $ine but. if t#e s!stem #as more t#an one device connected to it. t#e ,P- must identif! t#e interrupting perip#era$. so t#at it can ca$$ t#e appropriate interrupt service routine <I%9= from t#e memor!.

5. Perip#era$ service A #aving identified t#e perip#era$ *#ic# re8uested for t#e service. t#e program branc#es to t#e starting address of t#e specific subroutine in t#e memor! and it services t#e perip#era$. &. 9estore ,P- status A after comp$etion of t#e service subroutine. t#e data from t#e ,P- registers t#at *ere #e$d temporari$! in memor! are re$oaded bac+ to t#eir respective $ocations and t#e ,P- can ta+e up its norma$ tas+ '. 9esume main tas+ A *#en a$$ registers. program counter are restored *it# t#eir origina$ contents. t#e main program operation is resumed.

Program 1 <main = 1 2
Interrupt

Program 2 <I%9=

i iB1

. . . .

n 3igure 5." )ransfer of contro$ t#roug# t#e use of interrupts

Han(/+n $u/#+'/! D!*+,!s

7#en severa$ devices are connected to t#e ,P-. eac# capab$e of initiating interrupts t#en device identification is essentia$ for t#e ,P- to #and$e it. 4asica$$! t#ere are t*o basic *a!s of identif!ing t#e interrupting device; 1. Po$$ing 2. Cectoring

PO55ING
In t#is met#od. t#e interrupt signa$s I:) 9?( from a$$ t#e devices are DO96ed. )#e processor c#ec+s for t#e interrupting device one b! one < POEE%= and t#e device *#ic# ans*ers first is serviced first and t#e order of 8uestioning decides t#e priorit! of service in case of mu$tip$e interrupts. 3igure 5.5 Po$$ing

CPU Interrupt

Data bus

Input port

IN 1 IN 2 IN ! Addressab$e %$ip &$ops

OR IN R"#

?ac# interrupt $ine #as an addressab$e f$ip f$op. a 1/bit storage device *#ic# #o$ds t#e status of t#e interrupting device. )#e Interrupt %ervice 9outine <I%9=

interrogates t#e input port b! po$$ing t#e read! bit of eac# device to estab$is# t#e identit! of t#e interrupting device. A(*an#a ! ; it re8uires $ess amount of #ard*are <f$ip f$ops= D+sa(*an#a !s ; not a ver! good met#od *#en more number of devices are connected to t#e processor. and ,P- po$$s eac# device for interrupt c#ec+s. And interrupts are processed on first come first served basis. )o over come t#is a Dias! ,#ain arrangement is used.

DAIS- CHAIN 6s+n /! /!*!/ "u/#+'/! 'r+%r+#& +n#!rru'# s#ru,#ur!7

5ere. t#e device interfaces are connected seria$$! to t#e ,P-. t#e #ig# priorit! devices being nearest t#e ,P-. %uc# an arrangement is ca$$ed a Dais! ,#ain and is s#o*n in figure 5.&

IN R

CPU
DI 1 DI 2

Daisy C'ain

Device identi&ication bus Device identi&ication code

3igure 5.& Dais! c#ain arrangement 7#en I:) re8uest signa$ is sent to t#e ,P- t#roug# t#e I:)9 $ine b! t#e

re8uesting device. t#e s*itc# to t#e rig#t of t#e interrupting device is set open so t#at t#e $o*er priorit! devices cannot interrupt t#e ,P- *#en it is bus!. 5ere. po$$ing is done b! soft*are. )#e code of t#e interrupting device is sent t#roug# t#e device identification bus. )#e ,P- recogni0es it and services t#at particu$ar device. If an! of t#e #ig#er priorit! device interrupts in bet*een. t#e ,P- *i$$ suspend t#e service to t#e $o*er priorit! interrupt and services it and t#en resumes its ot#er operations. A(*an#a !s ; possibi$it! of attending to #ig#er priorit! devices *#i$e servicing $o*er priorit! devices. D+sa(*an#a !s ; :eed to po$$ t#e device and fair$! comp$icated interrupt #and$ing soft*are. )o overcome t#is prob$em. vectoring is used.

VECTORED INTERRUPTS OR VECTORING

5ere. mu$tip$e priorit! structure is used. It is a #ard*are priorit! interrupt. )#e device identification is t#roug# t#e device address and priorities t#roug# dais! c#ain arrangement. ?ac# interrupting device provides a code +no*n as Cector. it is used b! t#e ,P- for device identification. )#is met#od is faster t#an po$$ing but re8uires additiona$ #ard*are suc# as priorit! $ogic for so$ving t#e priorit! for mu$tip$e interrupts.

ADVANTAGES AND DISADVANTAGES

)#e advantage of t#is interrupt mode of I/O is t#at t#e data transfer ta+es p$ace on$! *#en t#e device is read! and t#erefore as t#e ,P- is not id$e it can put to ot#er usefu$ *or+. 5ence. t#e ,P-6s po*er cou$d be uti$i0ed effective$!. )#e main disadvantages #ere is t#e additiona$ cost for interrupt $ogic. And it ma! not

be suitab$e for #and$ing ver! fast devices. )#erefore Direct <D A= is used.

emor! Access

5.... DIRECT $E$OR- ACCESS

Direct memor! access refers to t#at data transfer. *#en $arge b$oc+s of data are to be transferred at #ig# speeds bet*een I/O devices and main memor!. *it#out invo$ving t#e ,P-. In order to perform D A transfer. an additiona$ interface circuitr! is re8uired +no*n as D A contro$$er.

D$A CONTRO55ER
contro$ circuit used for D A transfer t#e operation of t#is is under t#e contro$ of a program. e2ecuted b! t#e ,P

to initiate t#e transfer. t#e processor sends t#e starting address of t#e b$oc+. t#e number of *ords in t#e b$oc+. t#e direction of transfer A to or from memor! on receiving t#is information. t#e contro$$er performs t#e re8uested transfer. On comp$etion. it informs ,P- about it. )#e D A contro$$er s#o*n in figure 5.'. #as t#e fo$$o*ing four registers to perform transfer ; 1. An address register A used to #o$d t#e address of t#e ne2t *ord to be transferred 2. A data buffer register A used to store t#e data to be transferred 3. A data count register or *ord counter A used to store t#e number of *ords t#at are remaining to be transferred. It is automatica$$! decrements after t#e transfer of eac# *ord and tested for 0ero. 7#en t#e data count reac#es 0ero. t#e D A transfer #a$ts. ". ,ontro$ register and circuits A used to contro$ t#e D A transfer )#ere are t*o sc#emes for connecting D A contro$$er and t#e I/O devices to t#e 4us 1. A sing$e A 4us structure 2. )*o/ 4us structure *it# a Ff$oatingG D A contro$$er

3igure 5.' s#o*ing D A contro$$er in a sing$e bus structure

+ystem bus

CPU

Main me mor

Memory address re(ister

Data count re(ister

Data )u&&er re(ister

Contro$ re(ister * circuits DMA contro$$er

I / O device 7#en bot# ,P- and t#e D A contro$$er tr! to access t#e main memor!. t#ere arises a conf$ict situation. difficu$t to #and$e. )o reso$ve t#is. a specia$ circuit +no*n as emor! bus contro$$er or 4us Arbiter is used.

D$A INITIATION
)#e perip#era$ devices initiate t#e D A transfer b! sending a D A re8uest signa$ to t#e ,P- *#en it is read! to perform a transfer. )#ere are t*o met#ods b! *#ic# D A transfer is initiated and operated ; 1. 4urst mode 2. ,!c$e/%tea$ing mode

BURST $ODE
7#en t#e data is being transferred to t#e memor! or from t#e memor!. t#e ,Premains id$e for re$ative$! $ong periods of time or t#e ,P- is in a +ind of 5OED state. )#e ,P- e2its form t#is state on$! after t#e D A re8uest signa$ is *it#dra*n from t#e I/O device. %uc# a transfer is +no*n as 4urst mode transfer.

)#e #o$d duration depends on t#e speed of t#e memor!. I/O device. number of b!tes to be transferred.

C-C5E-STEA5ING $ODE
)#e ,P- after receiving t#e D A re8uest signa$ from t#e perip#era$. *i$$ attend to t#e current instruction. it is doing and suspends its operation for t#e ne2t time s$ice <mac#ine c!c$e=. During t#e ne2t time s$ice. t#e D A transfer ta+es p$ace and one *ord is transferred bet*een t#e perip#era$ device and t#e main memor!. On comp$etion of t#e transfer. t#e ,P- can resume to its norma$ operation. D A transfers are essentia$$! time/s$iced *it# t#e operations of t#e main memor!. 5ere. t#e D A contro$$er can be regarded as Fstea$ingG memor! c!c$es from t#e ,P-. 5ence. t#is tec#ni8ue is +no*n as c!c$e/stea$ing. 3igure 5.H s#o*s t#e princip$e of c!c$e/stea$ing.

3igure 5.H princip$e of c!c$e/stea$ing

DMA re,uest

,!c$es for main program ,!c$es for D A

ADVANTAGES AND DISADVANTAGES

)#e Advantages/ during t#e actua$ transfer bet*een perip#era$ and memor!. ,P- is free from t#is activit! and can do some ot#er usefu$ *or+. )#e ,Pspeed *i$$ be s$o*ed do*n on$! b! memor! c!c$es sto$en b! D A. )#e main disadvantages being t#e cost of t#e D A #ard*are. need to store t#e data in continuous memor! $ocations and a$$ error conditions to be read I ana$!0ed b! t#e ,P-. %o. t#ese $imitations are and over come b! Input/Output ,#anne$s.

5.8

I/O CHANNE5S

A$t#oug#.

program/contro$$ed

I/O

and

D A

mec#anisms

fu$fi$$

a$$

I/O

re8uirements of man! mac#ines. %ome sort of D A arrangement is re8uired to effective$! use ,P- time. in case of $arge sing$e ,P- computers *#ere. t#e program/contro$$ed approac# is undesirab$e. )#erefore a sma$$ processor ca$$ed ,#anne$ is used t#at acts as a s#ared D A faci$it! for a number of devices. )#e organi0ation of t*o I/O c#anne$s is s#o*n in figure 5.J 3igure 5.J -se of I/O c#anne$s
CPU

Main memory

C'anne$ A

C'anne$ )
Contro$ unit Contro$ unit I/O device I/O device

)#ere are t#ree t!pes of c#anne$s. name$! 1. u$tip$e2er c#anne$ 2. %e$ector c#anne$ 3. 4$oc+ mu$tip$e2er c#anne$

5.5

STANDARD I/O INTERFACES

In order to connect and communicate I/O device and computer. different interfaces are re8uired. %o. it is re8uired to standardi0e t#e interfaces. 3or e2amp$e. a number of 4us standards #ave evo$ved $i+e t#e -nibus. C ? bus. u$tibus. I???/"HH etc.

5.9

SU$$AR-

In t#is unit. t#e focus *as on t#e t#ree basic approac#es to #and$ing of I/O transfers name$!. programmed AI/O. D A transfer and Interrupt I/O. )#e

simp$est tec#ni8ue being t#at of programmed I/O. *#ere t#e ,P- performs a$$ t#e necessar! contro$ functions. 7#en speed becomes a prob$em. t#en one ma! turn to t#e D A approac#. *#ic# re8uires additiona$ #ard*are. Interrupt #and$ing. t#e use of I/O c#anne$s and standard I/O interfaces *ere a$so discussed brief$!.

5.:

;UESTIONS

1. 7#at is t#e need of addressing an I/O device > 2. 7#at is t#e difference bet*een memor!/mapped I/O and I/O/mapped I/O > 3. 7#at are t#e different t!pes of data transfer > name. ". 7#at is programmed/I/O > 5. 4ring out t#e advantages and disadvantages of programmed/I/O. &. 7#at is D A> 5o* is it initiated > '. 7#at is an interrupt > 5o* is it #and$ed > H. 7#at does t#e term Fc!c$e stea$ingG mean > J. 7#at are I/O c#anne$s > #o* are t#e! usefu$ > 10. :ame an! t*o standard I/O interfaces.