LabVIEW Real-Time Sequencer on CompactRIO Documentation

Publish Date: Nov 25, 2013

Overview
The LabVIEW Real-Time Sequencer on CompactRIO sample project implements a user-customizable control sequence that controls a plant using an FPGA device. This sample project is based on the Simple State Machine and Queued Message Handler templates. National Instruments recommends you familiarize yourself with the concepts introduced in those templates and their documentation, available from the Create Project dialog box, before using this sample project.

Table of Contents
1. Features 2. Developer Walkthrough 3. System Requirements 4. Overview 5. Running this Sample Project 6. Modifying this Sample Project 7. LabVIEW Features and Concepts Used

1. Features
User-customizable control sequence User interface (UI) VIInteracts with the CompactRIO device and displays data. Error handling applicationReports and logs all errors from the CompactRIO device. For critical errors, places the FPGA device in a safe state and restarts the RT target.

2. Developer Walkthrough
Refer to ni.com for a developer walkthrough of the LabVIEW Real-Time sample projects.

3. System Requirements
Development System LabVIEW Full or Professional Development System LabVIEW Real-Time Module LabVIEW FPGA Module NI-RIO device driver software NI CompactRIO Device in FPGA Interface Mode If you have different hardware than what is listed in this section, adapt the sample project to your hardware . This sample project is compiled for an NI cRIO-9074 set to LabVIEW FPGA Interface mode. In addition, this sample project utilizes the following components: Software on the RT target: Network Streams Network Variable Engine NI System Configuration NI-RIO NI-Watchdog I/O modules: NI C Series analog input module (NI 9201 module in slot 1) NI C Series analog output module (NI 9263 module in slot 2) NI C Series digital input module (NI 9411 module in slot 3) NI C Series thermocouple input module (NI 9211 module in slot 4)

4. Overview
This sample project consists of ten parallel loops across three execution targets: Development Computer Loops Event Handling Loop in UI Main.viHandles events from the user interface by transferring messages to UI Message Loop based on user events. UI Message Loop in UI Main.viHandles messages from the user interface and other loops on the development computer by transferring messages between Event Handling Loop and Monitoring Loop. Monitoring Loop in UI Main.viDisplays messages and data from the CompactRIO device acquired from RT Loop - System Health and FPGA Monitoring.vi. Real-Time Controller Loops RT Loop - Sequence Engine.viExecutes steps in the user-defined control sequence with the parameters and the order specified in UI Main.vi. Responds to start, pause, resume, and stop commands sent from UI Main.vi. RT Loop - UI Commands.viReads commands sent from UI Main.vi and produces the appropriate messages. Message Handling Loop in RT Main.viHandles messages from all loops that run on the real-time controller. RT Loop - Watchdog.viResets the watchdog counter to ensure the real-time controller remains responsive. RT Loop - System Health and FPGA Monitoring.viMonitors the CPU and memory usage of the real-time controller. Writes the monitored information to network-published shared variables displayed on the Data Monitoring and System Monitoring front panel tabs of UI Main.vi. FPGA Device Loops

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Control Loop in FPGA Main.viReads data from the input modules, applies a control algorithm to each channel, and writes to the NI 9263 module outputs. The control algorithm uses setpoint data and PID gains specified in the control sequence. Watchdog Loop in FPGA Main.viChecks the watchdog register, set by RT Loop - Watchdog.vi, to ensure the real-time controller is communicating with the FPGA device. If communication cannot be established, Watchdog Loop sets the FPGA device to a safe state and restarts the device.

5. Running this Sample Project

1. Adapt the sample project to your hardware. 2. In the Project Explorer window, set the IP address for your RT target. 3. Right-click RT CompactRIO TargetRT Main.vi and select Run. This VI initializes the FPGA device and runs FPGA Main.vi. 4. Open and run My ComputerUI Main.vi. 5. Enter the IP address of the CompactRIO chassis in the Controller Address text box and click Connect. 6. After you connect to the CompactRIO chassis, click Build Control Sequence on the Sequence Steps tab to build or load a control sequence. 7. In the Build Control Sequence dialog box, build your control sequence by adding steps from the Available Steps list and customizing the step parameters that appear when you add steps to the Control Sequence list. You can save or load a control sequence by clicking the Save or Load buttons. 8. Click Done when you finish building your control sequence. 9. Click Start Sequence to send your configured control sequence to the RT target and begin executing the sequence. 10. When you finish using the sample project, click Exit to stop any sequence that may be running and exit the application.

6. Modifying this Sample Project

Adapting this Sample Project to Your Hardware In this sample project, FPGA Main.vi is compiled for specific FPGA and I/O hardware. If you have a different FPGA device or different C Series modules, you must adapt this sample project to your hardware. Note The following steps refer to NI CompactRIO devices, but you also can adapt this sample project to an NI Single-Board RIO device. 1. Configure the devices you plan to add to the project and connect them to the same network as the development computer. 2. In the Project Explorer window, add your RT CompactRIO target to the top-level project item. 3. Add your CompactRIO chassis to the RT CompactRIO target you added in the previous step. Ensure the chassis is set to LabVIEW FPGA Interface mode. 4. Add your FPGA target to the CompactRIO chassis you added in the previous step. When LabVIEW prompts you to deploy settings, click Deploy Later. 5. Add your C Series input and output modules to the FPGA target you added in the previous step. 6. Drag the following project items from the default RT CompactRIO target to the target you added in step 2: Error Handlers folder Globals folder Support VIs folder RT Loops folder Type Definitions folder Test Steps folder Shared Variables.lvlib RT Main.vi 7. Drag the following project items from the default FPGA target to the one you added in step 4: Support VIs folder Type Definitions folder FPGA Main.vi 8. Delete the default RT CompactRIO target item from the project. This item does not have associated VIs. 9. Re-establish the link between RT Main.vi and the bitfile: a. Open Initialize and Run FPGA VI.vi, located in the Support VIs folder on the RT CompactRIO target. b. Drag FPGA Main.vi from the Project Explorer window to the Open FPGA VI Reference function on the Initialize and Run FPGA VI.vi block diagram. 10. Open FPGA Main.vi and ensure the FPGA I/O nodes use the desired input and output channels. For example, you may want an FPGA I/O node to read from Mod2/AI5 instead of Mod1/AI0. The actual channels you read from and write to depend on your application. By default, the FPGA I/O nodes in this VI read from Mod1/AI0 and Mod4/TC0 and write to Mod2/AO01. 11. To minimize compile time, make necessary changes, such as defining a control algorithm and defining a safe state.

Defining a Control Algorithm Locate the Control (PID) subdiagram of the Case structure in FPGA Main.vi and modify this subdiagram to apply a control algorithm. For example, you can use the PID Express VI (included in the LabVIEW Real-Time Module when you activate a license for the NI LabVIEW PID & Fuzzy Logic Toolkit using your LabVIEW Real-Time Module serial number). Note Although this sample project is designed to implement a PID algorithm, you can modify the sample project to use any algorithm.

Defining Safe Values for Hardware Connected to the C Series Modules Modify the Safe State, Default subdiagram of the Case structure in FPGA Main.vi to write safe values to the output channels. The values you write here should be ones that you know the connected hardware can safely handle. By default, this subdiagram writes a value of 0 to all output channels. This subdiagram executes in the following situations: When FPGA Main.vi first runs When no control sequence is executing The watchdog algorithm times out An error occurs while reading from or writing to an FPGA I/O channel A "Critical" or "Non-Critical" error occurs on the development computer or real-time controller You click the Switch Target to Safe State, Stop Sequence, or Exit button in UI Main.vi Creating Custom Control Steps To add custom control steps, you must modify several projects files and create a VI that defines your step parameters: 1.

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1. In the Project Explorer window, right-click My ComputerControl Step Configuration VIsStep Configuration Template.vit and select New from Template. 2. Modify the new VI according to the front panel and block diagram comments. 3. Save the new VI to the Step Configuration VIs folder in the project's root directory on disk. 4. Open My ComputerControl Step Configuration VIsStep LUT.vi. 5. Edit the Step Names array to include the control step name you want to show the user, and edit the Step Paths array to include the relative path to the VI you created from Step Configuration Template.vit. Make sure you edit the control step name and relative path to the VI at matching indexes in both arrays. 6. Save Step LUT.vi. 7. Open RT CompactRIO TargetRT LoopsRT Loop - Sequence Engine.vi. 8. On the block diagram, locate the Sequence Steps Case structure within the Running subdiagram. Add your new control step as a new subdiagram in the Sequence Steps Case structure. The selector label text should match the name that you entered in the Step Names array. 9. Add the code for your control step to this new case. Parameters for your step are available in the variant input to the Sequence Steps Case structure. Configuring the Application In the Project Explorer window, open My ComputerGlobalsGlobal - Configuration Options.vi. Use this VI to configure the following settings: Network Stream Connect Timeout (ms)Specifies the time period during which both endpoints of a network stream must be established. The default is 5000 ms. Network Stream Polling Timeout (ms)Specifies how often the real-time controller polls the user interface for commands. The default is 500 ms. UI Stream Name and RT Stream NameSpecifies the names of the network streams. These controls affect the endpoint URLs but otherwise have no impact on the application. Watchdog Pet Rate (ms)Specifies how often the real-time controller resets the watchdog counter. The default is 100 ms. RT Error LogSpecifies the location of the error log file on disk. The default is c:\logs\logs.txt. Monitoring Loop Rate (ms)Specifies how often the user interface updates with monitoring and health information from the CompactRIO device. The default is 200 ms. Error Log Max Size (bytes)Specifies the maximum size of the error log. The default is 100000 bytes. Control Period (ticks)Specifies how often the control algorithm executes. The default is 40000 ticks of the FPGA clock. Error Log Duplicate Interval (ms)Specifies the time period during which identical errors are considered duplicates. The default is 5000 ms. Note Only the first in a series of identical errors will be logged during the interval of time specified by this control. For example, if an error occurs after 2000 ms have elapsed and occurs again after 5000 ms have elapsed, and Error Log Duplicate Interval (ms) is 6000 ms, the second occurrence is considered a duplicate and not logged. Only 3000 ms have elapsed, not the 6000 ms required to treat the second error as unique.

Timeout Period (ticks)Specifies how long the FPGA device has to respond to a watchdog counter reset. The default is 40000000 ticks of the FPGA clock. DebuggingIf you are programming or testing the application, leave Debugging as TRUE. If you are building an application for deployment, set Debugging to FALSE.

7. LabVIEW Features and Concepts Used

Asynchronous calls Case structures Clusters Control refnums Enums Error clusters Event structures Fixed-point data type Flat Sequence structures FPGA I/O Node FPGA Interface VIs and Functions Global variables LabVIEW Schema VIs and Functions Network-published shared variables Network streams Parallelism Producer/Consumer design pattern Project libraries Queued Message Handler template Queues Shared Variable Node, VI, and Functions Shift registers Simple State Machine template State machines Subpanels Typedefs Value change events User events Watchdog VIs While Loops

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