Mini Project Progress Report

We chose to do a complete mixed signal IC design process. With this purpose, we decided to design a Phase Locked Loop (PLL) because the design process would incorporate topics from digital, analog, IC design, and control s stems theor . !his range of topics is an ade"uate wa to incorporate the primar electrical engineering theories into one pro#ect. $ PLL is a closed loop fre"uenc s stem that locks the phase of an output signal to an input reference signal. !he term %lock& refers to a constant or 'ero phase difference between two signals. !he fre"uenc of the feedback signal, ffb is compared to the input reference signal, f ref, until the two signals are locked. If the phase is unmatched, this is called the unlocked state, and the signal is sent to each component in the loop to correct the phase difference. !hese components consist of the Phase (re"uenc )etector (P()), the charge pump (CP), the low pass filter (LP(), and the *oltage controlled oscillator (+C,). !he P() detects an phase differences in f ref and ffb and then generates an error signal. $ccording to that error signal the CP either increases or decreases the amount of charge to the LP(. !his amount of charge either speeds up or slows down the +C,. !he loop continues in this process until the phase difference between fref and ffb is 'ero or constant-this is the locked mode. $fter the loop has attained a locked status, the loop still continues in the process but the output of each component is constant. !he output signal, fout, has the same phase and.or fre"uenc as f ref. $ basic form of a PLL consists of four main blocks/ 0. Phase )etector or Phase (re"uenc )etector (P) or P()) 1. Charge Pump (CP) 2. Low Pass (ilter (LP() 3. +oltage Controlled ,scillator (+C,)

Work done this week !he phase fre"uenc detector, P(), measures the difference in phase between the reference and feedback signals. If there is a phase difference between the two signals, it generates %up& or %down& s nchroni'ed signals to the charge pump. low pass filter. If the error signal from the P() is an %up& signal, then the charge pump pumps charge onto the LP( capacitor which increases the control *oltage, +cntrl. ,n the contrar , if the error signal from the P() is a %down& signal, the charge pump remo*es charge from the LP( capacitor, which decreases +cntrl. +cntrl is the input to the +C,. !hus, the LP( is necessar to onl allow )C signals into the +C, and is also necessar to store the charge from the CP. !he purpose of the

+C, is to either speed up or slow down the feedback signal according to the error generated b the P(). If the P() generates an %up& signal, the +C, speeds up. ,n the contrar , if a %down& signal is generated, the +C, slows down. !he output of the +C, is then fed back to the P() in order to recalculate the phase difference, thus creating a closed loop fre"uenc control s stem.

Phase Frequency Detector (PFD)

4 Phase (re"uenc )etector allows for wide fre"uenc locking range, potentiall entire +C, tuning range 4 25stage operation with 6P and ),W7 outputs 4 8dge5triggered results in dut c cle insensiti*it . !he Phase fre"uenc detector circuit was implemented in the Cadence +irtuoso software.!he below figure shows the Phase (re"uenc detector circuit. It consists of two positi*e edge triggered ) flip flops and a $7) gate connected to the reset of the two flip flops. !he ) flip flops are implemented using two input and three input 7$7) gates which are in turn implemented in C9,: technolog . !he mosfets are modeled using the ;<nm technolog .

Figure 2

PFD Si u!ation resu!ts

!he !ransient anal sis of the P() is run for 0<< ns . !wo clock signals ha*ing a period of 0<ns and 1=ns with >< ? dut c cle are used as the two inputs in0 and in1 respecti*el . @a and @b are the outputs of the two ) flip flops. (igure 3 indicates the output of the simulation. In this example for the two gi*en inputs, in1 leads in0 b a phase difference. !his phase error between the two inputs is recorded b the output @b. $s the ) flip flops used are positi*e edge triggered, the phase difference between the positi*e edges of the two inputs is recorded. $ 'oomed *ersion of the pre*ious result is shown in figure > where it can be clearl obser*ed that the phase error between the two inputs is recorded between their positi*e edges. !here are spikes present in the signal @a which triggers the reset command of the ) flip flops and makes both @a and @b outputs 'ero .

Figure "

Figure #

Work to $e done ne%t week Charge Pump A !he phase fre"uenc detector pro*ides the phase error between the two inputs in the form of a fre"uenc *ar ing signal. !his phase error is re"uired to be a*eraged and con*erted to a *oltage error signal which can then be fed to a *oltage controlled oscillator.

R&F&R&'(&S 0.Bobert C. Chang and Lung5Chih Cuo , %$ )ifferential5! pe Cmos Phase (re"uenc )etector&, !he :econd I888 $sia Pacific Conference on $:ICs 1. )ennis (ischette, %Practical Phase Locked Loop )esign& , 1<<3 I::CC !utorial 2. D. Ba'a*i, Design of Analog Integrated Circuits , !ata 9cEraw5Fill 8dition 1<<1