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1. Mention any four binary logical operators in VHDL. 2. Bidirectional port is declared by using _____________ statement. 3. W ene!

er one of t e signal in ________________ c anges" t e se#uential statements in t e process body are e$ecuted in se#uence one time. %. & e output of '11() * +1(1, is ______________. -. .i!e an e$ample for !ariable statement in VHDL. /. 0ame t e libraries in VHDL. 1. W at are t e bloc2s used in be a!ioral modeling3 4. List t e types of conditional statements. 5. Write any t6o pre defined enumeration data type. 1(. W at is component instantiation3 11. Write t e synta$ for subtype declaration. 12. 7ignal assignment statements as default delay 2no6n as _________ . 13. 8s VHDL a typed language or not3 1%. W at is &est benc 3 1-. 9ompare signal and !ariable. Define !ariables in VHDL. Define constants in VHDL. W at are t e le!els of modeling3 Dra6 t e test benc arc itecture 0ame any t6o data ob:ect classes. /. 0ame any t6o logical operators used in VHDL. 1. ; component declaration declares _________. 4. 0ame some soft6are tools used for simulation. 5. Write t e synta$ for conditional signal assignment statement. 1(. W at is a test benc 3 Data ob:ects are created in VHDL by _________. /. W at is component instantiation3 1. <$plain 8= statement in VHDL. 4. W at is t e primary mec anism used to model t e be a!ior of an entity3 5. W at is netlist3 1(. 0ame t e t6o 6ays to perform association of formals 6it actuals. W at are t e t6o 2inds of identifiers in VHDL3 /. Mention some of t e 7 ift >perators. 1. Define Delta delay. 4. W at is t e use of bloc2 statement3 5. Write t e synta$ for component declaration. 1(. W at are t6o 6ays to perform t e association of formats 6it actuals3 W at are t e operators a!ailable in VHDL3 1. Ho6 is t e component declared in VHDL3 4. W at are t e types of assignment statements3 5. Differentiate concurrent and se#uential statements. 1(. <$plain about structural modeling. Write a VHDL ?rogram for full adder.

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W at is t e simulation action of t e follo6ing VHDL statement3 clk <= not clk after 10 nsec, 5. .i!e e$ample for conditional assignment statement in VHDL. 1(. Mention t e different types of Modeling in VHDL. <!ery component in VHDL is referred as __________. 4. __________does not define t e entity@arc itecture pair to be bound to eac instance" or e!en t e ports on t e entity 5. & e statements 6 en t ey are not contained in a VHDL process or Bloc2 is __________ 1(. .i!e t e synta$ for signal declaration.
.i!e one e$ample of constant declaration using VHDL. /. 0ame any t6o ma:or data types used in VHDL. 1. W at is delta delay3 4. W at is a selected signal assignment statement3 5. Ho6 do you con!ert integer into a time !alues3 1(. W at is a test benc 3

W at are t e different types of modeling in VHDL /. Mention different data types used in VHDL 1. ;ssert and report statements are used in concurrent assertion statement A BCesD0oE 4. 9onditional assignment statements are used for be a!ioral modeling A BCesD0oE 5. W at is 9omponent 8nstantiation. 1(. W at is meant by &est benc . 8n a standard HDL design flo6 =loor@planning is done before t e placement of logic cells. B&rue D =alseE /. 8n a data flo6 based modeling" t e modeling is done 6it respect to __________. 1. Mention any t6o conditional signal assignment3 4. Differentiate t e term <ntity and ;rc itecture in VHDL3 5. 8s structural modeling similar to .ate@le!el modeling3 B&rue D =alseE 1(. Define any t6o se#uential statements used in VHDL3