Reg. No.

Question Paper Code :

(Regulation 2009)
Time : Three hours
'*+.** jr ",r,,t:4.-

'=e., # "1r
Maximum : 1oo marks

Answer Al,ft'.luestfri4q,
'tt *" tr ..

PART A l. 2. 3. 4. What are the sources of po*"*

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i

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$0,a<,4; 2O'lnart<qj' i ;' i " ,.. "o$Sirngti.ht to..,,r,o''

;
i *",*:f'

in VLSI circuits?

List any four basic princjples o'fr{prw pcirver;fit St design. tr

o,-^-

state the effect of charirrel lpttgffi dhyporver dissipation in VLSI circuits. jivl
'. t# -

".iu'

what are the techniqueg #itu**e%r multipliers? "' .,., :,

reducing power consumption in

5.
6. 7.

How does the design of supply clock influence power dissipation?

Define sigiial Ae{i,yity with respect to a circuit node. What are- flre'dr.awbacks
:.:{, :,,11i ,.

,'i'tau,

8.

averggd p'ower in I/LSI circuits? .:' DiStingBishtet$l,een power estimation at circuit level and high level power ,, esti$atotsr.'". Larggimprovements in power dissipation are possible only at higher levels

of zero-delay mod.el used for determination

of

9':/

ofd""inf

straction.Why?

10. -Whatt'r61't the objectives of power minimization

rneg.rory that can be achieved using software?

techniques

related. to

PARf B -

(5

"

16 ='80 marks)

Or

(b) (il
(ir)

Discuss the dynamic logic and static respect to power dissipation.

k#-"

its with (6)

Explain h a94t about operation reduction substitution with examples.u*"

*"""u' il

and operation (E + S)

13. (a)

Explain any two techniquesfrviB, -ot, ' '$# "t."trtq"-pre consumption in memories. o

for reducing power

(b) Draw the resonantari$er ffiq

"t'",'

S*tf*"u''.
t''t- o"

"%*f

compare it with other nqetHo$;*[ls$ sive the imporLnce generation with reSppt topowei disfpation
fl'

ifu g"r"r.ting supply crock and

of clock

L4. (a)

Draw tfie fl"F"t q[]!:f MEhte-Cartobasedestimation of glitching powerfor secigent$ and expLain. ,"i (8) S "it"F (ir) write a note d'iqpow-g;fbsumation based.o"i"iilror*"tion theory .,,,,' approach. lA t \*^ t UL-*Or

(il

Explairr'..lhe method of estirnating average power in combinational an$se3rr"Cn#atcircuits using sta.tistical techniques., ." .S i.... pe.": "l:,Efllr"'' ", 15. (a) .D,iseuqpiifaetairi trre. various revels of abstraction at which power

(b)

tt":'Fte-*ot"*""

.i

estimated bJ software' *", "

(b) ',Larsif r*p.1o1r"*.rrts in power dissipation are possibre at higher levels on'{gqign"'abstraction. JustiS o-t'dgqlgn"'bbstraction. JustiS the-above the above statlment statement and and discuss discuss the the ", '' teoftniques ". used.

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77907

Reg. No. :

QuestionPaper Code: 98081

M.E. DEGREEEXAMINATION,NOVEMBERID
Electiue VLSI Design

YL9252 - LOW POWERVLSI DESIGN (Common to M.E. AppliedElectronics)

(Regulation Time : Three hours Answer ALL 100 Marks

PART A
1. 2.

Definesubthresholdswing.
What is body effect? What is meant by tra Define intrinsic delav. Draw a 6 transistor SRAM ceIL Com R type row decoder and NAND type row decoderin memories. computing? Imn"lemeni
ttu.

3.
4.
o.

6. 7.

nction A*

+ BX + C using two multipliers and two ad.ders.

9.

'-'.,, *rffl iO***Wdffi?f*o an algorithm to compute signal probabilities. "w _%,u

De "-%,"

% 'r %,

e"**fl

P A RTB- ( 5x 11. (a)

16=80M ar ks)

(t-'
(ii)

Derive an expressionfor short circuit power dissipation inverter. ffi write a short note on drain induced barrier roweri Or

(b)

(i) "'rFxplain basic principles of low power design. (iip Discuss the various sources of power d devices. Discuss the various features of technology J (8)
,w s"

12.

(a)

(,

i&

b-

(8) power (8)

dissipation. Or
(b) (il
(ii)

rchniquesfo, J

Explain the concept of state assignment for finite state machine to reducepower dissipation wi 5ample. (10)
Factoring out a common

Justi$r.

n can achieve power saving.

13. (a)

(t
(ii)

(6)
t}': i,+

How can power be red

amplifier circuits? Differentiate MT Explain the Design a How do diagrams? Discuss m circuits.

st t*

circuits and sense (10) (6)

(b) (il
(ii) 14.
l.* L"l

(a)
,.
f,

(t
".f

ff levetconverter. i.t'ttt.: lo g ic . * - * . jT u ' * i *:

(10) (6)

,aw
ds 5f Or

@mpu W* -

probability using binary decision ting average power in combinational (8)

;'o '

(s)

(ii)

0 tl \_,,,

??*er
15. (a)
1..* l tl

Explain in detail about Monte carlo method for estimating glitch power. the- principle of pre-computation logic for reducing power dtable example. /o\ (8)

(b) E*fr

Or
the tion.

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are? Expiain. costs

33
Reg.No.:

Q 0205
TNtryJULY 2009 D.A{.Tech. DEGRES SXAh{INATION, THIRDSEMESTFR VLSI DESIGN
VL5OO2 LOW POWERW.,SIDESIGN (Common to Applied Siectronics) (REGUI"ATION 2007) Tlrroe hor:re AnswerALL questions: (10 x 2 = h}marks) PARTA -..,ow the $witching Frequencyinfluencps tbe Power Dissipation in a logic

Maximum : 100narks

Whataretbg sources of Fower Dissipation"?

lltirat is a G.ate Dela;'podel.? Whqt is Bus lnvert Encoding? What is O-MOS Floating Node? i

I)raw the Adiabaticlogic Inverter for for:r phaseoperation.. What is Glitching Power? Write the eguationfor CapacitivePowerDissipationof a bircuit.

f,.

:
l1' . (a) '(b)

PARTts- (Ex tr6= g0marks)

-:rv t

State aud explain the basic principles and figure-of-merits oj'Low Ilorve Design. (t

I)erive an expression for the dyeanric Power Dissipatinn in a CMCI --F Inverter. ic

,Ot 'Discuss 72. in detail various limits of l-,owpower Design.

.i

13. ' Explsin i.r:. detail about p^.ecornpuLation logr. optimization: Cr !t1,,'Explain the variou.ecircrujt" tecl.rnl ,iiesfor reclucingp^orv*r gRDl-r"edpu Consumptionil Muitipliers. A* r IPL, DpL SDJr-r r DevJ(,
Iil,

Explain tbe methodsof reduci.g Wwer in V/riter Driver circuits and Sense Amplifier eircuits"

lo.

tT.

how a Sigual lhohsbility ie calculated using Bio"ry Decision 1*) RfP Diagram.
(b) Exptain in dei;ul how l:lr',

Bo-slt Ptga,ttr

[*lffi***"W*r?$/ L8. \E-TIEAGu*t u.,r"t ros Iogc

'oprrn.til::

ver Estimatio: #;ri T:i) oo .qY.*"r*.$":s lffi H"s$35

:o$

(8)

(8)

Simrrlation and)f,rchitldture L,evel' Analysie.

M.iftr

o*.":$*;;':5

1rr. (a) Discussin detail the Poweroptinization using operation Reductionand .!ubgti.tu.;:.i.,)::;.
(b) . what is meant by Technorory Mapping?Exprainwith Or t?-> 20. Iixllain in detgil Softwarel)enign Cptimization methods.
tt. .I

an exampre.

i1*; (4)

s{

fo0**"'o Y
;;;

9$thn*lion

a gJ, wd, wc)

* Atchr:fadh^'tal

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t't'"t t

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N 0036
M'E'&r'Tech' I)l:" GREIIEXAMINATI'NN''TEMBER,,E'EMBER 2008. THIRDSEME:STER APPI,IED ELECTRONICS ]./I,'OA}I,OW POWER WSI DESIGN (Common to VLSIcl.esign,l (REGUI,ATION 2OO7)
15me: Threehours Maximum : 100noarks AnswerALL questions. ' I'}ART A - (10 .{ ! =.e.{'t nrarks) ..ai od*, tru,,J**'nho\ t#;

1.' Listthe five levers"of Higlarchv offjpit, g-lqrpDissipation.,^ s:lij*: qtou'srds o).o'-sl/t<rr'9,r"tr*tliJ#;: * * i$r r.regs'p'E "H:: isrhe nu'iJprin.ipr.(oir,o* &" what po*r, -., il.is.,rs

[*[

T] :sJ,*;"ff-\

. ro*or* *"r*rrr;ilrr*4'
5. 6"

List few circuid hchniques for reducrng powerconsurnption.

I)ra;v i;he6T SiiAIvI ceil.

\!hat is Low S*ing Bus System?

7
8'

Define Sample Oorrelation.at o d1*;i+r" d

",il"';Tq:' rlo o.va no o\ :i'oglf** r*.iir,"o" yg",1l*.'::t',1 ;;TiT:;",{,*9. .5

Level can produ.ui * large improvement in power .S+pht

9' ffIj,Jehavioral

lnb+l;L;l\ of tlr.L P*do-

d:

11*,'."'Explain irr detailthe Physics of Power Dissipation in Submicron MOSfnf. tt\ Or

r't'r

,,} ,k tr,. \

L2. [a]' Derivean expression for the shortcircuitpowerdissipation in a CMCS Inverter. (S) G) Derivethe expression for powerdissipated in a \ILSI circuit d-ue to parasitic capacitor. WSt fil -"6' -l zi 13. ,.Explain in detailthe CircuitLevelLowpow :

r;;::;;:ff
.i
. 1K

(b) iixplain 'ihe Deiay Balance,j-.l'{ultiplier Oell and its impact on the pgwqr. consumption of a parallelsrray multiplier fdi

powerconsumption Explainthe techniques of reducing i n Mernories. .Or

t)
(8)

16'9 (a) V/hatis Adiabaticlcgtclnverter? Draw andexplainits operation.

(b). How rloesthe Cor.nplernenfary t -L AcliahstieCon:,putaticn Cif,br frr--:n r,ii.tr static cMos Gateirr powerDissipation? Explainin detail. (s)

Explainin detail.theLogicpowerEBtimation Technioues. ^ r ,n. Soqrcg uf ;n*u? dlsxtption, prob"trrn S'lnk-rng,t ,d.nqru,r-nd, .!tgu\ Csrtcthh 4zm?ottl t"twtah'rl, Spa*rOtc.*91-$F0h,gpd#io "lo*pr"",f CsryroJtirn;"*UU,i$t tgl bi \"/' J) 19 Tith the flowchart explain i;heMonte CarlobasedtecLiriqueto estimate the average power. in sequeutial circuits (g) Explain in detail aboutthe powerEstimatior.r usingEntropy. Frplain in^ dct'ail'tlic i.cila','icr.=.i Level Traiisfcuns (B)

fo. irnpr',rvirrg Fower ' Dissipation. j lnd olt(a,a* #roiar, actu^ l,H\ t)/ fb"a" &fteyar.n, onden

nnga.l+wdtfv\-wa.e r.cerr>siu!^ d,tff{"au , Sor,&"1 Or

20. (a) Discuss in detailthesources power of software ) (6) Dissipatioo.[ss.A ' (b) Explain in detailCod+sign for Lowpower. (10)

l;

I N 0036 |

Re g .No . :

it * F 1 #.d" Commonto M.E. Applied Electronics/ M.E. fhsl "'"..^*./ Electiue

EXAMINATION, JlJfiffi\e"fu1 DEGREE M.E./lVLTech.

fime: Three hours AnswerALL PART A 1. What is punch through? What is meant by Reve What is multilevel
What are the algorithm? of performance driven circuit optimization nnel effect? marks)

2.
3. 4.

D.

How is

reduced by using clock gating?

6. 7.

t'" /*i I What are"ttib sHlidntfeatures of adiabatic logic circuit?

-\***ts'

"\"4
\c/

P A RT B -(b x 1 6 = 8 0 ma rk s ) 11. (a) (r) (ii) Derive the expression for subthreshold current MOSFET. Explain the MIS structure and derive the of depletion region.

f
nel (8)

\U

for

or
unloadedinverter.

(b ).'(0 Deduce the expression for short circuit noi

(ii) 12. (a) Explain the circuit limits of low

f# -.1 \ i"Jl
of an (8)
gn.

#--h"

depth (8)

(8)

Explain the power dissipation algorithm. Apply the same

following function F = {fr, fr}

fi=ad+bcd and fz=a + b c + dhiltkl. \

logic optimization the power for the

lY ,t'"1
(b) (i)"-"'"Explain circuit example.
(ii)'- Write short 13. (a) for CMOS gate with an (10) (6) method in sense amplifier circuits of

(t (ii)

Explain SRAM. D

(10)
organization of SRAM. Or

(6)

(b)

(') (ii)

reduced swing clock technique for power reduction in (8) the power reduction effrciency of Adiabatic logic. (8)

L4. (? A)"*"ryphin the transition Density signal model and propagation of _ t-'" ""a jfiansition density. (f 0) d--"=J-/ \"- i j calculate the transition density and static probability of y = ab + c , if P (o)=o.2, P (b)= 0 . 3 ,P (c )=0 . a , D(a )= r, D(b )= 2 a n d D(" )= 3 . (6) Or 31143

{'o*hu"*'r

\ =''"--*-" #J

,#"Y

iT "*l

(b)

(il (ii)

Explain Monte Carlo power simulation. Write short notes on Gate-levelpower analysis.

lSr
(8)

15. (a)

Write short noteson:

(1) Power optimization using operation reductj{\*\o/ (8)

(ii) Architecture drivenvoltage scaling.

or /\

#l w
th,

(8)

(b)

(r)

(ii)

for low power Explain the first-order differedps--."ptff#h\f (8) (n, dissipation. orssrpaf,ron l**-\{f {"f d*\ f f l\ \ Write short notes on conskahed} l$ast square technique for (8) nonadaptivefrlters. f"*t3'*/

d' \

ui L-ot,\
'j

=-*./*} ,,
Lr

t"

'"

i '''
{*o..

i ".,"\""n ! '-b-*t'""

fl'\-, *o "- ti

f\/i

t ! t."". i i.,/ ..'''"L....:\=; />

l*l
i*,.
!.r'

1*

31148

". aq"i

i
I

Reg. No. :

&o

7 t

,q

u 0046
M.E ;/M.Tech:DEGREE EXAMINATION, NOVEMBER/DE OEMBERz010 . THIRD SEMESTER APPLIED ELECTRONICS VL5OO2 LOW POWERVLSI DESIGN

(REGULATION2007) fime : Three hours Answer ALL questions.

.a

Maximum : 100marks

1.' 2'

What is short channel effeet? Give the expression for the energy transferred out of the power-supply during a low-to-high transition, at the gate output. What are the four componentg of performance driven circuit optimization algorithms? What is transistor reordering? What is clock gating? " Draw the Boolgan decision diagram for the logic expression y =ffi. List the three steps invorved in Monte carro power simulation. Defi.ne Ttansition Density. what is the use of DCM technique in the realization of FIR frrters? ^"*o"y bandwidth reguirements. :

3'

4. 5. 6. 7. 8. 9.

10. List the four practices that minimize

11.

the physicsof power fieeipation in ,"5tplain (a) Iong channelMOSFET.

-t'o'

(8) (8)

(b)

SubmicronMOSFET.

Or
L2. (a) Derive an expression for the power dissipation due to the charging and (8) discharging of a capacitance in a CMOS Inverter. (8)

(b},t"'Di""use the basic principles of Inw Power d,esign.

13. (a) , What is Factoring?What is its effectin powersaving? Explain. (b) Write a note onTechnologyMapping. Or

(10) (g)

14;"'e"l)i"" ss in 'detail' about the rcircuit level techniques for , reducing power eonsumption. .

15.)(a) (b)

Explain the concept of red.ucing power in sense amplifi.er circuits employed for SRAM circuits. (8) How low core voltiges are achibved from a single supply? (8)

Or
16. Explain in d.etail about Low SwingBus. Charge Recycling Bus. , (8)

:, (a) O)

17. (a) (b)

Defrne etatic probability. Brplain the propagationrof static probability in logic'circuits. (8) Computethe transition density and static probability of y = ab + c given P(o) = o.z, P(b)= 0.3, P(c)= s.4 , ' : ' D (a )=l , D (b )= 2 , D( e) =s rprobabitities and ff'here P(a) P(b) PG) are the inpur sraric O(") A(a) A(c) are the transition density of the inputs). (g)
Or

18.

Prove that Lag-one signal Model provides one additional degree of freedom over the memoryless'signal model.

itul

t "m*J
-

19. Explain the first.order differenceg algorithm and second-order.differences algorithm for improvementin power dissipationtargeted for digital filters. (1.6)

20.

Explain in detail about ,(a) ,(b) Software Power Estimation. ,Software Power Optimization. .: ,

Re g . No . :

Question Paper Code : 9L852

M.E. DEGREE EXAMINATION, JANUARY 2012, Elective \T,SI Design YL 9252 - LOW POWER VLSI DESIGN (Regulation 2009) Time : Three hours Answer ALL questions. P A RTA-(1 0 1. x 2 = 2 0 ma rk s ) Maximum : 100 marks

Why is power dissipation consideredas the most critical factor in development of microelectronicstechnology? What is DIBL? Minimum area is not always associated with minimum power dissipation for CMOS circuits. Justifv this statement. Name two techniquesfor reduction of power in multipliers. Define Gate reorsanization. What is clock gating? List the steps involved to estimate maximum and minimum averagepower of i circuit. What are glitches?How doesit affect power requirement? Name the various levels of design abstraction where power dissipation can be reduced. Compare gate level and architecture level power estimation.

2. 3.

4. 5. 6. 7.

8. 9.

10.

P A RT B -(5 x 1 6 = 8 0 ma rk s ) 11. (a) Elaborate on the various factors that contribute to power dissipation in CMOS circuits. Or (b) Discuss the different limits that are to be applied at various levels for design of low power VLSI circuits. Explain the optimization techniques for reduced power consumption in muitiplier circuits. Or (b) 13. (a) Explain the muitilevel, logic optimization procedurefor low power. Describe in detail the various techniques used for reducing power consumptionin memories. Or (b) With circuit schematic compare the circuit performance and power dissipation of ratioed logic, DCVS logic, pass transistor logic, Domino logic and DCSL logic. Discuss the Monte Carlo based method for power estimation of combinational and sequential logic circuits. Or (b) Explain the simuiation based approach for determining maximum dynamic power in static CMOS. With an example, enumerate power optimization using operation reduction, operation substitution and precomputation. Or (b) (i) (ii) What are the various sources of power dissipation in a CPU that (8) Explain. can be influenced by sofbware? Discuss how the memory access costs can be minimized using (8) software techniqueswith example.

L2. (a)

14. (a)

15.

(a)

91852

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