California Eastern Laboratories APPLICATION NOTE AN1033 NonLinear HJ-FET Model Verification in a PCS Amplifier

PCS Amplifier Design Part 3

I. Introduction Lower development costs and shorter times to market of telecommunication subsystems require effective and accurate circuit simulation. This translates into designs that work at turn-on or with limited tuning. Simulation is now considered part of the standard design procedure. To perform extensive nonlinear simulations on a circuit, nonlinear models for the active devices need to be developed. This paper describes the steps involved in verifying a commercially available nonlinear Hetero-Junction Field Effect Transistor (HJ-FET) model. The non-linear model is then validated when it is used to predict circuit performance in a low noise PCS amplifier. The modeled results are then compared to measured data. II. Model types There are several types of models which can be developed to predict the behavior of an active device. One type of model is a linear model. A linear model is fairly easy to generate, easy to use, and is usually developed at a particular bias. The designer can relate parameter values to the equivalent circuit model, and a linear model can be used by both linear and nonlinear simulators. However, the linear model cannot be used to predict nonlinear performance such as compressed output power, mixing products, or intermodulation performance. The nonlinear model consists of a series of analytical mathematical relationships where parameters have been linked to physical device behavior. Nonlinear models are more complex, but when properly developed can be used over a range of biases and can predict nonlinear behaviors. Nonlinear models are used to simulate mixer and oscillator applications and provide useful information on the linearity and output power of an amplifier. III. Requirements for a nonlinear device model Most amplifier designs, and other telecommunication

subsystems such as mixers and oscillators, start with linear simulations. This first step usually requires only linear components such as measured S-parameters and noise parameters. With experience, the engineer can develop a feel for the practical problems involved in linear matching. Additionally, there are many well outlined references and design approaches to small signal simulations that yield accurate laboratory results on a first prototype. However, for the nonlinear performance of such designs, the results are often less accurate and test bench tuning can result in considerable frustration. Developing a good understanding of nonlinear models, their expected performance and technical limitations can improve the accuracy of a circuit and reduce turn around time for a new design. The engineer can use the nonlinear model to optimize and center a design on such nonlinear device performance such as the output power of an oscillator, conversion gain of a mixer, or IP3 of a low noise amplifier. IV. Choosing the nonlinear model Once it has been established that a nonlinear model of a device would be useful, and supporting laboratory measurements have been taken, a nonlinear model must be chosen. The choice of model is determined by evaluating the DC characteristics of the device and comparing these measured characteristics to characteristics of available nonlinear models. Different models implement the DC I-V curve equations differently [1]. For the device under consideration, NECs NE34018, it was determined Triquints Own Model (TOM) would best represent the I-V curves because the HJ-FET showed an almost linear increase in drain current with increasing drain voltage at lower gate voltages and an approximately constant drain current with respect to increasing drain voltage at higher gate voltages (see Fig. 2).

V. Extracting the device model Just as there is more than one nonlinear model to choose from, there is more than one method available for extracting model parameters. Parameter extraction methods range from expensive extraction software products to a more simple but less efficient method of optimizing model parameters until the model reflects the measured data within the range of interest. Whatever method is chosen, it is important to have an idea of how the model parameters affect the predicted results and what the appropriate limits are for the parameters. CEL currently has a process for developing an HJFET model. This is accomplished by extracting DC model parameters which reflect the measured I-V curves, and then the AC parameters are adjusted. Once the DC and AC performance of the model is satisfactory, the model can be optimized to fit measured power and noise data. Model parameters affect more than one type of simulation response. For example, the model parameter Rg effects both the I-V curves and the S-parameters, and Cds effects both the S-parameters and output power. These dependencies are evaluated during the model extraction phase. The

value of a parameter that results in the model providing the best S-parameter fit may not provide the best fit to measured power data. There is usually a trade-off when developing a device model over a wide range of biases and frequencies. VI. Device model extraction results The device model for the NE34018 was extracted over the following ranges: DC: Vds=0V to 5V, Vgs=0V to -0.7V AC: Vds=1V to 3V, Id=5mA to 40mA, Frequency=0.5 GHz to 6 GHz Power and IM3: Vds=3V, Id=20mA, Frequency=2 GHz. Fig. 1 and Table 1 present the final device model and Fig. 2-8 compare the results of the extracted device model to the measured data. S-parameter comparisons (Fig. 3-6) are shown at the desired PCS amplifier bias of Vds=3V, Ids=20mA.

CGD_PKG 0.02pF LD Q1 LG_PKG GATE 0.18nH 0.93nH CDS_PKG CGS_PKG 0.1pF LS 0.25nH 0.1pF LG 0.4nH LD_PKG DRAIN 0.18nH

LS_PKG 0.09nH

SOURCE

Fig. 1. NEC NE34018 Model Schematic

LIBRA PARAMETER PARAMETER VALUE VTO -0.6885 VTOSC 0 ALPHA 5 BETA 0.1838 GAMMA 0.038 GAMMADC 0.03 Q 1.8 DELTA 0.25 VBI 0.7 IS 3e-13 N 1 RIS 0 RID 0 TAU 4e-12 CDS 0.1e-12 RDB 5000 CBS 1e-11 CGSO 0.95e-12 CGDO 0.04e-12 DELTA1 0.3 DELTA2 0.05 FC 0.5 VBR infinity RD 4 RG 1.5 RS 2 RGMET 0 KF 0 AF 1 XTI 3 EG 1.43 VTOTC 0 BETATCE 0 FFE 1

DEFINITION nonscaleable portion of the threshold voltage scaleable portion of the threshold voltage current saturation parameter transconductance parameter or coefficient AC drain pull coefficient DC drain pull coefficient power law exponent output feedback coefficient built-in gate potential gate junction reverse saturation current gate junction ideality factor source end channel resistance drain end channel resistance transit time under gate drain-source capacitance dispersion source output impedance dispersion source capacitance zero bias gate-source junction capacitance zero bias gate-drain junction capacitance capacitance saturation transition voltage parameter capacitance threshold transition voltage parameter coefficient for forward bias depletion capacitance gate-drain junction reverse bias breakdown voltage drain ohmic resistance gate ohmic resistance source ohmic resistance gate metal resistance flicker noise coefficient flicker noise exponent temperature exponent for saturation current energy gap or band gap voltage VTO temperature coefficient BETA exponential temperature coefficient flicker noise frequency exponent

Table 1. Triquints Own Model (TOM) Parameters for the NE34018

100.0 90.0 80.0 M2 70.0 60.0 50.0 40.0 30.0 20.0 10.0 M1 0.0 0.0 Bias 2 0.5/DIV IDS M1: VGS = -0.744 V M2: VGS = 0 V VDS = 2 V VDS = 2 V IDS = 100 A IDSS = 70.9 mA 5.0 -0.2 V -0.3 V -0.4 V -0.5 V -0.6 V -0.7 V -0.744 V -0.1 V VGS: 0V

1.0 0.5 2.0

0.2

5.0

0.0 0.0

0.2

0.5

1.0

2.0

5.0

INF

-0.2

-5.0

-0.5 -1.0 Measured Modeled

-2.0

Frequency 0.5 to 6.0 GHz VDS = 3 V ID = 20 mA

Fig. 2a. NEC NE34018 Modeled I-V Curves

Fig. 3. NEC NE34018 Measured vs. Modeled S11

100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 0.0 Bias 2 0.5/DIV M1: VDS = 2 V M2: VDS = 2 V IDS = 7.116 mA IDSS = 70.9 mA 5.0 M1 -0.6 V -0.7 V -0.4 V -0.5 V M2 IDSS -0.1 V VGS: 0V

1.0 0.5 2.0

0.2
-0.2 V -0.3 V

5.0

0.0 0.0

0.2

0.5

1.0

2.0

5.0

INF

-0.2

-5.0

-0.5 -1.0 Measured Modeled

-2.0

Frequency 0.5 to 6.0 GHz VDS = 3 V ID = 20 mA

Fig. 2b. NEC NE34018 Measured I-V Curves

Fig. 4. NEC NE34018 Measured vs. Modeled S22

90 10.0 120 8.0 6.0 150 4.0 2.0 180 0.0 0 30 60

22.0 M1 20.0 18.0 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 M3 M2 Frequency, GHz
2.0 modeled 2.0 measured

-150

-30

0.0 -20.0 Power 5.0 dBm/DIV Gain Modeled (dB) POUT Modeled (dBm) Gain Measured (dB) POUT Measured (dBm) ang = 69.3 ang = 24.4 5.0

-120 -90 Measured Modeled

-60

VDS = 3 V Source Impedance: Load Impedance: M1: Power = -20.0 dBm M2: Power = -4.75 dBm M3: Power = -4.75 dBm

ID = 20 mA mag = 0.69 mag = 0.54

Frequency 0.5 to 6.0 GHz VDS = 3 V ID = 20 mA

Value = 20.2 dB Value = 19.2 dB Value = 14.5 dBm

Fig. 5. NEC NE34018 Measured vs. Modeled S21

Fig. 7. NEC NE34018 Measured vs. Modeled Gain and Power

90 0.2 120 0.15 60

40.0 Frequency, GHz 20.0 0.0

2.0 modeled 2.0 measured

150

0.1 0.05

30

-20.0 -40.0 -60.0

180

0.0

-80.0 -100.0 -120.0

-150

-30

-30.0 Power 5.0 dBm/DIV POUT Modeled (dBm) POUT Measured (dBm) ID = 20 mA mag = 0.69 mag = 0.45

0.0

IM3

IM5

-120 -90

-60

VDS = 3 V Source Impedance: Load Impedance:

ang = 69.3 ang = 72.4

Measured

Modeled

Frequency 0.5 to 6.0 GHz VDS = 3 V ID = 20 mA

Fig. 6. NEC NE34018 Measured vs. Modeled S12

Fig. 8. NEC NE34018 Measured vs. Modeled Power, IM3 and IM5

Because nonlinear model results are predicted through the use of mathematical expressions which have been simplified from actual behavior, a nonlinear model can not perfectly predict the actual performance of the device being modeled. CEL sets a model performance target over the desired frequency and bias range of 10% error from the measured data for the magnitude of the S-parameter predictions and 10 degrees for the angle.

error(magnitude) = (|S11|measured - |S11|modeled)/ (|S11|measured) (1) error(angle) = S11measured - S11modeled (2)

100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 -100.0 0.5
Frequency, GHz 1 V, 5 mA 3 V, 20 mA 3 V, 40 mA

10.0

Fig. 9-16 present the final AC error data for the extracted NEC NE34018 model at the three biases representing the low (1V,5mA), middle (3V,20mA) and high (3V,40mA) bias ranges of the device. Although the error target is 10%, exceptions are made when actual differences in magnitudes are less than 0.1. For instance, a measured magnitude value of S22 = 0.27 and a modeled magnitude = 0.35, results in a error of 30% using equation (1), but the magnitude difference is only 0.08.

Fig. 10. NEC NE34018 Error Graph - Phase of S11

100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 -100.0 0.5
Frequency, GHz 1 V, 5 mA 3 V, 20 mA 3 V, 40 mA

10.0

100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 -100.0 0.5
Frequency, GHz 1 V, 5 mA 3 V, 20 mA 3 V, 40 mA

10.0

Fig. 9. NEC NE34018 Error Graph - Magnitude of S11

Fig. 11. NEC NE34018 Error Graph - Magnitude of S22

100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 -100.0 0.5
Frequency, GHz 1 V, 5 mA 3 V, 20 mA 3 V, 40 mA

10.0

100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 -100.0 0.5
Frequency, GHz 1 V, 5 mA 3 V, 20 mA 3 V, 40 mA

10.0

Fig. 12. NEC NE34018 Error Graph - Phase of S22

Fig. 14. NEC NE34018 Error Graph - Phase of S21

100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 -100.0 0.5
Frequency, GHz 1 V, 5 mA 3 V, 20 mA 3 V, 40 mA

10.0

100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 -100.0 0.5
Frequency, GHz 1 V, 5 mA 3 V, 20 mA 3 V, 40 mA

10.0

Fig. 13. NEC NE34018 Error Graph - Magnitude of S21

Fig. 15. NEC NE34018 Error Graph - Magnitude of S12

100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 -100.0 0.5
Frequency, GHz 1 V, 5 mA 3 V, 20 mA 3 V, 40 mA

VII. Application circuit verification Once the nonlinear device model has been extracted and accurately predicts measured data, how well can it predict actual circuit behavior? This question can be answered by building a circuit and comparing the measured performance to the simulated performance using the nonlinear model. A PCS amplifier was designed [2], built and tested. The design goals for the amplifier were: Bias: Vds = 3V, Id = 20mA Frequency: 1.932 - 1.99GHz (tested at 1.96GHz) Noise figure: maximum of 0.8 dB Output return loss: minimum of -15 dB To achieve a realistic circuit simulation, the circuit elements and microstrip lines must be properly modeled in addition to having an accurate nonlinear model. The quality factor (Q) and the frequency at which it is defined (F) can be obtained from the component manufacturer for capacitors and inductors. Knowing the board material provides information needed to model the microstrip lines. Grounding and biasing must also be accurately represented in the simulation. Fig. 17-18 are HP-EEsof Series IV Libra schematic representations of the PCS amplifier used for simulation.
PORT P2 port = 2

10.0

Fig. 16. NEC NE34018 Error Graph - Phase of S12

CAP Cgdpkg C = Cgdpkg

IND Ld L = Id

PORT P1 port = 1

IND Lgx L = lgx

IND Lg L = lg

GAASFET FET2 AREA = 1 MODEL = FET1 MODE = nonlinear IND Ls L = Is

CAP Cdspkg C = Cdspkg

TOM FET1

CAP Cgspkg C = Cgspkg

VTO = vto VTOSC = vtosc ALPHA = alpha BETA = beta GAMMA = gamma GAMMADC = gammadc Q=q

DELTA = delta VBI = vbi IS = is N=n RIS = ris RID = rid TAU = tau

IND Lsx L = Isx PORT P3 port = 3 CDS = cds FC = 0.50 RDB = rdb VBR = 0 CBS = cbs RG = rg CGSD = cgso RD = rd CGDO = cgdo RS = rs DELTA1 = delta1 RGMET = 0 DETA2 = delta2 KF = 0

AF = 1 TNOM = 27 XTI = 3 EG = 1.43 VTOTC = 0 BETATCE = 0 FFE = 1

Fig. 17. HP-EEsof Series IV Libra NE34018 Schematic

TP TP-gate PORT P1 port = 1 CAPQ Cin C = cin MLIN Q = 100 TL1 F = 100 W = 50 MOD = prop-to sqrt-f L = 120 MSUB = MSUB 1 IND Lin L = lin

TP TP-drain

CAPQ Cout C = cout Q = 100 F = 100 MOD = prop-to sqrt-f

MLIN AMMETER MLIN MLIN TL3 TL4 TL2W = 50 340 8-sch AMM1 W = 50 X1 W = 50 L = 480 L = 100 L = 150 MSUB = MSUB 1 VIA RES MSUB = MSUB 1 MSUB = MSUB 1 DATA V8 Rout COND2-LAYER = cond2 RES D1 = 10 DIEL1 = diel MSUB R = rout INDQ R2 D2 = 15 DIEL2 = diel2 MSUB1 VIA Lout R = 56000 H = h-via-s HOLE = hole ER = 4.80 V6 L = LOUT MLIN T = 0.15 RES= resi H = 28 VIA D1 = 10 Q = 50 TL5 W = 25 T = 0.15 V7 D2 = 15 F = 100 W = 10 COND1-LAYER = cond D1 = 10 H = h-via MOD = prop-to sqrt-f COND2-LAYER = cond2 L = 230 HOLE-LAYER = hole T = 0.15 MLIN MSUB = MSUB 1 D2 = 15 COND2-LAYER = cond2 H = h-via-s W = 25 TL9 CAPP IND T = 0.15 COND1-LAYER = cond W = 10 C3 Li CAP W = 25 HOLE-LAYER = hole L = 340 C = 1000 L = 1000000000 C5 COND1-LAYER = cond MSUB = MSUB 1 TAND = 5.00e-03 C = 4700000 + DCVS HOLE-LAYER = hole Q = 50 SRC2 MLIN FQ = 20 IND CAPP DC = -0.44 TL6 FR = 25 Lo C6 W = 25 VIA L = 1000000000 CAP C = 1000 L = 75 V1 C7 TAND = 5.00e-03 VCR MSUB = MSUB 1 D1 = 10 C = 4700000 Q = 50 EQN CAPP + DCVS D2 = 15 FQ = 20 C4 SRCc VAR H = h-via VIA FR = 25 C = 120 DC = 3 -VAR T = 0.15 V5 TAND = 5.00e-03 VIA Cin = 56 COND2-LAYER = cond2 W = 25 D1 = 10 Q = 200 V3 Cout = 3.30 COND1-LAYER = cond D2 = 15 VIA FQ = 20 D1 = 10 Rout = 180 HOLE-LAYER = hole H = h-via V4 FR = 25 D2 = 15 Lin = 6.50 COND2-LAYER = cond2 T = 0.15 D1 = 10 H = h-via Lout = 1.80 W = 25 COND2-LAYER = cond2 D2 = 15 VIA T = 0.15 h-via = 180 COND1-LAYER = cond H = h-via V2 W = 25 h-via-s = 35 HOLE-LAYER = hole T = 0.15 D1 = 10 COND1-LAYER = cond W = 25 D2 = 15 HOLE-LAYER = hole COND1-LAYER = cond H = h-via HOLE-LAYER = hole T = 0.15 COND2-LAYER = cond2 W = 25 COND1-LAYER = cond HOLE-LAYER = hole

PORT P2 port = 2

Fig. 18. HP-EEsof Series IV Libra LNA Schematic using the NE34018 Model Fig. 19-24 illustrate how well the nonlinear model and appropriately modeled circuit elements can represent actual circuit behavior. For a low noise amplifier, the noise figure (Fig. 24) and the gain (Fig. 22) are key performance indicators.
0.0 24.0

0.0

-5.0

21.0

-5.0

-10.0

18.0

-10.0

-15.0

15.0

-15.0

-20.0

12.0

-20.0

-25.0

9.0

-25.0

-30.0 1.0
Frequency 0.5, GHz/DIV S11 (dB) S22 (dB) S21 (dB)

6.0 3.0

-30.0 1.0
Frequency 0.5, GHz/DIV Measured S11 Modeled S11 Measured S22 Modeled S22

3.0

VDS = 3 V ID = 20 mA

VDS = 3 V ID = 20 mA

Fig. 19. LNA Measured S11, S22 and S21

Fig. 20. LNA Measured vs. Modeled S11 and S22

20.0

40.0 Frequency, GHz 20.0

1.96 modeled 1.96 measured

0.0

15.0

-20.0 -40.0

-60.0

10.0

-80.0

-100.0 -18.0 Power 2.0 dBm/DIV

4.0

5.0 1.0
Frequency 0.5, GHz/DIV Measured Modeled

POUT Modeled (dBm)

POUT Measured (dBm)

IM3

IM5

3.0
POUT, IM3 and IM5 VDS = 3 V ID = 20 mA

S21 VDS = 3 V ID = 20 mA

Fig. 23. LNA Measured vs. Modeled Power, IM3 and IM5

Fig. 21. LNA Measured vs. Modeled S21

18.0 M1 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 -2.0 -18.0 Power 2.0 dBm/DIV POUT (dBm) VDS = 3 V M1: Power = -18.0 dBm M2: Power = 1.4 dBm M3: Power = -4.75 dBm Gain (dB) ID = 20 mA Value = 16.1 dB Value = 15.1 dB Value = 16.5 dBm

20.0
M3 M2 Frequency, GHz
1.96 modeled 1.96 measured

15.0

10.0

M1 0.5

4.0

0.0 1.0
Frequency 0.5, GHz/DIV NF (dB)

3.0

Fig. 22. LNA Measured vs. Modeled Gain and Power

NF VDS = 3 V ID = 20 mA M1 Frequency = 1.96 GHz NF = 0.505 dB

Fig. 24. LNA Modeled NF

VIII. Conclusions A nonlinear model is useful to predict and optimize the nonlinear performance of a design. A nonlinear device model was extracted for the NE34018, and the results of the model generated data were compared to the measured data with good correlation. The device model was further verified by using it in a PCS amplifier design and comparing the results of the simulation to data measured on the circuit, again with good correlation.

Acknowledgment The authors would like to thank Bernie Urborg at California Eastern Laboratories for measurements on the device and the circuit. References [1] AN1023 Converting GaAs FET Models for Different Nonlinear Simulators, California Eastern Laboratories [2] AN1022 Designing Low Noise Amplifiers for PCS Application, California Eastern Laboratories

California Eastern Laboratories

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California Eastern Laboratories 02/04/2003