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bq24725
www.ti.com SLUS702A JULY 2010 REVISED NOVEMBER 2010
2-4 Cell Li+ Battery SMBus Charge Controller with N-Channel Power MOSFET Selector and Advanced Circuit Protection
Check for Samples: bq24725
1
FEATURES
SMBus Host-Controlled NMOS-NMOS Synchronous Buck Converter with Programmable 615kHz, 750kHz, and 885kHz Switching Frequencies Automatic N-channel MOSFET Selection of System Power Source from Adapter or Battery Driven by Internal Charge Pumps Enhanced Safety Features for Over Voltage Protection, Over Current Protection, Battery, Inductor and MOSFET Short Circuit Protection Programmable Input Current, Charge Voltage, Charge Current Limits 0.5% Charge Voltage Accuracy up to 19.2V 3% Charge Current Accuracy up to 8.128A 3% Input Current Accuracy up to 8.064A 2% 20x Adapter Current or Charge Current Amplifier Output Accuracy Programmable Battery Depletion Threshold, and Battery LERAN Function Programmable Adapter Detection and Indicator Integrated Soft Start Integrated Loop Compensation Real Time System Control on ILIM pin to Limit Charge Current AC Adapter Operating Range 9V-24V 5A Off-State Battery Discharge Current 20-pin 3.5 x 3.5 mm2 QFN Package
DESCRIPTION
The bq24725 is a high-efficiency, synchronous battery charger, offering low component count for space-constraint, multi-chemistry battery charging applications. The bq24725 uses two charge pumps to separately drive n-channel MOSFETs (ACFET, RBFET and BATFET) for automatic system power source selection. SMBus controlled input current, charge current, and charge voltage DACs allow for high regulation accuracies that can be programmed by the system power management micro-controller. The bq24725 uses internal input current register or external ILIM pin to throttle down PWM modulation to reduce the charge current. The bq24725 charges two, three or four series Li+ cells, and is available in a 20-pin, 3.5 x 3.5 mm2 QFN package.
PHASE HIDRV REGN
16
20
19
18
17
BTST
VCC
15 14
bq24725
13 12
11 BATDRV
APPLICATIONS
Portable Notebook Computers, UMPC, UltraThin Notebook, and Netbook Personal Digital Assistant Handheld Terminal Industrial and Medical Equipment Portable Equipment
10
ACDET
IOUT
SDA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments.
Copyright 2010, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
SCL
ILIM
bq24725
SLUS702A JULY 2010 REVISED NOVEMBER 2010 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
R12 1M
EN
D2 BAT54C
U2 IMD2A
Adapter + Adapter -
SYSTEM
C3 0.1F ACN VCC R6 4.02k ACP CMSRC REGN ACDRV BATDRV C6 1F D1 BAT54 C15 0.01F Q5 (BATFET) FDS6680A R9 10 C5 1F Total Csys 220F
R10 4.02k
BTST
C8 10uF Q3 Sis412DN
C9 10uF
HIDRV ILIM
+3.3V
U1 bq24725
C7 0.047F PHASE
RSR 10m?
R3 10k
R4 10k
R5 10k SDA
Pack +
C10 10F C11 10F
HOST
SMBus
Pack -
SCL SRP
* *
Fs = 750kHz, IADPT = 4.096A, ICHRG = 2.944A, ILIM = 4A, VCHRG = 12.592V, 90W adapter and 3S2P battery pack See the application information about negative output voltage protection for hard shorts on battery to ground or battery reverse connection.
bq24725
www.ti.com SLUS702A JULY 2010 REVISED NOVEMBER 2010
D3 PDS1040
Adapter + Adapter -
RAC 10m?
SYSTEM
C1 0.1F C2 0.1F R11 4.02k C3 0.1F ACN VCC R6 4.02k ACP CMSRC REGN ACDRV BATDRV C6 1F D1 BAT54 C15 0.01F Q5 (BATFET) FDS6680A R9 10 C5 1F Total Csys 220F
Ri 2? Ci 2.2F
R10 4.02k
BTST
C8 10uF Q3 Sis412DN
C9 10uF
HIDRV ILIM
+3.3V
U1 bq24725
C7 0.047F PHASE
RSR 10m?
R3 10k
R4 10k
R5 10k SDA
Pack +
C10 10F C11 10F
HOST
SMBus
Pack -
SCL SRP
* *
Fs = 750kHz, IADPT = 2.688A, ICHRG = 1.984A, ILIM = 2.54A, VCHRG = 12.592V, 65W adapter and 3S2P battery pack See the application information about negative output voltage protection for hard shorts on battery to ground or battery reverse connection.
Figure 2. Typical System Schematic with One NMOS Selector and Schottky Diode ORDERING INFORMATION
PART NUMBER bq24725 IC MARKING BQ725 PACKAGE 20-PIN 3.5 x 3.5mm2 QFN ORDERING NUMBER (Tape and Reel) bq24725RGRR bq24725RGRT QUANTITY 3000 250
THERMAL INFORMATION
THERMAL METRIC (1) JA JT JB Junction-to-ambient thermal resistance (2) Junction-to-top characterization parameter (3) Junction-to-board characterization parameter
(4)
UNITS
C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA , using a procedure described in JESD51-2a (sections 6 and 7).
bq24725
SLUS702A JULY 2010 REVISED NOVEMBER 2010 www.ti.com
UNIT
C C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the data book for thermal limitations and considerations of packages.
ELECTRICAL CHARACTERISTICS
4.5 V VVCC 24 V, 0C TJ 125C, typical values are at TA = 25C, with respect to GND (unless otherwise noted)
PARAMETER OPERATING CONDITIONS VVCC_OP VBAT_REG_RNG VCC Input voltage operating range 4.5 24 V TEST CONDITIONS MIN TYP MAX UNIT
CHARGE VOLTAGE REGULATION BAT voltage regulation range ChargeVoltage() = 0x41A0H 1.024 16.716 -0.5% 12.529 0.5% 8.35 0.6% 8.4 12.592 16.8 19.2 16.884 0.5% 12.655 0.5% 8.45 0.6% V V V V
VBAT_REG_ACC
ChargeVoltage() = 0x3130H
ChargeVoltage() = 0x20D0H
bq24725
www.ti.com SLUS702A JULY 2010 REVISED NOVEMBER 2010
ChargeCurrent() = 0x0800H Charge Current Regulation Accuracy 10m current sensing resistor
ICHRG_REG_ACC
ChargeCurrent() = 0x0200H
ChargeCurrent() = 0x0100H
ChargeCurrent() = 0x0080H INPUT CURRENT REGULATION VIREG_DPM_RNG Input current regulation differential voltage range VIREG_DPM = VACP VACN InputCurrent() = 0x1000H
0 3973 3% 1946 5% 870 15% 384 25% 512 1024 2048 4096
mV mA
InputCurrent() = 0x0800H IDPM_REG_ACC Input current regulation accuracy 10m current sensing resistor InputCurrent() = 0x0400H
mA
mA
InputCurrent() = 0x0200H INPUT CURRENT OR CHARGE CURRENT SENSE AMPLIFIER VACP/N_OP VSRP/N_OP VIOUT IIOUT AIOUT Input common mode range Output Common Mode Range IOUT Output Voltage Range IOUT Output Current Current Sense Amplifier Gain V(ICOUT)/V(SRP-SRN) or V(ACP-ACN) V(SRP-SRN) or V(ACP-ACN) = 40.96mV V(SRP-SRN) or V(ACP-ACN) = 20.48mV VIOUT_ACC Current Sense Output Accuracy V(SRP-SRN) or V(ACP-ACN) = 10.24mV V(SRP-SRN) or V(ACP-ACN) = 5.12mV V(SRP-SRN) or V(ACP-ACN) = 2.56mV V(SRP-SRN) or V(ACP-ACN) = 1.28mV CIOUT_MAX VREGN_REG Maximum Output Load Capacitance For stability with 0 to 1mA load REGN REGULATOR REGN regulator voltage VVCC > 6.5V, VACDET > 0.6V (0-55mA load) VREGN = 0V, VVCC > UVLO charge enabled and not in TSHUT VREGN = 0V, VVCC > UVLO charge disabled or in TSHUT ILOAD = 100A to 65mA Voltage on ACP/ACN Voltage on SRP/SRN
mA
24 19.2 1.6 1
V V V mA V/V
5.5 65 7
6 80 16 1
6.5
V mA mA F
IREGN_LIM
CREGN
INPUT UNDERVOLTAGE LOCK-OUT COMPARATOR (UVLO) UVLO Under voltage rising threshold Under voltage hysteresis, falling VVCC rising VVCC falling 3.5 3.75 340 4 V mV
Fast DPM comparator (FAST_DPM) VFAST_DPM Fast DPM comparator stop charging rising threshold with respect to input current limit, voltage across input sense resistor rising edge (Specified by design) 108%
bq24725
SLUS702A JULY 2010 REVISED NOVEMBER 2010 www.ti.com
20
1 3
mA mA mA
ACOK COMPARATOR VACOK_RISE VACOK_FALL_HYS VVCC > UVLO, VACDET rising VVCC> UVLO, VACDET falling VVCC> UVLO, VACDET rising above 2.4V, First time OR ChargeOption() bit [15] = 0 (Default) VVCC> UVLO, VACDET rising above 2.4V, (NOT First time) AND ChargeOption() bit [15] = 1 VVCC> UVLO, VACDET rising VVCC> UVLO, VACDET falling VVCC falling towards VSRN VVCC rising above VSRN VACN falling towards VSRN VACN rising above VSRN ChargeOption() bit [8:7] = 00 VIFAULT_HI_RISE ACP to PHASE rising threshold ChargeOption() bit [8:7] = 01 ChargeOption() bit [8:7] = 10 (Default) ChargeOption() bit [8:7] = 11 LOW SIDE IFAULT COMPARATOR (IFAULT_LOW) VIFAULT_LOW_RISE VACOV VACOV_HYS PHASE to GND rising threshold 40 110 160 mV 0.3 2.376 35 100 0.9 2.4 55 150 1.3 0.57 0.51 2.424 75 200 1.7 0.8 V mV ms s V V
VACOK_RISE_DEG
VCC to SRN COMPARATOR (VCC_SRN) VCC-SRN falling threshold VCC-SRN rising hysteresis 70 100 125 150 180 200 mV mV
ACN to SRN COMPARATOR (ACN_SRN) VACN-SRN_FALL VACN-SRN_RHYS ACN to BAT falling threshold ACN to BAT rising hysteresis 120 40 200 80 280 120 mV mV
HIGH SIDE IFAULT COMPARATOR (IFAULT_HI) (1) 200 330 450 600 300 500 700 900 450 700 1000 1250 mV
INPUT OVER VOLTAGE COMPARATOR (ACOV) ACDET over voltage rising threshold ACDET over voltage falling hysteresis VACDET rising VACDET falling ChargeOption() bit [2:1] = 01 ChargeOption() bit [2:1] = 10 (Default) ChargeOption() bit [2:1] = 11 ChargeOption() Bit [2:1] = 01 (133%), InputCurrent () = 0x0400H (10.24mV) ChargeOption() Bit [2:1] = 11 (222%), InputCurrent () = 0x1F80H (80.64mV) Voltage across input sense resistor rising to disable charge 3.05 50 3.15 75 3.25 100 V mV
INPUT OVER CURRENT COMPARATOR (ACOC) (1) Adapter over current rising threshold with respect to input current limit, voltage across input sense resistor rising edge Min ACOC threshold clamp voltage Max ACOC threshold clamp voltage ACOC deglitch time (Specified by design) 120% 150% 200% 40 140 1.7 133% 166% 222% 45 150 2.5 145% 180% 240% 50 160 3.3 mV mV ms
VACOC
BAT OVER VOLTAGE COMPARATOR (BAT_OVP) VOVP_RISE VOVP_FALL Over voltage rising threshold as percentage of VBAT_REG Over voltage falling threshold as percentage of VBAT_REG VSRN rising VSRN falling 103% 104% 102% 106%
(1)
bq24725
www.ti.com SLUS702A JULY 2010 REVISED NOVEMBER 2010
VOCP_RISE
CHARGE UNDER CURRENT COMPARATOR (CHG_UCP) VUCP_FALL VLL_FALL VLL_RISE_HYST Charge undercurrent falling threshold VSRP falling towards VSRN 1 5 9 mV
LIGHT LOAD COMPARATOR (LIGHT_LOAD) Light load falling threshold Light load rising hysteresis Measure the voltage drop across current sensing resistor 1.25 1.25 mV mV
BATTERY DEPLETION COMPARATOR (BAT_DEPL) [1] ChargeOption() bit [12:11] Battery Depletion Falling Threshold, ChargeOption() bit [12:11] percentage of voltage regulation limit, VSRN ChargeOption() bit [12:11] falling ChargeOption() bit [12:11] = 00 = 01 = 10 = 11 (Default) 55.53% 59.19% 62.84% 58.68% 62.65% 66.62% 62.17% 66.55% 70.93% 66.06% 70.97% 75.88% 225 240 255 280 305 325 345 370 600 385 410 435 460 mV mV mV mV ms
VBATDEPL_FALL
ChargeOption() bit [12:11] = 00 VBATDEPL_RHYST Battery Depletion Rising Hysteresis, VSRN rising ChargeOption() bit [12:11] = 01 ChargeOption() bit [12:11] = 10 ChargeOption() bit [12:11] = 11 (Default) tBATDEPL_RDEG Battery Depletion Rising Deglitch (Specified by design) Delay to turn off ACFET and turn on BATFET during LEARN cycle
BATTERY LOWV COMPARATOR (BAT_LOWV) VBATLV_FALL VBATLV_RHYST IBATLV TSHUT TSHUT_HYS VILIM_FALL VILIM_RISE VIN_ VIN_ IIN_ Battery LOWV falling threshold Battery LOWV rising hysteresis Battery LOWV charge current limit VSRN falling VSRN rising 10 m current sensing resistor 2.4 2.5 200 0.5 2.6 V mV A
THERMAL SHUTDOWN COMPARATOR (TSHUT) Thermal shutdown rising temperature Thermal shutdown hysteresis, falling Temperature rising Temperature falling 155 20 C C
ILIM COMPARATOR ILIM as CE falling threshold ILIM as CE rising threshold VILIM falling VILIM rising 60 90 75 105 90 120 mV mV
Input low threshold Input high threshold Input bias current V=7V 2.1 1
0.8
V V
LEAK
LOGIC OUTPUT OPEN DRAIN (ACOK, SDA) VOUT_ LO IOUT_ LEAK IIN_ Output saturation voltage Leakage current 5 mA drain current V=7V 1 500 1 mV A
V=7V
PWM OSCILLATOR FSW FSW+ FSW IBATFET VBATFET RBATDRV_LOAD RBATDRV_OFF PWM switching frequency PWM increase frequency PWM decrease frequency ChargeOption () bit [9] = 0 (Default) ChargeOption() bit [10:9] = 11 ChargeOption() bit [10:9] = 01 600 665 465 750 885 615 900 1100 765 kHz kHz kHz
BATFET GATE DRIVER (BATDRV) BATDRV charge pump current limit Gate drive voltage on BATFET Minimum load resistance between BATDRV and SRN BATDRV turn-off resistance I = 30A VBATDRV - VSRN when VSRN > UVLO 40 5.5 500 5 6.2 7.4 60 6.1 6.5 A V k k
bq24725
SLUS702A JULY 2010 REVISED NOVEMBER 2010 www.ti.com
PWM HIGH SIDE DRIVER (HIDRV) RDS(on) VBTST_REFRESH High side driver (HSD) turn-on resistance High side driver turn-off resistance Bootstrap refresh comparator threshold voltage VBTST VPH = 5.5 V, I = 10mA VBTST VPH = 5.5 V, I = 10mA VBTST VPH when low side refresh pulse is requested 3.85 12 0.65 4.3 20 1.3 4.7 V
PWM LOW SIDE DRIVER (LODRV) RDS(on) Low side driver (LSD) turn-on resistance Low side driver turn-off resistance VREGN = 6 V, I = 10 mA VREGN = 6 V, I = 10 mA 15 0.9 25 1.4
PWM DRIVER TIMING tLOW_HIGH tHIGH_LOW ISTEP tSTEP tR tF tW(H) tW(L) tSU(STA) tH(STA) tSU(DAT) tH(DAT) tSU(STOP) t(BUF) FS(CL) ttimeout tBOOT Driver dead time from low side to high side Driver dead time from high side to low side 20 20 ns ns
INTERNAL SOFT START Soft start current step Soft start current step time In CCM mode 10m current sensing resistor 64 240 mA s
SMBus TIMING CHARACTERISTICS SCLK/SDATA rise time SCLK/SDATA fall time SCLK pulse width high SCLK Pulse Width Low Setup time for START condition START condition hold time after which first clock pulse is generated Data setup time Data hold time Setup time for STOP condition Bus free time between START and STOP condition Clock Frequency SMBus bus release timeout (2) Deglitch for watchdog reset signal Watchdog timeout period, ChargeOption() bit [14:13] = 01 (3) tWDI Watchdog timeout period, ChargeOption() bit [14:13] = 10 (3) Watchdog timeout period, ChargeOption() bit [14:13] = 11 (3) (Default) 4 4.7 4.7 4 250 300 4 4.7 10 100 1 300 50 s ns s s s s ns ns s s kHz
(2) (3)
Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have detected a timeout condition must reset the communication no later than the 35ms maximum timeout period. Both a master and a slave must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms). User can adjust threshold via SMBus ChargeOption() REG0x12.
bq24725
www.ti.com SLUS702A JULY 2010 REVISED NOVEMBER 2010
bq24725
SLUS702A JULY 2010 REVISED NOVEMBER 2010 www.ti.com
TYPICAL CHARACTERISTICS
Table 1. Table of Graphs
VCC, ACDET, REGN and ACOK Power up Charge Enable by ILIM Current Soft-start Charge Disable by ILIM Continuous Conduction Mode Switching Waveforms Cycle-by-Cycle Synchronous to Non-synchronous 100% Duty and Refresh Pulse System Load Transient (Input DPM) Battery Insertion Battery to Ground Short Protection Battery to Ground Short Transition Efficiency vs Output Current FIGURE NO. Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15
SPACER SPACER
CH1: VCC, 10V/div, CH2: ACDET, 2V/div, CH3: ACOK, 5V/div, CH4: REGN, 5V/div, 40ms/div Figure 4. VCC, ACDET, REGN and ACOK Power Up
CH1: ILIM, 1V/div, CH4: inductor current, 1A/div, 20ms/div Figure 5. Charge Enable by ILIM
CH1: Vin, 10V/div, CH2: LODRV, 5V/div, CH3: PHASE, 10V/div, CH4: inductor current, 2A/div, 2ms/div Figure 6. Current Soft-Start
CH1: ILIM, 1V/div, CH4: inductor current, 1A/div, 4us/div Figure 7. Charge Disable by ILIM
10
bq24725
www.ti.com SLUS702A JULY 2010 REVISED NOVEMBER 2010
CH1: HIDRV, 10V/div, CH2: LODRV, 5V/div, CH3: PHASE, 10V/div, CH4: inductor current, 2A/div, 400ns/div Figure 8. Continuous Conduction Mode Switching Waveforms
CH1: HIDRV, 10V/div, CH2: LODRV, 5V/div, CH3: PHASE, 10V/div, CH4: inductor current, 1A/div, 400ns/div Figure 9. Cycle-by-Cycle Synchronous to Non-synchronous
CH1: PHASE, 10V/div, CH2: LODRV, 5V/div, CH4: inductor current, 2A/div, 4us/div Figure 10. 100% Duty and Refresh Pulse
CH2: battery current, 2A/div, CH3: adapter current, 2A/div, CH4: system load current, 2A/div, 100us/div Figure 11. System Load Transient (Input DPM)
CH1: PHASE, 20V/div, CH2: battery voltage, 5V/div, CH3: LODRV, 10V/div, CH4: inductor current, 2A/div, 400us/div Figure 12. Battery Insertion
CH1: PHASE, 20V/div, CH2: LODRV, 10V/div, CH3: battery voltage, 5V/div, CH4: inductor current, 2A/div, 2ms/div Figure 13. Battery to Ground Short Protection
11
bq24725
SLUS702A JULY 2010 REVISED NOVEMBER 2010
98 97 96 95 4-cell 16.8 V
www.ti.com
Efficiency - %
3-cell 12.6 V 94 93 92 91 90 89 88 0 0.5 1 1.5 2 2.5 Charge Current 3 VI = 20 V, f = 750 kHz, L = 4.7 mH 3.5 4 4.5 2-cell 8.4 V
CH1: PHASE, 20V/div, CH2: LODRV, 10V/div, CH3: battery voltage, 5V/div, CH4: inductor current, 2A/div, 4us/div Figure 14. Battery to Ground Short Transition
FUNCTION DESCRIPTION
ACOK
ACDET
IOUT
8 9 10
11
BATDRV
12
SRN
12
bq24725
www.ti.com SLUS702A JULY 2010 REVISED NOVEMBER 2010
14 15 16
17 18 19 20
PowerPAD
13
bq24725
SLUS702A JULY 2010 REVISED NOVEMBER 2010 www.ti.com
VCC 20 ACDET 6
0.6V WAKEUP
4 ACDRV
ACOVP 3.15V ACGOOD ACDRV CMSRC+5.9V ACOC Latch off VCC_SRN ACDRV-CMSRC
Selector Logic
3 CMSRC
SRN+6V BATDRV CHARGE PUMP
ACOK 5
**
LEARN
11 BATDRV
BATDEPL SRN WATCHDOG TIMER WATCHDOG TIMEOUT 175s
ACP 2
20X
**
EN_CHRG Latch off
ACN 1 IOUT 7
1X MUX FBO IOUT_SEL Type III Compensation EAI
17 BTST
HSON
ILIM 10 SRP 13
20X
18 HIDRV 19 PHASE
SRN 12
VREF_ICHG VFB 200mV ILIM CE 105mV VREF_VREG 4mA in BATOVP WAKEUP 10uA Tj TSHUT 155oC LSON RAMP Frequency
**
EN_REGN
REGN LDO
16 REGN
15 LODRV
SRP-SRN DAC_VALID SMBus Interface CHARGE_INHIBIT LEARN VREF_VREG VREF_ICHG 1.25mV VREF_IAC SRP-SRN IOUT_SEL ACP-PH 700mV 5mV SRP-SRN 60mV/90mV/120mV
CHG_OCP
SDA 8 SCL 9
CHG_UCP
LIGHT_LOAD
IFAULT_HI
**
IFAULT_LO
PH-GND 110mV
ACP-ACN 1.66xVREF_IAC
**
ACOC
FAST_DPM
REFRESH
VFB 104%VREF_VREG
BATOVP
2.5V SRN
BAT_LOWV
VCC SRN+275mV
VCC-SRN
14
bq24725
www.ti.com SLUS702A JULY 2010 REVISED NOVEMBER 2010
Preset to 0b0001001
D7
D0
D15
D8
b) Read-Word Format
S SLAVE ADDRESS 7 BITS MSB LSB W 1b 0 ACK 1b 0 ACK 1b 0 S SLAVE ADDRESS 7 BITS MSB LSB R 1b 1 ACK 1b 0 LOW DATA BYTE 8 BITS MSB LSB ACK 1b 0 HIGH DATA BYTE 8 BITS MSB LSB NACK 1b 1 P
DeviceID() = 0xFFH Preset to D7 D0 D15 D8 ManufactureID() = 0xFEH 0b0001001 ChargeCurrent() = 0x14H ChargeVoltage() = 0x15H InputCurrent() = 0x3FH ChargeOption() = 0x12H LEGEND: S = START CONDITION OR REPEATED START CONDITION P = STOP CONDITION ACK = ACKNOWLEDGE (LOGIC-LOW) NACK = NOT ACKNOWLEDGE (LOGIC-HIGH) W = WRITE BIT (LOGIC-LOW) R = READ BIT (LOGIC-HIGH) MASTER TO SLAVE SLAVE TO MASTER
Preset to 0b0001001
15
bq24725
SLUS702A JULY 2010 REVISED NOVEMBER 2010 www.ti.com
tLOW
SMBCLK
t HIGH
SMBDATA
A = START CONDITION B = MSB OF ADDRESS CLOCKED INTO SLAVE C = LSB OF ADDRESS CLOCKED INTO SLA VE D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW F = ACKNOWLEDGE BIT CLOCKED INTO MASTER G = MSB OF DATA CLOCKED INTO MASTER H = LSB OF DATA CLOCKED INTO MASTER
Battery-Charger Commands
The bq24725 supports six battery-charger commands that use either Write-Word or Read-Word protocols, as summarized in Table 2. ManufacturerID() and DeviceID() can be used to identify the bq24725. The ManufacturerID() command always returns 0x0040H and the DeviceID() command always returns 0x0008H. Table 2. Battery Charger Command Summary
REGISTER ADDRESS 0x12H 0x14H 0x15H 0x3FH 0XFEH 0xFFH REGISTER NAME ChargeOption() ChargeCurrent() ChargeVoltage() InputCurrent() ManufacturerID() DeviceID() READ/WRITE Read or Write Read or Write Read or Write Read or Write Read Only Read Only DESCRIPTION Charger Options Control 7-Bit Charge Current Setting 11-Bit Charge Voltage Setting 6-Bit Input Current Setting Manufacturer ID Device ID POR STATE 0x7904H 0x0000H 0x0000H 0x1000H 0x0040H 0x0008H
16
bq24725
www.ti.com SLUS702A JULY 2010 REVISED NOVEMBER 2010
[14:13]
[12:11]
EMI Switching Frequency Adjust EMI Switching Frequency Enable IFAULT_HI Comparator Threshold Adjust
[6]
LEARN Enable
[0]
Charge Inhibit
17
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SLUS702A JULY 2010 REVISED NOVEMBER 2010 www.ti.com
18
bq24725
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(2)
where is the efficiency of the charger buck converter (typically 85% to 95%).
Copyright 2010, Texas Instruments Incorporated
19
bq24725
SLUS702A JULY 2010 REVISED NOVEMBER 2010 www.ti.com
To set the input current limit, write a 16-bit InputCurrent() command (0x3FH or 0b00111111) using the data format listed in Table 6. When using a 10m sense resistor, the bq24725 provides an input-current limit range of 128mA to 8.064A, with 128mA resolution. The suggested input current limit is set to no less than 512mA. Sending InputCurrent() below 128mA or above 8.064A clears the register and terminates charging. Upon POR, the default input current limit is 4096mA. The ACP and ACN pins are used to sense RAC with default value of 10m. However, resistors of other values can also be used. For a larger sense resistor, larger sense voltage is given, and a higher regulation accuracy; but, at the expense of higher conduction loss. If input current rises above 108% of input current limit set point, the charger will shut down immediately to allow the input current drop. After charging stops, the charger will soft restart to charge the battery if the adapter still has power left to charge the battery. This prevents a crash if the adapter is overloaded when the system has a high and fast loading transient. The waiting time between shut down and restart charging is a natural response time of the input current limit loop. Table 6. Input Current Register (0x3FH), Using 10m Sense Resistor
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BIT NAME Input Current, DACIIN 0 Input Current, DACIIN 1 Input Current, DACIIN 2 Input Current, DACIIN 3 Input Current, DACIIN 4 Input Current, DACIIN 5 DESCRIPTION Not used. Not used. Not used. Not used. Not used. Not used. Not used. 0 = Adds 0mA of input current. 1 = Adds 128mA of input current. 0 = Adds 0mA of input current. 1 = Adds 256mA of input current. 0 = Adds 0mA of input current. 1 = Adds 512mA of input current. 0 = Adds 0mA of input current. 1 = Adds 1024mA of input current. 0 = Adds 0mA of input current. 1 = Adds 2048mA of input current. 0 = Adds 0mA of input current. 1 = Adds 4096mA of input current. Not used. Not used. Not used.
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www.ti.com SLUS702A JULY 2010 REVISED NOVEMBER 2010
The rising edge delay default is 150ms after ACDET has a valid voltage to make ACOK pull high. The first time after IC POR always gives a 150ms ACOK rising edge delay no matter what the ChargeOption register value. To change this option, the VCC pin voltage must above UVLO, and the ACDET pin voltage must above 0.6V which enables the IC SMBus communication and sets ChargeOption() bit[15] to 1 which sets the ACOK rising deglitch time to be 1.3s. Only after the ACDET pin voltage is pulled below 2.4V (but not below 0.6V which will reset IC and force the ACOK rising edge deglitch time to be 150ms) and ACDRV has been turned off at least one time, the 1.3s delay time is effective for next time the ACDET pin voltage goes above 2.4V. The purpose of the option 1.3s rising edge deglitch time is to turn off the ACFET long enough when the ACDET pin is pulled below 2.4V by excessive system current, such as over current or short circuit.
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To limit the adapter inrush current when ACFET is turned on to power system from adapter, the Cgs and Cgd external capacitor of ACFET must be carefully selected. The larger the Cgs and Cgd capacitance, the slower turn on of ACFET will be and less inrush current of adapter. However, if Cgs or Cgd is too large, the ACDRV-CMSRC voltage may still go low after the 20ms turn on time window is expired. To make sure ACFET will not be turned on when adapter is hot plugged in, the Cgs value should be 20 times or higher than Cgd. The most cost effective way to reduce adapter in-rush current is to minimize system total capacitance.
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Charge Timeout
The bq24725 includes a watchdog timer to terminate charging if the charger does not receive a write ChargeVoltage() or write ChargeCurrent() command within 175s (adjustable via ChargeOption() command). If a watchdog timeout occurs all register values keep unchanged but charge is suspended. Write ChargeVoltage() or write ChargeCurrent() commands must be re-sent to reset watchdog timer and resume charging. The watchdog timer can be disabled, or set to 44s, 88s or 175s via SMBus command (ChargeOption() bit[14:13]). After watchdog timeout write ChargeOption() bit[14:13] to disable watchdog timer also resume charging.
Converter Operation
The synchronous buck PWM converter uses a fixed frequency voltage mode control scheme and internal type III compensation network. The LC output filter gives a characteristic resonant frequency 1 o = 2p Lo Co (3) The resonant frequency fo is used to determine the compensation to ensure there is sufficient phase margin and gain margin for the target bandwidth. The LC output filter should be selected to give a resonant frequency of 1020 kHz nominal for the best performance. Suggest component value as charge current of 750kHz default switching frequency is shown in Table 7. Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point. Table 7. Suggest Component Value as Charge Current of Default 750kHz Switching Frequency
Charge Current Output Inductor Lo (H) Output Capacitor Co (F) Sense Resistor (m) 2A 6.8 or 8.2 20 10 3A 5.6 or 6.8 20 10 4A 3.3 or 4.7 20 10 6A 3.3 30 10 8A 2.2 40 10
The bq24725 has three loops of regulation: input current, charge current and charge voltage. The three loops are brought together internally at the error amplifier. The maximum voltage of the three loops appears at the output of the error amplifier EAO. An internal saw-tooth ramp is compared to the internal error control signal EAO (see Figure 16) to vary the duty-cycle of the converter. The ramp has offset of 200mV in order to allow 0% duty-cycle. When the battery charge voltage approaches the input voltage, EAO signal is allowed to exceed the saw-tooth ramp peak in order to get a 100% duty-cycle. If voltage across BTST and PHASE pins falls below 4.3V, a refresh cycle starts and low-side n-channel power MOSFET is turned on to recharge the BTST capacitor. It can achieve duty cycle of up to 99.5%.
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working life. When the system is totally shutdown, it is not necessary to let the internal BATFET charge pump work. The host controller can use a digital signal EN to disconnect the battery power path to the VCC pin by U2 in Figure 1. As a result, battery quiescent current can be minimized. The host controller still can get power from BATFET body diode because the total system current is the lowest when the system is shutdown, so there is no high conduction loss of the body diode.
Inductor Selection
The bq24725 has three selectable fixed switching frequency. Higher switching frequency allows the use of smaller inductor and capacitor values. Inductor saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE): ISAT ICHG + (1/2) IRIPPLE (4) The inductor ripple current depends on input voltage (VIN), duty cycle (D = VOUT/VIN), switching frequency (fS) and inductance (L): V D (1 - D) IRIPPLE = IN fS L (5) The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging voltage range is from 9V to 12.6V for 3-cell battery pack. For 20V adapter voltage, 10V battery voltage gives the maximum inductor ripple current. Another example is 4-cell battery, the battery voltage range is from 12V to 16.8V, and 12V battery voltage gives the maximum inductor ripple current. Usually inductor ripple is designed in the range of (20-40%) maximum charging current as a trade-off between inductor size and efficiency for a practical design. The bq24725 has charge under current protection (UCP) by monitoring charging current sensing resistor cycleby-cycle. The typical cycle-by-cycle UCP threshold is 5mV falling edge corresponding to 0.5A falling edge for a 10m charging current sensing resistor. When the average charging current is less than 125mA for a 10m charging current sensing resistor, the low side MOSFET is off until BTST capacitor voltage needs to refresh the charge. As a result, the converter relies on low side MOSFET body diode for the inductor freewheeling current.
Input Capacitor
Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS current occurs where the duty cycle is closest to 50% and can be estimated by Equation 6:
ICIN = ICHG D (1 - D)
(6)
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage rating of the capacitor must be higher than normal input voltage level. 25V rating or higher capacitor is preferred for 19-20V input voltage. 10-20F capacitance is suggested for typical of 3-4A charging current. Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the input capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high input voltages and small capacitor packages. See the manufacturer's data sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point.
Output Capacitor
Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The output capacitor RMS current is given: I ICOUT = RIPPLE 0.29 IRIPPLE 2 3 (7)
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The bq24725 has internal loop compensator. To get good loop stability, the resonant frequency of the output inductor and output capacitor should be designed between 10 kHz and 20 kHz. The preferred ceramic capacitor is 25V X7R or X5R for output capacitor. 10-20F capacitance is suggested for a typical of 3-4A charging current. Place the capacitors after charging current sensing resistor to get the best charge current regulation accuracy. Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point.
The lower the FOM value, the lower the total power loss. Usually lower RDS(ON) has higher cost with the same package size. The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle (D=VOUT/VIN), charging current (ICHG), MOSFET's on-resistance (RDS(ON)), input voltage (VIN), switching frequency (fS), turn on time (ton) and turn off time (toff): 1 Ptop = D ICHG2 RDS(on) + VIN ICHG (t on + t off ) f s 2 (9) The first item represents the conduction loss. Usually MOSFET RDS(ON) increases by 50% with 100C junction temperature rise. The second term represents the switching loss. The MOSFET turn-on and turn-off times are given by: Q Q t on = SW , t off = SW Ion Ioff (10) where Qsw is the switching charge, Ion is the turn-on gate driving current and Ioff is the turn-off gate driving current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge (QGD) and gate-to-source charge (QGS): 1 QSW = QGD + QGS 2 (11) Gate driving current can be estimated by REGN voltage (VREGN), MOSFET plateau voltage (Vplt), total turn-on gate resistance (Ron) and turn-off gate resistance (Roff) of the gate driver: VREGN - Vplt Vplt Ion = , Ioff = Ron Roff (12) The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in synchronous continuous conduction mode:
Pbottom = (1 - D) x ICHG 2 x RDS(on) (13)
When charger operates in non-synchronous mode, the bottom-side MOSFET is off. As a result all the freewheeling current goes through the body-diode of the bottom-side MOSFET. The body diode power loss depends on its forward voltage drop (VF), non-synchronous mode charging current (INONSYNC), and duty cycle (D).
PD = VF x INONSYNC x (1 - D) (14)
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The maximum charging current in non-synchronous mode can be up to 0.25A for a 10m charging current sensing resistor or 0.5A if battery voltage is below 2.5V. The minimum duty cycle happens at lowest battery voltage. Choose the bottom-side MOSFET with either an internal Schottky or body diode capable of carrying the maximum non-synchronous mode charging current.
Adapter connector
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Adapter ACP SCP1 REGN COMP1 COMP2 SCP2 RAC ACN R PCB BTST High-Side MOSFET PHASE L Low-Side MOSFET RDC C Battery
Adapter Plug in
Count to 7 CLR
Figure 21. Block Diagram of bq24725 Short Circuit Protection In normal operation, the low side MOSFET current is from source to drain which generates a negative voltage drop when it turns on, as a result the over current comparator can not be triggered. When the high side switch short circuit or inductor short circuit happens, the large current of low side MOSFET is from drain to source and can trig low side switch over current comparator. bq24725 senses the low side switch voltage drop through the PHASE pin and GND pin. The high-side FET short is detected by monitoring the voltage drop between ACP and PHASE. As a result, it not only monitors the high side switch voltage drop, but also the adapter sensing resistor voltage drop and PCB trace voltage drop from ACN terminal of RAC to charger high side switch drain. Usually, there is a long trance between input sensing resistor and charger converting input, a careful layout will minimize the trace effect. To prevent unintentional charger shut down in normal operation, MOSFET RDS(on) selection and PCB layout is very important. Figure 22 shows a improvement PCB layout example and its equivalent circuit. In this layout, the system current path and charger input current path is not separated, as a result, the system current causes voltage drop in the PCB copper and is sensed by the IC. The worst layout is when a system current pull point is after charger input; as a result all system current voltage drops are counted into over current protection comparator. The worst case for IC is when the total system current and charger input current sum equals the DPM current. When the system pulls more current, the charger IC tries to regulate the RAC current as a constant current by reducing the charging current.
I DPM
R AC System Path PCB Trace System current
R AC ACP ACN
R PCB
To ACP
To ACN
Figure 22. Need improve PCB layout example. Figure 23 shows the optimized PCB layout example. The system current path and charge input current path is separated, as a result the IC only senses charger input current caused PCB voltage drop and minimized the possibility of unintentional charger shut down in normal operation. This also makes PCB layout easier for high system current application.
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R AC System Path PCB Trace System current
I DPM
R AC ACP
To ACP
To ACN
Figure 23. Optimized PCB layout example. The total voltage drop sensed by IC can be express as the following equation.
Vtop = RAC x IDPM + RPCB x (ICHRGIN + (IDPM - ICHRGIN) x k) + RDS(on) x IPEAK (15)
where the RAC is the AC adapter current sensing resistance, IDPM is the DPM current set point, RPCB is the PCB trace equivalent resistance, ICHRGIN is the charger input current, k is the PCB factor, RDS(on) is the high side MOSFET turn on resistance and IPEAK is the peak current of inductor. Here the PCB factor k equals 0 means the best layout shown in Figure 23 where the PCB trace only goes through charger input current while k equals 1 means the worst layout shown in Figure 22 where the PCB trace goes through all the DPM current. The total voltage drop must below the high side short circuit protection threshold to prevent unintentional charger shut down in normal operation. The low side MOSFET short circuit voltage drop threshold is fixed to typical 110mV. The high side MOSFET short circuit voltage drop threshold can be adjusted via the SMBus command. ChargeOption() bit[8:7] = 00, 01, 10, 11 sets the threshold at 300mV, 500mV, 700mV and 900mV respectively. For a fixed PCB layout, the host should set the proper short circuit protection threshold level to prevent unintentional charger shut down in normal operation.
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PCB Layout
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize high frequency current path loop (see Figure 24) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB according to this specific order is essential. 1. Place input capacitor as close as possible to switching MOSFETs supply and ground connections and use shortest copper trace connection. These parts should be placed on the same layer of PCB instead of on different layers and using vias to make this connection. 2. The IC should be placed close to the switching MOSFETs gate terminals and keep the gate drive signal traces short for a clean MOSFET drive. The IC can be placed on the other side of the PCB of switching MOSFETs. 3. Place inductor input terminal to switching MOSFETs output terminal as close as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane. 4. The charging current sensing resistor should be placed right next to the inductor output. Route the sense leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop area) and do not route the sense leads through a high-current path (see Figure 25 for Kelvin connection for best current accuracy). Place decoupling capacitor on these traces next to the IC 5. Place output capacitor next to the sensing resistor output and ground 6. Output capacitor ground connections need to be tied to the same copper that connects to the input capacitor ground before connecting to system ground. 7. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC use analog ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling 8. Route analog ground separately from power ground. Connect analog ground and connect power ground separately. Connect analog ground and power ground together using power pad as the single ground connection point. Or using a 0 resistor to tie analog ground to power ground (power pad should tie to analog ground in this case if possible). 9. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible 10. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers. 11. The via size and number should be enough for a given current path. See the EVM design for the recommended component placement with trace and via locations. For the QFN information, See SCBA017 and SLUA271.
L1
R1
VBAT
VIN C1
BAT GND C2
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REVISION HISTORY
Changes from Original (July 2010) to Revision A Page
Changed the Functional Block Diagrams, Figure 1 and Figure 2 ......................................................................................... 2 Updated the Test Conditions for QUIESCENT CURRENT .................................................................................................. 6 Updated the description for the SRN and SRP pins ........................................................................................................... 12 Deleted C12, added R14 and R15 in Table 8 .................................................................................................................... 25 Added section: Negative Output Voltage Protection .......................................................................................................... 26
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PACKAGING INFORMATION
Orderable Device BQ24725RGRR BQ24725RGRT Status
(1)
Package Type Package Pins Package Drawing Qty VQFN VQFN RGR RGR 20 20 3000 250
Eco Plan
(2)
Top-Side Markings
(4)
Samples
NRND NRND
BQ725 BQ725
(1)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Device
Package Package Pins Type Drawing VQFN VQFN VQFN VQFN RGR RGR RGR RGR 20 20 20 20
SPQ
Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 330.0 180.0 180.0 12.4 12.4 12.4 12.4 3.75 3.75 3.75 3.75
Pack Materials-Page 1
Pins 20 20 20 20
Pack Materials-Page 2
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