Pen Tek Catalog

Last Updated: December 2013
PRODUCT CATALOG
Company Profile
Founded in 1986, Pentek has become the premier source for high-speed real-time recording systems, DSP (Digital Signal Processing), SDR (Software-Defined Radio), and data acquisition products. Our customers enjoy our ISO 9001:2008 certification and the performance and flexibility afforded by our board- and system-level commercial and ruggedized product lines and our world-class applications support. Pentek is the leading board and system manufacturer offering COTS and ruggedized products in formats such as VME, VXS, OpenVPX, PMC/XMC, PCI Express, AMC, CompactPCI, and PCI, featuring Freescale PowerPCs and the latest Xilinx Virtex FPGAs. Penteks data acquisition line is extensive and includes A/Ds, D/As, Digital Receivers/ Transmitters, Digital I/O and much more. Pentek equips its products with high-speed interfaces including Fibre Channel, Serial RapidIO and others. No other embedded vendor can provide such seasoned, in-depth technical expertise in data acquisition, digital signal processing and software-defined radio. Penteks mission is to provide the embedded community with leading edge board- and system-level solutions for the most demanding requirements in data acquisition, digital signal processing and software radio applications through excellence and innovation. We support an aggressive new product development cycle to meet market demands as we design the next generation of embedded DSP products. We consistently invest more than 15% of revenues in product development, engineering and applications support. We will help you solve the most challenging DSP problems through our dedicated staff of systems engineers who are trained to provide the answers to your hardware, software or applications questions. We recognize todays time-to-market pressures and budget constraints on development resources and we offer low-risk, easy-to-use embedded solutions. You can select from a variety of recording systems and the industrys most extensive line of advanced analog and digital I/O products, along with exclusive development tools that help you create a custom system. Many of these products include Xilinx Virtex FPGAs for customized signal processing.
Mission Statement Pentek Strategies
Product Overview
High-Speed Real-Time Recording Systems

Economical Fully
alternatives to in-house development tested and ready to run right out-of-the-box Easy to use with full-featured software installed
Processor Engines
Processor Xilinx Single
boards with Freescale PowerPC engines Virtex FPGAs
Data Acquisition
or multichannel A/Ds and D/As rates to 3.6 GHz Resolution to 24 bits
Sampling
Software Radio
to 512 channels per slot wide- and multi-band versions Downconverters and upconverters For more information about us, please visit: http://pentek.com/about/about.cfm?HID2=TM
Narrow-, Up
Pentek takes pride in listening to its customers and creating new products to meet their needs. We promise an atmosphere of freedom and creativity among our engineers, so they can design industry-leading products to satisfy the most demanding applications. This has been the key to our success through the years. Rodger Hosking, Vice President and Cofounder
Penteks 88,000 sq. ft. facility in Upper Saddle River, NJ
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
PRODUCT CATALOG CONTENTS

RAD AR & SDR I/O RADAR
RAD AR & SDR I/O - PMC/XMC RADAR RAD AR & SDR I/O - 3U & 6U CompactPCI RADAR RAD AR & SDR I/O - PCI RADAR RAD AR & SDR I/O - x8 PCI Express RADAR RAD AR & SDR I/O - 3U VPX - FORMA T 1 RADAR FORMAT RAD AR & SDR I/O - AMC RADAR RAD AR & SDR I/O - 3U VPX - FORMA T 2 RADAR FORMAT
ANALOG & DIGIT AL I/O DIGITAL PROCESSORS HIGH-SPEED RECORDING SYSTEMS CLOCK & SYNC GENERA TORS GENERATORS SOF TW ARE & FPGA TOOLS SOFTW TWARE
Last updated: December 2013

www.pentek.com
RAD AR & SDR I/O - PMC/XMC RADAR

MODEL
7150 7151 7152 7153 7156 7158 Cobalt 71620 Cobalt 71621 Cobalt 71630 Cobalt 71640 Cobalt 71641 Cobalt 71650 Cobalt 71651 Cobalt 71660 Cobalt 71661 Cobalt 71662 Cobalt 71670 Cobalt 71671 Cobalt 71690 Onyx 71720 Onyx 71760 Onyx 71730
DESCRIPTION
Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - PMC/XMC 256-Channel DDC with four 200 MHz, 16-bit A/Ds - PMC 32-Channel DDC with four 200 MHz, 16-bit A/Ds - PMC 4/2-Channel DDC, four 200 MHz 16-bit A/Ds, Beamformer - PMC/XMC Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC 3-Channel 200 MHz A/D, 2-Channel 800 MHz D/A, Virtex-6 FPGA - XMC 3-Channel 200 MHz A/D with DDC, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - XMC 1 GHz A/D and D/A, Virtex-6 FPGA - XMC 1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D, Virtex-6 FPGA - XMC 1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D, Wideband DDC, Virtex-6 FPGA - XMC Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - XMC 2-Chan 500 MHz A/D with DDC, DUC with 2-Chan 800 MHz D/A, Virtex-6 FPGA - XMC 4-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - XMC 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - XMC 4-Channel 200 MHz A/D with 32-Channel DDC and Virtex-6 FPGA - XMC 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - XMC 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - XMC L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - XMC 3-Channel 200 MHz A/D with DDC, DUC, 2-Channel 800 MHz D/A, Virtex-7 FPGA - XMC 4-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - XMC 1 GHz A/D and D/A, Virtex-7 FPGA - XMC Customer Information
RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR
& & & & & &
SDR SDR SDR SDR SDR SDR
I/O I/O I/O I/O I/O I/O
CompactPCI PCI x 8 PCI Express 3U VPX - FORMA T 1 FORMAT AMC 3U VPX - FORMA T 2 FORMAT
Last updated: November 2013

www.pentek.com
Model 7150
Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - PMC/XMC

General Information
Model 7150 is a quad, high-speed data converter suitable for connection as the HF or IF input of a communications system. It features four 200 MHz, 16-bit A/Ds supported by an array of data processing and transport resources ideally matched to the requirements of high-performance systems. Model 7150 uses the popular PMC format and supports the emerging VITA 42 XMC standard for switched-fabric interfaces. DDR2 SDRAM memory, interface FPGA, programmable LVPECL I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T and FX100T. The SXT parts feature between 288 and 640 DSP48E Slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the Model 7150 can be optionally configured with an LX155T in the processing FPGA position for 155,648 logic cells. A second Virtex-5 FPGA provides board interfaces including PCI-X or PCI Express. Implementing the PCI interfaces in this second FPGA, keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT or an SXT family part, providing not only interface functionality, but processing resources up to an additional 640 DSP48E Slices. Option -104 installs the P4 PMC connector with 16 pairs of LVDS connections to the processing FPGA and 16 pairs of LVDS connections to the interface FPGA for custom I/O.
A/D Converter Stage

The front end accepts four full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-5 FPGA for signal processing or for routing to other module resources.
Virtex-5 FPGAs
The Model 7150 architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factoryshipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the A/D converters,
Features

Complete software radio interface solution VITA 42.0 XMC compatible with switched fabric interfaces Four 200 MHz 16-bit A/Ds Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Up to 2.56 seconds of data capture at 200 MHz LVPECL clock/sync bus for multimodule synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
Clocking and Synchronization

The Model 7150 architecture includes a flexible timing and synchronization circuit that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus.
RF In
RF XFORMR Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF In
RF XFORMR
RF In
RF XFORMR
RF In
RF XFORMR
Clock/Sync Bus
TTL In
200 MHz 16 bit A/D
200 MHz 16 b t A/D
200 MHz 16 bit A/D
200 MHz 16 bit A/D
LVPECL Bus
XTL OSC To All Sections Control/ PROCESSING FPGA VIRTEX 5 LX50T, SX50T, SX95T, LX155T or FX100T
LVDS GTP GTP GTP
Timing Bus
Status
32 DDR2 SDRAM 512 MB
8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T

LVDS PCI X GTP
4X
GTP
4X
4X
PMC P4 FPGA I/O (Option -104)
32
32
PCI-X BUS (64 Bits, 100 MHz)
64
4X
P15 XMC VITA 42.x (Option -5xx)
Pentek, Inc.
www.pentek.com
Model 7150

The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to three slave 7150s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. More modules can be synchronized with an external clock and sync generator.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VLX155T and XC5VFX100T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs P4 connector with 16 LVDS pairs to the processing FPGA and 16 pairs to the interface FPGA Memory DDR2 SDRAM: Up to 1 GB in two banks PCI Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard PMC module, 2.91 in. x 5.87 in.
XMC Interface
The Model 7150 complies with the VITA 42.0 XMC specification for carrier boards. This emerging standard provides serial data links with up to 3.125 GHz bit clock between the XMC module and the carrier board. With two 4X links, the 7150 achieves up to 2.5 GB/sec streaming data transfer rate independent of the PCI interface and supports switched fabric protocols such as Serial RapidIO and PCI Express.
Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGA. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering. Each memory bank can be easily accessed through the PCI interface using the on-board DMA controllers. Custom user-installed functions within the FPGA can take advantage of the SDRAM for many other purposes.
PCI-X Interface
The Model 7150 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the module. Data widths of 32 or 64 bits and data rates of 33, 66, 100 MHz are supported.
Optional PCI Express Interface

For systems that require a PCI Express board interface, the Model 7150 can be optionally factory-configured with x4 PCI Express in the interface FPGA. Other serial protocols as well as different bus widths can be accommodated with custom IP cores.
Ordering Information
Model 7150 Description Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs PMC/XMC
Options: -104 FPGA I/O through the P4 connector -5xx XMC interface
Contact Pentek for additional available options.
Pentek, Inc.
www.pentek.com
Model 7151
256-Channel DDC with four 200 MHz, 16-bit A/Ds - PMC

General Information
Model 7151 is a 4-channel, high-speed software radio module designed for processing baseband RF or IF signals from a communications receiver. It features four 200 MHz 16-bit A/Ds supported by a highperformance 256-channel installed DDC (digital downconverter) IP Core and interfaces ideally matched to the requirements of real-time software radio and radar systems. Model 7151 uses the industry standard PMC daughtercard format compatible with numerous carrier boards for VME, PCI, and CompactPCI.
Decimation and Filtering

All of the 64 channels within a bank share a common decimation setting that can range from 128 to 1024, programmable in steps of 64. For example, with a sampling rate of 200 MHz, the available output bandwidths range from 156.25 kHz to 1.25 MHz. Each 64-channel bank can have its own unique decimation setting supporting as many as four different output bandwidths for the board. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N. Any number of channels can be enabled with each bank, selectable from 0 to 64. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within the bank.
A/D Converter Stage Features

256 channels of DDC Four 200 MHz 16-bit A/Ds Independent tuning for each channel DDC decimation from 128 to 1024 in steps of 64 Independent decimation for each bank Each bank independently selects one of four A/Ds User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multimodule synchronization
The front end accepts four full-scale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing operations.
DDC Input Selection and Tuning

The Model 7151 employs an advanced FPGA-based digital downconverter engine consisting of four identical 64-channel DDC banks. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC bank. In this way, many different configurations can be achieved including one A/D driving all 256 DDC channels and each of the four A/Ds driving its own DDC bank. Each of the 256 DDCs has an independent 32-bit tuning frequency setting that ranges from DC to s where s is the A/D sample rate.
Output Multiplexers and FIFOs

Four output MUXs can be independently switched to deliver either A/D data or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D data or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI-X bus.
CH 1 RF In
RF XFORMR
200 MHz 16-bit A/D
CH 2 RF In
RF XFORMR
200 MHz 16-bit A/D
CH 1 CH 2 CH 3 CH 4
M U X DIGITAL DOWNCONVERTER BANK 1: CH 1-64 DEC: 128 - 1024
CH 1 I+Q
M U X
FIFO 1
CH 3 RF In
RF XFORMR
200 MHz 16-bit A/D
CH 1 CH 2 CH 4 RF In
RF XFORMR 200 MHz 16-bit A/D
CH 2
CH 3 CH 4
I+Q
M U X
FIFO 2
PCI-X BUS Sample Clock In PPS In TTL In LVPECL Bus Timing Bus Clock / Sync / Gate / PPS CH 1 CH 2 XTAL OSC CH 3 CH 4
CH 1 TIMING BUS GENERATOR CH 2 CH 3 CH 4

CH 3 I+Q
M U X
FIFO 3
PCI-X INTERFACE Xilinx XC5VLX30T
CH 4 I+Q
M U X
FIFO 4
XILINX XC5VSX95T
Pentek, Inc.
www.pentek.com
Model 7151

The Model 7151 architecture includes a flexible timing and synchronization circuit that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to three slave 7151s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. More modules can be synchronized with an external clock and sync generator.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, and XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface in the standard unit; optional FPGA: XC5VSX50T PCI Interface PCI-X Bus: 64-bits, 133 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Environmental Operating Temp: Standard: 0 to 50 C L2 Extended Temp (Option -702): 20 to 65 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard PMC module, 2.91 in. x 5.87 in.
PCI-X Interface
The Model 7151 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the module. Data widths of 32 or 64 bits and data rates of 33, 66 and 133 MHz are supported.
Model 7151 Description 256-Channel DDC with four 200 MHz, 16-bit A/Ds - PMC
Options: -702 L2 Extended temperature operation -730 Two-slot heat sink
Pentek, Inc.
www.pentek.com
Model 7152

General Information
Model 7152 is a 4-channel, high-speed software radio module designed for processing baseband RF or IF signals from a communications receiver. It features four 200 MHz 16-bit A/Ds supported by a highperformance 32-channel installed DDC (digital downconverter) IP Core and interfaces ideally matched to the requirements of real-time software radio and radar systems. Model 7152 uses the industry standard PMC daughtercard format compatible with numerous carrier boards for VME, PCI, and CompactPCI.

Features

32 channels of DDC in four banks of 8 channels Four 200 MHz, 16-bit A/Ds Independent 32-bit DDC tuning for all 32 channels DDC decimation from 16 to 8192 in steps of 8 Bandwidths from 20 kHz to 10 MHz Common decimation factor within each DDC bank Different decimation factors between banks User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection Power meters and threshold detectors LVPECL clock/sync bus for multimodule synchronization
A/D Converter Stage


Power Meters and Threshold Detectors

The 7152 features 32 power meters that continuously measure the individual average power output of each of the 32 DDC channels. The time constant of the averaging interval for each meter is programmable up to 16K samples. In addition, 32 threshold detectors automatically send an interrupt to the processor if the average power level of any DDC falls below or exceeds a programmable threshold.
CH 1 RF In
RF XFORMR
200 MHz 16-bit A/D

8X4 CHANNEL SUMMATION M U X DIGITAL DOWNCONVERTER BANK 1: CH 1-8 DEC: 16 - 8192
CH 1 I+Q
M U X F I F 0 1 F I F 0 2
CH 2 RF In
RF XFORMR
200 MHz 16-bit A/D
CH 1 CH 2 CH 3 CH 4 I+Q
POWER METER & THRESHOLD DETECTORS
CH 3 RF In
RF XFORMR
200 MHz 16-bit A/D
CH 2
M U X
CH 3 CH 4
M U X
DIGITAL DOWNCONVERTER BANK 2: CH 9-16 DEC: 16 - 8192
I+Q
PCI-X BUS CH 3
M U X F I F 0 3 F I F 0 4
Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
CH 1 CH 2 CH 3 CH 4
I+Q
PCI-X INTERFACE Xilinx XC5VLX30T
TTL In
CH 1 CH 2 CH 3 CH 4
CH 4
M U X
LVPECL Bus
I+Q
XTAL OSC
Timing Bus
XILINX XC5VSX95T
Pentek, Inc.
www.pentek.com
Model 7152

Four output MUXs can be independently switched to deliver either A/D data or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D data or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input rate and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI-X bus.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, and XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface in the standard unit; optional FPGA: XC5VSX50T PCI Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard PMC module, 2.91 in. x 5.87 in.

The Model 7152 architecture includes a flexible timing and synchronization circuit that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to three slave 7152s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. For larger systems, many more modules can be synchronized with an external clock and sync generator.
PCI-X Interface
The Model 7152 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the module. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.
Model 7152 Description 32-Channel DDC with four 200 MHz, 16-bit A/Ds - PMC
Options: -730 Two-slot heat sink
Pentek, Inc.
www.pentek.com
Model 7153
4/2-Ch. DDC, four 200 MHz 16-bit A/Ds, Beamformer - PMC/XMC

General Information
Model 7153 is a 4-channel, high-speed software radio module designed for processing baseband RF or IF signals. It features four 200 MHz 16-bit A/Ds supported by a high-performance 4-channel DDC (digital downconverter) and a complete set of beamforming functions. With built-in multiboard synchronization, it is ideally matched to the requirements of real-time software radio and radar systems. Model 7153 uses the industry standard PMC daughtercard format compatible with numerous carrier boards for VME, PCI, and CompactPCI. Each of the DDC channels has an independent 32-bit tuning frequency setting that ranges from DC to s where s is the A/D sampling frequency.

Each of the four DDC channels can have its own unique decimation setting, supporting as many as four different output bandwidths for the board. The DDC core can be configured in four-channel mode with each channel offering decimations between 2 and 256, or in two-channel mode with each channel having a decimation range of 2 to 65536, for applications that require a wider range of decimations. The decimating filter for each DDC channel accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N.
Built-in Beamformer supports multiboard systems Programmable Power Meter and Threshold Detect per channel Four 200 MHz, 16-bit A/Ds 2 or 4 Channels of DDC Independent 32-bit DDC tuning for all channels DDC decimation range from 2 to 256 or from 2 to 65536 Independent decimation factors for each channel Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multimodule synchronization
The front end accepts four full scale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling to four Texas Instruments ADS5485 200 MHz, 16-bit A/Ds. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing operations.

The Model 7153 employs an advanced FPGA-based digital downconverter engine consisting of two or four DDC channels. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC channel. In this way, many different configurations can be achieved including one A/D driving all four DDC channels and each of the four A/Ds driving its own DDC bank.
Power Meters
Each DDC includes a power meter that continuously measures the individual average power output. The power meters calculate and present average power measurements for each channel in easy-to-read registers. The time constant of the averaging interval for each meter is programmable up to 8 kilosamples. Threshold detectors can generate interrupts when the calculated power levels exceed or fall below user-programmable thresholds, ideal for scanning and monitoring applications.
SUM IN SUM OUT 4X 4X P15 XMC
F I F 0 1 F I F 0 2
CH 1 RF In
RF XFORMR
200 MHz 16-bit A/D
CH 1 CH 2 CH 3 CH 4 CH 1 CH 2 CH 3 CH 4
M U X SUMMER
AURORA G GAB T SERIAL INTERFACE
CH 2 RF In
RF XFORMR
200 MHz 16-bit A/D
I+Q CH 1
M U X
CH 3 RF In
RF XFORMR
200 MHz 16-bit A/D
D G TAL DOWNCONVERTER CH 1 DEC: 2 - 65536 (DEC: 2 - 256)*
I+Q
CH 4 RF In
RF XFORMR
200 MHz 16-bit A/D
CH 1 CH 2 CH 3 CH 4
M U X
CH 2
M U X
I+Q
PCI-X BUS CH 3
M U X F I F 0 3 F I F 0 4
Sample Clock In PPS In TTL In LVDS Bus Timing Bus
CH 1 TIM NG BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 XTAL OSC CH 3 CH 4

M U X D G TAL DOWNCONVERTER CH 4 (DEC: 2 - 256)*
CH 2 CH 3 CH 4
M U X
D G TAL DOWNCONVERTER CH 3 (DEC: 2 - 256)*
I+Q
PCI-X NTERFACE
XILINX XC5VLX30T
CH 4
M U X
I+Q
*2 Channel Mode: Dec 2-65536, 4 Channel Mode: Dec 2-256
XILINX XC5VSX95T
Pentek, Inc.
www.pentek.com
Model 7153

Beamformer
In addition to the A/Ds and DDCs, the 7153 includes essential resources of a complete beamforming subsystem. First, each DDC channel provides user-programmable I & Q phase and gain adjustments to apply beamforming weights. Then, a summation block adds the four DDC output channels. An additional programmable-gain stage compensates for summation bit growth. A power meter and threshold detect block is provided for the sum output. The sum output is then delivered to the Channel 1 FIFO for delivery through the PCI-X bus. For larger systems, multiple 7153s can be chained together using a built-in Xilinx Aurora engine. It accepts an x4 gigabit sum input stream from a previous board and propagates an x4 sum output stream to the next board through the P15 XMC connector.

The Model 7153 architecture includes a flexible timing and synchronization circuit that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven from the internal crystal oscillator, a front panel reference or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to three slave 7153s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. More modules may be synchronized with an external clock and sync generator.
XMC Interface
The Model 7153 complies with the VITA 42.0 XMC specification. This standard provides serial data links between the XMC module and the carrier board. The 7153 beamformer architecture uses this link to create a board-to-board summation expansion chain for creating larger multichannel beamformer systems. Xilinxs Aurora protocol is used to provide an efficient x4, 1.25 GB/sec point-to-point data path between boards.

Four output MUXs can be independently switched to deliver either A/D or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input and output rate to support different DDC decimation settings between the channels and to enable efficient block transfers to the PCI-X bus.
PCI-X Interface
The Model 7153 includes an industrystandard PCI-X interface. The interface includes four separate DMA controllers for efficient transfers to and from the module. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.
PHASE SHIFT
DECIMAT ON: 2-65536 (DECIMATION: 2-256)*
GAIN
I Q
I Q
I
Q
I
Q
DIG TAL DOWNCONVERTER A
Weigh Phase I Weight Phase Q Weight Gain PHASE SHIFT
POWER METER & THRESHO D DETECT A
AURORA PORT
SUMMAT ON EXPANSION CHAIN IN 1 25 GByte/sec x4 Au ora Link
F om P evious Board
P15
GAIN
I
Q
I
Q
I
Q
I
Q
DIG TAL DOWNCONVERTER B
POWER METER & THRESHO D DETECT B
SUMMAT ON CHAIN BIT GROWTH COMPENSAT ON
I Q
I Q
I Q
To FIFO 1 (Final Result or Intermediate Result
GAIN
(DECIMATION: 2-256)*
I Q
I Q
I
Q
I
Q
Summation Chain Gain POWER METER & THRESHO D DETECT C
SUMMATION POWER METER & THRESHO D DETECT
DIG TAL DOWNCONVERTER C
AURORA PORT
SUMMAT ON EXPANS ON CHAIN OUT 1 25 GByte/sec x4 Au ora Link
To Next Boa d
GAIN
P15 I Q
I Q
I Q
I Q
DIG TAL DOWNCONVERTER D
Weigh Phase I Weight Phase Q Weight Gain
POWER METER & THRESHO D DETECT D
BEAMFORMER DATA FLOW DETAIL
Pentek, Inc.
www.pentek.com
Model 7153

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillator, external reference or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC-coupled 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS, input/output LVPECL bus; one gate/trigger and one sync/PPS input TTL signal Digital Downconverter Type: IP core for Xilinx Virtex-5 Qty of DDC Channels: 2 or 4 Center Frequency Tuning: 4 tuning words, one for each DDC channel Center Frequency Tuning Range: DC to s with 32 bit resolution NCO SFDR: 120 dBFS Channel Phase Offset Adjustment: 32-bit resolution Channel Gain Adjustment: 32-bit resolution Input Selection for DDC Banks: Any channel can select any of the four A/Ds Decimation Range (N): 2-Channel Mode: 2 to 65536 4-Channel Mode: 2 to 256 FIR Filter: Default passband 0.8*s/N with 0.2 dB passband ripple and 100 dB adjacent channel rejection FIR Filter Coefficients: 18 bits, userprogrammable (default values provided) Qty FIR Filter Taps: 28*N/8 Output Format: 24 bits I + 24 bits Q Output Spectrum Modes: Normal or frequency-reversed Output Spectrum Offset: No offset or offset by one-half the output bandwidth Beamformer Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Output Multiplexer and FIFO Qty Output FIFOs: Four FIFO Source Selection: Independent multiplexer selects DDC output or A/D PCI Interface Type: IP core in Xilinx FPGA PCI-X Bus: 64 bits, 100 MHz and 64 or 32 bits at 33 or 66 MHz DMA: 4-channel demand mode and chaining controller Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard PMC module, 2.91 in. x 5.87 in.
Model 7153 Description 4-Channel DDC with four 200 MHz, 16-bit A/Ds and Beamformer - PMC/XMC
Contact Pentek for available options.
Pentek, Inc.
www.pentek.com
Model 7156
Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC
General Information
Model 7156 is a dual-channel, highspeed data converter suitable for connection to HF or IF ports of a communications system. It includes two A/D and two D/A converters, two Virtex-5 FPGAs and two banks of DDR2 SDRAM. The Model 7156 uses the popular PMC format and supports the VITA 42 XMC standard for switched fabric interfaces.
Virtex-5 FPGAs
The Model 7156 architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family part, providing not only interface
RF In
RF XFORMR
A/D Converter Stage

The front end accepts two full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into TI ADS5474 14-bit 400 MHz A/Ds. Designed with a 750 MHz input bandwidth, the A/Ds are excellent for undersampling applications. The digital outputs are delivered into the Virtex-5 processing FPGA for signal processing, data capture or routing to other module resources.
Digital Upconverter and D/A Stage

A TI DAC5688 digital upconverter (DUC) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as an upconverter, it interpolates and translates real or complex baseband input signals to any IF center frequency between DC and 300 MHz. It delivers real or quadrature (I+Q) outputs at up to 500 MHz to the 16-bit D/A converter. Analog output is through a pair of front panel SMC connectors at +4 dBm into 50 ohms. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x.
Features

Complete software radio interface solution Two 400 MHz, 14-bit A/Ds One digital upconverter Two 800 MHz, 16-bit D/As Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization VITA 42.0 XMC compatible with switched fabric interfaces 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O on P14
RF In
RF XFORMR
RF Out
RF XFORMR
RF Out
RF XFORMR
Sample Clk / Reference Clk In PPS In
TIMING BUS GENERATOR Clock / Sync / Gate / PPS
A/D Clock Bus
400 MHz 14 BIT A/D
400 MHz 14 BIT A/D
800 MHz 16 BIT D/A
800 MHz 16 BIT D/A
TTL Gate / Tr g TTL Sync / PPS Sample Clk Sync Clk Gate A Gate B Sync PPS
DIGITAL UPCONVERTER
D/A Clock Bus

14 To All Sections 14 32
Timing Bus
VCXO
Control/ Status
PROCESSING FPGA VIRTEX 5 LX50T, LX155T, SX50T, SX95T or FX100T

LVDS GTP GTP GTP
8 64 FLASH 32 MB 4X
GTP
4X
4X
INTERFACE FPGA VIRTEX 5 LX30T, SX50T or FX70T

LVDS PCI X GTP
P14 PMC FPGA I/O
32
32
64
4X
P15 XMC VITA 42.x (PCIe, etc.)
Pentek, Inc.
www.pentek.com
Model 7156
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 adds the P14 PMC connector with 16 pairs of LVDS connections to each FPGA for custom I/O.
Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 400 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs the P14 connector with 16 LVDS pairs to the processing FPGA and 16 pairs to the interface FPGA mapped as two 16-bit read/write registers Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard PMC module, 2.91 in. x 5.87 in.
XMC Interface
The Model 7156 complies with the VITA 42.0 XMC specification for carrier boards. This standard provides, among others, for a 4X link with a 3.125 GHz bit clock between the XMC module and the carrier board. With two 4X links, the 7156 achieves 2.5 GB/sec streaming data transfer rate independent of the PCI interface and supports switched fabric protocols such as Serial RapidIO and PCI Express.

Two internal timing buses can provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An internal clock generator receives an external sample clock from the front panel SMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage controlled crystal oscillator. In this mode, the front panel SMC connector can be used to provide a 10 MHz system reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to three slave 7156s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGA. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.
PCI-X Interface Ordering Information

Model 7156 Description Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC
The Model 7156 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the module. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB
Pentek, Inc.
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Model 7158
General Information
Model 7158 is a dual-channel, highspeed data converter suitable for connection to HF or IF ports of a communications system. It includes two A/D and two D/A converters, two Virtex-5 FPGAs and two banks of DDR2 SDRAM. The Model 7158 uses the popular PMC format and supports the VITA 42 XMC standard for switched fabric interfaces.
Virtex-5 FPGAs
RF In
RF XFORMR
A/D Converter Stage

The front end accepts two full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into TI ADS5463 12-bit 500 MHz A/Ds. Designed with a 750 MHz input bandwidth, the A/Ds are excellent for undersampling applications. The digital outputs are delivered into the Virtex-5 processing FPGA for signal processing, data capture or routing to other module resources.

Features

Complete software radio interface solution Two 500 MHz, 12-bit A/Ds One digital upconverter Two 800 MHz, 16-bit D/As Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization VITA 42.0 XMC compatible with switched fabric interfaces 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O on P14
RF In
RF XFORMR
RF Out
RF XFORMR
RF Out
RF XFORMR
A/D Clock Bus
500 MHz 12 BIT A/D
500 MHz 12 BIT A/D
800 MHz 16 BIT D/A
800 MHz 16 BIT D/A
TTL Gate / Trig TTL Sync / PPS Sample C k Sync Clk Gate A Gate B Sync PPS
DIGITAL UPCONVERTER
D/A Clock Bus

14 To A l Sections 14 32
Timing Bus
VCXO
Control/ Status
PROCESSING FPGA VIRTEX 5 LX50T, LX155T, SX50T, SX95T or FX100T

LVDS GTP GTP GTP
8 64 FLASH 32 MB 4X
GTP
4X
4X
INTERFACE FPGA VIRTEX 5 LX30T, SX50T or FX70T

LVDS PCI X GTP
P14 PMC FPGA I/O
32
32
64
4X
P15 XMC VITA 42.x (PCIe, etc.)
Pentek, Inc.
www.pentek.com
Model 7158
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 adds the P14 PMC connector with 16 pairs of LVDS connections to each FPGA for custom I/O.
Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits D/A Converters Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 20 to 500 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs the P14 connector with 16 LVDS pairs to the processing FPGA and 16 pairs to the interface FPGA mapped as two 16-bit read/write registers Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard PMC module, 2.91 in. x 5.87 in.
XMC Interface
The Model 7158 complies with the VITA 42.0 XMC specification for carrier boards. This standard provides, among others, for a 4X link with a 3.125 GHz bit clock between the XMC module and the carrier board. With two 4X links, the 7158 achieves 2.5 GB/sec streaming data transfer rate independent of the PCI interface and supports switched fabric protocols such as Serial RapidIO and PCI Express.

Two internal timing buses can provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An internal clock generator receives an external sample clock from the front panel SMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can also be sourced from an on-board programmable voltage controlled crystal oscillator. In this mode, the front panel SMC connector can be used to provide a 10 MHz system reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to three slave 7158s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Memory Resources
Two independent 256 MB banks of DDR2 SDRAM are available to the processing FPGA. These can be upgraded to 512 MB banks with option -140. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.
Model 7158 Description Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC
PCI-X Interface
Options: -104 FPGA I/O through the P14 connector -140 1 GB DDR2 SDRAM -5xx XMC interface
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors
Pentek, Inc.
www.pentek.com
! w e N
Model 71620
3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - XMC
General Information
Model 71620 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture and playback features offer an ideal turnkey solution. It includes three A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71620 includes general purpose and gigabit serial connectors for application-specific I/O . nization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable the 71620 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
The Cobalt Architecture

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71620 factory-installed functions include three A/D acquisition and a D/A waveform playback IP modules, ideally matched to the boards analog interfaces. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchro-
Xilinx Virtex-6 FPGA

The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O. Option -105 installs the P16 XMC connector with one 8X or two 4X gigabit links to the FPGA to support serial protocols.
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three 200 MHz 16-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF In
RF Out
RF Out
RF XFORMR Sample Clk / Reference Clk In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
800 MHz 16-BIT D/A DIGITAL UPCONVERTER 32
16
16
16
Timing Bus
VCXO
VIRTEX-6 FPGA LX130T, LX240T or SX315T

GTX
GTX
GTX
LVDS
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB
8X
4X
4X
40
QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
x8 PCIe
Gigabit FPGA Serial I/O GPIO (option 105) (option 104) P16 XMC P14 PMC
P15 XMC
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
www.pentek.com
Model 71620
A/D Acquisition IP Modules
The 71620 features three A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from any of the three A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
A/D Converter Stage
The front end accepts three full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71620s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.

A TI DAC5688 DUC (digital upconverter) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x.
Memory Resources
The 71620 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the
to D/A D/A loopback
TEST SIGNAL GENERATOR

Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths.
from A/D Ch 1 from A/D Ch 2 from A/D Ch 3
D/A Waveform Playback IP Module

The Model 71620 factoryinstalled functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users to easily play back to the dual D/As waveforms stored in either onboard memory or off-board host memory. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 individual link entries can be chained together to create complex waveforms with a minimum of programming.
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3
DATA UNPACKING & FLOW CONTROL MUX
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
MEMORY CONTROL
to Mem Bank 4
LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE
VIRTEX-6 FPGA DATAFLOW DETAIL
PCIe INTERFACE
(supports user installed IP)
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 71620
modules DMA capabilities, providing
FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks. 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
Model 8266
The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards (Models 78xxx). It was created to save engineers and system integrators the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards.
XMC Interface
The Model 71620 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71620 supports x8 PCIe on the first XMC connector leaving the second connector free to support userinstalled transfer protocols specific to the target application.
PCI Express Interface

The Model 71620 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the module.
Model 71620 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-6 FPGA XMC XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits
Options: -062 -064 -104 -105 -150
-160
-155
-165
Contact Pentek for availability of rugged and conduction-cooled versions

Model 8266 Description PC Development System See 8266 Datasheet for Options
Pentek, Inc.
www.pentek.com
! w e N
Model 71621
3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - XMC
General Information
Model 71621 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with a programmable DDC, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes three A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71621 includes a general purpose connector for application-specific I/O. sition modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 71621 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71621 factory installed functions include three A/D acquisition and a D/A waveform playback IP modules. Each of the three acquisition IP modules contains a powerful, programmable DDC IP core. The waveform playback IP module contains an intrepolation IP core, ideal for matching playback rates to the data and decimation rates of the acquiRF In

The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O.
RF In RF In RF Out RF Out
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three 200 MHz 16-bit A/Ds Three multiband DDCs (digital downconverters) Two 800 MHz 16-bit D/As One DUC (digital upconverter) Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
16
Timing Bus
VCXO
VIRTEX-6 FPGA LX240T or SX315T

GTX
GTX
GTX
LVDS
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
8X
4X
4X
40
Sum to next board x8 PCIe Aurora Gigabit Serial P16 XMC FPGA GPIO (option 104) P14 PMC
P15 XMC
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
www.pentek.com
Model 71621
s, where s is the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as three different output bandwidths for the board. Decimations can be programmed from 2 to 65,536 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the three DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 71621s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the P16 XMC connector. This allows summation across channels on multiple boards.
Beamformer IP Core
In addition to the DDCs, the 71621 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average

The Model 71621 factory-installed functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users to easily play back to the dual D/As waveforms stored in either on-board memory or off- board host memory . Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 individual link entries can be chained together to create complex waveforms with a minimum of programming.
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3 D/A loopback
to D/A
INPUT MULTIPLEXER
DDC DEC: 2 TO 65536
DDC DEC: 2 TO 65536

POWER METER & THRESHOLD DETECT
DDC DEC: 2 TO 65536

INTERPOLATOR 2 TO 65536 IP CORE DATA UNPACKING & FLOW CONTROL MUX
DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all three DDCs or each of the three A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to
MUX
DDC CORE
DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
AURORA GIGABIT SERIAL INTERFACE 4X 4X
sum out sum in
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
to next from previous board board
8X PCIe
Pentek, Inc.
www.pentek.com
Model 71621
A/D Converter Stage
The front end accepts three analog HF or IF inputs on front panel SSMC connectors with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71621s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.

A TI DAC5688 DUC (digital upconverter) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x. In addition to the DAC5688, an FPGA based interpolator core provides additional interpolation from 2x to 65,536x. The two interpolators can be combined to create a total range from 2x to 524,288x.
Memory Resources
The 71621 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
XMC Interface
The Model 71621 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71621 supports x8 PCIe on the first XMC connector. The second connector is used for the Aurora interface and provides a dedicated board-to board interface for beamforming accross multiple modules.

Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator.

Pentek, Inc.
www.pentek.com
Model 71621
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Three channels Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformer Summation: Three channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
Model 8266
Model 71621 Description 3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA XMC
Options: -062 -064 -104 -150 XC6VLX240T XC6VSX315T LVDS FPGA I/O through P14 connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
-160
-155
-165

Pentek, Inc.
www.pentek.com
! ew N
Model 71630
1 GHz A/D and 1 GHz D/A, Virtex-6 FPGA - XMC

General Information
Model 71630 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes 1 GHz A/D and D/A converters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71630 includes optional general purpose and gigabit serial card connectors for application-specific I/O. synchronization functions, a test signal generator and a PCIe interface complete the factory-installed functions and enable the 71630 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace the Pentek IP with their own.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71630 factory-installed functions include an A/D acquisition and a D/A waveform playback IP module. In addition, IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and

RF In RF Out
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One 1 GHz 12-bit A/D One 1 GHz 16-bit D/A Up to 2 GB of DDR3 SDRAM or 16 MB of QDRII+ SRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Sample Clk / Reference Clk In TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Sync In
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12
1 GHz 16-BIT D/A 16
D/A Sync Bus
VCXO

GTX
GTX
GTX
LVDS
16
16
16
16
8X
4X
4X
40
Memory Banks 1 & 2 DDR3 option 155 QDRII+ SRAM 8 MB QDRII+ SRAM 8 MB
Memory Banks 3 & 4 DDR3 option 165
x8 PCIe
P15 XMC
QDRII+ option 150
Pentek, Inc.
www.pentek.com
Model 71630

A/D Converter Stage
Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or 16 to provide different lower frequency A/D and D/A clocks. A pair of front panel Sync connectors allows multiple modules to be synchronized. They accept CML inputs that drive the boards sync and gate/trigger signals. The Pentek Model 7192 and Model 9192 Cobalt Synchronizers can drive multiple 71630 Sync connectors enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connector.
A/D Acquisition IP Module

The 71630 features an A/D Acquisition IP Module for easy capture and data moving. The IP module can receive data from the A/D, a test signal generator, or from the D/A Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for storing data in transient capture mode. The memory banks are supported with a DMA engine for moving A/D data through the PCIe interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processors job of identifying and executing on the data.
The front end accepts an analog HF or IF input on a front panel SSMC connector with transformer coupling into a Texas Instruments ADS5400 1 GHz, 12-bit A/D converter. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources.
D/A Converter Stage

The 71630 features a TI DAC5681Z 1 GHz, 16-bit D/A. The converter has an input sample rate of 1 GSPS, allowing it to acept full rate data from the FPGA. Additionally, the D/A includes a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is through a front panel SSMC connector.
Memory Resources
to D/A

Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives a sample clock either from the front panel SSMC connector or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this latter mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock to phase-lock the VCXO.
from A/D D/A loopback


The Model 71630 factoryinstalled functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users to easily play back waveforms stored in either on-board memory or off- board host memory to the D/A. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 individual link entries can be chained together to create complex waveforms with a minimum of programming.
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROLLER MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE MEMORY CONTROLLER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
(supports user installed IP) 8X PCIe Gigabit Serial I/O 4X 4X 40
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 71630

XMC Interface
The Model 71630 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71630 supports x8 PCIe on the first XMC connector leaving the second connector free to support userinstalled transfer protocols specific to the target application. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Option 150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1: x4 or x8; Gen 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
PCI Express Interface Model 8266

The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards (Models 78xxx). It was created to save engineers and system integrators the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. The Model 71630 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the module.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz to 1 GHz Resolution: 12 bits D/A Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock
Model 71630 Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector -105 Gigabit serial FPGA I/O through P16 connector -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required Description 1 GHz A/D and D/A, Virtex-6 FPGA - XMC

Pentek, Inc.
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! w e N
Model 71640
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - XMC
General Information
Model 71640 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71640 includes optional general purpose and gigabit serial connectors for application-specific I/O. and a PCIe interface complete the factoryinstalled functions and enable the 71640 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71640 factory-installed functions include an A/D acquisition IP module. In addition, IP modules for DDR3 memories, a controller for all data clocking and synchronization functions, a test signal generator

The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O. Option -105 installs the P16 XMC connector with dual 4X gigabit links to the FPGA to support other serial protocols.
Features

Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One-channel mode with 3.6 GHz, 12-bit A/D Two-channel mode with 1.8 GHz, 12-bit A/Ds 2 GB of DDR3 SDRAM Sync bus for multimodule synchronization PCI Express Gen. 2 interface x8 wide Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
Sample Clk TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Reset In Ref Clk In Ref Clk Out
3.6 GHz (1 Channel) or 1.8 GHz (2 Channel) 12-Bit A/D

12 12
Sync Bus

GTX
GTX
GTX
LVDS
8X
4X
4X
40
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCIe
P15 XMC
Pentek, Inc.
www.pentek.com
Model 71640
A/D Converter Stage
The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the 71640 to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple modules. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple 71640s can be synchronized using the Cobalt high speed sync module to drive the sync bus.
Memory Resources
The 71640 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the modules DMA and data capture capabilities. Built-in memory functions include an A/D data transient capture mode for taking snapshots of data for transfer to a host computer. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

The 71640 features an A/D Acquisition IP Module for easy capture and data moving. The IP module can receive data from the A/D, or a test signal generator. The IP module has associated memory banks for buffering data in FIFO mode or for storing data in transient capture mode. In single-channel mode, all four banks are used to store the single-channel of input data. In dual-channel mode, memory banks 1 and 2 store data from input channel 1 and memory banks 3 and 4 store data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving A/D data through the PCIe interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processors job of identifying and executing on the data.
XMC Interface
The Model 71640 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 5 GHz bit clock. With dual XMC connectors, the 71640 supports x8 PCIe on the first XMC connector leaving the optional second connector free to support user-installed transfer protocols specific to the target application.

The 71640 accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connector. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multi-pin sync bus connector allows multiple modules to be synchronized, ideal for larger multichanel
from A/D
from A/D

(Two channel mode shown) INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE to MEM CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE
MEMORY CONTROLLER PCIe INTERFACE
MEMORY CONTROLLER
(supports user installed IP) to Mem Bank 1 to Mem Bank 2 8X PCIe Gigabit Serial I/O 4X 4X 40 to Mem Bank 3 to Mem Bank 4
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 71640
The Model 71640 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the module. External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2, or XC6VSX315T-2 Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Sample Clock Sources: Front panel SSMC connector Sync Bus: Multi-pin connectors, bus includes gate, reset and in and out ref clock
Model 8266
Model 71640 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - XMC
Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T XC6VSX315T LVDS FPGA I/O through P14 connector -105 Gigabit serial FPGA I/O through P16 connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required

Pentek, Inc.
www.pentek.com
! w e N
Model 71641
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, w/ Wideband DDC, Virtex-6 FPGA - XMC
General Information
Model 71641 is a member of the Cobalt family of high-performance XMC modules based on the Xilinx Virtex-6 FPGA. A highspeed data converter with a programmable digital downconverter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. It includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, Model 71641 includes an optional connection to the Virtex-6 FPGA for custom I/O . controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factoryinstalled functions and enable the 71641 to operate as a complete turnkey solution, without the need to develop any FPGA IP. For applications that require additional control and status signals, option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O.
A/D Converter Stage

The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the 71641 to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple modules. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71641 factory-installed functions include an A/D acquisition IP module. In addition, IP modules for DDR3 memories, a
Features

Ideal radar and software radio interface solution One-channel mode with 3.6 GHz, 12-bit A/D Two-channel mode with 1.8 GHz, 12-bit A/Ds Programmable one- or twochannel DDC (Digital Downconverter) 2 GB of DDR3 SDRAM Sync bus for multimodule synchronization PCI Express Gen. 2 interface up to x8 Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus

12 12
Sync Bus
VIRTEX-6 FPGA SX315T

GTX
LVDS
8X
40
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCIe
FPGA GPIO (option 104) P14 PMC
P15 XMC
Pentek, Inc.
www.pentek.com
Model 71641
The 71641 features an A/D Acquisition IP Module for easy capture and data moving. The IP module can receive data from the A/D, or a test signal generator. The IP module has associated memory banks for buffering data in FIFO mode or for storing data in transient capture mode. In single-channel mode, all four banks are used to store the single-channel of input data. In dual-channel mode, memory banks 1 and 2 store data from input channel 1 and memory banks 3 and 4 store data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving A/D data through the PCIe interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
DDC IP Cores
Within the FPGA is a powerful DDC IP core. The core supports a single-channel mode, accepting data samples from the A/D at the full 3.6 GHz rate. Additionally, a dual-channel mode supports the A/Ds 1.8 GHz two-channel operation . In dual-channel mode, each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. In single-channel mode, decimation can be programmed to 8x, 16x or 32x. In dual-channel mode, both channels share the same decimation rate, programmable to 4x, 8x or 16x. The decimating filter for each DDC accepts a unique set of user-supplied 16-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 16-bit I + 16-bit Q samples at a rate of s/N.

The 71641 accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connector. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multipin sync bus connector allows multiple modules to be synchronized, ideal for multichannel systems. The sync bus includes gate, reset, and in and out reference clock signals. Two 71641s can be synchronized with a simple cable. For larger systems, multiple 71641s can be synchronized using the Cobalt 7192 highspeed sync module to drive the sync bus.
Memory Resources
The 71641 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the modules DMA and data capture capabilities. Built-in memory functions include an A/D data transient capture mode for taking snapshots of data for transfer to a host computer.
from A/D
from A/D

*Two channel mode shown. Programmable decimation of 8, 16 or 32 available in one channel mode.
INPUT MULTIPLEXER TEST SIGNAL GENERATOR DDC *DEC: 4, 8 or 16
DDC *DEC: 4, 8 or 16
DDC CORE DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE MEMORY CONTROLLER A/D ACQUISITION IP MODULE PCIe INTERFACE to MEM CONTROL
DDC CORE DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE MEMORY CONTROLLER
to Mem Bank 1
to Mem Bank 2
8X PCIe
FPGA GPIO
40
to Mem Bank 3
to Mem Bank 4
Pentek, Inc.
www.pentek.com
Model 71641
The Model 71641 complies with the VITA 42.3 XMC specification and includes an industry-standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the module. Sample Clock Sources: Front panel SSMC connector Sync Bus: Multipin front panel connector, includes gate, reset, and in and out ref clock External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include trigger and gate Field Programmable Gate Array: Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Digital Downconverters Modes: One or two channels, programmable Supported Sample Rate: One-channel mode: 3.6 GHz, two-channel mode: 1.8 GHz Decimation Range: One-channel mode: 8x, 16x or 32x, two-channel mode: 4x, 8x, or 16x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: User-programmable 18-bit coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation
Model 8266
Model 71641 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D with Wideband DDC, Virtex-6 FPGA - XMC
Options: -002* -064* -104 -2 FPGA speed grade XC6VSX315T LVDS FPGA I/O through P14 connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required

Pentek, Inc.
www.pentek.com
! w e N
Model 71650
Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - XMC
General Information
Model 71650 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes two A/Ds, one DUC (Digital Upconverter), two D/As, and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71650 includes optional general-purpose and gigabit serial card connectors for application-specific I/O. memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factory-installed functions and enable the 71650 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71650 factory-installed functions include two A/D acquisition and one D/A waveform playback IP modules. In addition, IP modules for either DDR3 or QDRII+
RF In

RF In RF Out RF Out
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two 500 MHz 12-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 VITA 42.0 XMC compatible with switched fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
500 MHz 12-BIT A/D
500 MHz 12-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
VCXO

GTX
GTX
Timing Bus
GTX
LVDS
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
8X
4X
4X
40
x8 PCIe
P15 XMC
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
www.pentek.com
Model 71650
A/D Converter Stage
Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an onboard programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71650s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.

The 71650 features two A/D Acquisition IP Modules for easy capture and data moving. Each IP module can receive data from either of the two A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfers, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp, and data length information. These actions simplify the host processors job of identifying and executing on the data.
The front end accepts two full scale analog HF or IF inputs on front panel SSMC connectors at +5 dBm into 50 ohms with transformer coupling into two Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources.

A TI DAC5688 DUC and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x.
Memory Resources

from A/D Ch 1
from A/D Ch 2 D/A loopback TEST SIGNAL GENERATOR
to D/A
INPUT MULTIPLEXER

The Model 71650 factoryinstalled functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users to easily play back waveforms stored in either on-board memory or off- board host memory to the dual D/As. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 individual link entries can be chained together to create complex waveforms with a minimum of programming.
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
MEMORY CONTROL
to Mem Bank 3
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 71650
FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1 or Gen.2, x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
Model 8266
XMC Interface
PCI Express Interface Ordering Information

Model 71650 Description Two 500 MHz A/Ds, one DUC, Two 800 MHz D/As with Virtex-6 FPGA - XMC
Options: -002* -014 -062 -064 -104 -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240 FPGA XC6VSX315 FPGA LVDS FPGA I/O through P14 connector -105 Gigabit serial FPGA I/O through P16 connector -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -160 Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (option 014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz, max. Output IF: DC to 400 MHz, max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz, max. with interpolation Resolution: 16 bits

Pentek, Inc.
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Model 71651
General Information
Model 71651 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with a programmable DDC, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes two A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71651 includes a general purpose connector for application-specific I/O. sition modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 71651 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71651 factory installed functions include two A/D acquisition and a D/A waveform playback IP modules. Each of the two acquisition IP modules contains a powerful, programmable DDC IP core. The waveform playback IP module contains an intrepolation IP core, ideal for matching playback rates to the data and decimation rates of the acquiRF In

RF In RF Out RF Out
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two 500 MHz 12-bit A/Ds Two multiband DDCs (digital downconverters) Two 800 MHz 16-bit D/As One DUC (digital upconverter) Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 16 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
500 MHz 12-BIT A/D
500 MHz 12-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
VCXO

GTX
GTX
Timing Bus
GTX
LVDS
8X 4X Sum from previous board x8 PCIe
4X
40
Sum to next board Aurora Gigabit Serial P16 XMC FPGA GPIO (option 104) P14 PMC
P15 XMC
QDRII+ option 150
Pentek, Inc.
www.pentek.com
Model 71651
The 71651 features two A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from either of the two A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
frequency. Each DDC can have its own unique decimation setting, supporting as many as two different output bandwidths for the board. Decimations can be programmed from 2 to 131,072 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 16-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the two DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 71651s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the P16 XMC connector. This allows summation across channels on multiple boards.
Beamformer IP Core

from A/D Ch 1

INPUT MULTIPLEXER
to D/A
DDC DEC: 2 TO 131027

DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving both DDCs or each of the two A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling
MUX
DDC CORE
to Mem Bank 1
to Mem Bank 2
to Mem Bank 4
sum out sum in
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
8X PCIe
Pentek, Inc.
www.pentek.com
Model 71651
A/D Converter Stage
The front end accepts two analog HF or IF inputs on front panel SSMC connectors with transformer coupling into two Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71651s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.

Memory Resources
The 71651 architecture supports up to three independent memory banks which can be configured with QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
XMC Interface
The Model 71651 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71651 supports x8 PCIe on the first XMC connector. The second connector is used for the Aurora interface and provides a dedicated board-to board interface for beamforming accross multiple modules.


The Model 71651 includes an industrystandard interface fully compliant with PCI Express Gen. 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the module.
Pentek, Inc.
www.pentek.com
Model 71651
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (option -014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits Digital Downconverters Quantity: Two channels Decimation Range: 2x to 131,072x in two programmable stages of 2x to 256x and one fixed 2x stage LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 16-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformer Summation: Two channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T-2 Optional: Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Memory Option -150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option -155 or -165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
Model 8266
Model 71651 Description 2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA XMC
Options: -002* -014 -062 -064 -104 -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required

Pentek, Inc.
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Model 71660
4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - XMC

General Information
Model 71660 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes four A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71660 includes general purpose and gigabit serial connectors for application-specific I/O . generator, and a PCIe interface complete the factory-installed functions and enable the 71660 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71660 factory-installed functions include four A/D acquisition IP modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 VITA 42.0 XMC compatible with switched fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF In
RF In
Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

GTX
GTX
GTX
LVDS
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
8X
4X
4X
40
x8 PCIe
P15 XMC
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
www.pentek.com
Model 71660

A/D Converter Stage
The front end accepts four full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71660s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.
Memory Resources
The 71660 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An onboard clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the

The 71660 features four A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
XMC Interface
The Model 71660 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71660
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
TEST SIGNAL GENERATOR DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL DATA PACKING & FLOW CONTROL
INPUT MULTIPLEXER
MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 71660

supports x8 PCIe on the first XMC connector leaving the second connector free to support user-installed transfer protocols specific to the target application. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

Model 8266
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock
Model 71660 Options: -062 -064 -104 -105 -150 XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Description 4-Channel 200 MHz A/D with Virtex-6 FPGA - XMC
-160
-155
-165

Pentek, Inc.
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Model 71661
4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - XMC
General Information
Model 71661 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with programmable DDCs (digital downconverters), it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture feature offers an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes four A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71661 includes a general purpose connector for application-specific I/O. for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 71661 to operate as a complete turnkey solution without the need to develop any FPGA IP.
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71661 factory-installed functions include four A/D acquisition IP modules. Each of the four acquisition IP modules contains a powerful, programmable DDC (Digital Downconverter) IP core. IP modules

RF In RF In RF In RF In
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Four multiband DDCs Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

GTX
GTX
GTX
LVDS
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
8X x8 PCIe
4X
4X
40
Aurora Gigabit Serial I/O
Sum from previous board

P15 XMC
Sum to next board

P16 XMC
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
www.pentek.com
Model 71661
providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 71661s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the P16 XMC connector. This allows summation across channels on multiple boards.
A/D Converter Stage

The front end accepts four analog HF or IF inputs on front panel SSMC connectors with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources.
Beamformer IP Core
In addition to the DDCs, the 71661 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the four DDC core outputs. An additional programmable gain stage compensates for summation

An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a builtin clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquistion IP Modules, many different configurations can be achieved including one A/D driving all four DDCs or each of the four A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as four different output bandwidths for the board. Decimations can be programmed from 2 to 65,536
INPUT MULTIPLEXER
DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

MUX
DDC CORE
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
sum out sum in
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
8X PCIe
Pentek, Inc.
www.pentek.com
Model 71661
XMC Interface
The Model 71661 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71661 supports x8 PCIe on the first XMC connector. The second connector is used for the Aurora interface and provides a dedicated board-to board interface for beam-forming accross multiple boards.
controlled crystal oscillator. In this mode,
the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71661s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. Beamformer Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

The Model 71661 includes an industry-standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the module.
Memory Resources
Model 8266
The Model 8266 is a PC development system for Pentek Cobalt and Onyx PCI Express boards (Models 78xxx). It was created to save engineers the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards.
Model 71661 Description 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - XMC XC6VLX240T XC6VSX315T LVDS FPGA I/O Two 8 MB QDRII+ SRAM Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Banks (Banks 3 and 4)
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Four channels Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation
Options: -062 -064 -104 -150 -160 -155 -165

Pentek, Inc.
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Model 71662
4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - XMC
General Information
Model 71662 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. This fourchannel, high-speed data converter with programmable DDCs (digital downconverters) is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture feature offers an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. interface complete the factory-installed functions and enable the 71662 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, and triggering. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71662 factory-installed functions include four A/D acquisition IP modules. Each of the four acquisition IP modules contains a powerful, programmable 8-channel DDC IP core. IP modules for control of all data clocking, synchronization, gate and trigger functions, a test signal generator, voltage and temperature monitoring, DDR3 SDRAM memory controllers, and a PCIe

The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O. Option -105 installs the P16 XMC connector with one 8X or two 4X gigabit links to the FPGA to support serial protocols.
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Four multiband DDCs Up to 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable serial gigabit interfaces Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

GTX
GTX
GTX
LVDS
8X
4X
4X
40
x8 PCIe
P15 XMC
Pentek, Inc.
www.pentek.com
Model 71662
available output bandwidths range from 19.53 kHz to 10.0 MHz. Each 8-channel bank can have its own unique decimation setting supporting a different bandwidth associated with each of the four acquisition modules. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N. Any number of channels can be enabled within each bank, selectable from 0 to 8. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within a bank.

An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a builtin clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltagecontrolled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a reference clock, typically 10 MHz, for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71662s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.
A/D Converter Stage

Memory Resources
The 71662 architecture supports up to four independent memory banks which can be configured with DDR3 SDRAM.
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
DDC IP Cores
Within each A/D Acquisition IP Module is a powerful 8-channel DDC bank. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all 32 DDC channels or each of the four A/Ds driving its own DDC bank. Each of the 32 channels has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. All of the 8 channels within a bank share a common decimation setting that can range from 16 to 8192, programmable in steps of 8. For example, with a sampling rate of 200 MHz, the
INPUT MULTIPLEXER
DIGITAL DOWNCONVERTER BANK 1: CH 1-8 DEC: 16 TO 8192

.

.

.

.
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
32 Memory Bank 1
32 Memory Bank 2
32 Memory Bank 3
32 Memory Bank 4
8X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 71662
Each DDR3 SDRAM bank can be up to
512 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory and capture space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock, or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
XMC Interface Model 8266

The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards (Models 78xxx). It was created to save engineers and system integrators the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. The Model 71662 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71662 supports x8 PCIe on the first XMC connector leaving the second connector free to support user-installed transfer protocols specific to the target application.

Specifications Ordering Information

Model 71662 Description 4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - XMC XC6VLX240T XC6VSX315T LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Options: -062 -064 -104 -105 -155
-165
Contact Pentek for availability of ruged and conduction-cooled versions

Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Four 8-channel banks, one per acquisition module Decimation Range: 16x to 8192x in steps of 8x LO Tuning Freq. Resolution: 32 bits, 0 to s Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, >100 dB stopband attenuation
Pentek, Inc.
www.pentek.com
! ew N
Model 71670
4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - XMC

General Information
Model 71670 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. This 4-channel, high-speed data converter is suitable for connection to transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As, four digital upconverters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71670 includes general purpose and gigabit serial connectors for application-specific I/O . a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 71670 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71670 factory-installed functions include four D/A waveform playback IP modules, to support waveform generation through the D/A converters. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions,

The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O. Option -105 installs the P16 XMC connector with dual 4X gigabit links to the FPGA to support serial protocols.
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 1.25 GHz 16-bit D/As Four digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF Out
RF Out
RF Out
RF Out
RF XFORMR Sample Clk / Reference Clk In Trigger In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
Clock/Sync Bus A Clock/Sync Bus B
Gate In Sync In
1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER
1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER 16
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO

GTX
GTX
GTX
LVDS
8X
4X
4X
40
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCIe
P15 XMC
Pentek, Inc.
www.pentek.com
Model 71670

Two Texas Instruments DAC3484s provide four DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals to a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs to a 16-bit D/A converter. If translation is disabled, each D/A acts as an interpolating 16-bit D/A with output sampling rates up to 1.25 GHz. In both modes, the D/A provides interpolation factors of 2x, 4x, 8x and 16x. Analog output is through four front panel SSMC connectors. A pair of front panel Sync connectors allows multiple modules to be synchronized. They accept CML inputs that drive the boards sync and trigger/gate signals. The Pentek Models 7192 or 9192 Cobalt Synchronizers can drive multiple 71670 Sync connectors enabling large, multichannel synchronous configurations.
Memory Resources
The 71670 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the modules DMA and waveform playback capabilities. Waveform tables can be loaded into the memories with playback managed by the linked list controllers. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

An internal timing bus provides all required D/A clocking. The bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives a sample clock either from the front panel SSMC connector or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this latter mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock to phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided by 2, 4, 8, or 16 to provide lower frequency D/A clocks.
16
XMC Interface
The Model 71670 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 3.125 GHz bit clock. With dual XMC connectors, the 71670 supports x8 PCIe on the first XMC connector leaving the second connector free to support user-installed transfer protocols specific to the target application.

The Model 71670 factoryinstalled functions include a sophisticated D/A Waveform Playback IP module. Four linked list controllers support waveform generation to the four D/As from tables stored in either on-board memory or offboard host memory. Data for Channel 1 and Channel 2 are interleaved for delivery to a dual channel D/A device. For this reason, they must share a common trigger/ gate, sample rate, interpolation factor, and other parameters. The same rules apply to Channel 3 and Channel 4. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up to 64 individual link entries for each D/A channel can be chained together to create complex waveforms with a minimum of programming.
to D/A Ch 1 & 2
16
to D/A Ch 3 & 4
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
MEMORY CONTROL LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE 1
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 71670

The Model 71670 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the module. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connector Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as two 4X or one 8X gigabit serial links to the FPGA Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
Specifications Model 8266

The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards (Models 78xxx). It was created to save engineers and system integrators the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the D/A clock
Model 71670 Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector -105 Gigabit serial FPGA I/O through P16 connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required Description 4-Channel 1.25 GHz D/A with Virtex-6 FPGA - XMC

Pentek, Inc.
www.pentek.com
! ew N
Model 71671
4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - XMC
General Information
Model 71671 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. This 4-channel, high-speed data converter is suitable for connection to transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As with a wide range of programmable interpolation factors, four digital upconverters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71671 includes optional generalpurpose and gigabit serial connectors for application-specific I/O . SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 71671 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71671 factory-installed functions include four D/A waveform playback IP modules, to support waveform generation through the D/A converters. IP modules for DDR3

The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O. Option -105 installs the P16 XMC connector with dual 4X gigabit links to the FPGA to support serial protocols.
RF Out RF Out RF Out
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 1.25 GHz 16-bit D/As Four digital upconverters Extended interpolation range from 2x to 1,048,576x Programmable output levels 250 MHz max. output bandwidth 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO

GTX
GTX
GTX
LVDS
8X
4X
4X
40
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCIe
P15 XMC
Pentek, Inc.
www.pentek.com
Model 71671
Two Texas Instruments DAC3484s provide four DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals to a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs to a 16-bit D/A converter. If translation is disabled, each D/A acts as an interpolating 16-bit D/A with output sampling rates up to 1.25 GHz. In both modes, the D/A provides interpolation factors of 2x, 4x, 8x and 16x. In addition to the DAC3484, the 71671 features an FPGA-based interpolation engine which adds two additonal interpolation stages programmable from 2x to 256x. The combined interpolation results in a range from 2x to 1,048,576x for each D/A channel and is ideal for matching the digital downconversion and data reduction used on the receiving channels of many communications systems. Analog output is through four front panel SSMC connectors. on-board clock generator receives a sample clock either from the front panel SSMC connector or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this latter mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock to phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided by 2, 4, 8, or 16 to provide lower frequency D/A clocks. A pair of front panel Sync connectors allows multiple modules to be synchronized. They accept CML inputs that drive the boards sync and trigger/gate signals. The Pentek Models 7192 or 9192 Cobalt Synchronizers can drive multiple 71671 Sync connectors enabling large, multichannel synchronous configurations.
Memory Resources
The 71671 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the modules DMA and waveform playback capabilities. Waveform tables can be loaded into the memories with playback managed by the linked-list controllers. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
Clocking and Synchronization D/A Waveform Playback IP Module

The Model 71671 factoryinstalled functions include a sophisticated D/A Waveform Playback IP module. Four linkedlist controllers support waveform generation to the four D/As from tables stored in either onboard memory or off-board host memory. Data for Channel 1 and Channel 2 are interleaved for delivery to a dual channel D/A device. For this reason, they must share a common trigger/ gate, sample rate, interpolation factor, and other parameters. The same rules apply to Channel 3 and Channel 4. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up to 64 individual link entries for each D/A channel can be chained together to create complex waveforms with a minimum of programming. An internal timing bus provides all required D/A clocking. The bus includes a clock, sync and a gate or trigger signal. An
16
to D/A Ch 1 & 2
16
to D/A Ch 3 & 4
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4

Memory Bank 1 Memory Bank 2 Memory Bank 3 Memory Bank 4
PCIe INTERFACE
8X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 71671
XMC Interface
The Model 71671 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 3.125 GHz bit clock. With dual XMC connectors, the 71671 supports x8 PCIe on the first XMC connector leaving the second connector free to support user-installed transfer protocols specific to the target application. Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connector Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML Field Programmable Gate Array: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as two 4X or one 8X gigabit serial links to the FPGA Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards (Models 78xxx). It was created to save engineers and system integrators the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. The Model 71671 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the module.
Specifications
D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15
Model 71671 Description 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - XMC
Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector -105 Gigabit serial FPGA I/O through P16 connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required

Pentek, Inc.
www.pentek.com
! w e N
Model 71690
L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - XMC

General Information
Model 71690 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A 2-Channel high-speed data converter, it is suitable for connection directly to the RF port of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes an L-Band RF tuner, two A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71690 includes general purpose and gigabit serial connectors for application-specific I/O . generator, and a PCIe interface complete the factory-installed functions and enable the 71690 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71690 factory-installed functions include two A/D acquisition IP modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal
Ref In

RF In
MAX2112
Features

Accepts RF signals from 925 MHz to 2175 MHz Programmable LNA boosts LNB (low-noise block) antenna signal levels with up to 60 dB gain Programmable analog downconverter provides I + Q baseband signals with bandwidths ranging from 4 to 40 MHz Two 200 MHz 16-bit A/Ds digitize the I + Q signals synchronously Supports Xilinx Virtex-6 LXT and SXT FPGAs 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference PCI Express (Gen. 1 & 2) interface, up to x8 Clock/sync bus for multimodule synchronization VITA 42.0 XMC compatible with switched fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Ref Out GC
12-BIT D/A
Sample Clk / Reference Clk In Trigger 1 Trigger 2 TIMING GENERATOR Clock / Sync / Gate / PPS
Ref A/D Clock/Sync
Control
I 200 MHz 16-BIT A/D Q 200 MHz 16-BIT A/D
TTL Gate / Trig TTL Sync / PPS Sample Clk Ref In Gate A Gate B Sync / PPS A Sync / PPS B
16
16
IC
2
Timing Bus
VCXO

GTX
GTX
GTX
LVDS
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
Config FLASH 64 MB
8X
4X
4X
40
x8 PCIe
P15 XMC
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
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Model 71690

RF Tuner Stage
A front panel SSMC connector accepts L-Band signals between 925 MHz and 2175 MHz from an antenna LNB (low noise block). A Maxim MAX2112 tuner directly converts these L-Band signals to baseband using a broadband I/Q downconverter. The device includes an RF variable-gain LNA (low noise amplifier), a PLL (phaselocked loop) synthesized local oscillator, quadrature (I + Q) downconverting mixers, baseband lowpass filters with programmable cutoff frequency, and variable-gain baseband amplifiers. The fractional-N PLL synthesizer locks its VCO to the timing generator output, or to an external reference input between 12 and 30 MHz. Together, the baseband amplifiers and the RF LNA offer a programmable linear gain range of 60 dB. An integrated lowpass filter with variable bandwidth provides bandwidths ranging from 4 to 40 MHz, programmable with 8 bits of resolution.
A/D Clocking and Synchronization

An internal timing generator provides all timing, gating, triggering and synchronization functions required by the A/D converters. It also serves as an optional source for the L-Band tuner reference. The front panel SSMC clock input can be used directly as the A/D sample clock. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (voltage-controlled crystal oscillator). In this mode, the front panel SSMC clock input connector accepts a 10 MHz reference signal for synchronizing the VCXO using a PLL. The timing generator uses a front panel LVPECL 26-pin clock/sync connector for one clock, two sync, and two gate/trigger signals. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate/ trigger signals within the module. In the master mode, the LVPECL bus drives output timing signals to synchronize multiple slave modules, supporting synchronous sampling and sync functions across all connected modules.

The 71690 features two A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from either of the two A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
A/D Converter Stage

The analog baseband I and Q analog tuner outputs are then applied to two Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources.
Memory Resources
The 71690 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, all DDR3 SDRAM, or as combination of two banks of each type of memory.
from A/D (I)
from A/D (Q)
TEST SIGNAL GENERATOR DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2
to Mem Bank 1
to Mem Bank 2
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 71690

Each QDRII+ SRAM bank can be up to
8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. The factory-installed A/D acquisition modules use memory banks 1 & 2. Banks 3 & 4 can be optionally installed to support custom user-installed IP within the FPGA . A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board timing generator/synthesizer A/D Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, for the A/D clock Timing Generator External Clock Input Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 200 MHz (up to 800 MHz when Timing Generator divider is enabled) or PLL system reference Timing Generator Bus: 26-pin front panel connector LVPECL bus includes, clock/ sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Input Quantity: 2 Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8; Gen. 2 x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
Model 8266
XMC Interface

Model 71690 Description L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - XMC XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Options: -062 -064 -104 -105 -150
Specifications
Front Panel Analog Signal Input Connector: Front panel female SSMC Impedance: 50 ohms L-Band Tuner Type: Maxim MAX2112 Input Frequency Range: 925 MHz to 2175 MHz Monolithic VCO Phase Noise: -97 dBc/Hz at 10 kHz Fractional-N PLL Synthesizer: freqVCO = (N.F) x freqREF where integer N = 19 to 251 and fractional F is a 20-bit binary value PLL Reference (freqREF): Front panel SSMC connector or on-board 27 MHz crystal (Option -100), 12 to 30 MHz LNA Gain: 0 to 65 dB, controlled by a programmable 12-bit D/A converter* Baseband Amplifier Gain: 0 to 15 dB, in 1 dB steps* *Usable Full-Scale Input Range: 50 dBm to +10 dBm Baseband Low Pass Filter: Cutoff frequency programmable from 4 to 40 MHz with 8-bit resolution
-160
-155
-165

Pentek, Inc.
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Model 71720
General Information
Model 71720 is a member of the Onyx family of high-performance XMC modules based on the Xilinx Virtex-7 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture and playback features offer an ideal turnkey solution. It includes three A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 3 as a native interface, the Model 71720 includes general-purpose and gigabit-serial connectors for application-specific I/O . IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable the 71720 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
The Onyx Architecture

Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 FPGAs from Xilinx. As the central feature of the board architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71720 factory-installed functions include three A/D acquisition and a D/A waveform playback IP modules for simplifying data capture and data transfer.

The Virtex-7 FPGA site can be populated with one of two FPGAs to match the specific requirements of the processing task. Supported FPGAs are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 installs the P14 PMC connector with 24 pairs of LVDS connections to the FPGA for custom I/O. Option -105 installs the P16 XMC connector with dual 4X gigabit links to the FPGA to support serial protocols.
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Three 200 MHz 16-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up to x8 VITA 42.0 XMC compatible with switched-fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-7 FPGA for custom I/O
RF In
RF In
RF In
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
16
Timing Bus
VCXO
VIRTEX-7 FPGA VX330T or VX690T

GTX
GTX
GTX
LVDS
CONFIG FLASH 1 GB
FPGA Config Bus
PCIe Gen. 3 x8
4X
4X
48
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
GATEXPRESS PCIe CONFIGURATION MANAGER
PCIe Gen. 3 x8 P15 XMC
Gigabit Serial I/O (option 105) P16 XMC
Pentek, Inc.
www.pentek.com
Model 71720
GateXpress for FPGA Configuration
The Onyx architecture includes GateXpress, a sophisticated FPGA-PCIe configuration manager for loading and reloading the FPGA. At power up, GateXpress immediately presents a PCIe target for the host computer to discover, effectively giving the FPGA time to load from FLASH. This is especially important for larger FPGAs where the loading times can exceed the PCIe discovery window, typically 100 msec on most PCs. The boards configuration FLASH can hold four FPGA images. Images can be factory-installed IP or custom IP created by the user, and programmed into the FLASH via JTAG using Xilinx iMPACT or through the boards PCIe interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the FPGA with a new IP image. The first is the option to load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the FPGA image must be loaded directly through the PCIe interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the FPGA IP may need to change many times during the course of a mission, images can be stored on the host computer and loaded through PCIe as needed. The third option, typically used during development, allows the user to directly load the FPGA through JTAG using Xilinx iMPACT. In all three FPGA loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the PCIe configuration space allowing dynamic FPGA reconfiguration without needing to reset the host computer to rediscover the board. After the reload, the host simply continues to see the board with the expected device ID.
A/D Converter Stage

The front end accepts three full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-7 FPGA for signal processing, data capture or for routing to other module resources.

A TI DAC5688 DUC (digital upconverter) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages.
from A/D Ch 1
from A/D Ch 2

to D/A

INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
MEMORY CONTROL
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
48
Pentek, Inc.
www.pentek.com
Model 71720
Memory Resources
The 71720 architecture supports four independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode.
When operating as a DUC, it interpolates
and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x. D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Installs the PMC P14 connector with 24 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Gen. 3 available only with the VX330T-2 and VX690T-2 FPGAs Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
XMC Interface
The Model 71720 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to 10 GB/sec per lane. With dual XMC connectors, the 71720 supports x8 PCIe on the first XMC connector leaving the second connector free to support user-installed transfer protocols specific to the target application.

Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules.
Model 8266
Model 71720 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-7 FPGA XMC XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector

The Model 71720 includes an industrystandard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the module.
Options: -073 -076 -104 -105
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits

Pentek, Inc.
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Model 71760

General Information
Model 71760 is a member of the Onyx family of high-performance XMC modules based on the Xilinx Virtex-7 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes four A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 3 as a native interface, the Model 71760 includes general-purpose and gigabitserial connectors for application-specific I/O. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable the 71760 to operate as a complete turnkey solution without the need to develop any FPGA IP.

Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 FPGAs from Xilinx. As the central feature of the board architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71760 factory-installed functions include four A/D acquisition IP modules for simplifying data capture and data transfer.

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Four 200 MHz 16-bit A/Ds 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up to x8 Advanced reconfigurability features VITA 42.0 XMC compatible with switched fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-7 FPGA for custom I/O
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

GTX
GTX
GTX
LVDS
CONFIG FLASH 1 GB
FPGA Config Bus
PCIe Gen. 3 x8
4X
4X
48
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
Pentek, Inc.
www.pentek.com
Model 71760

A/D Converter Stage

The front end accepts four full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-7 FPGA for signal processing, data capture or for routing to other module resources.


An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generator receives an
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
Gigabit Serial I/O
4X
4X
FPGA GPIO
48
Pentek, Inc.
www.pentek.com
Model 71760

external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltagecontrolled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71760s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.
A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Installs the PMC P14 connector with 24 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Gen. 3 available only with the VX330T-2 and VX690T-2 FPGAs Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
Model 8266
Memory Resources
The 71760 architecture supports four independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
XMC Interface
The Model 71760 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to 10 Gb/sec per lane. With dual XMC connectors, the 71760 supports x8 PCIe on the first XMC connector leaving the second connector free to support userinstalled transfer protocols specific to the target application.
Model 71760 Options: -073 -076 -104 -105 XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector Description 4-Channel 200 MHz A/D with Virtex-7 FPGA - XMC


Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz
Pentek, Inc.
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! ew N
Model 71730

General Information
Model 71730 is a member of the Onyx family of high performance XMC modules based on the Xilinx Virtex-7 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes 1 GHz A/D and D/A converters and four banks of memory. In addition to supporting PCI Express Gen. 3 as a native interface, the Model 71730 includes optional general purpose and gigabit serial card connectors for application-specific I/O. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factoryinstalled functions and enable the 71730 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 FPGAs from Xilinx. As the central feature of the board architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71730 factory-installed functions include an A/D acquisition and a D/A waveform playback IP module for simplifying data capture and data transfer.

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe One 1 GHz 12-bit A/D One 1 GHz 16-bit D/A 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up to x8 VITA 42.0 XMC compatible with switched fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-7 FPGA for custom I/O
RF In
RF Out
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Sync In
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12
1 GHz 16-BIT D/A 16
D/A Sync Bus
VCXO
GTX
GTX

GTX
LVDS
CONFIG FLASH 1 GB
FPGA Config Bus
PCIe Gen. 3 x8
4X
4X
48
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
Pentek, Inc.
www.pentek.com
Model 71730

A/D Converter Stage

D/A Converter Stage

The 71730 features a TI DAC5681Z 1 GHz, 16-bit D/A. The converter has an input sample rate of 1 GS/sec, allowing it to accept full-rate data from the FPGA. Additionally, the D/A includes a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is through a front panel SSMC connector.
to D/A


INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
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Model 71730

Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Installs the PMC P14 connector with 24 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
XMC Interface
The Model 71730 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to 10 Gb/sec per lane. With dual XMC connectors, the 71730 supports x8 PCIe on the first XMC connector leaving the second connector free to support user-installed transfer protocols specific to the target application.

The Model 71730 includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the module.
Model 8266
Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives a sample clock either from the front panel SSMC connector or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this latter mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock to phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or 16 to provide different lower frequency A/D and D/A clocks. A pair of front panel Sync connectors allows multiple modules to be synchronized. They accept CML inputs that drive the boards sync and gate/trigger signals. The Pentek Model 7192 and Model 9192 Cobalt Synchronizers can drive multiple 71630 Sync connectors enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connector.
Memory Resources
Model 71730 Options: -073 -076 -104 -105 XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector Description 1 GHz A/D and D/A, Virtex-7 FPGA - XMC
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz to 1 GHz Resolution: 12 bits D/A Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: 16 bits

Pentek, Inc.
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RAD AR & SDR I/O - CompactPCI RADAR

MODEL
7250, 7350 7251, 7351 7252, 7352 7253, 7353 7256, 7356 7258, 7358 Cobalt 72620, 73620, 74620 Cobalt 72621, 73621, 74621 Cobalt 72630, 73630, 74630 Cobalt 72640, 73640, 74640 Cobalt 72641, 73641, 74641 Cobalt 72650, 73650, 74650 Cobalt 72651, 73651, 74651 Cobalt 72660, 73660, 74660 Cobalt 72661, 73661, 74661 Cobalt 72662, 73662, 74662 Cobalt 72670, 73670, 74670 Cobalt 72671, 73671, 74671 Cobalt 72690, 73690, 74690 Onyx 72720, 73720, 74720 Onyx 72760, 73760, 74760 Onyx 72730, 73730, 74730
DESCRIPTION
Quad or Octal 200 MHz, 16-bit A/D with Virtex-5 FPGAs - 6U/3U cPCI 256- or 512-Channel DDC with 4 or 8 200 MHz, 16-bit A/Ds - 6U/3U cPCI 32- or 64-Channel DDC with 4 or 8 200 MHz, 16-bit A/Ds - 6U/3U cPCI 4/8-Channel DDC, 4/8 200 MHz 16-bit A/Ds, Beamformer - 6U/3U cPCI Dual/Quad 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 6U/3U cPCI Dual/Quad 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 6U/3U cPCI 3/6-Ch 200 MHz A/D, 2/4-Ch 800 MHz D/A, Virtex-6 FPGA - 6U/3U cPCI 3/6-Ch 200 MHz A/D, DDCs, DUC, 2/4-Ch. 800 MHz D/A, Virtex-6 FPGA - 6U/3U cPCI 1/2-Ch 1 GHz A/D and 1/2-Ch 1 GHz D/A, Virtex-6 FPGA - 6U/3U cPCI 1/2-Ch 3.6 GHz or 2/4-Ch 1.8 GHz 12-bit A/D, Virtex-6 FPGA - 6U/3U cPCI 1/2-Ch 3.6 GHz or 2/4-Ch 1.8 GHz 12-bit A/D, DDC, Virtex-6 FPGA - 6U/3U cPCI 2/4 500 MHz A/Ds, 1/2 DUCs, 2/4 800 MHz D/As, Virtex-6 FPGA - 6U/3U cPCI 2/4-Ch 500 MHz A/D w. DDC, DUC w. 2/4-Ch 800 MHz D/A, Virtex-6 FPGA - 6U/3U cPCI 4/8-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - 6U/3U cPCI 4/8-Ch 200 MHz A/D with DDCs, Beamformer and Virtex-6 FPGA - 6U/3U cPCI 4/8-Ch 200 MHz A/D with 32/64-Ch DDC and Virtex-6 FPGA - 6U/3U cPCI 4/8-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - 6U/3U cPCI 4/8-Ch 1.25 GHz D/A with DUC, Extend. Interpol. and Virtex-6 FPGA - 6U/3U cPCI 1/2-Ch L-Band RF Tuner, 2/4-Ch 200 MHz A/D, Virtex-6 FPGA - 6U/3U cPCI 3/6-Ch 200 MHz A/D, 2/4-Ch 800 MHz D/A, Virtex-67FPGA - 6U/3U cPCI 4/8-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - 6U/3U cPCI 1/2-Ch 1 GHz A/D and 1/2-Ch 1 GHz D/A, Virtex-7 FPGA - 6U/3U cPCI Customer Information
& & & & & &
PMC/XMC PCI x 8 PCI Express 3U VPX - FORMA T 1 FORMAT AMC 3U VPX - FORMA T 2 FORMAT

www.pentek.com
Models 7250, 7250D and 7350
Quad or Octal 200 MHz, 16-bit A/D with Virtex-5 FPGAs - cPCI
General Information
Models 7250 and 7350 are cPCI Quad 200 MHz A/Ds. They consist of one Model 7150 Quad A/D mounted on a cPCI carrier. The Model 7250 is a 6U cPCI board, while the Model 7350 is a 3U cPCI board. Model 7250D is the same as the Model 7250, except it contains two 7150s rather than one. different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T and FX100T. The SXT parts feature between 288 and 640 DSP48E Slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the Models 7250 and 7350 can be optionally configured with an LX155T in the processing FPGA position for 155,648 logic cells. A second Virtex-5 FPGA provides board interfaces including PCI-X or PCI Express. Implementing the PCI interfaces in this second FPGA, keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT or an SXT family part, providing not only interface functionality, but processing resources up to an additional 640 DSP48E Slices. Option -104 installs the J3 connector (Model 7250) or the J2 connector (Model 7350) with 16 pairs of LVDS connections to the processing FPGA and 16 pairs of LVDS connections to the interface FPGA for custom I/O. With Model 7250D, the option provides an additional 16 pairs of LVDS connections through the J5 connector to the processing FPGA and 16 pairs of LVDS connections to the interface FPGA.
A/D Converter Stage

The front end accepts four or eight fullscale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into four or eight Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into Xilinx Virtex-5 FPGAs for routing, formatting and DDC signal processing operations.
Virtex-5 FPGAs
The architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory-shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the A/D converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of
Model 7350
Model 7250D

The architecture includes a flexible timing and synchronization circuit that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus.
RF In
RF XFORMR
Features

Complete software radio interface solutions Four or eight 200 MHz, 16-bit A/Ds Up to 1 or 2 GB of DDR2 SDRAM Two or four Xilinx Virtex-5 FPGAs Up to 2.56 seconds of data capture at 200 MHz LVPECL clock/sync bus for multiboard synchronization 32 or 64 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR
RF In
RF XFORMR
RF In
RF XFORMR
Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS 200 or 135 MHz 16 BIT A/D 200 or 135 MHz 16 BIT A/D 200 or 135 MHz 16 BIT A/D 200 or 135 MHz 16 BIT A/D
TTL In
Clock/Sync Bus
LVPECL Bus
XTL OSC
To All Sections
Timing Bus
Control/ Status
32 DDR2 SDRAM 512 MB 32 DDR2 SDRAM 512 MB
PROCESSING FPGA VIRTEX 5 LX50T, SX50T, SX95T or LX155T LVDS 8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T LVDS 32 4X LVDS
PCI X INTERFACE
64
Model 7250 and 7350 Block Diagram Model 7250D doubles all resources except the PCI Bridge
FPGA I/O (Option -104)
32
PCI-X BUS
Model 7250 uses J3 Model 7350 uses J2 Model 7250D uses J3 and J5
PCI BUS
PCI-TO-PCI BRIDGE
Pentek, Inc.
www.pentek.com
Models 7250, 7250D and 7350
The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to two slave 7250Ds and three slave 7350s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.
Specifications
Model 7250 or Model 7350: 4 A/Ds Model 7250D: 8 A/Ds Model 7250D shown in the Specifications Front Panel Analog Signal Inputs (8) Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources (4): Selectable from onboard crystal oscillators, external or LVPECL clocks External Clocks (4) Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/PPS input TTL signal Field Programmable Gate Array (4) Processing FPGA: Two Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VLX155T and XCV5FX100T Interface FPGA: Two Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs the J3 and J5 cPCI connectors with 32 pairs of LVDS connections to the processing FPGA and 32 pairs of LVDS connections to the interface FPGA for custom I/O Memory DDR2 SDRAM: Up to 2 GB in four banks PCI Interface PCI Bus: 32- or 64-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U cPCI board
Memory Resources
PCI Interface
Both Models include an industry-standard interface fully compliant with PCI bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33, and 66 MHz are supported.
Model 7250 Description Quad 200 MHz, 16-bit A/D with two Virtex-5 FPGAs 6U cPCI Octal 200 MHz, 16-bit A/D with four Virtex-5 FPGAs 6U cPCI Quad 200 MHz, 16-bit A/D with two Virtex-5 FPGAs 3U cPCI FPGA I/O through cPCI J3 for 7250 or J2 for 7350; cPCI J3 and J5 for 7250D

For systems that require a PCI Express board interface, these Models can be optionally factory-configured with x4 PCI Express in the interface FPGA. Other serial protocols as well as different bus widths can be accommodated with custom IP cores.
7250D
7350
Options: -104
Pentek, Inc.
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Models 7251, 7251D and 7351
256 or 512-Channel DDC with 4 or 8 200 MHz, 16-bit A/Ds - cPCI

General Information
Models 7251 and 7351 are high-speed software radio cPCI boards. They consist of one Model 7151 Quad A/D digitizer with a factory-installed high-performance 256-channel DDC IP Core mounted on a cPCI carrier board. The Model 7251 is a 6U cPCI board, while the Model 7351 is a 3U cPCI board. Model 7251D is the same as the Model 7251, except it contains two 7151s rather than one.

A/D Converter Stage

Model 7351
Model 7251D
Features

256 or 512 channels of DDC Four or eight 200 MHz 16-bit A/Ds Independent tuning for each channel DDC decimation from 128 to 1024 in steps of 64 Independent decimation for each bank Each bank independently selects one of four A/Ds User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multiboard synchronization

These Models employ an advanced FPGA-based digital downconverter engine consisting of four identical 64-channel DDC banks. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC bank. In this way, many different configurations can be achieved including one A/D driving all 256 DDC channels and each of the four A/Ds driving its own DDC bank. Each of the 256 DDCs has an independent 32-bit tuning frequency setting that ranges from DC to s where s is the A/D sample rate.

Four output MUXs can be independently switched to deliver either A/D data or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D data or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input rate and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI bus.
CH 1 RF In
RF XFORMR 200 MHz 16-bit A D
CH 2 RF In
RF XFORMR
200 MHz 16-bit A D
CH 1 CH 2 CH 3 CH 4
M U X D G TAL DOWNCONVERTER BANK 1: CH 1-64 DEC: 128 - 1024
CH 1 I+Q
M U X
FIFO 1
CH 3 RF In
RF XFORMR
200 MHz 16-bit A D
CH 2
CH 3 CH 4
I+Q
M U X
FIFO 2
PCI-X BUS CH 1 Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 CH 3 CH 4
CH 3
CH 2 CH 3 CH 4
I+Q
M U X
FIFO 3
PCI-X NTERFACE Xilinx XC5VLX30T
PCI BUS 64 bits/ 66 MHz PCI-TO PCI BRIDGE
TTL In
CH 4 I+Q
M U X
FIFO 4
LVPECL Bus
XTAL OSC
XILINX XC5VSX95T
Timing Bus
Pentek, Inc.
www.pentek.com
Models 7251, 7251D and 7351

The architecture includes a flexible timing and synchronization circuit that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to two slave 7251Ds or three slave 7351s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.
Specifications
Model 7251 or 7351: 4 A/Ds, 256-channel DDC Model 7251D: 8 A/Ds, 512-channel DDC Model 7251D shown in the Specifications Front Panel Analog Signal Inputs (8) Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources (4): Selectable from onboard crystal oscillators, external or LVPECL clocks External Clocks (4) Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array (4) Processing FPGA: Two Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, and XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface in the standard unit; optional FPGA: XC5VSX50T PCI Interface PCI Bus: 32 or 64 bits at 66 MHz and 32 or 64 bits at 33 MHz DMA: 8 channel demand-mode and chaining controller Local Bus: 64 bits at 33, 66 and 100 MHz Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: standard 6U cPCI board
PCI Interface
Both models include an industry-standard interface fully compliant with PCI bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the boards. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported.
Model 7251 Description 256-Channel DDC with four 200 MHz, 16-bit A/Ds - 6U cPCI 512-Channel DDC with eight 200 MHz, 16-bit A/Ds - 6U cPCI 256-Channel DDC with four 200 MHz, 16-bit A/Ds - 3U cPCI
7251D
7351
Pentek, Inc.
www.pentek.com
Models 7252, 7252D and 7352

General Information
Models 7252 and 7352 are high-speed software radio cPCI boards. They consist of one Model 7152 Quad A/D digitizer with a factory-installed high-performance 32-channel DDC IP Core mounted on a cPCI carrier board. The Model 7252 is a 6U cPCI board, while the Model 7352 is a 3U cPCI board. Model 7252D is the same as the Model 7252, except it contains two 7152s rather than one.

A/D Converter Stage

Model 7352
Model 7252D
Features

32 or 64-channel DDC with four or eight banks of 8 channels Four or eight 200 MHz, 16-bit A/Ds Independent 32-bit DDC tuning for all channels DDC decimation from 16 to 8192 in steps of 8 Bandwidths: 20 kHz to 10 MHz Different decimation factors between banks User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection Power meters and threshold detectors LVPECL clock/sync bus for multiboard synchronization

These Models employ an advanced FPGA-based digital downconverter engine consisting of four identical 8-channel DDC banks. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC bank. In this way, many different configurations can be achieved including one A/D driving all 32 DDC channels and each of the four A/Ds driving its own DDC bank. Each of the 32 DDCs has an independent 32-bit tuning frequency setting that ranges from DC to s where s is the A/D sample rate.

These models feature 32 power meters that continuously measure the individual average power output of each of the 32 DDC channels. The time constant of the averaging interval for each meter is programmable up to 16K samples. In addition, 32 threshold detectors automatically send an interrupt to the processor if the average power level of any DDC falls below or exceeds a programmable threshold.
CH 1 RF In
RF XFORMR
200 MHz 16-bit A D

8X4 CHANNEL SUMMAT ON M U X DIG TAL DOWNCONVERTER BANK 1: CH 1-8 DEC: 16 - 8192
CH 1 I+Q
M U X F I F 0 1 F I F 0 2
CH 2 RF In
RF XFORMR
200 MHz 16-bit A D
POWER METER & THRESHO D DETECTORS
CH 3 RF In
RF XFORMR
200 MHz 16-bit A D
CH 2
M U X
CH 3 CH 4
M U X
DIG TAL DOWNCONVERTER BANK 2: CH 9-16 DEC: 16 - 8192
I+Q
PCI-X BUS CH 3
M U X F I F 0 3 F I F 0 4
PCI BUS 64 bits/ 66 MHz
CH 1 Sample Clk In PPS In T M NG BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 CH 3 CH 4

CH 2 CH 3 CH 4
M U X
D G TAL DOWNCONVERTER BANK 3: CH 17-24 DEC: 16 - 8192
I+Q
PCI-X NTERFACE Xilinx XC5VLX30T
TTL In
PCI-TO-PCI BRIDGE
CH 4
M U X
I+Q
LVPECL Bus
XTAL OSC
Timing Bus
XILINX XC5VSX95T
Pentek, Inc.
www.pentek.com
Models 7252, 7252D and 7352

Specifications
Model 7252 or 7352: 4 A/Ds, 32-channel DDC Model 7252D: 8 A/Ds, 64-channel DDC Model 7252D shown in the Specifications Front Panel Analog Signal Inputs (8) Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources (4): Selectable from onboard crystal oscillators, external or LVPECL clocks External Clocks (4) Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array (4) Processing FPGA: Two Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, and XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface in the standard unit; optional FPGA: XC5VSX50T PCI Interface PCI Bus: 32 or 64 bits at 66 MHz and 32 or 64 bits at 33 MHz DMA: 8 channel demand-mode and chaining controller Local Bus: 64 bits at 33, 66 and 100 MHz Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U cPCI board

PCI Interface
Both models include an industry-standard interface fully compliant with PCI bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the boards. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported.
Model 7252 Description 32-Channel DDC with four 200 MHz, 16-bit A/Ds - 6U cPCI 64-Channel DDC with eight 200 MHz, 16-bit A/Ds - 6U cPCI 32-Channel DDC with four 200 MHz, 16-bit A/Ds - 3U cPCI
7252D
7352
Pentek, Inc.
www.pentek.com
Models 7253, 7253D and 7353
4/8-Ch. DDC, 4/8 200 MHz 16-bit A/Ds, Beamformer - cPCI

General Information
Models 7253 and 7353 are high-speed software radio boards designed for processing baseband RF or IF signals from a communications receiver. They feature four 200 MHz 16-bit A/Ds (Models 7253 and 7353) or eight A/Ds (Model 7253D). Each group of four A/Ds is supported by a high-performance 4-channel installed DDC and a complete set of beamforming functions. With built-in multiboard synchronization, they are ideally matched to the requirements of real-time software radio and radar systems. Model 7253 is a 6U cPCI board while Model 7353 is a 3U cPCI board. Model 7253D is the same as the 7253 except it provides twice the resources. achieved including one A/D driving all four DDC channels and each of the four A/Ds driving its own DDC bank. Each of the DDC channels has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency.

Model 7353
Model 7253D
A/D Converter Stage

The front end accepts four or eight fullscale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into four or eight Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into Xilinx Virtex-5 FPGAs for routing, formatting and signal processing.
Features

Built-in Beamformer supports multiboard systems Programmable Power Meter and Threshold Detect per channel 6U and 3U cPCI boards 2 or 4 (Models 7253 and 7353) and 4 or 8 (Model 7753D) channels of DDC Four or eight 200 MHz, 16-bit A/Ds Independent 32-bit DDC tuning for all channels DDC decimation range from 2 to 256 or from 2 to 65536 LVPECL clock/sync bus for multiboard synchronization

These Models employ an advanced FPGA-based digital downconverter engine consisting of two or four DDC channels. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC channel. In this way, many different configurations can be
Power Meters
Each DDC includes a power meter that continuously measures the individual average power output. The power meters calculate and present average power measurements for each channel in easy-to-read registers. The time constant of the averaging interval for each meter is programmable up to 8 kilosamples. Threshold detectors can generate interrupts when the
CH 1 RF In
M U X SUMMER
SUM IN SUM OUT
AURORA G GAB T SERIAL NTERFACE F I F 0 1 F I F 0 2
4X 4X P15 XMC
CH 2 RF In
RF XFORMR
200 MHz 16-bit A D
I+Q CH 1
M U X
CH 3 RF In
RF XFORMR
200 MHz 16-bit A D
DIGITAL DOWNCONVERTER CH 1 DEC: 2 - 65536 (DEC: 2 - 256)*
I+Q
CH 4 RF In
RF XFORMR
200 MHz 16-bit A D
CH 1 CH 2 CH 3 CH 4
M U X
CH 2
M U X
I+Q
PCI-X BUS CH 3
M U X F I F 0 3 F I F 0 4
PCI BUS

M U X DIGITAL DOWNCONVERTER CH 4 (DEC: 2 - 256)*
CH 2 CH 3 CH 4
M U X
DIGITAL DOWNCONVERTER CH 3 (DEC: 2 - 256)*
I+Q
PCI-X INTERFACE
XIL NX XC5VLX30T
PCI-TO-PCI BRIDGE
CH 4
M U X
I+Q
XIL NX XC5VSX95T
Pentek, Inc.
www.pentek.com
Models 7253, 7253D and 7353

calculated power levels exceed or fall

below user-programmable thresholds, ideal for scanning and monitoring applications.
Beamformer
In addition to the A/Ds and DDCs, these Models include essential resources of a complete beamforming subsystem. First, each DDC channel provides user-programmable I & Q phase and gain adjustments to apply beamforming weights. Then, a summation block adds the four DDC output channels. An additional programmable-gain stage compensates for summation bit growth. A power meter and threshold detect block is provided for the sum output. The sum output is then delivered to the Channel 1 FIFO for delivery through the PCI bus. For larger systems, multiple Models can be chained together using a built-in Xilinx Aurora engine. It accepts an x4 gigabit sum input stream from a previous board and propagates an x4 sum output stream to the next board through the P15 XMC connector.
XMC Interface
For large systems, multiple 7253s, 7353s or 7253Ds can be chained together via a built-in Xilinx Aurora interface through the P15 XMC connector. This link creates a board-toboard summation expansion chain for creating larger multichannel beamformer systems. Xilinxs Aurora protocol is used to provide an efficient x4, 1.25 GB/sec point-to-point data path between boards.

PCI Interface
These models include an industry-standard interface fully compliant with PCI bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the boards. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported.
PHASE SHIFT
GA N
I Q
I Q
I
Q
I
Q
DIGITAL DOWNCONVERTER A
Weight Phase I Weight Phase Q Weight Gain PHASE SHIFT
AURORA PORT
SUMMAT ON EXPANS ON CHAIN IN 1 25 GByte/sec x4 Au ora Link
From Previous Boa d
P15
GA N
I
Q
I
Q
I
Q
I
Q
DIGITAL DOWNCONVERTER B
SUMMATION CHAIN BIT GROWTH COMPENSAT ON
I Q
I Q
I Q
GA N
I
Q
I
Q
I
Q
Summa ion Chain Gain POWER METER & THRESHO D DETECT C
SUMMAT ON POWER METER & THRESHO D DETECT
DIGITAL DOWNCONVERTER C
AURORA PORT
To Next Board
GA N
P15 I
Q
I Q
I Q
I
Q
DIGITAL DOWNCONVERTER D
Weight Phase I Weight Phase Q Weight Gain
Pentek, Inc.
www.pentek.com
Models 7253, 7253D and 7353

Specifications
Model 7253 or 7353: 4-Channel Beamformer Model 7253D: 8-Channel Beamformer Model 7253D shown in the Specifications Front Panel Analog Signal Inputs (8) Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources (4): Selectable from onboard crystal oscillator, external reference or LVPECL clocks External Clocks (4) Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC-coupled 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS, input/output LVPECL bus; one gate/trigger and one sync/PPS input TTL signal Digital Downconverter Type: IP core for Xilinx Virtex-5 Qty of DDC Channels: 4 or 8 Center Frequency Tuning: 8 tuning words, one for each DDC channel Center Frequency Tuning Range: DC to s with 32 bit resolution NCO SFDR: 120 dBFS Channel Phase Offset Adjustment: 32-bit resolution Channel Gain Adjustment: 32-bit resolution Input Selection for DDC Banks: Any channel can select any of the four A/Ds Decimation Range (N): 2-Channel Mode: 2 to 65536 4-Channel Mode: 2 to 256 FIR Filter: Default passband 0.8*s/N with 0.2 dB passband ripple and 100 dB adjacent channel rejection FIR Filter Coefficients: 18 bits, userprogrammable (default values provided) Qty FIR Filter Taps: 28*N/8 Output Format: 24 bits I + 24 bits Q Output Spectrum Modes: Normal or frequency-reversed Output Spectrum Offset: No offset or offset by one-half the output bandwidth Beamformer Summation: Four or eight channels onboard; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Output Multiplexer and FIFO Qty Output FIFOs: Eight FIFO Source Selection: Independent multiplexer selects DDC output or A/D PCI Interface PCI Bus: 32 or 64 bits at 66 MHz and 32 or 64 bits at 33 MHz DMA: 8 channel demand-mode and chaining controller Local Bus: 64 bits at 33, 66 and 100 MHz Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U cPCI board
Model 7253 Description 4-Channel DDC with four 200 MHz, 16-bit A/Ds and Beamformer - 6U cPCI 8-Channel DDC with eight 200 MHz, 16-bit A/Ds and Beamformers - 6U cPCI 4-Channel DDC with four 200 MHz, 16-bit A/Ds and Beamformer - 3U cPCI
7253D
7353
Pentek, Inc.
www.pentek.com
Models 7256, 7256D and 7356
Dual/Quad 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - cPCI
General Information
Models 7256 and 7356 are cPCI boards that include two 400 MHz A/Ds, 800 MHz D/As and Virtex-5 FPGAs. They consist of one Model 7156 PMC module mounted on a cPCI carrier. The Model 7652 is a 6U cPCI board, while the Model 7356 is a 3U cPCI board. Model 7256D is the same as the Model 7652, except it contains two 7156s rather than one.
Virtex-5 FPGAs
The architecture includes two or four Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family part, providing not only interface
RF In
RF XFORMR
A/D Converter Stage

The front end accepts two or four full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into TI ADS5474 14-bit 400 MHz A/Ds. Designed with a 750 MHz input bandwidth, the A/Ds are excellent for undersampling applications. The digital outputs are delivered into the Virtex-5 processing FPGA for signal processing, data capture or routing to other board resources. Model 7356 Model 7256D

Features

Complete software radio interface solution Two or four 400 MHz, 14-bit A/Ds One or two digital upconverters Two or four 800 MHz, 16-bit D/As Up to 2 GB of DDR2 SDRAM Two or four Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 or 64 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR
RF Out
RF XFORMR
RF Out
RF XFORMR
A/D Clock Bus
400 MHz 14 BIT A/D
400 MHz 14 BIT A D
800 MHz 16 BIT D/A
800 MHz 16 BIT D A
TTL Gate / Trig TTL Sync / PPS Sample C k Sync C k Gate A Gate B Sync PPS
DIGITAL UPCONVERTER
D/A Clock Bus

Timing Bus
VCXO
Control/ Status
PROCESSING FPGA VIRTEX 5 LX50T LX155T SX50T SX95T or FX100T LVDS 8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T LVDS 32
4X
PCI X INTERFACE
64
PGA /O (Option -104)
32
PCI-X BUS
PCI-TO PC BRIDGE
PCI BUS
Pentek, Inc.
www.pentek.com
Models 7256, 7256D and 7356
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 installs the J3 connector (Model 7256) or the J2 connector (Model 7356) with 16 pairs of LVDS connections to the processing FPGA and 16 pairs to the interface FPGA for custom I/O. With Model 7256D, the option provides an additional 16 pairs of LVDS connections through the J5 connector to the processing FPGA and 16 pairs to the interface FPGA.
Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (4) Type: TI ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters (4) Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs (4) Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 400 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays (4) Processing FPGA: Two Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: Two Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs the J3 and J5 cPCI connectors with 32 pairs of LVDS connections to the processing FPGA and 32 pairs of LVDS connections to the interface FPGA for custom I/O Environmental Specifications Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U cPCI board
PCI Interface
All Models include an industrystandard interface fully compliant with PCI bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported.

Two internal timing buses can provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An internal clock generator receives an external sample clock from the front panel SMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage controlled crystal oscillator. In this mode, the front panel SMC connector can be used to provide a 10 MHz system reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to two slave 7256Ds and three slave 7356s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Memory Resources Ordering Information

Model 7256 Description Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 6U cPCI Quad 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 6U cPCI Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U cPCI
7256D
Up to four independent 512 MB banks of DDR2 SDRAM are available to the processing FPGAs. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.
7356
Specifications
Models 7256 or 7356: Dual version Model 7256D: Quad version Model 7256D shown in the Specifications Front Panel Analog Signal Inputs (4) Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB
Options: -104 FPGA I/O through cPCI J3 for 7256 or J2 for 7356; cPCI J3 and J5 for 7256D
Pentek, Inc.
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Models 7258, 7258D and 7358
General Information
Models 7258 and 7358 are cPCI boards that include two or four 500 MHz A/Ds and 800 MHz D/As and Virtex-5 FPGAs. They consist of one Model 7158 PMC module mounted on a cPCI carrier. The Model 7258 is a 6U cPCI board, while the Model 7358 is a 3U cPCI board. Model 7258D is the same as the Model 7258, except it contains two 7158s rather than one.
Virtex-5 FPGAs
The architecture includes two or four Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family part, providing not only interface
RF In
RF XFORMR
A/D Converter Stage

The front end accepts two or four full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into TI ADS5463 12-bit 500 MHz A/Ds. Designed with a 750 MHz input bandwidth, the A/Ds are excellent for undersampling applications. The digital outputs are delivered into the Virtex-5 processing FPGA for signal processing, data capture or routing to other board resources. Model 7358 Model 7258D

Features

Complete software radio interface solution Two or four 500 MHz, 12-bit A/Ds One or two digital upconverters Two or four 800 MHz, 16-bit D/As Up to 2 GB of DDR2 SDRAM Two or four Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 or 64 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR
RF Out
RF XFORMR
RF Out
RF XFORMR
A/D Clock Bus
500 MHz 12 BIT A/D
500 MHz 12 BIT A D
800 MHz 16 BIT D/A
800 MHz 16 BIT D A
DIGITAL UPCONVERTER
D/A Clock Bus

Timing Bus
VCXO
Control/ Status
PROCESSING FPGA VIRTEX 5 LX50T LX155T SX50T SX95T or FX100T LVDS 8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T LVDS 32
4X
PCI X INTERFACE
64
PGA /O (Option -104)
32
PCI-X BUS
PCI-TO PC BRIDGE
PCI BUS
Pentek, Inc.
www.pentek.com
Models 7258, 7258D and 7358
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 installs the J3 connector (Model 7258) or the J2 connector (Model 7358) with 16 pairs of LVDS connections to the processing FPGA and 16 pairs to the interface FPGA for custom I/O. With Model 7258D, the option provides an additional 16 pairs of LVDS connections through the J5 connector to the processing FPGA and 16 pairs to the interface FPGA.
Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (4) Type: TI ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits D/A Converters (4) Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs (4) Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 500 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays (4) Processing FPGA: Two Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: Two Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs the J3 and J5 cPCI connectors with 32 pairs of LVDS connections to the processing FPGA and 32 pairs of LVDS connections to the interface FPGA for custom I/O Environmental Specifications Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U cPCI board
PCI Interface
All Models include an industrystandard interface fully compliant with PCI bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported.

Two internal timing buses can provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An internal clock generator receives an external sample clock from the front panel SMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage controlled crystal oscillator. In this mode, the front panel SMC connector can be used to provide a 10 MHz system reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to two slave 7258Ds and three slave 7358s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Model 7258 Description Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 6U cPCI Quad 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 6U cPCI Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U cPCI
Memory Resources
7258D
7358
Options: -104 FPGA I/O through cPCI J3 for 7258 or J2 for 7358; cPCI J3 and J5 for 7258D -140 1 GB DDR2 SDRAM, Models 7258 and 7358; 2 GB DDR2 SDRAM, Model 7258D
Specifications
Models 7258 or 7358: Dual version Model 7258D: Quad version Model 7258D shown in the Specifications Front Panel Analog Signal Inputs (4) Input Type: Transformer-coupled, front panel female SMC connectors
Pentek, Inc.
www.pentek.com
! w e N
Models 72620 73620 and 74620
3- or 6-Channel 200 MHz A/D, 2- or 4-Channel 800 MHz D/A, Virtex-6 FPGA - cPCI
General Information
Models 72620, 73620 and 74620 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71620 XMC modules mounted on a cPCI carrier board. Model 72620 is a 6U cPCI board while the Model 73620 is a 3U cPCI board; both are equipped with one Model 71620 XMC. Model 74620 is a 6U cPCI board with two XMC modules rather than one. These models include three or sixA/Ds, one or two DUCs, two or four D/As and four or eight banks of memory. clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable these models to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include three or six A/D acquisition and one or two D/A waveform playback IP modules. IP modules for either DDR3 or QDRII+ memories, controllers for all data

The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73620; J3 connector, Model 72620; J3 and J5 connectors, Model 74620.
Model 74620 Model 73620
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three or six 200 MHz 16-bit A/Ds One or two DUCs (digital upconverters) Two or four 800 MHz 16-bit D/As Up to 2 or 4 GB of DDR3 SDRAM; or: 32 MB or 64MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Block Diagram, Model 72620 Model 74620 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In
RF In
RF In
RF In
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
16
Timing Bus
VCXO

LVDS
MODEL 73620 INTERFACES ONLY VIRTEX-6 FPGA

LVDS
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
40
x4 PCIe
4X
GTX
QDRII+ option 150 40
PCIe to PCI BRIDGE
From/To Other XMC Module of MODEL 74620
Optional FPGA I/O (Option -104) J2
PCIe to PCI BRIDGE
DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
PCI to PCI BRIDGE
PCI/PCI-X BUS 32-bit, 33/66 MHz
Memory Banks 1 & 2
Memory Banks 3 & 4
PCI/PCI-X BUS 32/64-bit, 33/66 MHz
Pentek, Inc.
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Models 72620 73620 and 74620

These models feature three or six A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from any of the three A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
A/D Converter Stage
The front end accepts three or six fullscale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into three or six Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

One or two TI DAC5688 DUCs (digital upconverters) and D/As accept baseband real or complex data streams from the FPGA and provide that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes, the DAC5688 provides interpolation factors of 2x, 4x and 8x.
Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory.

to D/A D/A loopback

D/A Waveform Playback IP Modules

These models include one or two factory-installed sophisticated D/A Waveform Playback IP modules. Linked-list controllers allow users to easily play back to the dual D/As waveforms stored in either on-board memory or off-board host memory. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 or 128 individual link entries can be chained together to create complex waveforms with a minimum of programming.
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
MEMORY CONTROL
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
40 FPGA I/O
Pentek, Inc.
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Models 72620 73620 and 74620
Each QDRII+ SRAM bank can be up
to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Sample Clock Sources (2 or 4) On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus (1 or 2): 26-pin connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73620; J3 connector, Model 72620; J3 and J5 connectors, Model 74620 Memory Banks (1 or 2) Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks. 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73620: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73620: 32 bits only.
Specifications
Model 72620 or Model 73620: 3 A/Ds, 1 DUC, 2 D/As Model 74620: 6 A/Ds, 2 DUCs, 4 D/As Front Panel Analog Signal Inputs (3 or 6) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (3 or 6) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits D/A Converters (2 or 4) Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs (2 or 4) Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz
Model 72620 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-6 FPGA 6U cPCI 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-6 FPGA 3U cPCI 6-Channel 200 MHz A/D and 4-Channel 800 MHz D/A and two Virtex-6 FPGAs - 6U cPCI XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73620; J3 connector, Model 72620; J3 and J5 connectors, Model 74620 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
73620
74620
Options: -062 -064 -104
-150
-160
-155
-165
Pentek, Inc.
www.pentek.com
! w e N
Model 72621, 73621 and 74621
3 or 6-Channel 200 MHz A/D with DDC, DUC with 2- or 4-Channel 800 MHz D/A, with Virtex-6 FPGA - cPCI
General Information
Models 72621, 73621 and 74621 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71621 XMC modules mounted on a cPCI carrier board. Model 72621 is a 6U cPCI board while the Model 73621 is a 3U cPCI board; both are equipped with one Model 71621 XMC. Model 74621 is a 6U cPCI board with two XMC modules rather than one. These models include three or six A/Ds, three or six multiband DDCs, one ot two DUCs, two or four D/As and four or eight banks of memory. ideal for matching playback rates to the data and decimation rates of the acquisition modules. IP modules for either DDR3 or QDRII+ memories, controllers for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions, without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include three or six A/D acquisition and one or two D/A waveform playback IP modules. Each of the acquisition IP modules contains a powerful, programmable DDC IP core. The waveform playback IP module contains an intrepolation IP core,
Sample Clk / Reference Clk In

The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed.
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three or six 200 MHz 16-bit A/Ds Three or six multiband DDCs (digital downconverters) One or two DUCs (digital upconverters) Two or four 800 MHz 16-bit D/As One or two multiboard programmable beamformers Up to 2 or 4 GB of DDR3 SDRAM; or: 32 MB or 64MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
16
Timing Bus
VCXO

GTX

LVDS
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
4X
4X
x4 PCIe
4X
GTX
QDRII+ option 150
Aurora 4X I/O Sum from previous board J2
4X
Sum to next board
PCIe to PCI BRIDGE
PCIe to PCI BRIDGE
Sum to next board
PCI to PCI BRIDGE
Memory Banks 1 & 2
Memory Banks 3 & 4
J3
Pentek, Inc.
www.pentek.com
Model 72621, 73621 and 74621

A/D Acquisition IP
Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as three different output bandwidths for the board. Decimations can be programmed from 2 to 65,536 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the three DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple boards can be chained together via the built-in Xilinx Aurora gigabit serial interfaces through the J3 and J5 connectors. This allows summation across channels on multiple boards.
Modules
Beamformer IP Cores
In addition to the DDCs, these models feature one or two complete beamforming subsystems. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers.

The factory-installed functions include sophisticated D/A Waveform Playback IP modules. Linked-list controllers allow users to easily play back to the dual D/As waveforms stored in either on-board memory or off- board host memory . Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 or 128 individual link entries can be chained together to create complex waveforms with a minimum of programming.
from A/D Ch 1
from A/D Ch 2
to D/A
INPUT MULTIPLEXER
DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all three DDCs or each of the three A/Ds driving its own DDC.
MEMORY CONTROL
MUX
DDC CORE
DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
sum out sum in
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
4X PCIe
Pentek, Inc.
www.pentek.com
Model 72621, 73621 and 74621
A/D Converter Stage
The front end accepts three or six analog HF or IF inputs on front panel SSMC connectors with transformer coupling into three or six Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources. nate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

One or two TI DAC5688 DUCs (digital upconverters) and D/As accept baseband real or complex data streams from the FPGA and provide that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x. In addition to the DAC5688, an FPGA based interpolator core provides additional interpolation from 2x to 65,536x. The two interpolators can be combined to create a total range from 2x to 524,288x.
Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alter-
PCI-X Interface
Pentek, Inc.
www.pentek.com
Model 72621, 73621 and 74621
Specifications
Model 72621 or Model 73621: 3 A/Ds, 3 DDCs, 1 DUC, 2 D/As Model 74621: 6 A/Ds, 6 DDCs, 2 DUCs, 4 D/As Front Panel Analog Signal Inputs (3 or 6) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (3 or 6) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters (3 or 6) Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters (2 or 4) Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolators (1 or 2) Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformers (1 or 2) Summation: Three channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via J3 connector using Aurora protocol; via J3 and J5 for Model 74621 Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs (2 or 4) Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources (2 or 4) On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus (1 or 2): 26-pin connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Memory Banks (1 or 2) Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73621: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
Model 72621 Description 3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA 6U cPCI 3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA 3U cPCI 6-Channel 200 MHz A/D with DDCs, DUCs with 4-Channel 800 MHz D/A, and two Virtex-6 FPGAs 6U cPCI XC6VLX240T XC6VSX315T Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
73621
74621
Options: -062 -064 -150
-160
-155
-165
Pentek, Inc.
www.pentek.com
! ew N
Models 72630, 73630 and 74630
1- or 2-Channel 1 GHz A/D, 1- or 2-Channel 1 GHz D/A with Virtex-6 FPGA - cPCI
General Information
Models 72630, 73630 and 74630 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71630 XMC modules mounted on a cPCI carrier board. Model 72630 is a 6U cPCI board while the Model 73630 is a 3U cPCI board; both are equipped with one Model 71630 XMC. Model 74630 is a 6U cPCI board with two XMC modules rather than one. These models include one or two 1 GHz A/D and D/A converters and four or eight banks of memory clocking and synchronization functions, a test signal generator and a PCIe interface complete the factory-installed functions and enable these modles to operate as complete turnkey solutions, without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include one or two A/D acquisition and one or two D/A waveform playback IP module. IP modules for either DDR3 or QDRII+ memories, controllers for all data

Model 74630
Model 73630
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One or two 1 GHz 12-bit A/D One or two 1 GHz 16-bit D/A Up to 2 or 4 GB of DDR3 SDRAM; or: 16 MB or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF Out
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Sync In
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12
1 GHz 16-BIT D/A 16
D/A Sync Bus

VCXO

LVDS

LVDS
GTX
16
16
16
16
40
x4 PCIe
4X
GTX
40
Memory Banks 1 & 2 DDR3 option 155 PCIe QDRII+ SRAM 8 MB QDRII+ SRAM 8 MB
PCIe to PCI BRIDGE
to PCI Optional BRIDGE FPGA I/O (Option -104)
PCI to PCI BRIDGE
QDRII+ option 150
J2
Pentek, Inc.
www.pentek.com
Models 72630, 73630 and 74630

These models feature one or two A/D Acquisition IP Modules for easy capture and data moving. The IP module can receive data from the A/D, a test signal generator, or from the D/A Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for storing data in transient capture mode. The memory banks are supported with a DMA engine for moving A/D data through the PCIe interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processors job of identifying and executing on the data.
A/D Converter Stage
The front end accepts one or two analog HF or IF input on front panel SSMC connectors with transformer coupling into one or two Texas Instruments ADS5400 1 GHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or 16 to provide different lower frequency A/D and D/A clocks. A pair of front panel Sync connectors allows multiple boards to be synchronized. They accept CML inputs that drive the boards sync and gate/trigger signals. The Pentek Model 7292 and Model 9192 Cobalt Synchronizers can drive multiple Sync connectors enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connector.
D/A Converter Stage

The 71630 features one or two TI DAC5681Z 1 GHz, 16-bit D/As. The converters have an input sample rate of 1 GSPS, allowing them to acept full rate data from the FPGA. Additionally, the D/As include a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is through front panel SSMC connectors.
Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

to D/A

The factory-installed functions include one or two sophisticated D/A Waveform Playback IP modules. A linked-list controller allows users to easily play back waveforms stored in either on-board memory or offboard host memory to the D/A. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 or 128 individual link entries can be chained together to create complex waveforms with a minimum of programming.
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
(supports user installed IP) 4X PCIe 40 FPGA I/O
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
Pentek, Inc.
www.pentek.com
Models 72630, 73630 and 74630
PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73630: 32 bits only. External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73630; J3 connector, Model 72630; J3 and J5 connectors, Model 74630 Memory Banks (1 or 2) Option 150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73630: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
Specifications
Model 72630 or Model 73630: 1 A/D, 1 D/A Model 74630: 2 A/Ds, 2 D/As Front Panel Analog Signal Inputs (1 or 2) Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converters (1 or 2) Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz to 1 GHz Resolution: 12 bits D/A Converters (1 or 2) Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: 16 bits Front Panel Analog Signal Outputs (1 or 2) Output Type: Transformer-coupled, front panel female SSMC connectors Sample Clock Sources (1 or 2) On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock
Model 72630 73630 74630 Options: -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73630; J3 connector, Model 72630; J3 and J5 connectors, Model 74630 -160 Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required -002* -062 -064 -104 Description 1 GHz A/D and D/A, Virtex-6 FPGA - 6U cPCI 1 GHz A/D and D/A, Virtex-6 FPGA - 3U cPCI Two 1 GHz A/D and D/A, Virtex-6 FPGA - 6U cPCI
Pentek, Inc.
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! w e N
Models 72640, 73640 and 74640
1- or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - cPCI
General Information
Models 72640, 73640 and 74640 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71640 XMC modules mounted on a cPCI carrier board. Model 72640 is a 6U cPCI board while the Model 73640 is a 3U cPCI board; both are equipped with one Model 71640 XMC. Model 74640 is a 6U cPCI board with two XMC modules rather than one. These models include one or two 3.6 GHz, 12-bit A/D converters and four or eight banks of memory. generator and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions, without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include one or two A/D acquisition IP modules. In addition, IP modules for DDR3 memories, controllers for all data clocking and synchronization functions, a test signal

Model 74640
Model 73640
Features

Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One or two 1-channel mode with 3.6 GHz, 12-bit A/Ds Two or four 2-channel mode with 1.8 GHz, 12-bit A/Ds 2 or 4 GB of DDR3 SDRAM Sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
3.6 GHz (1 Channel) or 1.8 GHz (2 Channel) 12-bit A/D

12 12
Sync Bus
VIRTEX-6 FPGA LX130T, LX240T or SX315T MODEL 73640 INTERFACES ONLY VIRTEX-6 FPGA
LVDS LVDS
GTX
40
GTX
x4 PCIe
4X
40
PCIe
Memory Banks 1 & 2
Memory Banks 3 & 4
PCIe to PCI BRIDGE
PCI to PCI BRIDGE
J2
Pentek, Inc.
www.pentek.com
Models 72640, 73640 and 74640
A/D Converter Stage
The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing these models to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple boards. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple boards can be synchronized using the Cobalt high speed sync board to drive the sync bus.
Memory Resources
The Cobalt architecture supports four or eight independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and data capture capabilities. Built-in memory functions include an A/D data transient capture mode for taking snapshots of data for transfer to a host computer. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

These models feature one or two A/D Acquisition IP Modules for easy capture and data moving. The IP modules can receive data from the A/Ds, or a test signal generator. The IP modules have associated memory banks for buffering data in FIFO mode or for storing data in transient capture mode. In single-channel mode, all banks are used to store the single-channel of input data. In dual-channel mode, memory banks 1 and 2 store data from input channel 1 and memory banks 3 and 4 store data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving A/D data through the PCIe interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processors job of identifying and executing on the data.
PCI-X Interface

These models accept a 1.8 GHz dualedge sample clock via front panel SSMC connectors. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multi-pin sync bus connector allows multiple boards to be
from A/D
from A/D

MEMORY CONTROLLER
(supports user installed IP) to Mem Bank 1 to Mem Bank 2 4X PCIe 40 FPGA I/O to Mem Bank 3 to Mem Bank 4
Pentek, Inc.
www.pentek.com
Models 72640, 73640 and 74640
Specifications
Model 72640 or Model 73640: One A/D Model 74640: Two A/Ds Front Panel Analog Signal Inputs (2 or 4) Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter (1 or 2) Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Sample Clock Sources (1 or 2) Front panel SSMC connector Sync Bus (1 or 2) Multi-pin connectors, bus includes gate, reset and in and out ref clock External Trigger Input (1 or 2) Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73640; J3 connector, Model 72640; J3 and J5 connectors, Model 74640 Memory Banks (1 or 2) Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73640: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
Model 72640 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - 6U cPCI 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - 3U cPCI 2-Ch. 3.6 GHz or 4-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - 6U cPCI
73640
74640
Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T XC6VSX315T LVDS I/O between the FPGA and J2 connector, Model 73640; J3 connector, Model 72640; J3 and J5 connectors, Model 74640 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
www.pentek.com
! w e N
Models 72641, 73641 and 74641
1- or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit A/D, w/ Wideband DDC, Virtex-6 FPGA - cPCI
General Information
Models 72641, 73641 and 74641 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71641 XMC modules mounted on a cPCI carrier board. Model 72641 is a 6U cPCI board while the Model 73641 is a 3U cPCI board; both are equipped with one Model 71641 XMC. Model 74641 is a 6U cPCI board with two XMC modules rather than one. These models include one or two 3.6 GHz, 12-bit A/D converters and four or eight banks of memory. and synchronization functions, a test signal generator and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions, without the need to develop any FPGA IP. For applications that require additional control and status signals, option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73641; J3 connector, Model 72641; J3 and J5 connectors, Model 74641.
A/D Converter Stage


The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include one or two A/D acquisition IP modules. In addition, IP modules for DDR3 memories, controllers for all data clocking
Model 74641
Model 73641
Features

Ideal radar and software radio interface solution One or two 1-channel mode with 3.6 GHz, 12-bit A/Ds Two or four 2-channel mode with 1.8 GHz, 12-bit A/Ds Programmable one- or twochannel DDC (Digital Downconverter) 2 or 4 GB of DDR3 SDRAM Sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus

12 12
Sync Bus
VIRTEX-6 FPGA SX315T MODEL 73641 INTERFACES ONLY VIRTEX-6 FPGA

LVDS LVDS
GTX
40
GTX
x4 PCIe
4X
40
PCIe
Memory Banks 1 & 2
Memory Banks 3 & 4
PCIe to PCI BRIDGE
PCI to PCI BRIDGE
J2
Pentek, Inc.
www.pentek.com
Models 72641, 73641 and 74641

DDC IP Cores

These models accept a 1.8 GHz dualedge sample clock via front panel SSMC connectors. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multipin sync bus connector allows multiple boards to be synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple boards can be synchronized using the Cobalt high-speed sync board to drive the sync bus.
Memory Resources
The Cobalt architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and data capture capabilities. Built-in memory functions include an A/D data transient capture mode for taking snapshots of data for transfer to a host computer.
from A/D
from A/D

to Mem Bank 1
to Mem Bank 2
4X 4x PCIe
FPGA GPIO
40
to Mem Bank 3
to Mem Bank 4
Pentek, Inc.
www.pentek.com
Models 72641, 73641 and 74641
PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73641: 32 bits only. Sample Clock Sources (1 or 2) Front panel SSMC connector Sync Bus (1 or 2) Multi-pin connectors, bus includes gate, reset and in and out ref clock External Trigger Input (1 or 2) Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73640; J3 connector, Model 72640; J3 and J5 connectors, Model 74640 Memory Banks (1 or 2) Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73641: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
Specifications
Model 72641 or Model 73641: One A/D Model 74641: Two A/Ds Front Panel Analog Signal Inputs (2 or 4) Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converters (1 or 2) Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Digital Downconverters (2 or 4) Modes: One or two channels, programmable Supported Sample Rate: One-channel mode: 3.6 GHz, two-channel mode: 1.8 GHz Decimation Range: One-channel mode: 8x, 16x or 32x, two-channel mode: 4x, 8x, or 16x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: User-programmable 18-bit coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation
Model 72641 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, with Wideband DDC, Virtex-6 FPGA - 6U cPCI 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, with Wideband DDC, Virtex-6 FPGA - 3U cPCI 2-Ch. 3.6 GHz or 4-Ch. 1.8 GHz, 12-bit A/D, with Wideband DDC, Virtex-6 FPGA - 6U cPCI
73641
74641
Options: -002* -064* -104 -2 FPGA speed grade XC6VSX315T LVDS I/O between the FPGA and J2 connector, Model 73640; J3 connector, Model 72640; J3 and J5 connectors, Model 74640 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
www.pentek.com
! w e N
Models 72650, 73650 and 74650
2- or 4-Channel 500 MHz A/D, DUC with 2-or 4-Channel 800 MHz D/A, Virtex-6 FPGA - cPCI
General Information
Models 72650, 73650 and 74650 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71650 XMC modules mounted on a cPCI carrier board. Model 72650 is a 6U cPCI board while the Model 73650 is a 3U cPCI board; both are equipped with one Model 71650 XMC. Model 74650 is a 6U cPCI board with two XMC modules rather than one. These models include two or four A/Ds, one or two DUCs, two or four D/As and four banks of memory. clocking and synchronization functions, a test signal generator and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions, without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these modles include two or four A/D acquisition and one or two D/A waveform playback IP modules. IP modules for either DDR3 or QDRII+ memories, controllers for all data

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two or four 500 MHz 12-bit A/Ds One or two DUCs (digital upconverters) Two or four 800 MHz 16-bit D/As Up to 2 or 4 GB of DDR3 SDRAM; or: 32 MB or 64MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF Out
RF Out
A/D Clock/Sync Bus
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
500 MHz 12-BIT A/D
500 MHz 12-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
VCXO

LVDS
Timing Bus

LVDS
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
40
x4 PCIe
4X
GTX
QDRII+ option 150 40 to PCI Optional BRIDGE FPGA I/O (Option -104) PCIe DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
PCIe to PCI BRIDGE
PCI to PCI BRIDGE
Memory Banks 1 & 2
Memory Banks 3 & 4
J2
Pentek, Inc.
www.pentek.com
Models 72650, 73650 and 74650

These models feature two A/D Acquisition IP Modules for easy capture and data moving. Each IP module can receive data from either of the two A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp, and data length information. These actions simplify the host processors job of identifying and executing on the data.
A/D Converter Stage
The front end accepts two or four full scale analog HF or IF inputs on front panel SSMC connectors at +5 dBm into 50 ohms with transformer coupling into two or four Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an onboard programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

One or two TI DAC5688 DUCs and D/As accept a baseband real or complex data streams from the FPGA and provide that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x.
Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the

from A/D Ch 1 from A/D Ch 2
to D/A D/A loopback TEST SIGNAL GENERATOR

These models include one or two factory-installed sophisticated D/A Waveform Playback IP modules. Linked-list controllers allow users to easily play back waveforms stored in either on-board memory or off- board host memory to the dual D/As. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 or 128 individual link entries can be chained together to create complex waveforms with a minimum of programming.
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
MEMORY CONTROL
to Mem Bank 3
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
40 FPGA I/O
Pentek, Inc.
www.pentek.com
Models 72650, 73650 and 74650
boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
Sample Clock Sources (2 or 4) On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus (1 or 2): 26-pin front panel connector LVPECL bus includes, clock/sync/ gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73650; J3 connector, Model 72650; J3 and J5 connectors, Model 74650 Memory Banks (1 or 2) Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73650: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
PCI-X Interface

Model 72650 Description Two 500 MHz A/Ds, One DUC, Two 800 MHz D/As with Virtex-6 FPGA - 6U cPCI Two 500 MHz A/Ds, One DUC, Two 800 MHz D/As with Virtex-6 FPGA - 3U cPCI Four 500 MHz A/Ds, Two DUCs, Four 800 MHz D/As with Virtex-6 FPGA - 6U cPCI
73650
74650
Options: -002* -014 -062 -064 -104 -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73650; J3 connector, Model 72650; J3 and J5 connectors, Model 74650 -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -160 Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required
Models 72650 and 73650: 2 A/Ds, 1 DUC, 2 D/As Model 74650: 4 A/Ds, 2 DUCs, 4 D/As Front Panel Analog Signal Inputs (2 or 4) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) (2 or 4) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (option 014) (2 or 4) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters (2 or 4) Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz, max. Output IF: DC to 400 MHz, max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz, max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs (2 or 4) Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz
Pentek, Inc.
www.pentek.com
! w e N
Model 72651, 73651 and 74651
General Information
Models 72651, 73651 and 74651 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71651 XMC modules mounted on a cPCI carrier board. Model 72651 is a 6U cPCI board while the Model 73651 is a 3U cPCI board; both are equipped with one Model 71651 XMC. Model 74651 is a 6U cPCI board with two XMC modules rather than one. These models include two or four A/Ds, two or four multiband DDCs, one ot two DUCs, two or four D/As and three or six banks of memory. ideal for matching playback rates to the data and decimation rates of the acquisition modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions, without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include two or four A/D acquisition and one or two D/A waveform playback IP modules. Each of the acquisition IP modules contains a powerful, programmable DDC IP core. The waveform playback IP module contains an intrepolation IP core,

RF Out
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two or four 500 MHz 12-bit A/Ds Two or four multiband DDCs (digital downconverters) Two or four 800 MHz 16-bit D/As One or two DUCs (digital upconverters) One or two multiboard programmable beamformers Up to 2 or 4 GB of DDR3 SDRAM; or 16 or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization
RF In
RF In
RF Out
A/D Clock/Sync Bus
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
500 MHz 12-BIT A/D
500 MHz 12-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
VCXO

GTX
Timing Bus

LVDS
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
4X
4X
4X
PCIe to PCI BRIDGE
GTX
QDRII+ option 150
QDRII+ option 160
4X
PCIe to PCI Sum to BRIDGE
next board
Sum to next board
PCI to PCI BRIDGE
Memory Banks 1 & 2
J3
Pentek, Inc.
www.pentek.com
Model 72651, 73651 and 74651

These models feature two or four A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from either of the two A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
frequency. Each DDC can have its own unique decimation setting, supporting as many as two or four different output bandwidths for the board. Decimations can be programmed from 2 to 131,072 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 16-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple models can be chained together via a built-in Xilinx Aurora gigabit serial interface through the dual 4X serial connector. This allows summation across channels on multiple boards.
Beamformer IP Core
In addition to the DDCs, these models feature one or two complete beamforming subsystems. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average

The factory-installed functions in these models include one or two sophisticated D/A Waveform Playback IP modules. A linked-list controller allows users to easily play back to the dual D/As waveforms stored in either on-board memory or offboard host memory . Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 individual link entries can be chained together to create complex waveforms with a minimum of programming.
from A/D Ch 1

INPUT MULTIPLEXER
to D/A


DDC IP Cores
MEMORY CONTROL
MUX
DDC CORE
to Mem Bank 1
to Mem Bank 2
to Mem Bank 4
sum out sum in
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
4X PCIe
Pentek, Inc.
www.pentek.com
Model 72651, 73651 and 74651
A/D Converter Stage
The front end accepts two or four analog HF or IF inputs on front panel SSMC connectors with transformer coupling into two or four Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources. nate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

One or two TI DAC5688 DUCs (digital upconverters) and D/As accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x. In addition to the DAC5688, an FPGA based interpolator core provides additional interpolation from 2x to 65,536x. The two interpolators can be combined to create a total range from 2x to 524,288x.
Memory Resources
The Cobalt architecture supports up to three or six independent memory banks which can be configured with QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boardss DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

PCI-X Interface
Pentek, Inc.
www.pentek.com
Model 72651, 73651 and 74651
Specifications
Model 72651 or Model 73651: 2 A/Ds, 2 DDCs, 1 DUC, 2 D/As Model 74651: 4 A/Ds, 4 DDCs, 2 DUCs, 4 D/As Front Panel Analog Signal Inputs (2 or 4) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) (2 or 4) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (Option -014) (2 or 4) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits Digital Downconverters (2 or 4) Decimation Range: 2x to 131,072x in two programmable stages of 2x to 256x and one fixed 2x stage LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 16-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters (2 or 4) Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolators (1 or 2) Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformers (1 or 2) Summation: Two channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via a dual 4X connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs (2 or 4) Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources (2 or 4) On-board clock synthesizer generates two clocks: one A/D clock and one D/ A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus (1 or 2): 26-pin connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX240T-2 Optional: Xilinx Virtex-6 XC6VSX315T-2 Memory (1 or 2) Option -150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option -155 or -165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73651: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
Model 72651 Description 2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA 6U cPCI 2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA 3U cPCI 4-Channel 500 MHz A/D with DDCs, DUCs with 4-Channel 800 MHz D/A, and two Virtex-6 FPGAs 6U cPCI
73651
74651
Options: 002* -014 -062 -064 -150 -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240T FPGA XC6VSX315T FPGA Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required
Pentek, Inc.
www.pentek.com
! w e N
Models 72660, 73660 and 74660
4- or 8-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - cPCI

General Information
Models 72660, 73660 and 74660 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71660 XMC modules mounted on a cPCI carrier board. Model 72660 is a 6U cPCI board while the Model 73660 is a 3U cPCI board; both are equipped with one Model 71660 XMC. Model 74660 is a 6U cPCI board with two XMC modules rather than one. These models include four or eight A/Ds and four or eight banks of memory. generator, and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions without the need to develop FPGA IP.

The Pentek Cobalt Architecture features Virtex-6 FPGAs. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factoryinstalled functions of these models include four or eight A/D acquisition IP modules. IP modules for either DDR3 or QDRII+ memories, controllers for all data clocking and synchronization functions, a test signal

Model 74660
Model 73660
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four or eight 200 MHz 16-bit A/Ds Up to 2 or 4 GB of DDR3 SDRAM; or: 32 or 64 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

LVDS

LVDS
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
40
4X
PCIe to PCI BRIDGE
GTX
PCI to PCI BRIDGE
J2
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
www.pentek.com
Models 72660, 73660 and 74660

A/D Converter Stage
The front end accepts four or eight full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into four or eight Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources. LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An onboard clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the

These models feature four or eight A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of four A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
PCI-X Interface
from A/D Ch 1
from A/D Ch 2
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
40 FPGA I/O
Pentek, Inc.
www.pentek.com
Models 72660, 73660 and 74660

Specifications
Model 72660 or Model 73660: 4 A/Ds Model 74660: 8 A/Ds Front Panel Analog Signal Inputs (4 or 8) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (4 or 8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources (1 or 2) On-board clock synthesizers Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus (1 or 2): 26-pin front panel connector; LVPECL bus includes, clock/ sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73660; J3 connector, Model 72660; J3 and J5 connectors, Model 74660 Memory Banks (1 or 2) Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73660: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
Model 72660 Description 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGA 6U cPCI 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGA 3U cPCI 8-Channel 200 MHz 16-bit A/D with two Virtex-6 FPGAs - 6U cPCI XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73660; J3 connector, Model 72660; J3 and J5 connectors, Model 74660 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
73660
74660
Options: -062 -064 -104
-150
-160
-155
-165
Pentek, Inc.
www.pentek.com
! w e N
Models 72661, 73661 and 74661
4- or 8-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - cPCI
General Information
Models 72661, 73661 and 74661 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71662 XMC modules mounted on a cPCI carrier board. Model 72661 is a 6U cPCI board while the Model 73661 is a 3U cPCI board; both are equipped with one Model 71661 XMC. Model 74661 is a 6U cPCI board with two XMC modules rather than one. These models include four or eight A/Ds, four or eight multiband DDCs and four or eight banks of memory. QDRII+ memories, controllers for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory- installed functions and enable these models to operate as complete turnkey solutions without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include four or eight A/D acquisition IP modules. Each of the acquisition IP modules contains a powerful, programmable DDC IP core. IP modules for either DDR3 or

Model 74661
Model 73661
RF In
RF In
RF In
RF In
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four or eight 200 MHz 16-bit A/Ds Four or eight multiband DDCs (digital downconverters) One or two multiboard programmable beamformers Up to 2 or 4 GB of DDR3 SDRAM; or: 32 MB or 64MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

GTX

LVDS
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
4X
4X
x4 PCIe
4X
GTX
QDRII+ option 150
4X
PCIe to PCI BRIDGE
Sum to next board
PCIe to PCI BRIDGE
Sum to next board
PCI to PCI BRIDGE
Memory Banks 1 & 2
Memory Banks 3 & 4
J3
Pentek, Inc.
www.pentek.com
Models 72661, 73661 and 74661

These models feature four or eight A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
Beamformer IP Cores
In addition to the DDCs, these models feature one or two complete beamforming subsystems. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the four DDC core outputs. An additional programmable gain stage compensates for summation
A/D Converter Stage

The front end accepts four or eight analog HF or IF inputs on front panel SSMC connectors with transformer coupling into four or eight Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources.

An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage
from A/D Ch 1
DDC IP Cores
INPUT MULTIPLEXER
DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

MUX
DDC CORE
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
sum out sum in
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
4X PCIe
Pentek, Inc.
www.pentek.com
Models 72661, 73661 and 74661
the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation Beamformers (1 or 2) Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Sample Clock Sources (1 or 2) On-board clock synthesizer Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus (1 or 2): 26-pin connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Memory Banks (1 or 2) Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73661: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
PCI-X Interface
Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
Model 72661 Description 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - 6U cPCI 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - 3U cPCI 8-Channel 200 MHz A/D with DDCs and Virtex-6 FPGAs - 6U cPCI XC6VLX240T XC6VSX315T Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Specifications
Model 72661 or Model 73661: 4 A/Ds Model 74660: 8 A/Ds Front Panel Analog Signal Inputs (4 or 8) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (4 or 8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters (4 or 8) Quantity: Four channels Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients
73661
74661
Options: -062 -064 -150
-160
-155
-165
Pentek, Inc.
www.pentek.com
! w e N
Models 72662, 73662 and 74662
4- or 8-Channel 200 MHz A/D with 32- or 64-Channel DDC and Virtex-6 FPGA - cPCI
General Information
Models 72662, 73662 and 74662 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71662 XMC modules mounted on a cPCI carrier board. Model 72662 is a 6U cPCI board while the Model 73662 is a 3U cPCI board; both are equipped with one Model 71662 XMC. Model 74662 is a 6U cPCI board with two XMC modules rather than one. These models include four or eight A/Ds, 32 or 64 multiband DDCs and four or eight banks of memory. trigger functions, a test signal generator, voltage and temperature monitoring, DDR3 SDRAM memory controllers, and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, and triggering. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include four or eight A/D acquisition IP modules. Each of the acquisition IP modules contains a powerful, programmable 8-channel DDC IP core. IP modules for control of all data clocking, synchronization, gate and

The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73662; J3 connector, Model 72662; J3 and J5 connectors, Model 74662.
Model 74662
Model 73662
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four or eight 200 MHz 16-bit A/Ds 32 or 64 channels of multiband DDCs (digital downconverters) Up to 2 or 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

LVDS
MODEL 73662 INTERFACES ONLY

32 32 DDR3 SDRAM 512 MB 32 DDR3 SDRAM 512 MB 32 DDR3 SDRAM 512 MB 16 Config FLASH 64 MB
GTX
VIRTEX-6 FPGA
LVDS
40
GTX
DDR3 SDRAM 512 MB
x4 PCIe
4X
40
PCIe
PCIe to PCI BRIDGE
PCI to PCI BRIDGE
J2
Pentek, Inc.
www.pentek.com
Models 72662, 73662 and 74662

These models feature four or eight A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
of 8. For example, with a sampling rate of 200 MHz, the available output bandwidths range from 19.53 kHz to 10.0 MHz. Each 8-channel bank can have its own unique decimation setting supporting a different bandwidth associated with each of the four acquisition modules. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N. Any number of channels can be enabled within each bank, selectable from 0 to 8. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within a bank.

An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a builtin clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltagecontrolled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a reference clock, typically 10 MHz, for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
A/D Converter Stage

The front end accepts four or eight analog HF or IF inputs on front panel SSMC connectors with transformer coupling into four or eight Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources.
from A/D Ch 1
Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with DDR3 SDRAM.
INPUT MULTIPLEXER
DDC IP Cores
Within each A/D Acquisition IP Module is a powerful 8-channel DDC bank. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all 32 DDC channels or each of the four A/Ds driving its own DDC bank. Each of the 32 channels has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. All of the 8 channels within a bank share a common decimation setting that can range from 16 to 8192, programmable in steps
.

.

.

.
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
32 Memory Bank 1
32 Memory Bank 2
32 Memory Bank 3
32 Memory Bank 4
4X PCIe
40 FPGA I/O
Pentek, Inc.
www.pentek.com
Models 72662, 73662 and 74662
512 MB deep and is an integral part of the Boards DMA capabilities, providing FIFO memory and capture space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Sample Clock Sources (1 or 2) On-board clock synthesizer Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock, or PLL system reference Timing Bus (1 or 2): 26-pin connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array (1 or 2) Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73662; J3 connector, Model 72662; J3 and J5 connectors, Model 74662 MemoryBanks (1 or 2) Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73662: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
PCI-X Interface
Specifications
Model 72662 or Model 73662: 4 A/Ds, 32 DDCs Model 74660: 8 A/Ds, 64 DDCs Front Panel Analog Signal Inputs (4 or 8) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (4 or 8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters (32 or 64) Quantity: Four 8-channel banks, one per acquisition module Decimation Range: 16x to 8192x in steps of 8x LO Tuning Freq. Resolution: 32 bits, 0 to s Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, >100 dB stopband attenuation
Model 72662 Description 4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - 6U cPCI 4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - 3U cPCI 8-Ch 200 MHz A/D with 64-Ch DDC and Virtex-6 FPGA - 6U cPCI XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73662; J3 connector, Model 72662; J3 and J5 connectors, Model 74662 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
73662
74662
Options: -062 -064 -104
-155
-165
Pentek, Inc.
www.pentek.com
! ew N
Models 72670, 73670 and 74670
4- or 8-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - cPCI

General Information
Models 72670, 73670 and 74670 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71670 XMC modules mounted on a cPCI carrier board. Model 72670 is a 6U cPCI board while the Model 73670 is a 3U cPCI board; both are equipped with one Model 71670 XMC. Model 74670 is a 6U cPCI board with two XMC modules rather than one. These models include four or eight D/As, four or eight DUCs, and four or eight banks of memory. controllers for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable these models to operate as complete turnkey solutions, without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions in these models include four or eightD/A waveform playback IP modules, to support waveform generation through the D/A converters. IP modules for DDR3 SDRAM memories,

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four or eight 1.25 GHz 16-bit D/As Four or eight digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 or 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-or Quad Sync clock/ sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Sample Clk / Reference Clk In Trigger In
RF Out
RF Out
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO

LVDS

LVDS
GTX
40
x4 PCIe
4X
GTX
Memory Banks 1 & 2 40 to PCI Optional BRIDGE FPGA I/O (Option -104) PCIe
Memory Banks 3 & 4
PCIe to PCI BRIDGE
From/To Other XMC Module of Model 74670
PCI to PCI BRIDGE
J2
Pentek, Inc.
www.pentek.com
Models 72670, 73670 and 74670

Two or four Texas Instruments DAC3484s provide four or eight DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals to a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs to a 16-bit D/A converter. If translation is disabled, each D/A acts as an interpolating 16-bit D/A with output sampling rates up to 1.25 GHz. In both modes, the D/A provides interpolation factors of 2x, 4x, 8x and 16x. Analog output is through four front panel SSMC connectors. 2, 4, 8, or 16 to provide lower frequency D/A clocks. A pair of front panel Sync connectors allows multiple boards to be synchronized. They accept CML inputs that drive the boards sync and trigger/gate signals. The Pentek Models 7292, 7392 and 7492 or the 9192 Cobalt Synchronizers can drive multiple Sync connectors enabling large, multichannel synchronous configurations.
Memory Resources
The architecture of these models supports four or eight independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and waveform playback capabilities. Waveform tables can be loaded into the memories with playback managed by the linked list controllers. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

An internal timing bus provides all required D/A clocking. The bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives a sample clock either from the front panel SSMC connector or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this latter mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock to phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided by
PCI-X Interface

The factory-installed functions in these models include one or two sophisticated D/A Waveform Playback IP modules. Four or eight linked list controllers support waveform generation to the four or eight D/As from tables stored in either on-board memory or offboard host memory. Data for Channel 1 and Channel 2 are interleaved for delivery to a dual channel D/A device. For this reason, they must share a common trigger/ gate, sample rate, interpolation factor, and other parameters. The same rules apply to Channel 3 and Channel 4, as well as to the other four channels of Model 74670. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up to 64 or 128 individual link entries for each D/A channel can be chained together to create complex waveforms with a minimum of programming.
16
to D/A Ch 1 & 2
16
to D/A Ch 3 & 4
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
40 FPGA I/O
Pentek, Inc.
www.pentek.com
Models 72670, 73670 and 74670

Specifications
Models 72670 and 73670: 4-Channel DUC, 4-channel D/A Model 74670: 8-Channel DUC, 4-channel D/A D/A Converters (4 or8) Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Front Panel Analog Signal Outputs (4 or 8) Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the D/A clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus (1 or 2): 19-pin Sync bus connector includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73670; J3 connector, Model 72670; J3 and J5 connectors, Model 74670 Memory Banks (1 or 2) Four or eight 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73670: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
Model 72670 Description 4-Channel 1.25 GHz D/A with Virtex-6 FPGA - 6U cPCI 4-Channel 1.25 GHz D/A with Virtex-6 FPGA - 3U cPCI 8-Channel 1.25 GHz D/A with Virtex-6 FPGA - 6U cPCI
73670
74670
Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73670; J3 connector, Model 72670; J3 and J5 connectors, Model 74670 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
www.pentek.com
! ew N
Models 72671, 73671 and 74671
4- or 8-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - cPCI
General Information
Models 72671, 73671 and 74671 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71671 XMC modules mounted on a cPCI carrier board. Model 72671 is a 6U cPCI board while the Model 73671 is a 3U cPCI board; both are equipped with one Model 71671 XMC. Model 74671 is a 6U cPCI board with two XMC modules rather than one. These models include four or eight D/As with a wide range of programmable interpolation factors, four or eight DUCs, and four or eight banks of memory. modules for DDR3 SDRAM memories, controllers for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable these models to operate as complete turnkey solutions, without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions in these models include four or eight D/A waveform playback IP modules, to support waveform generation through the D/A converters. IP

The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73671; J3 connector, Model 72671; J3 and J5 connectors, Model 74671.
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four or eight 1.25 GHz 16-bit D/As Four or eight digital upconverters Extended interpolation range from 2x to 1,048,576x Programmable output levels 250 MHz max. output bandwidth 2 or 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-or Quad Sync clock/ sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF Out
RF Out
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO

LVDS

LVDS
GTX
40
x4 PCIe
4X
GTX
Memory Banks 3 & 4
PCIe to PCI BRIDGE
PCI to PCI BRIDGE
J2
Pentek, Inc.
www.pentek.com
Models 72671, 73671 and 74671
Two or four Texas Instruments DAC3484s provide four or eight DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals to a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs to a 16-bit D/A converter. If translation is disabled, each D/A acts as an interpolating 16-bit D/A with output sampling rates up to 1.25 GHz. In both modes, the D/A provides interpolation factors of 2x, 4x, 8x and 16x. In addition to the DAC3484, these models feature an FPGA-based interpolation engine which adds two additonal interpolation stages programmable from 2x to 256x. The combined interpolation results in a range from 2x to 1,048,576x for each D/A channel and is ideal for matching the digital downconversion and data reduction used on the receiving channels of many communications systems. Analog outputs are through front panel SSMC connectors. on-board clock generator receives a sample clock either from the front panel SSMC connector or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this latter mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock to phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided by 2, 4, 8, or 16 to provide lower frequency D/A clocks. A pair of front panel Sync connectors allows multiple boards to be synchronized. They accept CML inputs that drive the boards sync and trigger/gate signals. The Pentek Models 7292, 7392 and 7492 or the 9192 Cobalt Synchronizers can drive multiple Sync connectors enabling large, multichannel synchronous configurations.
Memory Resources
The architecture of these models supports four or eight independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and waveform playback capabilities. Waveform tables can be loaded into the memories with playback managed by the linked-list controllers. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

The factory-installed functions in these models include one or two sophisticated D/A Waveform Playback IP modules. Four or eight linked-list controllers support waveform generation to the four or eight D/As from tables stored in either on-board memory or offboard host memory. Data for Channel 1 and Channel 2 are interleaved for delivery to a dual channel D/A device. For this reason, they must share a common trigger/ gate, sample rate, interpolation factor, and other parameters. The same rules apply to Channel 3 and Channel 4, as well as to the other four channels of Model 74671. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up to 64 or 128 individual link entries for each D/A channel can be chained together to create complex waveforms with a minimum of programming.

An internal timing bus provides all required D/A clocking. The bus includes a clock, sync and a gate or trigger signal. An
16
to D/A Ch 1 & 2
16
to D/A Ch 3 & 4
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4

PCIe INTERFACE
4X PCIe
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Models 72671, 73671 and 74671
PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73671: 32 bits only. External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus (1 or 2): 19-pin Sync bus connector includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Arrays (1 or 2) Xilinx Virtex-6 XC6VLX240T-2, or XC6VSX315T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73671; J3 connector, Model 72671; J3 and J5 connectors, Model 74671 Memory Banks (1 or 2) Four or eight 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73671: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
Specifications
Models 72671 and 73671: 4-Channel DUC, 4-channel D/A Model 74671: 8-Channel DUC, 8-channel D/A D/A Converters (4 or8) Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Front Panel Analog Signal Outputs (4 or 8) Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the D/A clock
Model 72671 Description 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - 6U cPCI 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - 3U cPCI 8-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - 6U cPCI
73671
74671
Pentek, Inc.
www.pentek.com
! w e N
Models 72690, 73690 and 74690
One or two L-Band RF Tuners, 2- or 4-Channel 200 MHz A/D, Virtex-6 FPGA - cPCI
General Information
Models 72690, 73690 and 74690 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71690 XMC modules mounted on a cPCI carrier board. Model 72690 is a 6U cPCI board while the Model 73690 is a 3U cPCI board; both are equipped with one Model 71690 XMC. Model 74690 is a 6U cPCI board with two XMC modules rather than one. These models include one ot two L-Band RF tuners, two or four A/Ds and four or eight banks of memory. test signal generator, and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions in these models include two or four A/D acquisition IP modules. IP modules for either DDR3 or QDRII+ memories, controllers for all data clocking and synchronization functions, a

Model 74690
Model 73690
Features
One or two L-Band tuners accept RF signals from 925 MHz to 2175 MHz One or two programmable LNAs boost LNB (low-noise block) antenna signal levels with up to 60 dB gain One or two programmable analog downconverters provide I + Q baseband signals with bandwidths ranging from 4 to 40 MHz Two or four 200 MHz 16-bit A/Ds Supports Xilinx Virtex-6 LXT and SXT FPGAs Up to 2 or 4 GB of DDR3 SDRAM; or: 32 MB or 64MB of QDRII+ SRAM Clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Ref In
RF In
MAX2112
Ref Out GC
12-BIT D/A
Ref A/D Clock/Sync
Control
16
16
IC
2
Timing Bus
VCXO

LVDS

LVDS
GTX
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
Config FLASH 64 MB
40
x4 PCIe
4X
GTX
PCIe to PCI BRIDGE
PCI to PCI BRIDGE
J2
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
www.pentek.com
Models 72690, 73690 and 74690
RF Tuner Stage
One or two front panel SSMC connectors accept L-Band signals between 925 MHz and 2175 MHz from the antenna LNBs (low noise blocks). The Maxim MAX2112 tuners directly convert these L-Band signals to baseband using broadband I/Q downconverters. The devices include RF variable-gain LNAs (low noise amplifiers), PLL (phaselocked loops) synthesized local oscillators, quadrature (I + Q) downconverting mixers, baseband lowpass filters with programmable cutoff frequency, and variable-gain baseband amplifiers. The fractional-N PLL synthesizers lock their VCOs to the timing generator output, or to an external reference input between 12 and 30 MHz. Together, the baseband amplifiers and the RF LNA offer a programmable linear gain range of 60 dB. The integrated lowpass filters with variable bandwidths provide bandwidths ranging from 4 to 40 MHz, programmable with 8 bits of resolution.

An internal timing generator provides all timing, gating, triggering and synchronization functions required by the A/D converters. It also serves as an optional source for the L-Band tuner reference. The front panel SSMC clock input can be used directly as the A/D sample clock. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (voltage-controlled crystal oscillator). In this mode, the front panel SSMC clock input connector accepts a 10 MHz reference signal for synchronizing the VCXO using a PLL. The timing generator uses a front panel LVPECL 26-pin clock/sync connector for one clock, two sync, and two gate/trigger signals. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate/ trigger signals within the bosrd. In the master mode, the LVPECL bus drives output timing signals to synchronize multiple slave bosrds, supporting synchronous sampling and sync functions across all connected boards.

These models feature two or fourA/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from either of the two A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
A/D Converter Stage

The analog baseband I and Q analog tuner outputs are then applied to two or four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources.
Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, all DDR3 SDRAM, or as combination of two banks of each type of memory.
from A/D (I)
from A/D (Q)
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
40 FPGA I/O
Pentek, Inc.
www.pentek.com
Models 72690, 73690 and 74690
Each QDRII+ SRAM bank can be up to 8
MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. The factory-installed A/D acquisition modules use memory banks 1 & 2. Banks 3 & 4 can be optionally installed to support custom user-installed IP within the FPGA . Sample Clock Sources (1 or 2) On-board timing generator/synthesizer A/D Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, for the A/D clock Timing Generator External Clock Inputs (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 200 MHz (up to 800 MHz when Timing Generator divider is enabled) or PLL system reference Timing Generator Bus (1 or 2): 26-pin front panel connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Inputs (2 or 4) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or2) Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73690; J3 connector, Model 72690; J3 and J5 connectors, Model 74950 Memory Banks (1 or 2) Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73690: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
PCI-X Interface
The models include an industry-standard interface compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73690: 32 bits only.
Specifications
Model 72690 or Model 73690: 1 RF tuner, 2 A/Ds Model 74690: 2 RF tuners, four A/Ds Front Panel Analog Signal Inputs (1 or 2) Connector: Front panel female SSMC Impedance: 50 ohms L-Band Tuners (1 or 2) Type: Maxim MAX2112 Input Frequency Range: 925 MHz to 2175 MHz Monolithic VCO Phase Noise: -97 dBc/Hz at 10 kHz Fractional-N PLL Synthesizer: freqVCO = (N.F) x freqREF where integer N = 19 to 251 and fractional F is a 20-bit binary value PLL Reference (freqREF): Front panel SSMC connector or on-board 27 MHz crystal (Option -100), 12 to 30 MHz LNA Gain: 0 to 65 dB, controlled by a programmable 12-bit D/A converter* Baseband Amplifier Gain: 0 to 15 dB, in 1 dB steps* *Usable Full-Scale Input Range: 50 dBm to +10 dBm Baseband Low Pass Filter: Cutoff frequency programmable from 4 to 40 MHz with 8-bit resolution A/D Converters (2 or 4) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits
Model 71690 Description L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - XMC XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73690; J3 connector, Model 72690; J3 and J5 connectors, Model 74690 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Options: -062 -064 -104
-150
-160
-155
-165
Pentek, Inc.
www.pentek.com
! w e N
Models 72720 73720 and 74720
General Information
Models 72720, 73720 and 74720 are members of the Onyx family of high-performance CompactPCI boards based on the Xilinx Virtex-7 FPGA. They consist of one or two Model 71720 XMC modules mounted on a cPCI carrier board. Model 72720 is a 6U cPCI board while the Model 73720 is a 3U cPCI board; both are equipped with one Model 71720 XMC. Model 74720 is a 6U cPCI board with two XMC modules rather than one. These models include three or sixA/Ds, one or two DUCs, two or four D/As and four or eight banks of memory. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCI-X interface complete the factoryinstalled functions and enable these models to operate as a complete turnkey solutions, without the need to develop any FPGA IP.

Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 FPGAs from Xilinx. As the central feature of the board architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include three A/D acquisition and a D/A waveform playback IP modules for simplifying data capture and data transfer.
RF In

The Virtex-7 FPGA site can be populated with one of two FPGAs to match the specific requirements of the processing task. Supported FPGAs are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73720; J3 connector, Model 72720; J3 and J5 connectors, Model 74720.
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCI/PCI-X bus Three or six 200 MHz 16-bit A/Ds One or two DUCs (digital upconverters) Two or four 800 MHz 16-bit D/As Four or eight GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Sample Clk / Reference Clk In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF In
RF In
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus

VCXO
16
16
16
Timing Bus

LVDS

LVDS
GTX
GTX
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
40
FPGA Config Bus

CONFIG FLASH 1 GB
40 CONFIG FLASH 1 GB
x4 PCIe
FPGA Config Bus
x4 PCIe
x4 PCIe
PCIe to PCI BRIDGE
x4 PCIe
PCIe to PCI BRIDGE PCI to PCI BRIDGE
J2 PCI/PCI-X BUS 32-bit, 33/66 MHz
Pentek, Inc.
www.pentek.com
Models 72720 73720 and 74720

The Onyx architecture includes GateXpress, a sophisticated FPGA configuration manager for loading and reloading the FPGA. At power up, GateXpress immediately presents a target for the host computer to discover, effectively giving the FPGA time to load from FLASH. This is especially important for larger FPGAs where the loading times can exceed the PCI-X discovery window, typically 100 msec on most PCs. The boards configuration FLASH can hold four FPGA images. Images can be factory-installed IP or custom IP created by the user, and programmed into the FLASH via JTAG using Xilinx iMPACT or through the boards PCI-X interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the FPGA with a new IP image. The first is the option to load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the FPGA image must be loaded directly through the PCI-X interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the FPGA IP may need to change many times during the course of a mission, images can be stored on the host computer and loaded as needed. The third option, typically used during development, allows the user to directly load the FPGA through JTAG using Xilinx iMPACT. In all three FPGA loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the PCI-X configuration space allowing dynamic FPGA reconfiguration without needing to reset the host computer to rediscover the board. After the reload, the host simply continues to see the board with the expected device ID.
A/D Converter Stage

The front end accepts three or six fullscale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into three or six Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources.

One or two TI DAC5688 DUCs (digital upconverters) and D/As accept baseband real or complex data streams from the FPGA and provide that input to the upconvert, interpolate and dual D/A stages.
from A/D Ch 1
from A/D Ch 2

to D/A

These models include one or two factory-installed sophisticated D/A Waveform Playback IP modules. Linked-list controllers allow users to easily play back to the dual D/As waveforms stored in either on-board memory or off-board host memory. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 or 128 individual link entries can be chained together to create complex waveforms with a minimum of programming.
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
MEMORY CONTROL
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Models 72720 73720 and 74720
and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes, the DAC5688 provides interpolation factors of 2x, 4x and 8x. D/A Converters (2 or 4) Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs (2 or 4) Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources (2 or 4) On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus (1 or 2): 26-pin connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73720; J3 connector, Model 72720; J3 and J5 connectors, Model 74720 Memory Banks (1 or 2) Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73620: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
Memory Resources
The architecture supports four or eight independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factoryinstalled functions, custom userinstalled IP within the FPGA can take advantage of the memories for many other purposes.

Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
PCI-X Interface
Model 72720 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex7 FPGA 6U cPCI 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-7 FPGA 3U cPCI 6-Channel 200 MHz A/D and 4-Channel 800 MHz D/A and two Virtex-7 FPGAs - 6U cPCI XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS I/O between the FPGA and J2 connector, Model 73720; J3 connector, Model 72720; J3 and J5 connectors, Model 74720
Specifications
Model 72620 or Model 73620: 3 A/Ds, 1 DUC, 2 D/As Model 74620: 6 A/Ds, 2 DUCs, 4 D/As Front Panel Analog Signal Inputs (3 or 6) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (3 or 6) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits
73720
74720
Options: -073 -076 -104
Pentek, Inc.
www.pentek.com
! w e N
Models 72760, 73760 and 74760

General Information
Models 72760, 73760 and 74760 are members of the Onyx family of high-performance CompactPCI boards based on the Xilinx Virtex-7 FPGA. They consist of one or two Model 71760 XMC modules mounted on a cPCI carrier board. Model 72760 is a 6U cPCI board while the Model 73760 is a 3U cPCI board; both are equipped with one Model 71760 XMC. Model 74760 is a 6U cPCI board with two XMC modules rather than one. These models include four or eight A/Ds and four or eight banks of memory. IP modules for DDR3 SDRAM memories, controllers for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable these models to operate as complete turnkey solutions without the need to develop FPGA IP.

The Pentek Onyx Architecture features Virtex-7 FPGAs. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include four or eight A/D acquisition IP modules for simplifying data capture and data transfer.

Model 74760
Model 73760
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCI/PCI-X bus Four or eight 200 MHz 16-bit A/Ds Four or eight GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-7 FPGA for custom I/O
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16 VCXO
16
16
16
Timing Bus

LVDS

LVDS
GTX
GTX
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
40
FPGA Config Bus

CONFIG FLASH 1 GB
x4 PCIe
FPGA Config Bus
x4 PCIe
x4 PCIe
PCIe to PCI BRIDGE
x4 PCIe
Pentek, Inc.
www.pentek.com
Models 72760, 73760 and 74760

A/D Converter Stage

The front end accepts four or eight fullscale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into four or eight Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-7 FPGA for signal processing, data capture or for routing to other board resources.

These models feature four or eight A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of four A/Ds or the test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
40 FPGA I/O
Pentek, Inc.
www.pentek.com
Models 72760, 73760 and 74760

An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An onboard clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. A/D Converters (4 or 8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: (1 or 2) On-board clock synthesizer Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus (1 or 2) 26-pin front panel connector; LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73760; J3 connector, Model 72760; J3 and J5 connectors, Model 74760 Memory Banks (1 or 2) Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73760: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
Memory Resources
The Onyx architecture supports four or eight independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
Model 72760 Description 4-Channel 200 MHz 16-bit A/D with Virtex-7 FPGA 6U cPCI 4-Channel 200 MHz 16-bit A/D with Virtex-7 FPGA 3U cPCI 8-Channel 200 MHz 16-bit A/D with two Virtex-7 FPGAs - 6U cPCI XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS I/O between the FPGA and J2 connector, Model 73760; J3 connector, Model 72760; J3 and J5 connectors, Model 74760
PCI-X Interface
73760
74760
Specifications
Model 72760 or Model 73760: 4 A/Ds Model 74760: 8 A/Ds Front Panel Analog Signal Inputs (4 or 8) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz
Options: -073 -076 -104
Pentek, Inc.
www.pentek.com
! ew N
Models 72730, 73730 and 74730
General Information
Models 72730, 73730 and 74730 are members of the Onyx family of high performance CompactPCI boards based on the Xilinx Virtex-7 FPGA. They consist of one or two Model 71730 XMC modules mounted on a cPCI carrier board. Model 72730 is a 6U cPCI board while the Model 73730 is a 3U cPCI board; both are equipped with one Model 71730 XMC. Model 74730 is a 6U cPCI board with two XMC modules rather than one. These models include one or two 1 GHz A/D and D/A converters and four or eight banks of memory IP modules for DDR3 SDRAM memories, controllers for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable these models to operate as complete turnkey solutions without the need to develop FPGA IP.

The Pentek Onyx Architecture features Virtex-7 FPGAs. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include ne or two A/D acquisition and one or two D/A waveform playback IP modules for simplifying data capture and data transfer.

Model 74730
Model 73730
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCI/PCI-X bus One or two 1 GHz 12-bit A/D One or two 1 GHz 16-bit D/A Four or eight GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multimodule synchronization Optional LVDS connections to the Virtex-7 FPGA for custom I/O
RF In
RF Out
RF XFORMR
RF XFORMR
Gate In Sync In
A/D Clock/Sync Bus
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12 VCXO
1 GHz 16-BIT D/A 16
D/A Sync Bus

LVDS

LVDS
GTX
GTX
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
40
FPGA Config Bus

CONFIG FLASH 1 GB
x4 PCIe
FPGA Config Bus
x4 PCIe
x4 PCIe
PCIe to PCI BRIDGE
x4 PCIe
Pentek, Inc.
www.pentek.com
Models 72730, 73730 and 74730

The Onyx architecture includes GateXpress, a sophisticated FPGA configuration manager for loading and reloading the FPGA. At power up, GateXpress immediately presents a target for the host computer to discover, effectively giving the FPGA time to load from FLASH. This is especially important for larger FPGAs where the loading times can exceed the PCI-X discovery window, typically 100 msec on most PCs. The boards configuration FLASH can hold four FPGA images. Images can be factory-installed IP or custom IP created by the user, and programmed into the FLASH via JTAG using Xilinx iMPACT or through the boards PCI-X interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the FPGA with a new IP image. The first is the option to load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the FPGA image must be loaded directly through the PCI-X interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the FPGA IP may need to change many times during the course of a mission, images can be stored on the host computer and loaded as needed.
The third option, typically used during development, allows the user to directly load the FPGA through JTAG using Xilinx iMPACT. In all three FPGA loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the PCI-X configuration space allowing dynamic FPGA reconfiguration without needing to reset the host computer to rediscover the board. After the reload, the host simply continues to see the board with the expected device ID.
A/D Converter Stage

The front end accepts one or two analog HF or IF input on front panel SSMC connectors with transformer coupling into one or two Texas Instruments ADS5400 1 GHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-7 FPGA for signal processing, data capture or for routing to other module resources.
D/A Converter Stage

These models feature one or two TI DAC5681Z 1 GHz, 16-bit D/As. The converters have an input sample rate of 1 GSPS, allowing them to acept full rate data from the FPGA. Additionally, the D/As include a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is through front panel SSMC connectors.
to D/A

INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
Pentek, Inc.
www.pentek.com
Models 72730, 73730 and 74730
Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives a sample clock either from the front panel SSMC connector or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this latter mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock to phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or 16 to provide different lower frequency A/D and D/A clocks. A pair of front panel Sync connectors allows multiple modules to be synchronized. They accept CML inputs that drive the boards sync and gate/trigger signals. The Pentek Model 7192 and Model 9192 Cobalt Synchronizers can drive multiple 71630 Sync connectors enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connector. Front Panel Analog Signal Outputs (1 or 2) Output Type: Transformer-coupled, front panel female SSMC connectors Sample Clock Sources (1 or 2) On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73730; J3 connector, Model 72730; J3 and J5 connectors, Model 74730 Memory Banks (1 or 2) Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73730: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
PCI-X Interface
Memory Resources

Model 72730 73730 74730 Options: -073 -076 -104 XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS I/O between the FPGA and J2 connector, Model 73730; J3 connector, Model 72730; J3 and J5 connectors, Model 74730 Description 1 GHz A/D and D/A, Virtex-7 FPGA - 6U cPCI 1 GHz A/D and D/A, Virtex-7 FPGA - 3U cPCI Two 1 GHz A/D and D/A, Virtex-7 FPGA - 6U cPCI
Model 72730 or Model 73730: 1 A/D, 1 D/A Model 74730: 2 A/Ds, 2 D/As Front Panel Analog Signal Inputs (1 or 2) Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converters (1 or 2) Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz to 1 GHz Resolution: 12 bits D/A Converters (1 or 2) Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: 16 bits
Pentek, Inc.
www.pentek.com
RAD AR & SDR I/O - PCI RADAR

MODEL
7650 7651 7652 7653 7656 7658
DESCRIPTION
Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - PCI 256-Channel DDC with four 200 MHz, 16-bit A/Ds - PCI 32-Channel DDC with four 200 MHz, 16-bit A/Ds - PCI 4/2-Channel DDC, four 200 MHz 16-bit A/Ds, Beamformer - PCI Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI Customer Information
& & & & & &
PMC/XMC CompactPCI x 8 PCI Express 3U VPX - FORMA T 1 FORMAT AMC 3U VPX - FORMA T 2 FORMAT

www.pentek.com
Model 7650
Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - PCI

General Information
Model 7650 is a half-length PCI Quad 200 MHz A/D. It consists of one Model 7150 Quad A/D mounted on a PCI carrier board. The Model 7650 attaches directly to computer motherboards with PCI bus slots. Front panel connectors are brought out on the rear panel. programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T and FX100T. The SXT parts feature between 288 and 640 DSP48E Slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the Model 7650 can be optionally configured with an LX155T in the processing FPGA position for 155,648 logic cells. A second Virtex-5 FPGA provides board interfaces including PCI-X or PCI Express. Implementing the PCI interfaces in this second FPGA, keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT or an SXT family part, providing not only interface functionality, but additional processing resources up to an additional 640 DSP48E Slices. Option -104 installs a 64-pin DIN connector with 16 pairs of LVDS connections to the processing FPGA and 16 pairs of LVDS connections to the interface FPGA for custom I/O.
A/D Converter Stage

Virtex-5 FPGAs
The architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory-shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the A/D converters, DDR2 SDRAM memory, interface FPGA,

Features

Complete software radio interface solution Four or 200 MHz, 16-bit A/Ds Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Up to 2.56 seconds of data capture at 200 MHz LVPECL clock/sync bus for multiboard synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS 200 or 135 MHz 16 BIT A/D
RF In
RF XFORMR
RF In
RF XFORMR
RF In
RF XFORMR
TTL In
Clock/Sync Bus
200 or 135 MHz 16 BIT A/D
LVPECL Bus
XTL OSC
To A l Sections
Timing Bus
Control/ Status
PROCESSING FPGA VIRTEX 5 LX50T, SX50T, SX95T or LX155T LVDS 8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T LVDS 32 4X LVDS
PCI X INTERFACE
64
LVDS 32 32
32
PCI-X BUS
64-pin DIN FPGA I/O (Option -104) PCI-X BUS
PCI-TO-PCI BRIDGE
Pentek, Inc.
www.pentek.com
Model 7650

The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to three slave 7650s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VLX155T and XC5VFX100T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs a 64-pin DIN connector with 16 pairs of LVDS connections to the processing FPGA and 16 pairs to the interface FPGA for custom I/O Memory DDR2 SDRAM: Up to 1 GB in two banks PCI Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard half-length PCI card
Memory Resources
PCI-X Interface
The Model 7650 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.

Model 7650 Description Quad 200 MHz, 16-bit A/D with two Virtex-5 FPGAs PCI FPGA I/O through a 64-pin DIN connector
Options: -104
Pentek, Inc.
www.pentek.com
Model 7651
256-Channel DDC with four 200 MHz, 16-bit A/Ds - PCI

General Information
Model 7651 is a high-speed software radio half-length PCI board. It consists of one Model 7151 Quad A/D digitizer with a factory- installed high-performance 256-channel DDC IP Core mounted on a PCI carrier board. The Model 7651 attaches directly to computer motherboards with PCI bus slots. Front panel connectors are brought out on the rear panel.

A/D Converter Stage

Features


256 channels of DDC Four 200 MHz 16-bit A/Ds Independent tuning for each channel DDC decimation from 128 to 1024 in steps of 64 Independent decimation for each bank Each bank independently selects one of four A/Ds User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multiboard synchronization

CH 1 RF In
RF XFORMR
200 MHz 16-bit A D
CH 2 RF In
RF XFORMR
200 MHz 16-bit A D
CH 1 CH 2 CH 3 CH 4
CH 1 I+Q
M U X
FIFO 1
CH 3 RF In
RF XFORMR
200 MHz 16-bit A D
CH 2
CH 3 CH 4
I+Q
M U X
FIFO 2
PCI-X BUS CH 1 Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 CH 3 CH 4
M U X D GITAL DOWNCONVERTER BANK 4: CH 193-256 DEC: 128 - 1024
PCI-X BUS
CH 3
CH 2 CH 3 CH 4
I+Q
M U X
FIFO 3
PCI-X INTERFACE Xilinx XC5VLX30T PCI-TO-PCI BRIDGE
TTL In
CH 4 I+Q
M U X
FIFO 4
LVPECL Bus
XTAL OSC
XILINX XC5VSX95T
Timing Bus
Pentek, Inc.
www.pentek.com
Model 7651

The architecture includes a flexible timing and synchronization circuit that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to three slave 7651s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. For larger systems, many more boards can be synchronized with an external clock and sync generator.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, and XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface in the standard unit; optional FPGA: XC5VSX50T PCI Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Local Bus: 64-bit, 66 MHz Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard half-length PCI card
PCI-X Interface
Model 7651 Description 256-Channel DDC with four 200 MHz, 16-bit A/Ds - PCI
Pentek, Inc.
www.pentek.com
Model 7652

General Information
Model 7652 is a high-speed softwaare radio half-length PCI board. It consists of one Model 7152 Quad A/D digitizer with a factory- installed high-performance 32-channel DDC IP Core mounted on a PCI carrier board. The Model 7652 attaches directly to computer motherboards with PCI bus slots. Front panel connectors are brought out on the rear panel.

A/D Converter Stage

Features

32 channels of DDC in four banks of 8 channels Four 200 MHz, 16-bit A/Ds Independent 32-bit DDC tuning for all 32 channels DDC decimation from 16 to 8192 in steps of 8 Bandwidths from 20 kHz to 10 MHz Common decimation factor within each DDC bank Different decimation factors between banks User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection Power meters and threshold detectors LVPECL clock/sync bus for multiboard synchronization


The 7652 features 32 power meters that continuously measure the individual average power output of each of the 32 DDC channels. The time constant of the averaging interval for each meter is programmable up to 16K samples. In addition, 32 threshold detectors automatically send an interrupt to the processor if the average power level of any DDC falls below or exceeds a programmable threshold.
CH 1 RF In
RF XFORMR
200 MHz 16-bit A/D

8X4 CHANNEL SUMMATION M U X D G TAL DOWNCONVERTER BANK 1: CH 1-8 DEC: 16 - 8192
CH 1 I+Q
M U X F I F 0 1 F I F 0 2
CH 2 RF In
RF XFORMR
200 MHz 16-bit A/D
CH 3 RF In
RF XFORMR
200 MHz 16-bit A/D
CH 2
M U X
CH 3 CH 4
M U X
I+Q
PCI-X BUS CH 3
M U X F I F 0 3 F I F 0 4
PCI-X BUS
CH 1 Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 CH 3 CH 4
CH 2 CH 3 CH 4
M U X
I+Q
PCI-X NTERFACE X linx XC5VLX30T
TTL In
PCI-TO PCI BRIDGE
CH 4
M U X
I+Q
LVPECL Bus
XTAL OSC
Timing Bus
XILINX XC5VSX95T
Pentek, Inc.
www.pentek.com
Model 7652

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, and XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface in the standard unit; optional FPGA: XC5VSX50T PCI Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Local Bus: 64-bit, 66 MHz Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard half-length PCI board

The architecture includes a flexible timing and synchronization circuit that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to three 7652s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.
PCI-X Interface
Model 7652 Description 32-Channel DDC with four 200 MHz, 16-bit A/Ds - PCI
Pentek, Inc.
www.pentek.com
Model 7653
4/2-Ch. DDC, four 200 MHz 16-bit A/Ds, Beamformer - PCI

General Information
Model 7653 is a 4-channel, high-speed software radio board designed for processing baseband RF or IF signals. It features four 200 MHz 16-bit A/Ds supported by a high-performance 4-channel DDC (digital downconverter) and a complete set of beamforming functions. With built-in multiboard synchronization, it is ideally matched to the requirements of real-time software radio and radar systems. The Model 7653 attaches directly to computer motherboards with PCI bus slots. Front panel connectors are brought out on the rear panel. Each of the DDC channels has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency.


Built-in Beamformer supports multiboard systems Programmable Power Meter and Threshold Detect per channel Four 200 MHz, 16-bit A/Ds 2 or 4 Channels of DDC Independent 32-bit DDC tuning for all channels DDC decimation range from 2 to 256 or from 2 to 65536 Independent decimation factors for each channel Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multimodule synchronization

Power Meters
CH 1 RF In
RF XFORMR
200 MHz 16-bit A D
M U X SUMMER
SUM IN SUM OUT
AURORA G GABIT SERIAL NTERFACE F I F 0 1 F I F 0 2
4X 4X P15 XMC
CH 2 RF In
RF XFORMR
200 MHz 16-bit A D
I+Q CH 1
M U X
CH 3 RF In
RF XFORMR
200 MHz 16-bit A D
D GITAL DOWNCONVERTER CH 1 DEC: 2 - 65536 (DEC: 2 - 256)*
I+Q
CH 4 RF In
RF XFORMR
200 MHz 16-bit A D
CH 1 CH 2 CH 3 CH 4
M U X
CH 2
M U X
D GITAL DOWNCONVERTER CH 2 DEC: 2 - 65536 (DEC: 2 - 256)*
I+Q
PCI-X BUS CH 3
M U X F I F 0 3 F I F 0 4
PCI-X BUS
CH 1 TIMING BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 XTAL OSC CH 3 CH 4

M U X D GITAL DOWNCONVERTER CH 4 (DEC: 2 - 256)*
CH 2 CH 3 CH 4
M U X
D GITAL DOWNCONVERTER CH 3 (DEC: 2 - 256)*
I+Q
PCI-X NTERFACE
XILINX XC5VLX30T
PCI-TO-PCI BRIDGE
CH 4
M U X
I+Q
XILINX XC5VSX95T
Pentek, Inc.
www.pentek.com
Model 7653

Beamformer
In addition to the A/Ds and DDCs, the 7653 includes essential resources of a complete beamforming subsystem. First, each DDC channel provides user-programmable I & Q phase and gain adjustments to apply beamforming weights. Then, a summation block adds the four DDC output channels. An additional programmable-gain stage compensates for summation bit growth. A power meter and threshold detect block is provided for the sum output. The sum output is then delivered to the Channel 1 FIFO for delivery through the PCI-X bus. For larger systems, multiple 7653s can be chained together using a built-in Xilinx Aurora engine. It accepts an x4 gigabit sum input stream from a previous board and propagates an x4 sum output stream to the next board through the P15 XMC connector.

The architecture includes a flexible timing and synchronization circuit that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to three 7653s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.
XMC Interface
For large systems, multiple 7653s can be chained together via a built-in Xilinx Aurora interface through the P15 XMC connector. This link creates a board-toboard summation expansion chain for creating larger multichannel beamformer systems. Xilinxs Aurora protocol is used to provide an efficient x4, 1.25 GB/sec point-to-point data path between boards.

PCI-X Interface
PHASE SHIFT
GAIN
I Q
I Q
I
Q
I
Q
AURORA PORT
SUMMAT ON EXPANSION CHAIN IN 1 25 GByte/sec x4 Au ora Link
F om P evious Board
P15
GAIN
I
Q
I
Q
I
Q
I
Q
SUMMAT ON CHAIN BIT GROWTH COMPENSAT ON
I Q
I Q
I Q
GAIN
I Q
I Q
I
Q
I
Q
SUMMATION POWER METER & THRESHO D DETECT
AURORA PORT
To Next Boa d
GAIN
P15 I Q
I Q
I Q
I Q
Weigh Phase I Weight Phase Q Weight Gain
Pentek, Inc.
www.pentek.com
Model 7653

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillator, external reference or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC-coupled 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS, input/output LVPECL bus; one gate/trigger and one sync/PPS input TTL signal Digital Downconverter Type: IP core for Xilinx Virtex-5 Qty of DDC Channels: 2 or 4 Center Frequency Tuning: 4 tuning words, one for each DDC channel Center Frequency Tuning Range: DC to s with 32 bit resolution NCO SFDR: 120 dBFS Channel Phase Offset Adjustment: 32-bit resolution Channel Gain Adjustment: 32-bit resolution Input Selection for DDC Banks: Any channel can select any of the four A/Ds Decimation Range (N): 2-Channel Mode: 2 to 65536 4-Channel Mode: 2 to 256 FIR Filter: Default passband 0.8*s/N with 0.2 dB passband ripple and 100 dB adjacent channel rejection FIR Filter Coefficients: 18 bits, user-programmable (default values provided) Qty FIR Filter Taps: 28*N/8 Output Format: 24 bits I + 24 bits Q Output Spectrum Modes: Normal or frequency reversed Output Spectrum Offset: No offset or offset by one-half the output bandwidth Beamformer Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Output Multiplexer and FIFO Qty Output FIFOs: Four FIFO Source Selection: Independent multiplexer selects DDC output or A/D PCI Interface PCI-X Bus: 64 bits, 100 MHz and 64 or 32 bits at 33 or 66 MHz DMA: 4-channel demand-mode and chaining controller Local Bus: 64-bit, 66 MHz Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard half-length PCI board
Model 7653 Description 4-Channel DDC with four 200 MHz, 16-bit A/Ds and Beamformer - PCI
Pentek, Inc.
www.pentek.com
Model 7656
Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI
General Information
Model 7656 is a half-length PCI board that includes two 400 MHz A/Ds, 800 MHz D/As and Virtex-5 FPGAs. It consists of one Model 7156 PMC module mounted on a PCI carrier board. The Model 7656 attaches directly to computer motherboards with PCI bus slots. Front panel connectors are brought out on the rear panel.
Virtex-5 FPGAs
RF In
RF XFORMR
A/D Converter Stage

The front end accepts two full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into TI ADS5474 14-bit 400 MHz A/Ds. Designed with a 750 MHz input bandwidth, the A/Ds are excellent for undersampling applications. The digital outputs are delivered into the Virtex-5 processing FPGA for signal processing, data capture or routing to other board resources.

Features

Complete software radio interface solution Two 400 MHz, 14-bit A/Ds One digital upconverter Two 800 MHz, 16-bit D/As Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR
RF Out
RF XFORMR
RF Out
RF XFORMR
A/D Clock Bus
400 MHz 14 BIT A/D
400 MHz 14 BIT A/D
800 MHz 16 BIT D/A
800 MHz 16 BIT D/A
TTL Gate / Trig TTL Sync / PPS Sample Clk Sync Clk Gate A Gate B Sync PPS
DIGITAL UPCONVERTER
D/A Clock Bus

Tim ng Bus
VCXO
Control/ Status
PROCESSING FPGA VIRTEX 5 LX50T LX155T SX50T SX95T or FX100T LVDS 8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T LVDS 32 4X
LVDS
PCI X INTERFACE
64
LVDS 32 32
32
PCI-X BUS
64-pin DIN PGA /O (Option -104) PCI-X BUS
PCI-TO-PCI BRIDGE
Pentek, Inc.
www.pentek.com
Model 7656
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 adds a 64-pin DIN connector with 16 pairs of LVDS connections to each FPGA for custom I/O.
Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 400 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs a 64-pin DIN connector with 16 LVDS pairs to the processing FPGA and 16 pairs to the interface FPGA mapped as two 16-bit read/write registers Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard half-length PCI board

Two internal timing buses can provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An internal clock generator receives an external sample clock from the front panel SMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage controlled crystal oscillator. In this mode, the front panel SMC connector can be used to provide a 10 MHz system reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to three slave 7656s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGA. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.
PCI-X Interface
Model 7656 Description Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI
Options: -104 FPGA I/O through a 64-pin DIN connector
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB
Pentek, Inc.
www.pentek.com
Model 7658
General Information
Model 7658 is a half-length PCI board that includes two 500 MHz A/Ds, 800 MHz D/As and Virtex-5 FPGAs. It consists of one Model 7158 PMC module mounted on a PCI carrier board. The Model 7658 attaches directly to computer motherboards with PCI bus slots. Front panel connectors are brought out on the rear panel.
Virtex-5 FPGAs
RF In
RF XFORMR
A/D Converter Stage

The front end accepts two full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into TI ADS5463 12-bit 500 MHz A/Ds. Designed with a 750 MHz input bandwidth, the A/Ds are excellent for undersampling applications. The digital outputs are delivered into the Virtex-5 processing FPGA for signal processing, data capture or routing to other board resources.

Features

Complete software radio interface solution Two 500 MHz, 12-bit A/Ds One digital upconverter Two 800 MHz, 16-bit D/As Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR
RF Out
RF XFORMR
RF Out
RF XFORMR
A/D Clock Bus
500 MHz 12 BIT A/D
500 MHz 12 BIT A/D
800 MHz 16 BIT D/A
800 MHz 16 BIT D/A
DIGITAL UPCONVERTER
D/A Clock Bus

Tim ng Bus
VCXO
Control/ Status
PROCESSING FPGA VIRTEX 5 LX50T LX155T SX50T SX95T or FX100T LVDS 8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T LVDS 32 4X
LVDS
PCI X INTERFACE
64
LVDS 32 32
32
PCI-X BUS
64-pin DIN PGA /O (Option -104) PCI-X BUS
PCI-TO-PCI BRIDGE
Pentek, Inc.
www.pentek.com
Model 7658
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 adds a 64-pin DIN connector with 16 pairs of LVDS connections to each FPGA for custom I/O.
Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits D/A Converters Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 500 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs a 64-pin DIN connector with 16 LVDS pairs to the processing FPGA and 16 pairs to the interface FPGA mapped as two 16-bit read/write registers Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard half-length PCI board

Memory Resources
PCI-X Interface Ordering Information

Model 7658 Description Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI
Options: -104 FPGA I/O through a 64-pin DIN connector -140 1 GB DDR2 SDRAM
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors
Pentek, Inc.
www.pentek.com
RAD AR & SDR I/O - x 8 PCI Express RADAR

MODEL
7850 7851 7852 7853 7856 7858 Cobalt 78620 Cobalt 78621 Cobalt 78630 Cobalt 78640 Cobalt 78641 Cobalt 78650 Cobalt 78651 Cobalt 78660 Cobalt 78661 Cobalt 78662 Cobalt 78670 Cobalt 78671 Cobalt 78690 Cobalt 7809 Onyx 78720 Onyx 78760 Onyx 78730 8266
DESCRIPTION
Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - x8 PCIe 256-Channel DDC with Four 200 MHz, 16-bit A/Ds - x8 PCIe 32-Channel DDC with Four 200 MHz, 16-bit A/Ds - x8 PCIe 4/2-Channel DDC, four 200 MHz 16-bit A/Ds, Beamformer - x8 PCIe Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - x8 PCIe Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - x8 PCIe 3-Channel 200 MHz A/D, 2-Channel 800 MHz D/A, Virtex-6 FPGA - x8 PCIe 3-Channel 200 MHz A/D with DDC, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - x8 PCIe 1 GHz A/D and D/A, Virtex-6 FPGA - x8 PCIe 1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D, Virtex-6 FPGA - x8 PCIe 1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D, Wideband DDC, Virtex-6 FPGA - x8 PCIe Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - x8 PCIe 2-Chan 500 MHz A/D with DDC, DUC with 2-Chan 800 MHz D/A, Virtex-6 FPGA - x8 PCIe 4-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - x8 PCIe 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - x8 PCIe 4-Channel 200 MHz A/D with 32-Channel DDC and Virtex-6 FPGA - x8 PCIe 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - x8 PCIe 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - x8 PCIe L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - x8 PCIe 4-Channel SFP Transceiver PCIe Module for Cobalt Boards 3-Channel 200 MHz A/D, 2-Channel 800 MHz D/A, Virtex-7 FPGA - x8 PCIe 4-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - x8 PCIe 1 GHz A/D and D/A, Virtex-7 FPGA - x8 PCIe
PC Development System for PCIe Cobalt and Onyx Boards
Customer Information
& & & & & &
PMC/XMC CompactPCI PCI 3U VPX - FORMA T 1 FORMAT AMC 3U VPX - FORMA T 2 FORMAT

www.pentek.com
Model 7850
Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - x8 PCIe

General Information
Model 7850 is a high-speed data converter suitable for connection as the HF or IF input of a communications system. It features four 200 MHz, 16-bit A/Ds. These are supported by an array of data processing and transport resources ideally matched to requirements of high-performance systems. The 7850 attaches to motherboards with half-length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems. cessing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the A/D converters, DDR2 SDRAM memory, interface FPGA, programmable LVPECL I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T and FX100T. The SXT parts feature between 288 and 640 DSP48E Slices and are ideal for demodulation/modulation, decoding/ encoding, decryption/encryption, digital delay and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the Model 7150 can be optionally configured with an LX155T in the processing FPGA position for 155,648 logic cells. The interface FPGA provides board connections including PCI-X or PCI Express. Implementing the PCI interfaces in this FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT or an SXT family part, providing not only interface functionality, but processing resources up to an additional 640 DSP48E Slices. Option -104 installs a GPIO connector with 16 pairs of LVDS connections to the processing FPGA, and 16 pairs of LVDS connections to the interface FPGA for custom I/O.
RF In
RF XFORMR Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS To All Sections
A/D Converter Stage

The front end accepts four full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-5 FPGA for signal processing or for routing to other module resources.
Virtex-5 FPGAs
The Model 7850 architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory- shipped functions. There are two FPGA types on the 7850: processing and interface. The pro-
Features

Complete software radio interface solution PCI Express 2.0 (Gen. 2) Interface up to x8 wide Built-in fan for added cooling Four 200 MHz 16-bit A/Ds Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Up to 2.56 seconds of data capture at 200 MHz LVPECL clock/sync bus for multimodule synchronization Up to 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR
RF In
RF XFORMR
RF In
RF XFORMR
Clock/Sync Bus
TTL In
200 MHz 16 bit A/D
200 MHz 16 bit A/D
200 MHz 16 bit A D
200 MHz 16 bit A/D
LVPECL Bus
XTL OSC
Control/ Status
PROCESSING FPGA VIRTEX 5 LX50T SX50T SX95T LX155T or FX100T

GTP GTP GTP LVDS
Timing Bus
8
4X 4X
4X
GTP
64
FLASH 32 MB
INTERFACE FPGA VIRTEX 5 LX30T or SX50T

GTP PCI X LVDS
4X
64
32
PCI X BUS 1 (64 Bits, 100 MHz)
32
4X Gbit Serial
4X Gbit Ser al 4X 4X
PCI TO PCIe BRIDGE
GPIO 1 (68-Pin)
x4 PCIe
PCI EXPRESS SWITCH PEX 8648
x8 PCI Express
SER I/O A SER I/O B
Pentek, Inc.
www.pentek.com
Model 7850

The Model 7850 architecture includes a flexible timing and synchronization circuit for each bank of four A/D converters, allowing the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. Each timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/ Sync connector allows multiple boards to be synchronized. In the slave mode, each accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to three slave 7850s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VLX155T and XC5VFX100T Interface FPGA: Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Provides GPIO with 16 LVDS pairs to the processing FPGA and 16 pairs to the interface FPGA Memory DDR2 SDRAM: Up to 1 GB in two banks PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x8 width PCIe Ports: two x4 ports to processing FPGA; one can be alternately routed to interface FPGA one x4 port to PCI bus one x8 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe , 4.38 in. x 6.6 in.
Memory Resources

The 7850 includes a multiple port, 48-lane Gen. 2 PCI Express (PCIe) switch with integrated SerDes. The switch provides x8 wide connection to the PCIe interface, allowing high-speed data transfers to and from the motherboard. Switch ports each include buffer memory to minimize bottlenecks, with two x4 PCIe connections provided to the processing FPGA, as well as one x4 connection to the 64-bit PCI-X interface. Option -5xx adds two full duplex 4X gigabit serial paths on high-speed connectors, supporting PCIe or other gigabit protocols.
Model 7850 Description Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs Half-length x8 PCIe
Options: -104 FPGA I/O through the GPIO connector(s) -5xx Gigabit Serial I/O - two full duplex 4X paths
Pentek, Inc.
www.pentek.com
Model 7851
256-Channel DDC with Four 200 MHz, 16-bit A/Ds - x8 PCIe

General Information
Model 7851 is a high-speed software radio module designed for processing baseband RF or IF signals from a communications receiver. It features four 200 MHz 16-bit A/Ds. The A/D converters are supported by a high-performance 256-channel installed DDC (digital down-converter) IP Core and interfaces ideally matched to the requirements of real-time software radio and radar systems. The 7851 attaches to motherboards with half-length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems. including one A/D driving all 256 DDC channels and each of the four A/Ds driving its own DDC bank. Each of the DDCs has an independent 32-bit tuning frequency setting that ranges from DC to s where s is the A/D sample rate.

A/D Converter Stage

The front end accepts four full-scale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing.
Features


The Model 7851 SX95T FPGA employs an advanced FPGA-based digital downconverter engine consisting of four identical 64-channel DDC banks. Four independently controllable input multiplexers select one of the attached four A/Ds as the input source for each DDC bank. In this way, many different configurations can be achieved
Complete software radio interface solution PCI Express 2.0 (Gen. 2) Interface up to x8 wide Built-in fan for added cooling 256 DDC channels Four 200 MHz 16-bit A/Ds Independent tuning for each channel DDC decimation from 128 to 1024 in steps of 64 Independent decimation for each bank Each bank independently selects one of four A/Ds User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multimodule synchronization
CH 1 RF In
RF XFORMR
200 MHz 16-bit A/D
CH 2 RF In
RF XFORMR
200 MHz 16-bit A/D
CH 1 CH 2 CH 3 CH 4
CH 1 I+Q
M U X
FIFO 1
CH 3 RF In
RF XFORMR
200 MHz 16-bit A/D
CH 2
CH 3 CH 4
I+Q
M U X
FIFO 2
Sample Clock In PPS In TTL In LVPECL Bus Timing Bus

CH 3
CH 2 CH 3 CH 4
I+Q
M U X
FIFO 3
CH 4 I+Q
M U X
FIFO 4
XILINX XC5VSX95T
Xilinx XC5VLX30T PCI-X NTERFACE
PCI TO PCIe BRIDGE
PCI-X BUS 1
x4 PCIe
PCI EXPRESS SW TCH PEX 8648
x8 PCI Exp ess
Pentek, Inc.
www.pentek.com
Model 7851

Four output MUXs in the SX95T FPGA can be independently switched to deliver either A/D or DDC data into each output FIFO. This allows users to view either wideband A/D data or narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI bus.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX95T dedicated to digital downcoverters and output Interface FPGA: Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface PCI to PCIe Interface PCI-X Bus: 64-bits, 133 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x8 width PCIe Ports: one x4 port to PCI-X bus one x8 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe, 4.38 in. x 6.6 in.

The Model 7851 architecture includes a flexible timing and synchronization circuit for the bank of four A/D converters, allowing the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connectors allows multiple boards to be synchronized. In the slave mode, each accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple bords. Up to three slave 7851s can be driven from each LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.

The 7851 includes a multiple port, 48-lane Gen. 2 PCI Express (PCIe) switch with integrated SerDes. The switch provides x8 wide connection to the PCIe interface, allowing high-speed data transfers to and from the motherboard. Switch ports each include buffer memory to minimize bottlenecks, with a x4 connection provided to the 64-bit PCI-X interface.
Model 7851 Description 256-Channel DDC with four 200 MHz, 16-bit A/D - Half-length x8 PCIe
Pentek, Inc.
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Model 7852

General Information
Model 7852 is a high-speed software radio module designed for processing baseband RF or IF signals from a communications receiver. It features four 200 MHz 16-bit A/Ds. The A/Ds are supported by a high-performance 32-channel installed DDC (digital downconverter) IP Core, and interfaces ideally matched to the requirements of real-time software radio and radar systems. The 7852 attaches to motherboards with half-length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems.

All of the eight channels within a bank share a common decimation setting that can range from 16 to 8192, programmable in steps of 8. For example, with a sampling rate of 200 MHz, the available output bandwidths range from 19.53 kHz to 10.0 MHz. Each 8-channel bank can have a unique decimation setting supporting up to four different output bandwidths for the board. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. Rejection of adjacent-band components within the 80% bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N. Any number of channels can be enabled with each bank, selectable from 0 to 8. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within the bank.
A/D Converter Stage

The front end accepts four full-scale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing.

The Model 7852 SX95T FPGA employs an advanced FPGA-based digital downconverter engine consisting of four identical 8-channel DDC banks. Four independently controllable input multiplexers select one of the four attached A/Ds as the input source for each DDC bank. In this way, many different configurations can be achieved including one A/D driving all 32 DDC channels and each of the four A/Ds driving its own DDC bank. Each of the DDCs has an independent 32-bit tuning frequency setting ranging from DC to s (s is the A/D sample rate).

The 7852 features 32 power meters that continuously measure the individual average power output of each DDC channel. The time constant of the averaging interval for each meter is programmable up to 16 kilosamples. In addition, threshold detectors automatically send an interrupt to the processor if the average power level of any DDC falls below or exceeds a programmable threshold.
Features

Complete software radio interface solution PCI Express 2.0 (Gen. 2) Interface up to x8 wide Built-in fan for added cooling 32 channels of DDC in banks of 8 channels Independent 32-bit DDC tuning for all channels DDC decimation from 16 to 8192 in steps of 8 Bandwidths from 20 kHz to 10 MHz Different decimation factors between banks User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection Power meters and threshold detectors LVPECL clock/sync bus for multimodule synchronization
CH 1 RF In
RF XFORMR
200 MHz 16 bit A/D

8X4 CHANNEL SUMMATION M U X DDC BANK 1 CH 1 8 DEC 16 8192
CH 1 I+Q
M U X F I F 0 1 F I F 0 2 F I F 0 3 F I F 0 4
CH 2 RF In
RF XFORMR
200 MHz 16 bit A/D
CH 3 RF In
RF XFORMR
200 MHz 16 bit A/D
RF XFORMR 200 MHz 16 bit A/D
CH 2
M U X
CH 3 CH 4
M U X
DDC BANK 2 CH 9 16 DEC 16 8192
I+Q
Sample C k In PPS In
CH 1 TIMING BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 CH 3 CH 4

M U X DDC BANK 4 CH 25 32 DEC 16 8192
CH 3
M U X
CH 2 CH 3 CH 4
M U X
TTL In
DDC BANK 3 CH 17 24 DEC 16 8192
I+Q
CH 4
M U X
LVPECL Bus
I+Q
XTAL OSC
Timing Bus
XILINX XC5VSX95T
Xilinx XC5VLX30T PCI X INTERFACE
PCI TO PCIe BRIDGE
PCI X BUS 1
x4 PCIe
x8 PCI Express
Pentek, Inc.
www.pentek.com
Model 7852

Four output MUXs in the SX95T FPGA can be independently switched to deliver either A/D data or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D data or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input rate and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI bus.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX95T dedicated to digital downcoverters and output Interface FPGA: Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x8 width PCIe Ports: one x4 port to PCI-X bus one x8 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe , 4.38 in. x 6.6 in.

The Model 7852 architecture includes a flexible timing and synchronization circuit for the group of four A/D converters that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, each accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to three slave 7852s can be driven from each LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. For larger systems, many more modules can be synchronized with an external clock and sync generator.

The 7852 includes a multiple port, 48-lane Gen. 2 PCI Express (PCIe) switch with integrated SerDes. The switch provides x8 wide connection to the PCIe interface, allowing high-speed data transfers to and from the motherboard. Switch ports each include buffer memory to minimize bottlenecks, with one x4 connection provided to the 64-bit PCI-X interface.
Model 7852 Description 32-Channel DDC with four 200 MHz, 16-bit A/D s Half-length x8 PCIe
Pentek, Inc.
www.pentek.com
Model 7853
4/2-Ch. DDC, four 200 MHz 16-bit A/Ds, Beamformer - x8 PCIe

General Information
Model 7853 is a high-speed software radio board designed for processing baseband RF or IF signals from a communications receiver. It features four 200 MHz 16-bit A/Ds supported by a high-performance 4-channel installed DDC (digital downconverter) and a complete set of beamforming functions. With buit-in multiboard synchronization, it is ideally matched to the requirements of real-time software radio and radar systems. The 7853 attaches to motherboards with half-length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems. Each of the DDC channels has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency.

Features

A/D Converter Stage

Built-in Beamformer supports multiboard systems Programmable Power Meter and Threshold Detect per channel Four 200 MHz, 16-bit A/Ds 2 or 4 Channels of DDC PCI Express 2.0 (Gen. 2) interface up to x8 wide Independent 32-bit DDC tuning for all channels DDC decimation range from 2 to 256 or from 2 to 65536 Independent decimation factors for each channel Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multiboard synchronization

Power Meters
CH 1 RF In
RF XFORMR
200 MHz 16-bit A D
M U X SUMMER
SUM IN SUM OUT
AURORA GIGAB T SERIAL INTERFACE F I F 0 1 F I F 0 2 F I F 0 3 F I F 0 4
4X 4X P15 XMC
CH 2 RF In
RF XFORMR
200 MHz 16-bit A D
I+Q CH 1
M U X
CH 3 RF In
RF XFORMR
200 MHz 16-bit A D
I+Q
CH 4 RF In
RF XFORMR
200 MHz 16-bit A D
CH 1 CH 2 CH 3 CH 4
M U X
CH 2
M U X
I+Q
Xilinx XC5VLX30T PCI-X INTERFACE PCI-X BUS 1

M U X D G TAL DOWNCONVERTER CH 4 (DEC: 2 - 256)*
CH 3
M U X
CH 2 CH 3 CH 4
M U X
D G TAL DOWNCONVERTER CH 3 (DEC: 2 - 256)*
I+Q
PCI TO PCIe BRIDGE

x4 PCIe PCI EXPRESS SWITCH PEX 8648 x8 PCI Express
CH 4
M U X
I+Q
XILINX XC5VSX95T
Pentek, Inc.
www.pentek.com
Model 7853

Beamformer
In addition to the A/Ds and DDCs, these Models include essential resources of a complete beamforming subsystem. First, each DDC channel provides user-programmable I & Q phase and gain adjustments to apply beamforming weights. Then, a summation block adds the four DDC output channels. An additional programmable-gain stage compensates for summation bit growth. A power meter and threshold detect block is provided for the sum output. The sum output is then delivered to the Channel 1 FIFO for delivery through the PCI-X bus. For larger systems, multiple Models can be chained together using a built-in Xilinx Aurora engine. It accepts an x4 gigabit sum input stream from a previous board and propagates an x4 sum output stream to the next board through the P15 XMC connector.

The Model 7853 architecture includes a flexible timing and synchronization circuit for the group of four A/D converters that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, each accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to three slave 7853s can be driven from each LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. For larger systems, many more boards can be synchronized with an external clock and sync generator.
XMC Interface
For large systems, multiple 7853s can be chained together via a built-in Xilinx Aurora interface through the P15 XMC connector. This link creates a board-toboard summation expansion chain for creating larger multichannel beamformer systems. Xilinxs Aurora protocol is used to provide an efficient x4, 1.25 GB/sec point-to-point data path between boards.


The 7853 includes a multiple port, 48-lane Gen. 2 PCI Express (PCIe) switch with integrated SerDes. The switch provides x8 wide connection to the PCIe interface, allowing high-speed data transfers to and from the motherboard. Switch ports each include buffer memory to minimize bottlenecks, with one x4 connection provided to the 64-bit PCI-X interface.
PHASE SHIFT
GAIN
I Q
I Q
I
Q
I
Q
AURORA PORT
SUMMAT ON EXPANS ON CHAIN IN 1 25 GByte/sec x4 Auro a Link
F om P evious Boa d
P15
GAIN
I Q
I Q
I Q
I Q
SUMMATION CHA N B T GROWTH COMPENSAT ON
I Q
I Q
I Q
GAIN
I Q
I Q
I
Q
I
Q
SUMMATION POWER METER & THRESHOLD DETECT
AURORA PORT
SUMMAT ON EXPANS ON CHA N OUT 1 25 GByte/sec x4 Auro a Link
To Next Board
GAIN
P15 I
Q
I
Q
I
Q
Pentek, Inc.
www.pentek.com
Model 7853

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillator, external reference or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC-coupled 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS, input/output LVPECL bus; one gate/trigger and one sync/PPS input TTL signal Digital Downconverter Type: IP core for Xilinx Virtex-5 Qty of DDC Channels: 2 or 4 Center Frequency Tuning: 4 tuning words, one for each DDC channel Center Frequency Tuning Range: DC to s with 32 bit resolution NCO SFDR: 120 dBFS Channel Phase Offset Adjustment: 32-bit resolution Channel Gain Adjustment: 32-bit resolution Input Selection for DDC Banks: Any channel can select any of the four A/Ds Decimation Range (N): 2-Channel Mode: 2 to 65536 4-Channel Mode: 2 to 256 FIR Filter: Default passband 0.8*s/N with 0.2 dB passband ripple and 100 dB adjacent channel rejection FIR Filter Coefficients: 18 bits, user-programmable (default values provided) Qty FIR Filter Taps: 28*N/8 Output Format: 24 bits I + 24 bits Q Output Spectrum Modes: Normal or frequency-reversed Output Spectrum Offset: No offset or offset by one-half the output bandwidth Beamformer Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Output Multiplexer and FIFO Qty Output FIFOs: Four FIFO Source Selection: Independent multiplexer selects DDC output or A/D PCI to PCIe Interface PCI-X Bus: 64 bits, 100 MHz and 64 or 32 bits at 33 or 66 MHz DMA: 4-channel demand-mode and chaining controller PCIe Interface: Gen. 2, x8 width PCIe Ports: one x4 port to PCI-X bus one x8 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe, 4.38 in. x 6.6 in.
Model 7853 Description 4-Channel DDC with four 200 MHz, 16-bit A/Ds and Beamformer - Half-length x8 PCIe
Pentek, Inc.
www.pentek.com
Model 7856
Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - x8 PCIe
General Information
Model 7856 is a dual-channel, high-speed data converter suitable for connection to HF or IF ports of a communication system. It includes two 400 MHz A/Ds, 800 MHz D/ As and Virtex-5 FPGAs. The 7856 attaches to motherboards with half-length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems.
Virtex-5 FPGAs
The architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family
A/D Converter Stage

The front end accepts two full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into TI ADS5474 14-bit 400 MHz A/Ds. Designed with a 750 MHz input bandwidth, the A/Ds are excellent for undersampling applications. The digital outputs are delivered into the processing FPGA for signal processing, capture or routing to other board resources.

A TI DAC5688 digital upconverter (DUC) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as an upconverter, it interpolates and translates real or complex baseband input signals to any IF center frequency between DC and 300 MHz. It delivers real or quadrature (I+Q) outputs at up to 500 MHz to the 16-bit D/A converter. Analog output is through a pair of front panel SMC connectors at +4 dBm into 50 ohms. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC provides interpolation factors of 2x, 4x and 8x.
Features

Complete software radio interface solution PCI Express 2.0 (Gen. 2) Interface up to x8 wide Built-in fan for added cooling Two 400 MHz, 14-bit A/Ds One DUC (Digital Upconverter) Two 800 MHz, 16-bit D/As Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR Sample Clk / Reference Clk In PPS In TIM NG BUS GENERATOR Clock / Sync / Gate / PPS
RF In
RF XFORMR
RF Out
RF XFORMR
RF Out
RF XFORMR
A/D Clock Bus D/A Clock Bus
400 MHz 14 BIT A/D 14
400 MHz 14 BIT A D 14
800 MHz 16 BIT D A
800 MHz 16 BIT D/A
DIGITAL UPCONVERTER 32
To All Sections VCXO
T ming Bus
Control/ Status
PROCESSING FPGA VIRTEX 5 LX50T LX155T SX50T SX95T or FX100T

GTP GTP GTP LVDS
8 FLASH 32 MB
4X
4X
4X
GTP
64

PCI X LVDS
GTP
4X
64
32
32
PCI X BUS 1 (64 B ts 100 MHz)
4X Gbit Serial
4X Gbit Serial 4X 4X
PCI TO PCIe BRIDGE
GPIO 1 (68-Pin)
x4 PCIe
SER /O A
SER /O B
x8 PCI Exp ess
Pentek, Inc.
www.pentek.com
Model 7856
part, providing not only interface
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 installs a GPIO connector with 16 pairs of LVDS connections to the processing FPGA, and 16 pairs of LVDS connections to the interface FPGA for custom I/O. Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 400 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Provides GPIO with 16 LVDS pairs to each processing FPGA and 16 pairs to each interface FPGA Memory DDR2 SDRAM: Up to 1.0 GB in two banks to processing FPGA PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x8 width PCIe Ports: two x4 ports to FPGA; one x4 port to PCI bus; one x8 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe, 4.38 in. x 6.6 in.

The 7856 includes a multiple port, 48-lane Gen. 2 PCIe switch with integrated SerDes. The switch provides x8 wide connection to the PCIe interface, allowing high-speed data transfers to and from the motherboard. Switch ports include buffer memory to minimize bottlenecks. Two x4 PCIe connections are provided to the FPGA, as well as one x4 connection to the 64-bit PCI-X interface. Option -5xx adds two full duplex 4X gigabit serial paths on high-speed connectors, supporting PCIe or other gigabit protocols.

Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGAs. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.
Model 7856 Description Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Half-length x8 PCIe
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: TI DAC5688
Options: -104 FPGA I/O through the GPIO connector(s) -5xx Gigabit serial I/O: two fullduplex 4X paths
Pentek, Inc.
www.pentek.com
Model 7858
General Information
Model 7858 is a dual-channel, high-speed data converter suitable for connection to HF or IF ports of a communication system. It includes two 500 MHz A/Ds, 800 MHz D/ As and Virtex-5 FPGAs. The 7858 attaches to motherboards with half-length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems.
Virtex-5 FPGAs
The architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family part, providing not only interface
RF In
RF XFORMR
A/D Converter Stage


A TI DAC5688 digital upconverter (DUC) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as an upconverter, it interpolates and translates real or complex baseband input signals to any IF center frequency between DC and 300 MHz. It delivers real or quadrature (I+Q) outputs at up to 500 MHz to the 16-bit D/A converter. Analog output is through a pair of front panel SMC connectors at +4 dBm into 50 ohms. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC provides interpolation factors of 2x, 4x and 8x.
Features

Complete software radio interface solution PCI Express 2.0 (Gen. 2) Interface up to x8 wide Built-in fan for added cooling Two 500 MHz, 12-bit A/Ds One DUC (Digital Upconverter) Two 800 MHz, 16-bit D/As Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR
RF Out
RF XFORMR
RF Out
RF XFORMR
TIM NG BUS GENERATOR Clock / Sync / Gate / PPS
500 MHz 12 BIT A/D 14
500 MHz 12 BIT A D 14
800 MHz 16 BIT D A
800 MHz 16 BIT D/A
T ming Bus
Control/ Status
PROCESSING FPGA VIRTEX 5 LX50T LX155T SX50T SX95T or FX100T

GTP GTP GTP LVDS
8 FLASH 32 MB
4X
4X
4X
GTP
64

PCI X LVDS
GTP
4X
64
32
32
PCI X BUS 1 (64 B ts 100 MHz)
4X Gbit Serial
4X Gbit Serial 4X 4X
PCI TO PCIe BRIDGE
GPIO 1 (68-Pin)
x4 PCIe
SER /O A
SER /O B
x8 PCI Express
Pentek, Inc.
www.pentek.com
Model 7858
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 installs a GPIO connector with 16 pairs of LVDS connections to the processing FPGA, and 16 pairs of LVDS connections to the interface FPGA for custom I/O.
Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 500 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Provides GPIO with 16 LVDS pairs to each processing FPGA and 16 pairs to each interface FPGA Memory DDR2 SDRAM: Up to 1.0 GB in two banks to processing FPGA PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x8 width PCIe Ports: two x4 ports to FPGA; one x4 port to PCI bus; one x8 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe, 4.38 in. x 6.6 in.

The 7858 includes a multiple port, 48-lane Gen. 2 PCIe switch with integrated SerDes. The switch provides x8 wide connection to the PCIe interface, allowing high-speed data transfers to and from the motherboard. Switch ports include buffer memory to minimize bottlenecks. Two x4 PCIe connections are provided to the FPGA, as well as one x4 connection to the 64-bit PCI-X interface. Option -5xx adds two full duplex 4X gigabit serial paths on high-speed connectors, supporting PCIe or other gigabit protocols.

Memory Resources
Model 7858 Description Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Half-length x8 PCIe
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits D/A Converters Type: TI DAC5688
Options: -104 FPGA I/O through the GPIO connector -140 1 GB DDR2 SDRAM -5xx Gigabit serial I/O: two fullduplex 4X paths
Pentek, Inc.
www.pentek.com
! w e N
Model 78620
3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - x8 PCIe
General Information
Model 78620 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes three A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78620 includes optional general-purpose and gigabit serial card edge connectors for application-specific I/O . and a PCIe interface complete the factoryinstalled functions and enable the 78620 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 78620 factory-installed functions include three A/D acquisition and a D/A waveform playback IP modules, ideally matched to the boards analog interfaces. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator,
RF In

The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105 connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board.
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three 200 MHz 16-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
16
Timing Bus
VCXO

LVDS
GTX
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
40
8X
4X
4X
Optional FPGA GPIO 68-pin Header
x8 PCIe
Optional Serial I/O Dual 4X Serial Conn
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCI Express
Pentek, Inc.
www.pentek.com
Model 78620
A/D Converter Stage
The front end accepts three full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78620s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Memory Resources
to D/A D/A loopback


INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
MEMORY CONTROL
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 78620
boards DMA capabilities, providing
FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks. 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe card, 4.38 in. x 7.13 in.
Model 8266
The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards. It was created to save engineers and system integrators the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards.

The Model 78620 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the board.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz
Model 78620 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-6 FPGA PCIe XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector Gigabit serial FPGA I/O through two 4X top edge connectors Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Description PC Development System See 8266 Datasheet for Options
Options: -062 -064 -104
-105
-150
-160
-155
-165
Model 8266
Pentek, Inc.
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! w e N
Model 78621
3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe
General Information
Model 78621 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with programmable DDCs, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes three A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78621 includes an optional general-purpose connector for applicationspecific I/O. sition modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 78621 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 78621 factory installed functions include three A/D acquisition and a D/A waveform playback IP modules. Each of the three acquisition IP modules contains a powerful, programmable DDC IP core. The waveform playback IP module contains an intrepolation IP core, ideal for matching playback rates to the data and decimation rates of the acquiRF In

The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O.
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three 200 MHz 16-bit A/Ds Three multiband DDCs (digital downconverters) Two 800 MHz 16-bit D/As One DUC (digital upconverter) Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
16
Timing Bus
VCXO

LVDS
GTX
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
40
8X
4X
4X
x8 PCIe Optional FPGA GPIO 68-pin Header x8 PCI Express Sum from previous board
Aurora Gigabit Serial I/O Sum to next board Dual 4X Serial Conn
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
www.pentek.com
Model 78621
frequency. Each DDC can have its own unique decimation setting, supporting as many as three different output bandwidths for the board. Decimations can be programmed from 2 to 65,536 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or 16-bit I + 16-bit Q samples at a rate of s/N. A programmable summation block provides summing of any of the three DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 78621s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the P16 XMC connector. This allows summation across channels on multiple boards.
Beamformer IP Core
In addition to the DDCs, the 78621 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average power level of any DDC core falls below or exceeds a programmable threshold.

from A/D Ch 1
from A/D Ch 2
to D/A
INPUT MULTIPLEXER
DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all three DDCs or each of the three A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling
DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

MUX
DDC CORE
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
sum out sum in
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
8X PCIe
Pentek, Inc.
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Model 78621
A/D Converter Stage
The front end accepts three analog HF or IF inputs on front panel SSMC connectors with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other board resources. nate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78621s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

A TI DAC5688 DUC (digital upconverter) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x. In addition to the DAC5688, an FPGA based interpolator core provides additional interpolation from 2x to 65,536x. The two interpolators can be combined to crate a total range from 2x to 524,288x.
Memory Resources


Pentek, Inc.
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Model 78621
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Three channels Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformer Summation: Three channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.
Model 8266
Model 78621 Description 3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe
Options: -062 -064 -104 XC6VLX240T XC6VSX315T LVDS FPGA I/O through 68-pin ribbon cable connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Description PC Development System See 8266 Datasheet for Options
-150
-160
-155
-165
Model 8266
Pentek, Inc.
www.pentek.com
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Model 78630
1 GHz A/D and 1 GHz D/A with Virtex-6 FPGA - x8 PCIe

General Information
Model 78630 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes 1 GHz A/D and 1 GHz D/A converters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78630 includes optional general-purpose and gigabit serial card connectors for application specific I/O protocols. generator and a PCIe interface complete the factory-installed functions and enable the 78630 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory installed applications ideally matched to the boards analog interfaces. The 78630 factory-installed functions include an A/D acquisition and a D/A waveform playback IP module. In addition, IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal

RF In RF Out
Features

RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Sync In
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12
1 GHz 16-BIT D/A 16
D/A Sync Bus
VCXO

LVDS
GTX
GTX
GTX
16
16
16
16
16 Config FLASH 64 MB 40
8X
4X
4X
x8 PCIe
QDRII+ option 150
x8 PCI Express
Pentek, Inc.
www.pentek.com
Model 78630

A/D Converter Stage
The front end accepts an analog HF or IF input on a front panel SSMC connector with transformer coupling into a Texas Instruments ADS5400 1 GHz, 12-bit A/D converter. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources. Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or 16 to provide different lower frequency A/D and D/A clocks. A pair of front panel Sync connectors allows multiple boards to be synchronized. They accept CML inputs that drive the boards sync and gate/trigger signals. The Pentek Model 7892 and Model 9192 Cobalt Synchronizers can drive multiple 78630 Sync connectors enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connector.
D/A Converter Stage

Memory Resources
The 78630 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
to D/A


INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 78630

The Model 78630 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the board. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2, or XC6VSX315T-2 Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Option 150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1: x4 or x8 Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.
Specifications
Model 8266
Model 78630 Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T XC6VSX315T LVDS FPGA I/O through 68-pin ribbon cable connector -105 Gigabit serial FPGA I/O through two 4X top edge connectors -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required Model 8266 Description PC Development System See 8266 Datasheet for Options Description 1 GHz A/D and D/A, Virtex-6 FPGA - x8 PCIe
Pentek, Inc.
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! w e N
Model 78640
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, V-6 FPGA - x8 PCIe
General Information
Model 78640 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. The 78640 includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78640 includes optional general-purpose and gigabit serial connectors for application-specific I/O protocols. and a PCIe interface complete the factoryinstalled functions and enable the 78640 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

RF In RF In

Features

Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One-channel mode with 3.6 GHz, 12-bit A/D Two-channel mode with 1.8 GHz, 12-bit A/Ds 2 GB of DDR3 SDRAM Sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface, up to x8 Clock/sync bus for multiboard synchronization Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus

12 12
Sync Bus

LVDS
GTX
GTX
GTX
40
8X
4X
4X
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCIe
x8 PCI Express
Pentek, Inc.
www.pentek.com
Model 78640
A/D Converter Stage
The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the 78640 to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple boards. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple 78640s can be synchronized using the Cobalt high speed sync board to drive the sync bus.
Memory Resources
The 78640 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and data capture capabilities. Built-in memory functions include an A/D data transient capture mode for taking snapshots of data for transfer to a host computer. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.


The Model 78640 includes an industry standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links of x4 or x8, the interface includes multiple DMA controllers for efficient transfers to and from the board.

The 78640 accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connector. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multi-pin sync bus connector allows multiple boards to be
from A/D
from A/D

MEMORY CONTROLLER
FPGA GPIO
Pentek, Inc.
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Model 78640
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Sample Clock Sources: Front panel SSMC connector Sync Bus: Multi-pin connectors, bus includes gate, reset and in and out ref clock External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 XC6VSX315T-2 Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1or Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe card, 4.38 in. x 7.13 in.
Model 8266
Model 78640 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - x8 PCIe
Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector -105 Gigabit serial FPGA I/O through two 4X top edge connectors -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required Model 8266 Description PC Development System See 8266 Datasheet for Options
Pentek, Inc.
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! w e N
Model 78641
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, w/ Wideband DDC, Virtex-6 FPGA - x8 PCIe
General Information
Model 78641 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A highspeed data converter, with a programmable digital downconverter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. It includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78641 includes an optional connection to the Virtex-6 FPGA for custom I/O. nization functions, a test signal generator and a PCIe interface complete the factoryinstalled functions and enable the 78640 to operate as a complete turnkey solution, without the need to develop any FPGA IP. For applications that require additional control and status signals, option -104 provides 20 pairs of LVDS connections from the FPGA on PMC P14 to a 68-pin DIL ribboncable header on the PCIe board for custom I/O.
A/D Converter Stage

The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the 78641 to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple boards. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 78641 factory-installed functions include an A/D acquisition IP module. In addition, IP modules for DDR3 memories, a controller for all data clocking and synchro-
Features

Ideal radar and software radio interface solution One-channel mode with 3.6 GHz, 12-bit A/D Two-channel mode with 1.8 GHz, 12-bit A/Ds 2 GB of DDR3 SDRAM Programable one- or twochannel DDC (Digital Downconverter) 2 GB of DDR3 SDRAM Sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface, up to x8 Clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus

12 12
Sync Bus

GTX
LVDS
8X
40
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCIe
x8 PCI Express
Pentek, Inc.
www.pentek.com
Model 78641
DDC IP Cores

The 78641 accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connector. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multi-pin sync bus connector allows multiple boards to be synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple 78641s can be synchronized using the Cobalt high speed sync board to drive the sync bus.
Memory Resources
The 78640 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and data capture capabilities. Built-in memory functions include an A/D data transient capture mode for taking snapshots of data for transfer to a host computer.
from A/D
from A/D

to Mem Bank 1
to Mem Bank 2
8X PCIe
FPGA GPIO
40
to Mem Bank 3
to Mem Bank 4
Pentek, Inc.
www.pentek.com
Model 78641
The Model 78641 includes an industry standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links of x4 or x8, the interface includes multiple DMA controllers for efficient transfers to and from the board. Sample Clock Sources: Front panel SSMC connector Sync Bus: Multi-pin connectors, bus includes gate, reset and in and out ref clock External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1or Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe card, 4.38 in. x 7.13 in.
Specifications
Model 8266
Model 78641 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, with Wideband DDC, Virtex-6 FPGA - x8 PCIe
Options: -002* -064* -104 -2 FPGA speed grade XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required Model 8266 Description PC Development System See 8266 Datasheet for Options
Pentek, Inc.
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! w e N
Model 78650
Two 500 MHz A/Ds, DUC, 800 MHz D/As,Virtex-6 FPGA - x8 PCIe
General Information
Model 78650 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes two A/Ds, one DUC (Digital Upconverter), two D/As, and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78650 includes optional generalpurpose and gigabit serial card connectors for application specific I/O protocols. the factory-installed functions and enable the 78650 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory installed applications ideally matched to the boards analog interfaces. The 78650 factory-installed functions include two A/D acquisition and one D/A waveform playback IP modules. In addition, IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete
RF In

RF In RF Out RF Out
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two 500 MHz 12-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
A/D Clock/Sync Bus
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
500 MHz 12-BIT A/D
500 MHz 12-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
VCXO

LVDS
Timing Bus
GTX
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
8X
4X
4X
x8 PCIe
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCI Express
Pentek, Inc.
www.pentek.com
Model 78650
A/D Converter Stage
Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an onboard programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78650s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

The front end accepts two full scale analog HF or IF inputs on front panel SSMC connectors at +5 dBm into 50 ohms with transformer coupling into two Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources.

Memory Resources

from A/D Ch 1
to D/A
INPUT MULTIPLEXER

MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
MEMORY CONTROL
to Mem Bank 3
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 78650
boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1: x4 or x8 Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.
Model 8266

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (option 014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz, max. Output IF: DC to 400 MHz, max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz, max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock
Model 78650 Description Two 500 MHz A/Ds, one DUC, two 800 MHz D/As with Virtex-6 FPGA x8 PCIe
Options: -002* -014 -062 -064 -104 -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector -105 Gigabit serial FPGA I/O through two 4X top edge connectors -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -160 Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required Model 8266 Description PC Development System See 8266 Datasheet for Options
Pentek, Inc.
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! w e N
Model 78651
General Information
Model 78651 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A twochannel, high-speed data converter with a programmable DDC, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. The 78651 includes two A/Ds, two D/As and four banks of memory. It features native support for PCI Express Gen 2. memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 78651 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 78651 factory-installed functions include two A/D acquisition and a D/A waveform playback IP modules. Each of the two acquisition IP modules contains a powerful, programmable DDC IP core. The waveform playback IP module contains an intrepolation IP core, ideal for matching playback rates to the data and decimation rates of the acquisition modules. IP modules for either DDR3 or QDRII+
RF In

The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 connects 20 pairs of LVDS signals from the FPGA to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O.
RF In RF Out RF Out
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two 500 MHz 12-bit A/Ds Two multiband DDCs (digital downconverters) Two 800 MHz 16-bit D/As One DUC (digital upconverter) Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 16 MB of QDRII+ SRAM PCI Express (Gen. 2) interface up to x8 Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
500 MHz 12-BIT A/D
500 MHz 12-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
VCXO

LVDS
Timing Bus
GTX
GTX
GTX
8X
4X
4X
Optional FPGA GPIO
x8 PCIe Sum from previous board
68-pin Header x8 PCI Express
QDRII+ option 150
Pentek, Inc.
www.pentek.com
Model 78651
frequency. Each DDC can have its own unique decimation setting, supporting as many as two different output bandwidths for the board. Decimations can be programmed from 2 to 131,072 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 16-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the two DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 78651s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the dual 4X serial connector. This allows summation across channels on multiple boards.
Beamformer IP Core

from A/D Ch 1

INPUT MULTIPLEXER
to D/A

DDC IP Cores
MEMORY CONTROL
MUX
DDC CORE
to Mem Bank 1
to Mem Bank 2
to Mem Bank 4
sum out sum in
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
8X PCIe
Pentek, Inc.
www.pentek.com
Model 78651
A/D Converter Stage
The front end accepts two analog HF or IF inputs on front panel SSMC connectors with transformer coupling into two Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources. nate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78651s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Memory Resources
The 78651 architecture supports up to three independent memory banks which can be configured with QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boardss DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.


Pentek, Inc.
www.pentek.com
Model 78651
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (option -014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits Digital Downconverters Quantity: Two channels Decimation Range: 2x to 131,072x in two programmable stages of 2x to 256x and one fixed 2x stage LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 16-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformer Summation: Two channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via via a dual 4X connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T-2 Optional: Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Memory Option -150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option -155 or -165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.
Model 8266
Model 78651 Description 2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe
Options: -002* -014 -062 -064 -104 -2 FPGA speed grade 400 MHz, 14-bit A/Ds
XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through a 68-pin DIL connector -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required Model 8266 Description PC Development System See 8266 Datasheet for Options
Pentek, Inc.
www.pentek.com
! ew N
Model 78660
4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - x8 PCIe

General Information
Model 78660 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. It includes four A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78660 includes optional general-purpose and gigabit serial connectors for applicationspecific I/O protocols. 78660 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory installed applications ideally matched to the boards analog interfaces. The 78660 factory-installed functions include four A/D acquisition IP modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factory- installed functions and enable the

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

LVDS
GTX
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
8X
4X
4X
x8 PCIe
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCI Express
Pentek, Inc.
www.pentek.com
Model 78660

A/D Converter Stage
The front end accepts four full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources. LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78660s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Memory Resources
The 78660 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the


from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 78660

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.
Model 8266
Model 78660 Options: -062 -064 -104 XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector Gigabit serial FPGA I/O through two 4X top edge connectors Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Description PC Development System See 8266 Datasheet for Options Description 4-Channel 200 MHz A/D with Virtex-6 FPGA - PCIe
-105
-150
-160
-155
-165
Model 8266
Pentek, Inc.
www.pentek.com
! w e N
Model 78661
4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - x8 PCIe
General Information
Model 78661 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with programmable DDCs (digital downconverters), it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture feature offers an ideal turnkey solution. It includes four A/Ds, and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78661 includes an optional general-purpose connector for application-specific I/O. nization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory- installed functions and enable the 78661 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 78661 factory-installed functions include four A/D acquisition IP modules. Each of the four acquisition IP modules contains a powerful, programmable DDC (Digital Downconverter) IP core. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchro-

The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O.
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Four multiband DDCs Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

LVDS
GTX
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
40
8X
4X
4X
x8 PCIe Optional FPGA GPIO 68-pin Header Sum from previous board
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
www.pentek.com
Model 78661
A/D Converter Stage

The front end accepts three analog HF or IF inputs on front panel SSMC connectors with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other board resources.
Beamformer IP Core

from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
DDC IP Cores
INPUT MULTIPLEXER
DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

MUX
DDC CORE
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
sum out sum in
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
8X PCIe
Pentek, Inc.
www.pentek.com
Model 78661
the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78661s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. Beamformer Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.

The Model 78661 includes an industry-standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe Links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the board.
Memory Resources Model 8266

The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards. It was created to save engineers and system integrators the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. The 78661 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
Model 78621 Description 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - x8 PCIe XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Description PC Development System See 8266 Datasheet for Options
Specifications
Options: -062 -064 -104
-150
-160
-155
-165
Model 8266
Pentek, Inc.
www.pentek.com
! w e N
Model 78662
4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - PCIe
General Information
Model 78662 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. This fourchannel, high-speed data converter with programmable DDCs (digital downconverters) is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture feature offers an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes four A/Ds, and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78662 includes optional generalpurpose and gigabit serial connectors for application-specific I/O protocols. voltage and temperature monitoring, DDR3 SDRAM memory controllers, and a PCIe interface complete the factory-installed functions and enable the 78662 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, and triggering. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 78662 factory-installed functions include four A/D acquisition IP modules. Each of the four acquisition IP modules contains a powerful, programmable 8-channel DDC IP core. IP modules for control of all data clocking, synchronization, gate and trigger functions, a test signal generator,

The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105 connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board.
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Four multiband DDCs Up to 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable serial gigabit interfaces Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

LVDS
GTX
GTX
GTX
8X
4X
4X
x8 PCIe
x8 PCI Express
Pentek, Inc.
www.pentek.com
Model 78662

An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a builtin clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltagecontrolled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a reference clock, typically 10 MHz, for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78662s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
A/D Converter Stage

Memory Resources
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
DDC IP Cores
INPUT MULTIPLEXER

.

.

.

.
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
32 Memory Bank 1
32 Memory Bank 2
32 Memory Bank 3
32 Memory Bank 4
8X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 78662
512 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory and capture space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock, or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.

Model 8266
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Four 8-channel banks, one per acquisition module Decimation Range: 16x to 8192x in steps of 8x LO Tuning Freq. Resolution: 32 bits, 0 to s Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, >100 dB stopband attenuation Sample Clock Sources: On-board clock synthesizer
Model 78662 Description 4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - PCIe XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector Gigabit serial FPGA I/O through two 4X top edge connectors Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Description PC Development System See 8266 Datasheet for Options
Options: -062 -064 -104
-105
-155
-165
Model 8266
Pentek, Inc.
www.pentek.com
! ew N
Model 78670
4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - x8 PCIe

General Information
Model 78670 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. This 4-channel, high-speed data converter is suitable for connection to transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As, four digital upconverters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78670 includes optional general purpose and gigabit serial connectors for application-specific I/O. complete the factory-installed functions and enable the 78670 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 78670 factory-installed functions include four D/A waveform playback IP modules, to support waveform generation through the D/A converters. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface
RF Out

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 1.25 GHz 16-bit D/As Four digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO

LVDS
GTX
GTX
GTX
40
8X
4X
4X
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCIe
x8 PCI Express
Pentek, Inc.
www.pentek.com
Model 78670

Two Texas Instruments DAC3484s provide four DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals to a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs to a 16-bit D/A converter. If translation is disabled, each D/A acts as an interpolating 16-bit D/A with output sampling rates up to 1.25 GHz. In both modes, the D/A provides interpolation factors of 2x, 4x, 8x and 16x. Analog output is through four front panel SSMC connectors. 2, 4, 8, or 16 to provide lower frequency D/A clocks. A pair of front panel Sync connectors allows multiple boards to be synchronized. They accept CML inputs that drive the boards sync and trigger/gate signals. The Pentek Models 7892 or 9192 Cobalt Synchronizers can drive multiple 78670 Sync connectors enabling large, multichannel synchronous configurations.
Memory Resources
The 78670 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and waveform playback capabilities. Waveform tables can be loaded into the memories with playback managed by the linked list controllers. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.


The Model 78670 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the board.

16
to D/A Ch 1 & 2
16
to D/A Ch 3 & 4
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 78670

Specifications
D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connector Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.
Model 8266
Model 78670 Description 4-Channel 1.25 GHz D/A with Virtex-6 FPGA - x8 PCIe
Pentek, Inc.
www.pentek.com
! ew N
Model 78671
4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - x8 PCIe
General Information
Model 78671 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. This 4-channel, high-speed data converter is suitable for connection to transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As with a wide range of programmable interpolation factors, four digital upconverters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78671 includes optional generalpurpose and gigabit serial connectors for application-specific I/O. a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 78671 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105 connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board.

RF Out
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 1.25 GHz 16-bit D/As Four digital upconverters Extended interpolation range from 2x to 1,048,576x Programmable output levels 250 MHz max. output bandwidth 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO

LVDS
GTX
GTX
GTX
40
8X
4X
4X
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCIe
x8 PCI Express
Pentek, Inc.
www.pentek.com
Model 78671
Two Texas Instruments DAC3484s provide four DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals to a user-selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs to a 16-bit D/A converter. If translation is disabled, each D/A acts as an interpolating 16-bit D/A with output sampling rates up to 1.25 GHz. In both modes, the D/A provides interpolation factors of 2x, 4x, 8x and 16x. In addition to the DAC3484, the 78671 features an FPGA-based interpolation engine which adds two additonal interpolation stages programmable from 2x to 256x. The combined interpolation results in a range from 2x to 1,048,576x for each D/A channel and is ideal for matching the digital downconversion and data reduction used on the receiving channels of many communications systems. Analog output is through four front panel SSMC connectors. on-board clock generator receives a sample clock either from the front panel SSMC connector or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this latter mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock to phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided by 2, 4, 8, or 16 to provide lower frequency D/A clocks. A pair of front panel Sync connectors allows multiple boards to be synchronized. They accept CML inputs that drive the boards sync and trigger/gate signals. The Pentek Models 7892 or 9192 Cobalt Synchronizers can drive multiple 78671 Sync connectors enabling large, multichannel synchronous configurations.
Memory Resources
The 78671 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and waveform playback capabilities. Waveform tables can be loaded into the memories with playback managed by the linked-list controllers. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

The Model 78671 factoryinstalled functions include a sophisticated D/A Waveform Playback IP module. Four linked-list controllers support waveform generation to the four D/As from tables stored in either on-board memory or offboard host memory. Data for Channel 1 and Channel 2 are interleaved for delivery to a dual channel D/A device. For this reason, they must share a common trigger/ gate, sample rate, interpolation factor, and other parameters. The same rules apply to Channel 3 and Channel 4. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up to 64 individual link entries for each D/A channel can be chained together to create complex waveforms with a minimum of programming. An internal timing bus provides all required D/A clocking. The bus includes a clock, sync and a gate or trigger signal. An
16
to D/A Ch 1 & 2
16
to D/A Ch 3 & 4
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4

PCIe INTERFACE
8X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 78671
The Model 78671 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the board. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connector Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin Sync bus connector includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Array: Standard: Xilinx Virtex-6 XC6VLX240T-2 Optional: Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.
Specifications
D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the D/A clock
Model 8266
Model 78671 Description 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - x8 PCIe
Pentek, Inc.
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Model 78690
L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - x8 PCIe

General Information
Model 78690 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A 2-Channel high-speed data converter, it is suitable for connection directly to the RF port of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. It includes an L-Band RF tuner, two A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78690 includes optional general-purpose and gigabit serial connectors for application-specific I/O protocols. 78690 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 78690 factory-installed functions include two A/D acquisition IP modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable the
Ref In

RF In
MAX2112
Features

Accepts RF signals from 925 MHz to 2175 MHz Programmable LNA boosts LNB (low-noise block) antenna signal levels with up to 60 dB gain Programmable analog downconverter provides I + Q baseband signals with bandwidths ranging from 4 to 40 MHz Two 200 MHz 16-bit A/Ds Supports Xilinx Virtex-6 LXT and SXT FPGAs 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference PCI Express (Gen. 1 & 2) interface, up to x8 Clock/sync bus for multiboard synchronization Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Ref Out GC
12-BIT D/A
Ref A/D Clock/Sync
Control
Option 100
Q 200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
IC
2
Timing Bus
VCXO

LVDS
GTX
GTX
GTX
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
Config FLASH 64 MB 40
8X
4X
4X
x8 PCIe
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCI Express
Pentek, Inc.
www.pentek.com
Model 78690

RF Tuner Stage

An internal timing generator provides all timing, gating, triggering and synchronization functions required by the A/D converters. It also serves as an optional source for the L-Band tuner reference. The front panel SSMC clock input can be used directly as the A/D sample clock. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (voltage-controlled crystal oscillator). In this mode, the front panel SSMC clock input connector accepts a 10 MHz reference signal for synchronizing the VCXO using a PLL. The timing generator uses a front panel LVPECL 26-pin clock/sync connector for one clock, two sync, and two gate/trigger signals. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate/ trigger signals within the board. In the master mode, the LVPECL bus drives output timing signals to synchronize multiple slave boards, supporting synchronous sampling and sync functions across all connected boards.

A/D Converter Stage

The analog baseband I and Q analog tuner outputs are then applied to two Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources.
Memory Resources
from A/D (I)
from A/D (Q)
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 78690

8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. The factory-installed A/D Acquisition Modules use memory banks 1 & 2. Banks 3 & 4 can be optionally installed to support custom user-installed IP within the FPGA . Sample Clock Sources: On-board timing generator/synthesizer A/D Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, for the A/D clock Timing Generator External Clock Input Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 200 MHz (up to 800 MHz when Timing Generator divider is enabled) or PLL system reference Timing Generator Bus: 26-pin front panel connector LVPECL bus includes, clock/ sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Input Quantity: 2 Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8; Gen. 2 x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe card, 4.38 in. x 7.13 in.
Model 8266

Specifications
Front Panel Analog Signal Input Connector: Front panel female SSMC Impedance: 50 ohms L-Band Tuner Type: Maxim MAX2112 Input Frequency Range: 925 MHz to 2175 MHz Monolithic VCO Phase Noise: -97 dBc/Hz at 10 kHz Fractional-N PLL Synthesizer: freqVCO = (N.F) x freqREF where integer N = 19 to 251 and fractional F is a 20-bit binary value PLL Reference (freqREF): Front panel SSMC connector or on-board 27 MHz crystal (Option -100), 12 to 30 MHz LNA Gain: 0 to 65 dB, controlled by a programmable 12-bit D/A converter* Baseband Amplifier Gain: 0 to 15 dB, in 1 dB steps* *Usable Full-Scale Input Range: 50 dBm to +10 dBm Baseband Low Pass Filter: Cutoff frequency programmable from 4 to 40 MHz with 8-bit resolution A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits
Model 78690 Description L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - PCIe XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector Gigabit serial FPGA I/O through two 4X top edge connectors Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Description PC Development System See 8266 Datasheet for Options
Options: -062 -064 -104
-105
-150
-160
-155
-165
Model 8266
Pentek, Inc.
www.pentek.com
! w e
Model 7809
4-Channel SFP Transceiver PCIe Module for Cobalt Boards

General Information
Model 7809 is a PCIe module that provides gigabit serial transceiver network cable links for Penteks Cobalt family of high performance 786xx PCIe boards based on the Xilinx Virtex-6 FPGA. The 7809 and the Cobalt board are installed in adjacent slots in a PCIe motherboard or backplane and joined with a gigabit serial flex circuit cable. The 7809 takes advantage of the small form-factor pluggable (SFP) or Mini-GBIC standard, supporting a variety of hot-pluggable transceiver modules for optical and copper network cables. Up to four modules can be installed. Since the 7809 is protocol transparent, it is compatible with many protocols including Serial FPDP, PCIe, Xilinx Aurora, SerialRapidIO, Gigabit Ethernet, SONET, Fibre Channel, and others. Each of the four gigabit serial links within a 4X port consists of a transmit pair and a receive pair connected to one SFP module through an equalizer circuit to improve transceiver performance. The Virtex-6 FPGA in the Cobalt module is used to implement the required protocol engine for the P16 4X links to the 7809. Some Cobalt boards (such as the 78621 and 78661) are equipped with factory-installed FPGA IP supporting Xilinx Aurora links for cascade beamforming summation across multiple boards. Penteks GateFlow FPGA Design Kit allows users to implement custom protocols for other applications. GateFlow is compatible with the Xilinx ISE Foundation Tool Suite, and includes a complete project file and VHDL source code.
SFP Modules
SFP transceiver modules support a variety of different transmitter and receiver types. These modules simply plug into the SFP sockets so they can be easily installed or replaced by users. Users can choose the appropriate transceiver for each link to support the required distance and data rates. Both single-mode and multi-mode optical fibre devices are available for cable interconnection distances up to 550 m and 10 km, respectively. Pentek offers the 7809 with options for either two or four 850 nm multi-mode fibre optical SFP modules installed. Each 7809 is supplied with the gigabit serial flex circuit cable assembly for connection to a suitably equipped 786xx series PCIe Cobalt module.
Features
The Cobalt Connection

The 786xx series PCIe Cobalt boards feature two optional 4X gigabit serial connectors along the top edge of the circuit board. These two 4X ports are wired directly to P16 of the XMC module. The 7809 circuit board has one 4X gigabit serial connector along its top edge. A short flex circuit cable is installed between the 7809 4X connector and one of the two Cobalt 4X connectors. This provides a full-duplex 4X gigabit serial path between the modules that can operate at serial bit rates to 5 GHz. A second 7809 can be installed adjacent to the Cobalt board to support a second 4X transceiver link.
Compatible with Pentek 786xx PCI Express Cobalt boards Extends range of gigabit serial I/O links Four SFP modules drive cable lengths up to 10 km Support for both optical and copper cables Single-mode and multi-mode fibre optical Data rates to 5 Gbits/sec Payload data rates to 500 MB/sec for each cable
Model Description 7809 Options: -002 Two 850 nm multi-mode fiber optical channel SFPs (500 m distance) Four 850 nm multi-mode fiber optical channel SFPs (500 m distance) 4-Channel SFP Transceiver PCIe Module
4X Gigabit Serial Connector
SFP MODULE 1 SFP MODULE 2 SFP MODULE 3 SFP MODULE 4
Optical or Copper Cable Optical or Copper Cable Optical or Copper Cable Optical or Copper Cable
4X Flex Circuit Cable to Cobalt Module
EQUALIZER Pre-Emphasis De-Emphasis
-004
Contact Pentek for availability of other interfaces
Pentek, Inc.
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Model 78720
General Information
Model 78720 is a member of the Onyx family of high-performance PCIe boards based on the Xilinx Virtex-7 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes three A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 3 as a native interface, the Model 78720 includes optional general-purpose and gigabit-serial card edge connectors for application-specific I/O . nization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable the 78720 to operate as a complete turnkey solution without the need to develop any FPGA IP.

Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 FPGAs from Xilinx. As the central feature of the board architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 78720 factory-installed functions include three A/D acquisition and a D/A waveform playback IP modules for simplifying data capture and data transfer. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchroRF In

The Virtex-7 FPGA site can be populated with one of two FPGAs to match the specific requirements of the processing task. Supported FPGAs are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 connects 24 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105 connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board.
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Three 200 MHz 16-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1, 2 & 3) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-7 FPGA for custom I/O
RF In
RF In
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
16
Timing Bus
VCXO

GTX
GTX
GTX
LVDS
CONFIG FLASH 1 GB
FPGA Config Bus
PCIe Gen. 3 x8
4X
4X
48
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
Gigabit Serial I/O (option 105) Dual 4X Serial Conn
FPGA GPIO (option 104) 68-pin Header
PCIe Gen. 3 x8 x8 PCI Express
Pentek, Inc.
www.pentek.com
Model 78720
A/D Converter Stage

The front end accepts three full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-7 FPGA for signal processing, data capture or for routing to other board resources.

from A/D Ch 1
from A/D Ch 2

to D/A

INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
MEMORY CONTROL
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
48
Pentek, Inc.
www.pentek.com
Model 78720
Memory Resources
The 78720 architecture supports four independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factoryinstalled functions, custom userinstalled IP within the FPGA can take advantage of the memories for many other purposes.
and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x. Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Connects 24 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Gen. 3 available only with the VX330T-2 and VX690T-2 FPGAs Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe card, 4.38 in. x 7.13 in.

Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78620s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

The Model 78720 includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the board.
Model 8266
Model 78720 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-7 FPGA PCIe XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O through 68-pin ribbon cable connector Gigabit serial FPGA I/O through two 4X top edge connectors Description PC Development System See 8266 Datasheet for Options
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation
Options: -073 -076 -104
-105
Model 8266
Pentek, Inc.
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! w e N
Model 78760

General Information
Model 78760 is a member of the Onyx family of high-performance PCIe boards based on the Xilinx Virtex-7 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes four A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 3 as a native interface, the Model 78760 includes optional general-purpose and gigabit-serial connectors for applicationspecific I/O protocols. and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 78760 to operate as a complete turnkey solution without the need to develop any FPGA IP.

Based on the proven design of the Pentek Cobalt Family, Onyx raises the processing performance with the new flagship family of Virtex-7 FPGAs from Xilinx. As the central feature of the board architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 78760 factory-installed functions include four A/D acquisition IP modules for simplifying data capture and data transfer. IP modules for DDR3 SDRAM memories, a controller for all data clocking

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Four 200 MHz 16-bit A/Ds 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1, 2 & 3) interface up to x8 Advanced reconfigurability features Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-7 FPGA for custom I/O
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

GTX
GTX
GTX
LVDS
CONFIG FLASH 1 GB
FPGA CONFIG BUS
PCIe Gen. 3 x8
4X
4X
48
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
FPGA - PCIe CONFIGURATION MANAGER
Pentek, Inc.
www.pentek.com
Model 78760

A/D Converter Stage

The front end accepts four full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-7 FPGA for signal processing, data capture or for routing to other board resources.


from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
Gigabit Serial I/O
4X
4X
FPGA GPIO
48
Pentek, Inc.
www.pentek.com
Model 78760

external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78760s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Connects 24 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Gen. 3 available only with the VX330T-2 and VX690T-2 FPGAs Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.
Model 8266
Memory Resources
The 78760 architecture supports four independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

The Model 78760 includes an industrystandard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the board.
Model 78760 Description 4-Channel 200 MHz A/D with Virtex-7 FPGA - x8 PCIe XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O through 68-pin ribbon cable connector Gigabit serial FPGA I/O through two 4X top edge connectors Description PC Development System See 8266 Datasheet for Options
Specifications
Options: -073 -076 -104
-105
Model 8266
Pentek, Inc.
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Model 78730

General Information
Model 78730 is a member of the Onyx family of high-performance PCIe boards based on the Xilinx Virtex-7 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes 1 GHz A/D and 1 GHz D/A converters and four banks of memory. In addition to supporting PCI Express Gen. 3 as a native interface, the Model 78730 includes optional general-purpose and gigabit serial card connectors for application specific I/O. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factoryinstalled functions and enable the 78730 to operate as a complete turnkey solution, without the need to develop any FPGA IP.


RF In RF Out
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe One 1 GHz 12-bit A/D One 1 GHz 16-bit D/A 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Sync In
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12
1 GHz 16-BIT D/A 16
D/A Sync Bus
VCXO
GTX
GTX

GTX
LVDS
CONFIG FLASH 1 GB
FPGA Config Bus
PCIe Gen. 3 x8
4X
4X
48
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
Pentek, Inc.
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Model 78730

The Onyx architecture includes GateXpress, a sophisticated FPGA-PCIe configuration manager for loading and reloading the FPGA. At power up, GateXpress immediately presents a PCIe target for the host computer to discover, effectively giving the FPGA time to load from FLASH. This is especially important for larger FPGAs where the loading times can exceed the PCIe discovery window, typically 100 msec on most PCs. The boards configuration FLASH can hold four FPGA images. Images can be factory-installed IP or custom IP created by the user, and programmed into the FLASH via JTAG using Xilinx iMPACT or through the boards PCIe interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the FPGA with a new IP image. The first is the option to load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the FPGA image must be loaded directly through the PCIe interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the FPGA IP may need to change many times during the course of a mission, images can be stored on the host computer and loaded through PCIe as needed.
The third option, typically used during development, allows the user to directly load the FPGA through JTAG using Xilinx iMPACT. In all three FPGA loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the PCIe configuration space allowing dynamic FPGA reconfiguration without needing to reset the host computer to rediscover the board. After the reload, the host simply continues to see the board with the expected device ID.
A/D Converter Stage

The front end accepts an analog HF or IF input on a front panel SSMC connector with transformer coupling into a Texas Instruments ADS5400 1 GHz, 12-bit A/D converter. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources.
D/A Converter Stage

to D/A

INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
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Model 78730

Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives a sample clock either from the front panel SSMC connector or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this latter mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock to phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or 16 to provide different lower frequency A/D and D/A clocks. A pair of front panel Sync connectors allows multiple modules to be synchronized. They accept CML inputs that drive the boards sync and gate/trigger signals. The Pentek Model 7892 and Model 9192 Cobalt Synchronizers can drive multiple 78730 Sync connectors enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connector. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.
Model 8266
Memory Resources
Model 78730 Options: -073 -076 -104 XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O through 68-pin ribbon cable connector Gigabit serial FPGA I/O through two 4X top edge connectors Description 1 GHz A/D and D/A, Virtex-7 FPGA - x8 PCIe

-105
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz to 1 GHz Resolution: 12 bits D/A Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max.

Pentek, Inc.
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RAD AR & SDR I/O - 3U VPX - FORMA T 1 RADAR FORMAT

MODEL
5350 5351 5352 5353 5356 5358 5308 Cobalt 53620 Cobalt 53621 Cobalt 53630 Cobalt 53640 Cobalt 53641 Cobalt 53650 Cobalt 53651 Cobalt 53660 Cobalt 53661 Cobalt 53662 Cobalt 53670 Cobalt 53671 Cobalt 53690 Onyx 53720 Onyx 53760 Onyx 53730
DESCRIPTION
Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - 3U VPX 256-Channel DDC with four 200 MHz, 16-bit A/Ds - 3U VPX 32-Channel DDC with four 200 MHz, 16-bit A/Ds - 3U VPX 4/2-Channel DDC, four 200 MHz 16-bit A/Ds, Beamformer - 3U VPX Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U VPX Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U VPX Front Panel x8 PCI Express Adapter - 3U VPX 3-Channel 200 MHz A/D, 2-Channel 800 MHz D/A, Virtex-6 FPGA - 3U VPX 3-Channel 200 MHz A/D with DDC, DUC, 2-Channel 800 MHz D/A, 3U VPX 1 GHz A/D and D/A, Virtex-6 FPGA - 3U VPX 1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D, Virtex-6 FPGA - 3U VPX 1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D, DDC, Virtex-6 FPGA - 3U VPX Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - 3U VPX 2-Chan 500 MHz A/D with DDC, DUC with 2-Chan 800 MHz D/A, Virtex-6 FPGA - 3U VPX 4-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - 3U VPX 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - 3U VPX 4-Channel 200 MHz A/D with 32-Channel DDC and Virtex-6 FPGA - 3U VPX 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - 3U VPX 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - 3U VPX L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - 3U VPX 3-Channel 200 MHz A/D, 2-Channel 800 MHz D/A, Virtex-7 FPGA - 3U VPX 4-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - 3U VPX 1 GHz A/D and D/A, Virtex-7 FPGA - 3U VPX Customer Information
& & & & & &
PMC/XMC CompactPCI PCI x 8 PCI Express AMC 3U VPX - FORMA T 2 FORMAT

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ew
Model 5350
Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - 3U VPX

General Information
Model 5350 is a high-speed data converter suitable for connection as the HF or IF input of a communications system. It features four 200 MHz, 16-bit A/Ds. These are supported by an array of data processing and transport resources ideally matched to requirements of high-performance systems. The 5350 features built-in support for PCI Express (PCIe) Gen. 2 over the 3U VPX backplane. A unique fabric-transparent crossbar switch configuration adds gigabit serial data paths for Xilinx Aurora or Serial RapidIO applications. There are two FPGA types on the 5350: processing and interface. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the onboard resources including the A/D converters, DDR2 SDRAM memory, interface FPGA, programmable LVPECL I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T and FX100T. The SXT parts feature between 288 and 640 DSP48E Slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the Model 5350 can be optionally configured with an LX155T in the processing FPGA position for 155,648 logic cells. The interface FPGA provides board connections including PCI-X or PCI Express, preserving the processing FPGA resources for signal processing. The interface FPGA can be configured as an LXT or an SXT family part, providing not only interface functionality, but processing resources up to an additional 640 DSP48E Slices. Option -104 provides general purpose I/O to VPX-P2 with 16 pairs of LVDS connections to the processing FPGA, and 16 pairs of LVDS connections to the interface FPGA for custom I/O.
RF In
RF XFORMR TIMING BUS GENERATOR Clock / Sync / Gate / PPS To A l Sections
A/D Converter Stage

Model 5350 commercial (left) and conduction-cooled version The front end accepts four full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-5 FPGA for signal processing or for routing to other board resources.
Virtex-5 FPGAs Features
Complete software radio interface solution for 3U VPX systems Supports Gigabit Serial Fabrics including PCI Express, Serial RapidIO and Xilinx Aurora Four 200 MHz 16-bit A/Ds Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Up to 2.56 seconds of data capture at 200 MHz LVPECL clock/sync bus for multiboard synchronization Up to 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46 (VPX Baseline Standard) VITA-48 (VPX REDI) VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
The Model 5350 architecture includes two Virtex-5 FPGAs. All data and control paths are accessible by the FPGAs, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP.
RF In
RF XFORMR
RF In
RF XFORMR
RF In
RF XFORMR
Sample Clk In PPS In
Clock/Sync Bus
TTL In
200 MHz 16 bit A/D
200 MHz 16 bit A/D
200 MHz 16 b t A/D
200 MHz 16 bit A/D
LVPECL Bus
XTL OSC
Control/ Status
PROCESSING FPGA VIRTEX 5 LX50T SX50T SX95T LX155T or FX100T

GTP GTP GTP LVDS
8
4X 4X
Timing Bus
4X
GTP
64
FLASH 32 MB
NTERFACE FPGA VIRTEX 5 LX30T or SX50T

GTP PCI X LVDS
4X
64
PCI X BUS 1 (64 Bits, 100 MHz) 32
32
XMC - P15
4X 4X
PCI-X TO PCIe BRIDGE
PMC - P14
x4 PCIe
24
24 lanes / 6 ports each configurable as x1/x4/x8/x16
64
CROSSBAR SWITCH
4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P1 VPX-P2
VPX BACKPLANE
Pentek, Inc.
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Model 5350

The Model 5350 architecture includes a flexible timing and synchronization circuit for each bank of four A/D converters, allowing the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. Each timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, each accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to three slave 5350s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX50T standard; XC5VLX50T, XC5VSX95T, XC5VLX155T or XC5VFX100T, optional Interface FPGA: Xilinx Virtex-5 XC5VLX30T std.; XC5VSX50T optional Custom I/O Option -104: Provides GPIO to VPX-P2 with 16 LVDS pairs to processing FPGA (SX95T, LX155T or FX100T only) and 16 pairs to interface FPGA Memory DDR2 SDRAM: Up to 1 GB in two banks PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus Gigabit Serial I/O: Processing FPGA: Two 4X ports to Fabric-Transparent Switch; one can be alternately routed to interface FPGA VPX-P1: Four 4X ports to Fabric-Transparent Crossbar Switch PCI Express: Six ports to Fabric-Transparent Switch, each configurable as x1, x4, x8 or x16 lanes, 24 lanes total Environmental Operating Temperature: Forced-Air Cooled: 0 to 50 C std; -20 to 65 C (Level L2) Conduction-Cooled: -40 to 70 C (Level L3) Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGA. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering. Each memory bank can be easily accessed through the PCI interface using the on-board DMA controllers. Custom user-installed functions within the FPGA can take advantage of all three banks to support various applications.
Fabric-Transparent Crossbar Switch

The 5350 features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Data paths can be selected as single (x1) lanes, or groups of four lanes (x4).
Model 5350 Description Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs 3U VPX
Options: -104 FPGA I/O to VPX-P2 -5xx Gigabit Serial I/O to VPXP1- four full duplex 4X paths -703 Level L3 ConductionCooled Version
PCI Express Switch

Model 5350 includes a PCIe Gen. 2 switch. The switch provides a total of 24 PCIe lanes to the Fabric-Transparent Crossbar Switch on 6 ports. Dynamic lane width negotiation within the PCIe switch allows for x1, x4, x8 or x16 widths. These can be selected in any combination.
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Model 5351
256-Channel DDC with Four 200 MHz, 16-bit A/Ds - 3U VPX

General Information
Model 5351 is a high-speed software radio board designed for processing baseband RF or IF signals from a communications receiver. It features four 200 MHz 16-bit A/Ds. The A/D converters are supported by a high-performance 256-channel installed DDC (digital downconverter) IP Core and interfaces ideally matched to the requirements of real-time software radio and radar systems. The 5351 features built-in support for PCI Express (PCIe) Gen. 2 over the 3U VPX backplane. Each of the DDCs has an independent 32-bit tuning frequency setting that ranges from DC to s where s is the A/D sample rate.

A/D Converter Stage

The front end accepts four full-scale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer-coupling into Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing.
Features

256 DDC channels Four 200 MHz 16-bit A/Ds Independent tuning for each channel and decimation for each bank DDC decimation from 128 to 1024 in steps of 64 User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection Each bank independently selects one of four A/Ds LVPECL clock/sync bus for multiboard synchronization 3U VPX form factor with ruggedized and conductioncooled versions available

The Model 5351 SX95T FPGA employs an advanced FPGA-based digital downconverter engine consisting of four identical 64-channel DDC banks. Four independently controllable input multiplexers select one of the attached four A/Ds as the input source for each DDC bank. In this way, many different configurations can be achieved including one A/D driving all 256 DDC channels and each of the four A/Ds driving its own DDC bank.

Four output MUXs in the SX95T FPGA can be independently switched to deliver either A/D or DDC data into each output FIFO. This allows users to view either
CH 1 RF In
RF XFORMR
200 MHz 16-bit A/D
CH 2 RF In
RF XFORMR
200 MHz 16-bit A/D
CH 1 CH 2 CH 3 CH 4
CH 1 I+Q
M U X
FIFO 1
CH 3 RF In
RF XFORMR
200 MHz 16-bit A/D
PCI-X 64 bits PCI-X BUS 100 MHz
RF XFORMR 200 MHz 16-bit A/D A
CH 2
CH 3 CH 4
I+Q
M U X
FIFO 2
PCI-X INTERFACE
x4 PCIe
XILINX XC5VLX30T
Sample Clock In PPS In TTL In LVPECL Bus Timing Bus

CH 3
24
CH 2 CH 3 CH 4
I+Q
M U X
FIFO 3
CROSSBAR SWITCH
CH 4 I+Q
M U X
FIFO 4
4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P1
VPX BACKPLANE
XILINX XC5VSX95T
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Model 5351

wideband A/D data or narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI bus.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX95T dedicated to digital downcoverters and output Interface FPGA: Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus Gigabit Serial I/O VPX-P1: Four 4X ports to Fabric-Transparent Crossbar Switch PCI Express: Six ports to Fabric-Transparent Switch, each configurable as x1, x4, x8 or x16 lanes, 24 lanes total Environmental Operating Temperature: Forced-Air Cooled: 0 to 50 C std; -20 to 65 C (Level L2) Conduction-Cooled: -40 to 70C (Level L3) Storage Temperature: Forced-Air Cooled: -20 to 90 C std; -40 to 100 C (Level L1, L2) Conduction-Cooled: -50 to 100C (L3) Relative Humidity: 0 to 95%, non-cond.; 0 to 100% with conformal coating Size: 3.937 in. x 6.717 in. (100 mm x 170.6mm)

The Model 5351 architecture includes a flexible timing and synchronization circuit for the bank of four A/D converters, allowing the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connectors allows multiple boards to be synchronized. In the slave mode, each accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple bords. Up to three slave 5351s can be driven from each LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.

The 5351 features a unique high-speed switching configuration. A fabric-transparent crossbar switch connects the PCI Express switch with the VPX-P1 connector using gigabit serial data paths with no latency. This allows the user to select the desired output port on VPX-P1. Programmable signal input equalization and output pre-emphasis settings on the Crossbar Switch enable optimization.
PCI Express Switch Ordering Information

Model 5351 Description 256-Channel DDC with four 200 MHz, 16-bit A/D - 3U VPX
Options: -703 Level L3 ConductionCooled Version -731 Two-slot heat sink
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Model 5352

General Information
Model 5352 is a high-speed software radio module designed for processing baseband RF or IF signals from a communications receiver. It features four 200 MHz 16-bit A/Ds. The A/Ds are supported by a high-performance 32-channel installed DDC (digital downconverter) IP Core, and interfaces ideally matched to the requirements of real-time software radio and radar systems. The 5352 features built-in support for PCI Express (PCIe) Gen. 2 over the 3U VPX backplane.

All of the eight channels within a bank share a common decimation setting that can range from 16 to 8192, programmable in steps of 8. For example, with a sampling rate of 200 MHz, the available output bandwidths range from 19.53 kHz to 10.0 MHz. Each 8-channel bank can have a unique decimation setting supporting up to four different output bandwidths for the board. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. Rejection of adjacent-band components within the 80% bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N. Any number of channels can be enabled with each bank, selectable from 0 to 8. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within the bank.
A/D Converter Stage

Features

32 channels of DDC in banks of 8 channels Independent 32-bit DDC tuning for all channels DDC decimation from 16 to 8192 in steps of 8 Bandwidths from 20 kHz to 10 MHz User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection Power meters and threshold detectors LVPECL clock/sync bus for multiboard synchronization 3U VPX form factor with ruggedized and conductioncooled versions available

The Model 5352 SX95T FPGA employs an advanced FPGA-based digital down-converter engine consisting of four identical 8-channel DDC banks. Four independently controllable input multiplexers select one of the four attached A/Ds as the input source for each DDC bank. In this way, many different configurations can be achieved including one A/D driving all 32 DDC channels and each of the four A/Ds driving its own DDC bank. Each of the DDCs has an independent 32-bit tuning frequency setting ranging from DC to s (s is the A/D sample rate).

The 5352 features 32 power meters that continuously measure the individual average power output of each DDC channel. The time constant of the averaging interval is programmable up to 16 kilosamples. In addition, threshold detectors automatically send an interrupt to the processor if the average power level of any DDC falls below or exceeds a programmable threshold.
CH 1 RF In
RF XFORMR
200 MHz 16-bit A/D

8X4 CHANNEL SUMMATION M U X DDC BANK 1: CH 1-8 DEC. 16-8192
CH 1 I+Q
M U X F I F 0 1 F I F 0 2 F I F 0 3 F I F 0 4
CH 2 RF In
RF XFORMR
200 MHz 16-bit A/D
CH 3 RF In
RF XFORMR
200 MHz 16-bit A/D
CH 2
M U X
CH 3 CH 4
M U X
DDC BANK 2: CH 9-16 DEC. 16-8192
PCI-X INTERFACE
x4 PCIe
I+Q
XILINX XC5VLX30T
CH 1 TIMING BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 CH 3 CH 4

M U X DDC BANK 4: CH 25-32 DEC. 16-8192
CH 3
M U X
24
CH 2 CH 3 CH 4
M U X
TTL In
DDC BANK 3: CH 17-24 DEC. 16-8192
I+Q
CROSSBAR SWITCH
CH 4
M U X
LVPECL Bus
I+Q
XTAL OSC
VPX BACKPLANE
Timing Bus
XILINX XC5VSX95T
Pentek, Inc.
www.pentek.com
Model 5352

Four output MUXs in the SX95T FPGA can be independently switched to deliver either A/D data or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D data or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input rate and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI bus.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX95T dedicated to digital downcoverters and output Interface FPGA: Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus Gigabit Serial I/O VPX-P1: Four 4X ports to Fabric-Transparent Crossbar Switch PCI Express: Six ports to Fabric-Transparent Switch, each configurable as x1, x4, x8 or x16 lanes, 24 lanes total Environmental Operating Temperature: Forced-Air Cooled: 0 to 50 C std; -20 to 65 C (Level L2) Conduction-Cooled: -40 to 70 C (Level L3) Storage Temperature: Forced-Air Cooled: -20 to 90 C std; -40 to 100 C (Level L1, L2) Conduction-Cooled: -50 to 100 C (L3) Relative Humidity: 0 to 95%, non-cond.; 0 to 100% with conformal coating Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

The Model 5352 architecture includes a flexible timing and synchronization circuit for the group of four A/D converters that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, each accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to three slave 5352s can be driven from each LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. For larger systems, many more boards can be synchronized with an external clock and sync generator.

The 5352 features a unique high-speed switching configuration. A fabric-transparent crossbar switch connects the PCI Express switch with the VPX-P1 connector using gigabit serial data paths with no latency. This allows the user to select the desired output port on VPX-P1. Programmable signal input equalization and output pre-emphasis settings on the Crossbar Switch enable optimization.
Model 5352 Description 32-Channel DDC with four 200 MHz, 16-bit A/D s - 3U VPX
PCI Express Switch

Options: -703 Level L3 ConductionCooled Version -731 Two-slot heat sink
Pentek, Inc.
www.pentek.com
! ew N
Model 5353
4/2-Ch. DDC, four 200 MHz 16-bit A/Ds, Beamformer - 3U VPX

General Information
Model 5353 is a high-speed software radio board designed for processing baseband RF or IF signals from a communications receiver. It features four 200 MHz 16-bit A/Ds supported by a high-performance 4-channel installed DDC (digital downconverter) and a complete set of beamforming functions. With buit-in multiboard synchronization, it is ideally matched to the requirements of real-time software radio and radar systems. The 5353 features built-in support for PCI Express (PCIe) Gen. 2 over the 3U VPX backplane. A unique fabric-transparent crossbar switch configuration adds gigabit serial data paths for Xilinx Aurora or Serial RapidIO applications. Each of the DDC channels has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency.

Each of the four DDC channels can have its own unique decimation setting supporting as many as four different output bandwidths for the board. The DDC core can be configured in four-channel mode with each channel offering decimations between 2 and 256, or in two-channel mode with each channel having a decimation range of 2 to 65536, for applications that require a wider range of decimations. The decimating filter for each DDC channel accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N.
Features

Built-in Beamformer supports multiboard systems Programmable Power Meter and Threshold Detect per channel Four 200 MHz, 16-bit A/Ds 2 or 4 Channels of DDC Independent 32-bit DDC tuning for all channels DDC decimation range from 2 to 256 or from 2 to 65536 Independent decimation factors for each channel Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multiboard synchronization 3U VPX form factor with ruggedized and conductioncooled versions available
A/D Converter Stage

Power Meters

CH 1 RF In
RF XFORMR
200 MHz 16-bit A/D
M U X SUMMER
SUM IN SUM OUT
AURORA GIGABIT SERIAL INTERFACE F I F 0 1 F I F 0 2 F I F 0 3 F I F 0 4
4X 4X XMC - P15
CH 2 RF In
RF XFORMR
200 MHz 16-bit A/D
I+Q CH 1
M U X
CH 3 RF In
RF XFORMR
200 MHz 16-bit A/D
I+Q
CH 4 RF In
RF XFORMR
200 MHz 16-bit A/D
CH 1 CH 2 CH 3 CH 4
M U X
CH 2
M U X
I+Q
4X Gbit Serial PCI-X TO PCIe BRIDGE
4X Gbit Serial
PCI-X INTERFACE
x4 PCIe

M U X DIGITAL DOWNCONVERTER CH 4 (DEC: 2 - 256)*
CH 3
M U X
CH 2 CH 3 CH 4
M U X
DIGITAL DOWNCONVERTER CH 3 (DEC: 2 - 256)*
I+Q
XILINX XC5VLX30T
24

CROSSBAR SWITCH
CH 4
M U X
I+Q
XILINX XC5VSX95T
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 5353

Beamformer
In addition to the A/Ds and DDCs, the 5353 includes essential resources of a complete beamforming subsystem. First, each DDC channel provides user-programmable I & Q phase and gain adjustments to apply beamforming weights. Then, a summation block adds the four DDC output channels. An additional programmable gain stage compensates for summation bit growth. A power meter and threshold detect block is provided for the sum output. The sum output is then delivered to the Channel 1 FIFO for delivery through the PCIe interface out to the VPX backplane. For larger systems, multiple 5353s can be chained together using a built-in Xilinx Aurora engine. It accepts an x4 gigabit sum input stream from a previous board and propagates a x4 sum output stream to the next board through the VPX-P1 connector. for the group of four A/D converters that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/ Sync connector allows multiple boards to be synchronized. In the slave mode, each accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to three slave 5353s can be driven from each LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. For larger systems, many more boards can be synchronized with an external clock and sync generator.
VPX Interface
For large systems, multiple 5353s can be chained together via a built-in Xilinx Aurora interface through the VPX-P1 connector. This link creates a board-toboard summation expansion chain for creating larger multichannel beamformer systems. Xilinxs Aurora protocol is used to provide an efficient x4, 1.25 GB/sec point-to-point data path between boards.

Four output MUXs can be independently switched to deliver either A/D data or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D data or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input and output rates to support different DDC decimation settings between the banks and efficient block transfers to the PCI-X bus.


The Model 5353 architecture includes a flexible timing and synchronization circuit
PHASE SHIFT
DECIMATION: 2-65536 (DECIMATION: 2-256)*
GAIN
I Q
I Q
I
Q
I
Q
DIGITAL DOWNCONVERTER A
POWER METER & THRESHOLD DETECT A
AURORA PORT
SUMMATION EXPANSION CHAIN IN 1.25 GByte/sec x4 Aurora Link
From Previous Board
P15
GAIN
DECIMATION: 2-65536 (DECIMATION: 2-256)*
I Q
I Q
I Q
I Q
SUMMATION CHAIN BIT GROWTH COMPENSATION
DIGITAL DOWNCONVERTER B
POWER METER & THRESHOLD DETECT B
I Q
I Q
I Q
GAIN
I Q
I Q
I Q
I Q
Summation Chain Gain POWER METER & THRESHOLD DETECT C
SUMMATION POWER METER & THRESHOLD DETECT
DIGITAL DOWNCONVERTER C
AURORA PORT
SUMMATION EXPANSION CHAIN OUT 1.25 GByte/sec x4 Aurora Link
To Next Board
GAIN
P15 I
Q
I Q
I Q
I
Q
DIGITAL DOWNCONVERTER D
POWER METER & THRESHOLD DETECT D
Pentek, Inc.
www.pentek.com
Model 5353

PCI Express Switch
Model 5353 includes a PCIe Gen. 2 switch. The switch provides a total of 24 PCIe lanes to the Fabric-Transparent Crossbar Switch on 6 ports. Dynamic lane width negotiation within the PCIe switch allows for x1, x4, x8 or x16 widths. These can be selected in any combination. FIR Filter: Default passband 0.8*s/N with 0.2 dB passband ripple and 100 dB adjacent channel rejection FIR Filter Coefficients: 18 bits, userprogrammable (default values provided) Qty FIR Filter Taps: 28*N/8 Output Format: 24 bits I + 24 bits Q Output Spectrum Modes: Normal or frequency-reversed Output Spectrum Offset: No offset or offset by one-half the output bandwidth Beamformer Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Output Multiplexer and FIFO Qty Output FIFOs: Four FIFO Source Selection: Independent multiplexer selects DDC output or A/D PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus Gigabit Serial I/O: Processing FPGA: Two 4X ports to Aurora Gigabit Serial Interface VPX-P1: Four 4X ports to Fabric-Transparent Crossbar Switch PCI Express: Six ports to Fabric-Transparent Switch, each configurable as x1, x4, x8 or x16 lanes, 24 lanes total Environmental Operating Temperature: Forced-Air Cooled: 0 to 50 C std; -20 to 65 C (Level L2) Conduction-Cooled: -40 to 70C (Level L3) Storage Temperature: Forced-Air Cooled: -20 to 90 C std; -40 to 100 C (Level L1, L2) Conduction-Cooled: -50 to 100C (L3) Relative Humidity: 0 to 95%, non-cond.; 0 to 100% with conformal coating Size: 3.937 in. x 6.717 in. (100 mm x 170.6mm)
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillator, external reference or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC-coupled 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS, input/output LVPECL bus; one gate/trigger and one sync/PPS input TTL signal Digital Downconverter Type: IP core for Xilinx Virtex-5 Qty of DDC Channels: 2 or 4 Center Frequency Tuning: 4 tuning words, one for each DDC channel Center Frequency Tuning Range: DC to s with 32 bit resolution NCO SFDR: 120 dBFS Channel Phase Offset Adjustment: 32-bit resolution Channel Gain Adjustment: 32-bit resolution Input Selection for DDC Banks: Any channel can select any of the four A/Ds Decimation Range (N): 2-Channel Mode: 2 to 65536 4-Channel Mode: 2 to 256
Model 5353 Description 4/2-Channel DDC with four 200 MHz, 16-bit A/Ds and Beamformer - 3U VPX
Options: -5xx Gigabit Serial I/O to VPXP1- four full-duplex 4X paths -703 Level L3 ConductionCooled Version -730 Two-Slot Heat Sink
Pentek, Inc.
www.pentek.com
! w e N
Model 5356
Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U VPX
General Information
Model 5356 is a dual-channel, high-speed data converter suitable for connection to HF or IF ports of a communication system. It includes two 400 MHz A/Ds, 800 MHz D/As and Virtex-5 FPGAs. The 5356 features built-in support for PCI Express (PCIe) Gen. 2 over the 3U VPX backplane. A unique fabric-transparent crossbar switch configuration adds gigabit serial data paths for Xilinx Aurora or Serial RapidIO applications. Analog output is through a pair of front panel SMC connectors at +4 dBm into 50 ohms. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC provides interpolation factors of 2x, 4x and 8x.
Virtex-5 FPGAs
The architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between
RF In
RF XFORMR
A/D Converter Stage

Features

A TI DAC5688 digital upconverter (DUC) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as an upconverter, it interpolates and translates real or complex baseband input signals to any IF center frequency between DC and 300 MHz. It delivers real or quadrature (I+Q) outputs at up to 500 MHz to the 16-bit D/A converter.
Complete software radio interface solution for 3U VPX systems Supports Gigabit Serial Fabrics including PCI Express, Serial RapidIO and Xilinx Aurora Two 400 MHz 14-bit A/Ds One DUC (Digital Upconverter) Two 800 MHz, 16-bit D/As Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46 (VPX Baseline Standard) VITA-48 (VPX REDI) VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF XFORMR
RF Out
RF XFORMR
RF Out
RF XFORMR
400 MHz 14-BIT A/D 14
400 MHz 14-BIT A/D 14
800 MHz 16-BIT D/A
800 MHz 16-BIT D/A
Timing Bus
Control/ Status
PROCESSING FPGA VIRTEX-5 LX50T, LX155T, SX50T, SX95T or FX100T

GTP GTP GTP LVDS
8
4X 4X
4X
GTP
64
FLASH 32 MB
INTERFACE FPGA VIRTEX-5 LX30T or SX50T

GTP PCI-X LVDS
4X
64
PCI-X BUS 1 (64 Bits, 100 MHz) 32
32
XMC - P15
4X 4X
PMC - P14
x4 PCIe
24
64
CROSSBAR SWITCH
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 5356
reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. The interface FPGA can be configured as an LXT family or an SXT family part, providing not only interface functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 provides general purpose I/O to VPX-P2 with 16 pairs of LVDS connections to the processing FPGA, and 16 more to the interface FPGA for custom I/O. Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 400 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Option -104: Provides GPIO to VPX-P2 with 16 LVDS pairs to processing FPGA (SX95T, LX155T or FX100T only) and 16 pairs to interface FPGA Memory DDR2 SDRAM: Up to 1.0 GB in two banks to processing FPGA PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus Gigabit Serial I/O: Processing FPGA: Two 4X ports to Fabric-Transparent Switch; one can be alternately routed to interface FPGA VPX-P1: Four 4X ports to Fabric-Transparent Crossbar Switch PCI Express: Six ports to Fabric-Transparent Switch, each configurable as x1, x4, x8 or x16 lanes, 24 lanes total Environmental Operating Temperature: Forced-Air Cooled: 0 to 50 C std; -20 to 65 C (Level L2) Conduction-Cooled: -40 to 70 C (Level L3) Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Memory Resources


PCI Express Switch

Model 5356 Description Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U VPX
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation
Options: -104 FPGA I/O to VPX-P2 -5xx Gigabit Serial I/O to VPXP1- four full-duplex 4X paths -703 Level L3 ConductionCooled Version
Pentek, Inc.
www.pentek.com
e N
! w
Model 5358
General Information
Model 5358 is a dual-channel, high-speed data converter suitable for connection to HF or IF ports of a communication system. It includes two 500 MHz A/Ds, 800 MHz D/As and Virtex-5 FPGAs. The 5358 features built-in support for PCI Express (PCIe) Gen. 2 over the 3U VPX backplane. A unique fabric-transparent crossbar switch configuration adds gigabit serial data paths for Xilinx Aurora or Serial RapidIO applications. Analog output is through a pair of front panel SMC connectors at +4 dBm into 50 ohms. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC provides interpolation factors of 2x, 4x and 8x.
Virtex-5 FPGAs
The architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between
RF In
RF XFORMR
A/D Converter Stage

Features

A TI DAC5688 digital upconverter (DUC) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as an upconverter, it interpolates and translates real or complex baseband input signals to any IF center frequency between DC and 300 MHz. It delivers real or quadrature (I+Q) outputs at up to 500 MHz to the 16-bit D/A converter.
Complete software radio interface solution for 3U VPX systems Supports Gigabit Serial Fabrics including PCI Express, Serial RapidIO and Xilinx Aurora Two 500 MHz 12-bit A/Ds One DUC (Digital Upconverter) Two 800 MHz, 16-bit D/As Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46 (VPX Baseline Standard) VITA-48 (VPX REDI) VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF XFORMR
RF Out
RF XFORMR
RF Out
RF XFORMR
Sample C k / Reference Clk In PPS In
500 MHz 12 BIT A/D 14
500 MHz 12 BIT A/D 14
800 MHz 16 BIT D/A
800 MHz 16 BIT D/A
Timing Bus
Control/ Status
PROCESS NG FPGA VIRTEX 5 LX50T LX155T SX50T SX95T or FX100T

GTP GTP GTP LVDS
8
4X 4X
4X
GTP
64
FLASH 32 MB

GTP PCI X LVDS
4X
64
PCI X BUS 1 (64 Bits 100 MHz) 32
32
XMC - P15
4X 4X
PCI X TO PCIe BRIDGE
PMC - P14
x4 PCIe
24
64
CROSSBAR SWITCH
4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX P1 VPX P2
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 5358
reception and transmission. For applications
requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. The interface FPGA can be configured as an LXT family or an SXT family part, providing not only interface functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 provides general purpose I/O to VPX-P2 with 16 pairs of LVDS connections to the processing FPGA, and 16 more to the interface FPGA for custom I/O. Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 500 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Option -104: Provides GPIO to VPX-P2 with 16 LVDS pairs to processing FPGA (SX95T, LX155T or FX100T only) and 16 pairs to interface FPGA Memory DDR2 SDRAM: Up to 1.0 GB in two banks to processing FPGA PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus Gigabit Serial I/O: Processing FPGA: Two 4X ports to Fabric-Transparent Switch; one can be alternately routed to interface FPGA VPX-P1: Four 4X ports to Fabric-Transparent Crossbar Switch PCI Express: Six ports to Fabric-Transparent Switch, each configurable as x1, x4, x8 or x16 lanes, 24 lanes total Environmental Operating Temperature: Forced-Air Cooled: 0 to 50 C std; -20 to 65 C (Level L2) Conduction-Cooled: -40 to 70 C (Level L3) Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Memory Resources


PCI Express Switch

Model 5358 Description Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U VPX
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits D/A Converters Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation
Options: -104 FPGA I/O to VPX-P2 -140 1 GB DDR2 SDRAM -5xx Gigabit Serial I/O to VPXP1- four full-duplex 4X paths -703 Level L3 ConductionCooled Version
Pentek, Inc.
www.pentek.com
ew
Model 5308
Front Panel x8 PCI Express Adapter - 3U VPX

General Information
Model 5308 is a front panel PCI Express adapter for 3U VPX systems. It provides a convenient interface from a 3U VPX system to an external host computer, to simplify development. The 5308 features built-in support for PCI Express (PCIe) Gen. 2 over the 3U VPX backplane. A unique fabric-transparent crossbar switch configuration allows selection of the desired VPX-P1 port.

Two ports from the front panel PCI Express connector are attached to a FabricTransparent Crossbar switch. This switch bridges numerous interfaces on the board using gigabit serial data paths with no latency. This allows the user to select the desired port on VPX-P1. Data paths can be selected as single (x1) lanes, or groups of four lanes (x4). Programmable signal input equalization and output pre-emphasis settings enable optimization. A USB interface is provided for switch programming, and 4 MB onboard FLASH memory allows storage of up to 16 user configurations. Several useful configurations are pre-installed at the factory.
Front Panel Connection

The 5308 provides a front panel interface to the 3U VPX system for connection to a host computer. It supports x4 or x8 PCIe protocol in compliance with PCI-SIG PCI Express External Cabling 1.0 Specification. It can also be used to connect to an additional VPX system when ordered with Cascade Mode (option -002). Model 5308 contains built-in PCI Express ReDriverTM circuitry. This circuitry provides signal conditioning that allows the user to correct for signal loss or data errors due to cable length.
PCI Express Switch

The 5308 includes a multiport PCIe Gen. 2 switch. The switch provides a total of 24 PCIe lanes to the fabric-transparent crossbar switch. Dynamic lane width negotiation within the PCIe switch allows for x1, x4, x8 or x16 widths. These can be selected in any combination. Data to or from the panel cable can be selected as x4 or x8 width. Both PCIe Gen. 1 and Gen. 2 are supported.
Features

Front Panel x8 PCI Express connection to host PC 3U VPX form factor provides a compact, rugged platform Cascade mode provides connection to an addtional VPX system Compatible with several VITA standards including: VITA-46 (VPX Baseline Standard) VITA-48 (VPX REDI) VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
PC Connection
The most common use for Model 5308 is for connection to an external host computer. In order to make this connection, the PC requires a PCIe host adapter which is also compliant to PCI-SIG PCI Express External Cabling 1.0 Specification. Adapters supporting either PCIe x8 Gen. 1 or Gen. 2 are available from Pentek under Model 4235.
3U VPX Interface
The 5308 provides full-duplex links to the VPX P1 connector, each capable of peak rates up to 1 gigabyte per sec. Four sets of x4 links support PCI Express.
Model 5308 Description Front Panel x8 PCI Express Adadpter - 3U VPX
Front Panel I/O
-703
Level L3 ConductionCooled Version Accessories: Model Description 4235 PCI Express x8 Host Card for PC 2180 PCI Express x8 Cable
x4 PCIe* x4 PCIe* 48-Lane PCI Express Switch x4 PCIe* x4 PCIe*
48-Lane FabricTransparent Crossbar Switch
4X Gbit Serial 4X Gbit Serial
*Total of 24 lanes can be configured for x1, x4, x8 or x16 widths
USB Interface
CPLD
FLASH 4 MB
Pentek, Inc.
www.pentek.com
VPX V TA 46 BACKPLANE
Options: -001 Host Adapter Mode (for connection to external host computer) -002 Cascade Mode (for connection to additional VPX system)
XMC-P15
PCI Express x8 Cable Connector
x4 PCIe ReDriver x4 PCIe ReDriver
x4 PCIe x4 PCIe 4X Gbit Serial x4 PCIe* x4 PCIe* 4X Gbit Serial

VITA 46 P1
! ew N
Model 53620
3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - 3U VPX
General Information
Model 53620 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture and playback features offer an ideal turnkey solution. The 53620 includes three A/Ds, one upconverter, two D/As and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. and a PCIe interface complete the factoryinstalled functions and enable the 53620 to operate as a complete turnkey solution, without the need to develop any FPGA IP.


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O. Option -105 provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols.
Model 53620 COTS (left) and rugged version
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Supports gigabit serial fabrics including PCI Express, Serial RapidIO and Xilinx Aurora Three 200 MHz 16-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF In
RF In
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
16
Timing Bus
VCXO

LVDS
Option -105 Gigabit Serial I/O

GTX
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
40
Option -104 FPGA I/O
8X x8 PCIe
4X
4X
CROSSBAR SWITCH
Memory Banks 1 & 2
Memory Banks 3 & 4
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 53620
A/D Converter Stage
The front end accepts three full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an onboard programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 53620s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Memory Resources
to D/A D/A loopback

from A/D Ch 1
from A/D Ch 2
from A/D Ch 3

INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
MEMORY CONTROL
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 53620
FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O. Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols. Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

The Model 53620 includes an industry-standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the board.

The 53620 features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output preemphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (4X).
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock
Model 53620 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-6 FPGA 3U VPX XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 Gigabit serial FPGA I/O to VPX P1 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
VPX Families
Pentek offers two families of 3U VPX products: the 53xxx and the 52xxx. For more information on a 52xxx product, please refer to the product datasheet. The table below provides a comparison of their main features.
VPX Family Comparison
52xxx Form Factor # of XMCs Crossbar Switch PCIe path PCIe width Option -104 path Option -105 path Lowest Power Lowest Price
No VPX P1 x4 3U VPX One XMC Yes VPX P1 or P2 x8
Options: -062 -064 -104 -105 -150
53xxx
-160
-155
20 pairs on VPX P2 Two x4 or one x8 on VPX P1 Yes Yes Two x4 or one x8 on VPX P1 or P2 No No
-165
Pentek, Inc.
www.pentek.com
! ew N
Model 53621
3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - 3U VPX
General Information
Model 53621 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with a programmable DDC, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. The 53621 includes three A/Ds, one upconverter, two D/As and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. sition modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 53621 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Model 53621 COTS (left) and rugged version The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 53621 factory-installed functions include three A/D acquisition and a D/A waveform playback IP modules. Each of the three acquisition IP modules contains a powerful, programmable DDC IP core. The waveform playback IP module contains an intrepolation IP core, ideal for matching playback rates to the data and decimation rates of the acquiRF In

The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O.
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three 200 MHz 16-bit A/Ds Three multiband DDCs (digital downconverters) One DUC (digital upconverter) Two 800 MHz 16-bit D/As Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference Optional LVPECL clock/sync bus for multiboard synchronization 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
16
Timing Bus
VCXO
VIRTEX-6 FPGA LX240T, or SX315T

LVDS

GTX
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
40
8X x8 PCIe
Sum to next board
4X 4X
Sum from prior board
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB CROSSBAR SWITCH
Memory Banks 1 & 2
Memory Banks 3 & 4
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 53621
setting that ranges from DC to s, where s is the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as three different output bandwidths for the board. Decimations can be program-med from 2 to 65,536 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the three DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 53621s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the VPX P1 connector. This allows summation across channels on multiple boards.

Beamformer IP Core

The Model 53621 factory-installed functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users to easily play back to the dual D/As waveforms stored in either on-board memory or off-board host memory . Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 individual link entries can be chained together to create complex waveforms with a minimum of programming.
from A/D Ch 1
from A/D Ch 2
to D/A
INPUT MULTIPLEXER
DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all three DDCs or each of the three A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency
MEMORY CONTROL
MUX
DDC CORE
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
sum out sum in
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
8X PCIe
Pentek, Inc.
www.pentek.com
Model 53621
A/D Converter Stage
The front end accepts three analog HF or IF inputs on front panel SSMC connectors with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other board resources. Multiple 53621s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Memory Resources

A TI DAC5688 DUC (digital upconverter) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x. In addition to the DAC5688, an FPGA-based interpolator core provides additional interpolation from 2x to 65,536x. The two interpolators can be combined to crate a total range from 2x to 524,288x.


Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards.

The 53621 features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (4X).
Specifications
Pentek, Inc.
www.pentek.com
Model 53621
Digital Downconverters
Quantity: Three channels Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformer Summation: Three channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
VPX Families
Model 53621 Description 3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - 3U XMC XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
53xxx
Options: -062 -064 -104 -150
-160
-155
-165
Pentek, Inc.
www.pentek.com
! ew N
Model 53630
1 GHz A/D and D/A, Virtex-6 FPGA - 3U VPX

General Information
Model 53630 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes 1 GHz A/D and D/A converters and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. factory-installed functions and enable the 53630 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 53630 factory-installed functions include an A/D acquisition and a D/A waveform playback IP module. In addition, IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Supports gigabit serial fabrics including PCI Express, Serial RapidIO and Xilinx Aurora One 1 GHz 12-bit A/D One 1 GHz 16-bit D/A Up to 2 GB of DDR3 SDRAM or 16 MB of QDRII+ SRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF Out
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Sync In
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12
1 GHz 16-BIT D/A 16
D/A Sync Bus
VCXO

LVDS

GTX
GTX
GTX
16
16
16
16
40
8X x8 PCIe
4X
4X
CROSSBAR SWITCH
QDRII+ option 150
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 53630

A/D Converter Stage
Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or 16 to provide different lower frequency A/D and D/A clocks. A pair of front panel Sync connectors allows multiple boards to be synchronized. They accept CML inputs that drive the boards sync and gate/trigger signals. The Pentek Model 5392 and Model 9192 Cobalt Synchronizers can drive multiple 53630 Sync connectors enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connector.

D/A Converter Stage

Memory Resources
to D/A



INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 53630

The Model 53630 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the board. Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Option 150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1: x4 or x8; Gen 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz to 1 GHz Resolution: 12 bits D/A Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference
Model 53630 Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 -105 Gigabit serial FPGA I/O to VPX P1 -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required Description 1 GHz A/D and D/A, Virtex-6 FPGA - 3U VPX
VPX Families
53xxx
Pentek, Inc.
www.pentek.com
! ew N
Model 53640
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, V-6 FPGA - 3U VPX
General Information
Model 53640 is a member of the Cobalt family of high-performance XMC modules based on the Xilinx Virtex-6 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. The 53640 includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. installed functions and enable the 53640 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 53640 factory-installed functions include an A/D acquisition IP module. In addition, IP modules for DDR3 memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factory-

The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O. Option -105 provides dual 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols.
Features

Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One-channel mode with 3.6 GHz, 12-bit A/D Two-channel mode with 1.8 GHz, 12-bit A/Ds 2 GB of DDR3 SDRAM Sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF In
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus

12 12
Sync Bus

GTX

GTX
GTX
40
8X x8 PCIe
4X
4X
Memory Banks 1 & 2
Memory Banks 3 & 4
CROSSBAR SWITCH
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 53640
A/D Converter Stage
The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the 53640 to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple boards. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple 53640s can be synchronized using the Cobalt high-speed sync board to drive the sync bus.
Memory Resources



The 53640 accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connector. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multipin sync bus connector allows multiple boards to be
from A/D
from A/D

MEMORY CONTROLLER
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 53640
The 53640 features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (4X). Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1or Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Sample Clock Sources: Front panel SSMC connector Sync Bus: Multi-pin connectors, bus includes gate, reset and in and out reference clock External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS
VPX Families
53xxx
Model 53640 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - 3U VPX
Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 -105 Gigabit serial FPGA I/O to VPX P1 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
www.pentek.com
! ew N
Model 53641
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D w/ Wideband DDC, Virtex-6 FPGA - 3U VPX
General Information
Model 53641 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A highspeed data converter with a programmable digital downconverter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. The 53641 includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. nization functions, a test signal generator and a PCIe interface complete the factoryinstalled functions and enable the 53641 to operate as a complete turnkey solution, without the need to develop any FPGA IP. For applications that require additional control and status signals, option -104 provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O.
A/D Converter Stage

The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the 53641 to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple boards. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources.

Features

Ideal radar and software radio interface solution One-channel mode with 3.6 GHz, 12-bit A/D Two-channel mode with 1.8 GHz, 12-bit A/Ds 2 GB of DDR3 SDRAM Programmable one- or twochannel DDC (Digital Downconverter) PCI Express (Gen. 1 & 2) interface, up to x8 Sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF In
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus

12 12
Sync Bus

GTX
40
8X x8 PCIe
Memory Banks 1 & 2
Memory Banks 3 & 4
CROSSBAR SWITCH
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 53641
DDC IP Cores

The 53641 accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connector. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multipin sync bus connector allows multiple boards to be synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple 53641s can be synchronized using the Cobalt highspeed sync board to drive the sync bus.
Memory Resources
from A/D
from A/D

to Mem Bank 1
to Mem Bank 2
8X PCIe
FPGA GPIO
40
to Mem Bank 3
to Mem Bank 4
Pentek, Inc.
www.pentek.com
Model 53641
The Model 53641 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links of x4 or x8, the interface includes multiple DMA controllers for efficient transfers to and from the board. Sample Clock Sources: Front panel SSMC connector Sync Bus: Multipin connectors, bus includes gate, reset and in and out reference clock External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1or Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

Specifications
VPX Families
53xxx
Model 53641 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, with Wideband DDC, Virtex-6 FPGA - 3U VPX
Options: -002* -064* -104 -2 FPGA speed grade XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
www.pentek.com
! ew N
Model 53650
Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - 3U VPX
General Information
Model 53650 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A twochannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture and playback features offer an ideal turnkey solution. The 53650 includes two A/Ds, one DUC (digital upconverter), two D/As and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. the factory-installed functions and enable the 53650 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 53650 factory-installed functions include two A/D acquisition and one D/A waveform playback IP modules. In addition, IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete

RF In RF Out RF Out
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Supports gigabit serial fabrics including PCI Express, Serial RapidIO and Xilinx Aurora Two 500 MHz 12-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
500 MHz 12-BIT A/D
500 MHz 12-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
VCXO

GTX
GTX GTX LVDS
Timing Bus
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
8X
4X
4X
40
x8 PCIe
P15 XMC
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
www.pentek.com
Model 53650
A/D Converter Stage


Memory Resources

from A/D Ch 1
to D/A
INPUT MULTIPLEXER

MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
MEMORY CONTROL
to Mem Bank 3
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 53650
boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)


Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (option 014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz, max. Output IF: DC to 400 MHz, max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz, max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm,
Model 53650 Description Two 500 MHz A/Ds, one DUC, Two 800 MHz D/As with Virtex-6 FPGA - 3U VPX
Options: -002* -014 -062 -064 -104 -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 -105 Gigabit serial FPGA I/O to VPX P1 -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -160 Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required
VPX Families
53xxx
Pentek, Inc.
www.pentek.com
! ew N
Model 53651
General Information
Model 53651 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A twochannel, high-speed data converter with a programmable DDC, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. The 53651 includes two A/Ds, two D/As and four banks of memory. It features builtin support for PCI Express over the 3U VPX backplane. or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 53651 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Model 53651 COTS (left) and rugged version The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 53651 factory installed functions include two A/D acquisition and a D/A waveform playback IP modules. Each of the two acquisition IP modules contains a powerful, programmable DDC IP core. The waveform playback IP module contains an intrepolation IP core, ideal for matching playback rates to the data and decimation rates of the acquisition modules. IP modules for either DDR3
RF In

RF In RF Out RF Out
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two 500 MHz 12-bit A/Ds Two multiband DDCs (digital downconverters) Two 800 MHz 16-bit D/As One DUC (digital upconverter) Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 16 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
500 MHz 12-BIT A/D
500 MHz 12-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
VCXO

LVDS
Timing Bus
GTX

GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
40
8X x8 PCIe
Sum to next board
4X 4X
QDRII+ option 160 CROSSBAR SWITCH
Memory Banks 1 & 2
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 53651
frequency. Each DDC can have its own unique decimation setting, supporting as many as two different output bandwidths for the board. Decimations can be programmed from 2 to 131,072 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 16-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the two DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 53651s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the VPX P1 connector. This allows summation across channels on multiple boards.
Beamformer IP Core

from A/D Ch 1

INPUT MULTIPLEXER
to D/A

DDC IP Cores
MUX
DDC CORE
to Mem Bank 1
to Mem Bank 2
to Mem Bank 4
sum out sum in
SUMMER SUMMER
PCIe INTERFACE
BEAMFORMER CORE
8X PCIe
Pentek, Inc.
www.pentek.com
Model 53651
A/D Converter Stage
The front end accepts two analog HF or IF inputs on front panel SSMC connectors with transformer coupling into two Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources. Multiple 53651s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Memory Resources



Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits
Pentek, Inc.
www.pentek.com
Model 53651
A/D Converters (option -014)
Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits Digital Downconverters Quantity: Two channels Decimation Range: 2x to 131,072x in two programmable stages of 2x to 256x and one fixed 2x stage LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 16-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformer Summation: Two channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link over the VPX P1connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T-2 Optional: Xilinx Virtex-6 XC6VSX315T-T2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Memory Option -150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option -155 or -165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Model 53651 Description 2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - 3U VPX
VPX Families
Options: -002* -014 -062 -064 -104 -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240 FPGA XC6VSX315 FPGA LVDS FPGA I/O through the VPX P2 connector -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required
53xxx
Pentek, Inc.
www.pentek.com
! ew N
Model 53660
4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - 3U VPX

General Information
Model 53660 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution. The 53660 includes four A/Ds and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. the 53660 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 53660 factory-installed functions include four A/D acquisition IP modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Supports gigabit serial fabrics including PCI Express, Serial RapidIO and Xilinx Aurora Four 200 MHz 16-bit A/Ds Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

LVDS GTX

GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
40
8X x8 PCIe
4X
4X
Memory Banks 1 & 2
Memory Banks 3 & 4
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 53660

A/D Converter Stage
The front end accepts four full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 53660s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Memory Resources
The 53660 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.



from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 53660

The 53660 features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (4X). External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector LVPECL bus includes, clock/sync/ gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs
VPX Families
Model 53660 Description 4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - 3U VPX XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 Gigabit serial FPGA I/O to VPX P1 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Options: -062 -064 -104 -105 -150
53xxx
-160
-155
-165
Pentek, Inc.
www.pentek.com
! ew N
Model 53661
4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - 3U VPX
General Information
Model 53661 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with a programmable DDC, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. The 53661 includes four A/Ds and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. nization functions, a test signal generator, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 53661 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 53661 factory-installed functions include four A/D acquisition IP modules. Each of the four acquisition IP modules contains a powerful, programmable DDC (digital downconverter) IP core. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchro-

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Four multiband DDCs (digital downconverters) Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

LVDS

GTX
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
40
8X
Sum to x8 PCIe next board
4X 4X
Memory Banks 1 & 2
Memory Banks 3 & 4
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 53661
providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 53661s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the VPX P1 connector. This allows summation across channels on multiple boards.
A/D Converter Stage

Beamformer IP Core

from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
DDC IP Cores
INPUT MULTIPLEXER
DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

MUX
DDC CORE
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
sum out sum in
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
8X PCIe
Pentek, Inc.
www.pentek.com
Model 53661
the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, Functions: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O. Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCIe Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

Memory Resources
The 53661 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Four channels Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation Beamformer Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Sample Clock Sources: On-board clock synthesizer
Model 53661 Description 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - 3U VPX XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Options: -062 -064 -104 -150
VPX Families
-160
53xxx
-155
-165
Pentek, Inc.
www.pentek.com
! ew N
Model 53662
4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - 3U VPX
General Information
Model 53662 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. This fourchannel, high-speed data converter with programmable DDCs (digital downconverters) is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture feature offers an ideal turnkey solution. The 53662 includes four A/Ds and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. SDRAM memory controllers, and a PCIe interface complete the factory-installed functions and enable the 53662 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, and triggering. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 53662 factory-installed functions include four A/D acquisition IP modules. Each of the four acquisition IP modules contains a powerful, programmable 8-channel DDC IP core. IP modules for control of all data clocking, synchronization, gate and trigger functions, a test signal generator, voltage and temperature monitoring, DDR3

The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O. Option -105 provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols.
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Four multiband DDCs Up to 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

LVDS GTX

GTX
GTX
40
8X x8 PCIe
4X
4X
CROSSBAR SWITCH
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 53662

A/D Converter Stage

Memory Resources
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
DDC IP Cores
INPUT MULTIPLEXER

.

.

.

.
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
32 Memory Bank 1
32 Memory Bank 2
32 Memory Bank 3
32 Memory Bank 4
8X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 53662
512 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory and capture space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock, or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

The Model 53662 includes an industry standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the board.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Four 8-channel banks, one per acquisition module Decimation Range: 16x to 8192x in steps of 8x LO Tuning Freq. Resolution: 32 bits, 0 to s Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user-programmable coefficients Default Filter Set: 80% bandwidth, >100 dB stopband attenuation Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock
Model 53662 Description 4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - 3U VPX XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through VPX P2 Gigabit serial FPGA I/O through VPX P1 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
VPX Families
Options: -062 -064 -104 -105 -155
53xxx
-165
Pentek, Inc.
www.pentek.com
! ew N
Model 53670
4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - 3U VPX

General Information
Model 53670 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. This 4-channel, high-speed data converter is suitable for connection to transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As, four digital upconverters and four banks of memory. In addition to supporting PCI Express Gen. 2 over the 3U VPX backplane, the Model 53670 includes general purpose and gigabit serial connectors for application-specific I/O . a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 53670 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Model 53670 COTS (left) and rugged version The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 53670 factory-installed functions include four D/A waveform playback IP modules, to support waveform generation through the D/A converters. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions,
RF Out

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 1.25 GHz 16-bit D/As Four digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multiboard synchronization User-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO

LVDS

GTX
GTX
GTX
40
8X x8 PCIe
4X
4X
Memory Banks 1 & 2
Memory Banks 3 & 4
CROSSBAR SWITCH
Pentek, Inc.
www.pentek.com
Model 53670

Memory Resources



16
to D/A Ch 1 & 2
16
to D/A Ch 3 & 4
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 53670

The 53670 features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (4X). External Trigger Input Type: Front panel female SSMC connector Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin Sync bus connector includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Specifications
D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference
VPX Families
Model 53670 Description 4-Channel 1.25 GHz D/A with Virtex-6 FPGA - 3U VPX
53xxx
Pentek, Inc.
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Model 53671
4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - 3U VPX
General Information
Model 53671 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. This 4-channel, high-speed data converter is suitable for connection to transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As with a wide range of programmable interpolation factors, four digital upconverters and four banks of memory. In addition to supporting PCI Express Gen. 2 over the 3U VPX backplane, the Model 53671 includes optional generalpurpose and gigabit serial connectors for application-specific I/O . data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 53671 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 53671 factory-installed functions include four D/A waveform playback IP modules, to support waveform generation through the D/A converters. IP modules for DDR3 SDRAM memories, a controller for all
RF Out

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 1.25 GHz 16-bit D/As Four digital upconverters Programmable output levels Extended interpolation range from 2x to 1,048,576x 250 MHz max. output bandwidth 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multiboard synchronization Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO

LVDS

GTX
GTX
GTX
40
8X x8 PCIe
4X
4X
Memory Banks 1 & 2
Memory Banks 3 & 4
CROSSBAR SWITCH
Pentek, Inc.
www.pentek.com
Model 53671
Two Texas Instruments DAC3484s provide four DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals to a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs to a 16-bit D/A converter. If translation is disabled, each D/A acts as an interpolating 16-bit D/A with output sampling rates up to 1.25 GHz. In both modes, the D/A provides interpolation factors of 2x, 4x, 8x and 16x. In addition to the DAC3484, the 53671 features an FPGA-based interpolation engine which adds two additonal interpolation stages programmable from 2x to 256x. The combined interpolation results in a range from 2x to 1,048,576x for each D/A channel and is ideal for matching the digital downconversion and data reduction used on the receiving channels of many communications systems. Analog output is through four front panel SSMC connectors. clock either from the front panel SSMC connector or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this latter mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock to phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided by 2, 4, 8, or 16 to provide lower frequency D/A clocks. A pair of front panel Sync connectors allows multiple boards to be synchronized. They accept CML inputs that drive the boards sync and trigger/gate signals. The Pentek Models 5392 or 9192 Cobalt Synchronizers can drive multiple 53671 Sync connectors enabling large, multichannel synchronous configurations.
Memory Resources

An internal timing bus provides all required D/A clocking. The bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives a sample

The Model 53671 factoryinstalled functions include a sophisticated D/A Waveform Playback IP module. Four linked-list controllers support waveform generation to the four D/As from tables stored in either on-board memory or offboard host memory. Data for Channel 1 and Channel 2 are interleaved for delivery to a dual channel D/A device. For this reason, they must share a common trigger/ gate, sample rate, interpolation factor, and other parameters. The same rules apply to Channel 3 and Channel 4. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up to 64 individual link entries for each D/A channel can be chained together to create complex waveforms with a minimum of programming.
16
to D/A Ch 1 & 2
16
to D/A Ch 3 & 4
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4

PCIe INTERFACE
8X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 53671
The Model 53671 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the board. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connector Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin Sync bus connector includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Array: Standard: Xilinx Virtex-6 XC6VLX240T-2 Optional: Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

Specifications
D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the D/A clock
Model 53671 Description 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - 3U VPX
VPX Families
53xxx
Pentek, Inc.
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Model 53690
L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - 3U VPX

General Information
Model 53690 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A 2-Channel high-speed data converter, it is suitable for connection directly to the RF port of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. The Model 53690 includes an L-Band RF tuner, two A/Ds and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. factory-installed functions and enable the 53690 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 53690 factory-installed functions include two A/D acquisition IP modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the

Features

Accepts RF signals from 925 MHz to 2175 MHz Programmable LNA boosts LNB antenna signal levels with up to 60 dB gain Programmable analog downconverter provides I + Q baseband signals with bandwidths ranging from 4 to 40 MHz Two 200 MHz 16-bit A/Ds Supports Xilinx Virtex-6 LXT and SXT FPGAs 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference Clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
Ref In
RF In
MAX2112
Ref Out GC
12-BIT D/A
Ref A/D Clock/Sync
Control
16
16
IC
2
Timing Bus
VCXO

LVDS GTX

GTX
GTX
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
Config FLASH 64 MB
40
8X x8 PCIe
4X
4X
Memory Banks 1 & 2
Memory Banks 3 & 4
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 53690

RF Tuner Stage


A/D Converter Stage

Memory Resources
from A/D (I)
from A/D (Q)
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 53690
The Model 53690 includes an industry standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the board

8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. The factory-installed A/D Acquisition Modules use memory banks 1 & 2. Banks 3 & 4 can be optionally installed to support custom user-installed IP within the FPGA . 800 MHz when Timing Generator divider is enabled) or PLL system reference Timing Generator Bus: 26-pin front panel connector LVPECL bus includes, clock/ sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Input Quantity: 2 Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8; Gen. 2 x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

Specifications
Front Panel Analog Signal Input Connector: Front panel female SSMC Impedance: 50 ohms L-Band Tuner Type: Maxim MAX2112 Input Frequency Range: 925 MHz to 2175 MHz Monolithic VCO Phase Noise: -97 dBc/Hz at 10 kHz Fractional-N PLL Synthesizer: freqVCO = (N.F) x freqREF where integer N = 19 to 251 and fractional F is a 20-bit binary value PLL Reference (freqREF): Front panel SSMC connector or on-board 27 MHz crystal (Option -100), 12 to 30 MHz LNA Gain: 0 to 65 dB, controlled by a programmable 12-bit D/A converter* Baseband Amplifier Gain: 0 to 15 dB, in 1 dB steps* *Usable Full-Scale Input Range: 50 dBm to +10 dBm Baseband Low Pass Filter: Cutoff frequency programmable from 4 to 40 MHz with 8-bit resolution A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board timing generator/synthesizer A/D Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, for the A/D clock Timing Generator External Clock Input Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 200 MHz (up to
Model 53690 Description L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - 3U VPX XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 Gigabit serial FPGA I/O to VPX P1 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Options: -062 -064 -104 -105 -150
VPX Families
53xxx
-160
-155
-165
Pentek, Inc.
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! ew N
Model 53720
General Information
Model 53720 is a member of the Onyx family of high-performance 3U VPX boards based on the Xilinx Virtex-7 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture and playback features offer an ideal turnkey solution. The 53720 includes three A/Ds, one upconverter, two D/As and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable the 53720 to operate as a complete turnkey solution without the need to develop any FPGA IP.


The Virtex-7 FPGA site can be populated with one of two FPGAs to match the specific requirements of the processing task. Supported FPGAs are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O. Option -105 provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols.
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Three 200 MHz 16-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1 and 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-7 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
16
Timing Bus
VCXO

LVDS

GTX
GTX
GTX
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
FPGA Config Bus
PCIe Gen. 2 x8
4X
4X
PCIe Gen. 2 x8
CROSSBAR SWITCH
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 53720
A/D Converter Stage


A TI DAC5688 DUC (digital upconverter) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband
to D/A D/A loopback
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3

INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
MEMORY CONTROL
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 53720
input signals to any IF center frequency
up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x. Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O. Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8; Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Memory Resources
The 53720 architecture supports four independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode.

Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an onboard programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator.

Crossbar Switch
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock
VPX Families
Model 53720 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-7 FPGA 3U VPX XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O to VPX P2 Gigabit serial FPGA I/O to VPX P1
53xxx
Options: -073 -076 -104 -105
Pentek, Inc.
www.pentek.com
! ew N
Model 53760

General Information
Model 53760 is a member of the Onyx family of high-performance 3U VPX boards based on the Xilinx Virtex-7 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. The 53760 includes four A/Ds and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 53760 to operate as a complete turnkey solution without the need to develop any FPGA IP.


Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Four 200 MHz 16-bit A/Ds 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Advanced reconfigurability features Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-7 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D 16
200 MHz 16-BIT A/D 16
200 MHz 16-BIT A/D 16
200 MHz 16-BIT A/D 16

VCXO
LVDS
Timing Bus

GTX
GTX
GTX
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
FPGA Config Bus
PCIe Gen. 2 x8
4X
4X
PCIe Gen. 2 x8
CROSSBAR SWITCH
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 53760

A/D Converter Stage



An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generator receives an external sample clock from the front panel
from A/D Ch 1
from A/D Ch 2
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 53760

SSMC connector. This clock can be
used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 53760s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8; Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

The Model 53760 includes an industry-standard interface fully compliant with PCI Express Gen. 1 and 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the board.

Memory Resources
Specifications
VPX Families
Model 53760 Description 4-Channel 200 MHz A/D with Virtex-7 FPGA - 3U VPX XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O to VPX P2 Gigabit serial FPGA I/O to VPX P1
53xxx
Options: -073 -076 -104 -105
Pentek, Inc.
www.pentek.com
! ew N
Model 53730

General Information
Model 53730 is a member of the Onyx family of high performance 3U VPX boards based on the Xilinx Virtex-7 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes 1 GHz A/D and D/A converters and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factoryinstalled functions and enable the 53730 to operate as a complete turnkey solution, without the need to develop any FPGA IP.


RF In RF Out
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe One 1 GHz 12-bit A/D One 1 GHz 16-bit D/A 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional LVDS connections to the Virtex-7 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Sync In
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12
1 GHz 16-BIT D/A 16
D/A Sync Bus
VCXO

LVDS

GTX
GTX
GTX
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
FPGA Config Bus
PCIe Gen. 2 x8
4X
4X
PCIe Gen. 2 x8
CROSSBAR SWITCH
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 53730


A/D Converter Stage

D/A Converter Stage

to D/A

INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 53730

External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8; Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Memory Resources

Crossbar Switch
Specifications
VPX Families
Model 53730 Options: -073 -076 -104 -105 XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O to VPX P2 Gigabit serial FPGA I/O to VPX P1 Description 1 GHz A/D and D/A, Virtex-7 FPGA - 3U VPX
53xxx
Pentek, Inc.
www.pentek.com
RAD AR & SDR I/O - AMC RADAR

MODEL
Cobalt 56620 Cobalt 56621 Cobalt 56630 Cobalt 56640 Cobalt 56641 Cobalt 56650 Cobalt 56651 Cobalt 56660 Cobalt 56661 Cobalt 56662 Cobalt 56670 Cobalt 56671 Cobalt 56690 Onyx 56720 Onyx 56760 Onyx 56730
DESCRIPTION
3-Channel 200 MHz A/D, 2-Channel 800 MHz D/A, Virtex-6 FPGA - AMC 3-Channel 200 MHz A/D with DDC, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - AMC 1 GHz A/D and D/A, Virtex-6 FPGA - AMC 1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D, Virtex-6 FPGA - AMC 1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D, Wideband DDC, Virtex-6 FPGA - AMC Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - AMC 2-Chan 500 MHz A/D with DDC, DUC with 2-Chan 800 MHz D/A, Virtex-6 FPGA - AMC 4-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - AMC 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - AMC 4-Channel 200 MHz A/D with 32-Channel DDC and Virtex-6 FPGA - AMC 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - AMC 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - AMC L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - AMC 3-Channel 200 MHz A/D with DDC, DUC, 2-Channel 800 MHz D/A, Virtex-7 FPGA - AMC 4-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - AMC 1 GHz A/D and D/A, Virtex-7 FPGA - AMC Customer Information
& & & & & &
PMC/XMC CompactPCI PCI x 8 PCI Express 3U VPX - FORMA T 1 FORMAT 3U VPX - FORMA T 2 FORMAT

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Model 56620
3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - AMC
General Information
Model 56620 is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture and playback features offer an ideal turnkey solution. It includes three A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 56620 includes a front panel general-purpose connector for applicationspecific I/O . controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable the 56620 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 56620 factory-installed functions include three A/D acquisition and a D/A waveform playback IP modules, ideally matched to the boards analog interfaces. IP modules for either DDR3 or QDRII+ memories, a

The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 installs a front panel connector with 20 pairs of LVDS connections to the FPGA for custom I/O.
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three 200 MHz 16-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF In
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
16
Timing Bus
VCXO

GTX
LVDS
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
8X
IPMI CONTROLLER
40
x8 PCIe
RS-232
FPGA GPIO (option 104) Front Panel
AMC Ports 4 to 11
Front Panel
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
www.pentek.com
Model 56620
A/D Converter Stage
The front end accepts three full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 56620s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.

Memory Resources
to D/A D/A loopback


INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
MEMORY CONTROL
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 56620
FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks. 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8; Gen. 2: x4 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.
AMC Interface
The Model 56620 complies with the AMC.1 specification by providing an x8 PCIe connection to AdvancedTCA carriers or TCA chassis. Module management is provided by an IPMI 2.0 MMC (Module Management Controller).

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors
Model 56620 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-6 FPGA AMC XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through front panel connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Options: -062 -064 -104 -150
-160
-155
-165
Pentek, Inc.
www.pentek.com
! w e N
Model 56621
3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - AMC
General Information
Model 56621 is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with a programmable DDC, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes three A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 56621 includes a front panel general-purpose connector for applicationspecific I/O. the data and decimation rates of the acquisition modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 56621 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 56621 factory installed functions include three A/D acquisition and a D/A waveform playback IP modules. Each of the three acquisition IP modules contains a powerful, programmable DDC IP core. The waveform playback IP module contains an intrepolation IP core, ideal for matching playback rates to
RF In

The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 installs a front panel connector with 20 pairs of LVDS connections to the FPGA for custom I/O.
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three 200 MHz 16-bit A/Ds Three multiband DDCs (digital downconverters) Two 800 MHz 16-bit D/As One DUC (digital upconverter) Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
16
Timing Bus
VCXO

GTX
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
8X
IPMI CONTROLLER
4X
4X
Sum to next board Aurora Gigabit Serial Front Panel
x8 PCIe
RS-232
AMC Ports 4 to 11
Front Panel
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
www.pentek.com
Model 56621
s, where s is the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as three different output bandwidths for the board. Decimations can be programmed from 2 to 65,536 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the three DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 56621s can be chained together via a built-in Xilinx Aurora gigabit serial interface which allows summation across channels on multiple boards.
Beamformer IP Core

from A/D Ch 1
from A/D Ch 2
to D/A
INPUT MULTIPLEXER
DDC DEC: 2 TO 65536
DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all three DDCs or each of the three A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to
MUX
DDC CORE
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
sum out sum in
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
8X PCIe
Pentek, Inc.
www.pentek.com
Model 56621
A/D Converter Stage
The front end accepts three analog HF or IF inputs on front panel SSMC connectors with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 56621s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.

Memory Resources
AMC Interface


Pentek, Inc.
www.pentek.com
Model 56621
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Three channels Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformer Summation: Three channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.
Model 56621 Description 3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA AMC
Options: -062 -064 -104 -150 XC6VLX240T XC6VSX315T LVDS FPGA I/O through front panel connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
-160
-155
-165
Pentek, Inc.
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! ew N
Model 56630
1 GHz A/D and 1 GHz D/A, Virtex-6 FPGA - AMC

General Information
Model 56630 is a member of the Cobalt family of high performance AMC modules based on the Xilinx Virtex-6 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes 1 GHz A/D and D/A converters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 56630 includes a front panel general-purpose connector for application-specific I/O . memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factory-installed functions and enable the 56630 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 56630 factory-installed functions include an A/D acquisition and a D/A waveform playback IP module. In addition, IP modules for either DDR3 or QDRII+

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One 1 GHz 12-bit A/D One 1 GHz 16-bit D/A Up to 2 GB of DDR3 SDRAM or 16 MB of QDRII+ SRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF Out
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Sync In
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12
1 GHz 16-BIT D/A 16
D/A Sync Bus
VCXO

GTX
LVDS
16
16
16
16
8X
IPMI CONTROLLER
40
x8 PCIe
RS-232
AMC Ports 4 to 11
Front Panel
QDRII+ option 150
Pentek, Inc.
www.pentek.com
Model 56630

A/D Converter Stage

D/A Converter Stage

Memory Resources

to D/A

INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
(supports user installed IP) 8X PCIe 40
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 56630

AMC Interface
The Model 56630 complies with the AMC.1 specification by providing an x8 PCIe connection to AdvancedTCA carriers or TCA chassis. Module management is provided by an IPMI 2.0 MMC (Module Management Controller). External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory Option 150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1: x4 or x8; Gen 2: x4 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.

Specifications
Model 56630 Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through front panel connector -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required Description 1 GHz A/D and D/A, Virtex-6 FPGA - AMC
Pentek, Inc.
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! w e N
Model 56640
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - AMC
General Information
Model 56640 is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 56640 includes a front panel general-purpose connector for application-specific I/O . controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factoryinstalled functions and enable the 56640 to operate as a complete turnkey solution, without the need to develop any FPGA IP.


Features

Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One-channel mode with 3.6 GHz, 12-bit A/D Two-channel mode with 1.8 GHz, 12-bit A/Ds 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus

12 12
Sync Bus

GTX
LVDS
8X
IPMI CONTROLLER
40
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCIe
RS-232
AMC Ports 4 to 11
Front Panel
Pentek, Inc.
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Model 56640
A/D Converter Stage
The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the 56640 to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple modules. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple 56640s can be synchronized using the Cobalt high speed sync module to drive the sync bus.
Memory Resources

AMC Interface

The 56640 accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connector. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multi-pin sync bus connector allows multiple modules to be
from A/D
from A/D

MEMORY CONTROLLER
(supports user installed IP) to Mem Bank 1 to Mem Bank 2 8X PCIe 40 to Mem Bank 3 to Mem Bank 4
FPGA GPIO
Pentek, Inc.
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Model 56640
The Model 56640 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the module. External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2, or XC6VSX315T-2 Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.
Specifications
Model 56640 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - AMC
Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T XC6VSX315T LVDS FPGA I/O through front panel connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
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Model 56641
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, w/ Wideband DDC, Virtex-6 FPGA - AMC
General Information
Model 56641 is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6 FPGA. A highspeed data converter with a programmable digital downconverter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. It includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 56641 includes a front panel general-purpose connector for application-specific I/O . controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factoryinstalled functions and enable the 56641 to operate as a complete turnkey solution, without the need to develop any FPGA IP. For applications that require additional control and status signals, option -104 installs a front panel connector with 20 pairs of LVDS connections to the FPGA for custom I/O.
A/D Converter Stage


Features

Ideal radar and software radio interface solution One-channel mode with 3.6 GHz, 12-bit A/D Two-channel mode with 1.8 GHz, 12-bit A/Ds Programmable one- or twochannel DDC (Digital Downconverter) 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus

12 12
Sync Bus

GTX
LVDS
8X
IPMI CONTROLLER
40
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCIe
RS-232
AMC Ports 4 to 11
Front Panel
Pentek, Inc.
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Model 56641
The 56641 features an A/D Acquisition IP Module for easy capture and data moving. The IP module can receive data from the A/D, or a test signal generator. The IP module has associated memory banks for buffering data in FIFO mode or for storing data in transient capture mode. In single-channel mode, all four banks are used to store the single-channel of input data. In dual-channel mode, memory banks 1 and 2 store data from input channel 1 and memory banks 3 and 4 store data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving A/D data through the PCIe interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
DDC IP Cores

The 56641 accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connector. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multipin sync bus connector allows multiple modules to be synchronized, ideal for multichannel systems. The sync bus includes gate, reset, and in and out reference clock signals. Two 56641s can be synchronized with a simple cable. For larger systems, multiple 56641s can be synchronized using the Cobalt 7192 highspeed sync module to drive the sync bus.
Memory Resources
The 56641 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the modules DMA and data capture capabilities. Built-in memory functions include an A/D data transient capture mode for taking snapshots of data for transfer to a host computer.
from A/D
from A/D

to Mem Bank 1
to Mem Bank 2
8X PCIe
FPGA GPIO
40
to Mem Bank 3
to Mem Bank 4
Pentek, Inc.
www.pentek.com
Model 56641
AMC Interface
The Model 56641 complies with the AMC.1 specification by providing an x8 PCIe connection to AdvancedTCA carriers or TCA chassis. Module management is provided by an IPMI 2.0 MMC (Module Management Controller). LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: User-programmable 18-bit coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation Sample Clock Sources: Front panel SSMC connector Sync Bus: Multipin front panel connector, includes gate, reset, and in and out ref clock External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include trigger and gate Field Programmable Gate Array: Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.

The Model 56641 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the module.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Digital Downconverters Modes: One or two channels, programmable Supported Sample Rate: One-channel mode: 3.6 GHz, two-channel mode: 1.8 GHz Decimation Range: One-channel mode: 8x, 16x or 32x, two-channel mode: 4x, 8x, or 16x
Model 56641 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D with Wideband DDC, Virtex-6 FPGA - AMC
Options: -002* -064* -104 -2 FPGA speed grade XC6VSX315T LVDS FPGA I/O through front panel connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
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Model 56650
Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - AMC
General Information
Model 56650 is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes two A/Ds, one DUC (Digital Upconverter), two D/As, and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 56650 includes a front panel general-purpose connector for applicationspecific I/O . IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factory-installed functions and enable the 56650 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 56650 factory-installed functions include two A/D acquisition and one D/A waveform playback IP modules. In addition,

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two 500 MHz 12-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
500 MHz 12-BIT A/D
500 MHz 12-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
VCXO

GTX
LVDS
Timing Bus
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
8X
IPMI CONTROLLER
40
x8 PCIe
RS-232
AMC Ports 4 to 11
Front Panel
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
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Model 56650
A/D Converter Stage
Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an onboard programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 56650s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.

The front end accepts two full scale analog HF or IF inputs on front panel SSMC connectors at +5 dBm into 50 ohms with transformer coupling into two Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources.

Memory Resources

from A/D Ch 1
to D/A
INPUT MULTIPLEXER

MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
MEMORY CONTROL
to Mem Bank 3
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
FPGA GPIO
40
Pentek, Inc.
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Model 56650
FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
AMC Interface


Model 56650 Description Two 500 MHz A/Ds, one DUC, Two 800 MHz D/As with Virtex-6 FPGA - AMC
Options: -002* -014 -062 -064 -104 -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240 FPGA XC6VSX315 FPGA LVDS FPGA I/O through front panel connector -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -160 Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (option 014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz, max. Output IF: DC to 400 MHz, max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz, max. with interpolation Resolution: 16 bits
Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1 or Gen.2, x4 or x8 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.
Pentek, Inc.
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Model 56651
General Information
Model 56651 is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with a programmable DDC, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes two A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 56651 includes a front panel general-purpose connector for applicationspecific I/O. the data and decimation rates of the acquisition modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 56651 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 56651 factory-installed functions include two A/D acquisition and a D/A waveform playback IP modules. Each of the two acquisition IP modules contains a powerful, programmable DDC IP core. The waveform playback IP module contains an intrepolation IP core, ideal for matching playback rates to
RF In

RF In RF Out RF Out
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two 500 MHz 12-bit A/Ds Two multiband DDCs (digital downconverters) Two 800 MHz 16-bit D/As One DUC (digital upconverter) Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 16 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
500 MHz 12-BIT A/D
500 MHz 12-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
VCXO

GTX
GTX
Timing Bus
GTX
8X
IPMI CONTROLLER
4X
4X
x8 PCIe
RS-232
AMC Ports 4 to 11
Front Panel
QDRII+ option 150
Pentek, Inc.
www.pentek.com
Model 56651
frequency. Each DDC can have its own unique decimation setting, supporting as many as two different output bandwidths for the board. Decimations can be programmed from 2 to 131,072 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 16-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the two DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 56651s can be chained together via a built-in Xilinx Aurora gigabit serial interface to allow summation across channels on multiple boards.
Beamformer IP Core

from A/D Ch 1

INPUT MULTIPLEXER
to D/A

DDC IP Cores
MUX
DDC CORE
to Mem Bank 1
to Mem Bank 2
to Mem Bank 4
sum out sum in
SUMMER SUMMER
PCIe INTERFACE
BEAMFORMER CORE
8X PCIe
Pentek, Inc.
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Model 56651
A/D Converter Stage
The front end accepts two analog HF or IF inputs on front panel SSMC connectors with transformer coupling into two Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 56651s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.

Memory Resources
The 56651 architecture supports up to three independent memory banks which can be configured with QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
AMC Interface


The Model 56651 includes an industrystandard interface fully compliant with PCI Express Gen. 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the module.
Pentek, Inc.
www.pentek.com
Model 56651
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (option -014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits Digital Downconverters Quantity: Two channels Decimation Range: 2x to 131,072x in two programmable stages of 2x to 256x and one fixed 2x stage LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 16-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformer Summation: Two channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T-2 Optional: Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory Option -150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option -155 or -165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 2: x4 or x8 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.
Model 56651 Description 2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA AMC
Options: -002* -014 -062 -064 -104 -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through front panel connector -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required
Pentek, Inc.
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! w e N
Model 56660
4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - AMC

General Information
Model 56660 is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes four A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 56660 includes a front panel general-purpose connector for applicationspecific I/O. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 56660 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 56660 factory-installed functions include four A/D acquisition IP modules.

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

GTX
LVDS
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
8X
IPMI CONTROLLER
40
x8 PCIe
RS-232
AMC Ports 4 to 11
Front Panel
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
www.pentek.com
Model 56660

A/D Converter Stage
Memory Resources


AMC Interface
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 56660

The Model 56660 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the module. Timing Bus: 26-pin front panel connector; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference
Model 56660 Options: -062 -064 -104 -150 XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through front panel connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Description 4-Channel 200 MHz A/D with Virtex-6 FPGA - AMC
-160
-155
-165
Pentek, Inc.
www.pentek.com
! w e N
Model 56661
4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - AMC
General Information
Model 56661 is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with programmable DDCs (digital downconverters), it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture feature offers an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes four A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 56661 includes a front panel generalpurpose connector for application-specific I/O. for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 56661 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 56661 factory-installed functions include four A/D acquisition IP modules. Each of the four acquisition IP modules contains a powerful, programmable DDC (Digital Downconverter) IP core. IP modules

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Four multiband DDCs Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

GTX
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
8X
IPMI CONTROLLER
4X
4X
x8 PCIe
RS-232
AMC Ports 4 to 11
Front Panel
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
www.pentek.com
Model 56661
The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 56661s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the P16 XMC connector. This allows summation across channels on multiple boards.
Beamformer IP Core
In addition to the DDCs, the 56661 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the four DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and
A/D Converter Stage


An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a builtin clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage controlled crystal oscillator. In this
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquistion IP Modules, many different configurations can be achieved including one A/D driving all four DDCs or each of the four A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as four different output bandwidths for the board. Decimations can be programmed from 2 to 65,536 providing a wide range to satisfy most applications.
TEST SIGNAL GENERATOR INPUT MULTIPLEXER
DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

MUX
DDC CORE
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
sum out sum in
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
8X PCIe
Pentek, Inc.
www.pentek.com
Model 56661
mode, the front panel SSMC connector
can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 56661s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. Beamformer Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.
AMC Interface

The Model 56661 includes an industry-standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the module.
Memory Resources
Model 56661 Description 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - AMC XC6VLX240T XC6VSX315T LVDS FPGA I/O through front panel connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Specifications
Options: -062 -064 -104 -150
-160
-155
-165
Pentek, Inc.
www.pentek.com
! w e N
Model 56662
4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - AMC
General Information
Model 56662 is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6 FPGA. This fourchannel, high-speed data converter with programmable DDCs (digital downconverters) is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture feature offers an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes four A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 56662 includes a front panel general-purpose connector for applicationspecific I/O. all data clocking, synchronization, gate and trigger functions, a test signal generator, voltage and temperature monitoring, DDR3 SDRAM memory controllers, and a PCIe interface complete the factory-installed functions and enable the 56662 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, and triggering. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 56662 factory-installed functions include four A/D acquisition IP modules. Each of the four acquisition IP modules contains a powerful, programmable 8-channel DDC IP core. IP modules for control of

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Four multiband DDCs Up to 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

GTX
LVDS
8X
IPMI CONTROLLER
40
x8 PCIe
RS-232
AMC Ports 4 to 11
Front Panel
Pentek, Inc.
www.pentek.com
Model 56662

An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a builtin clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltagecontrolled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a reference clock, typically 10 MHz, for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 56662s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.
A/D Converter Stage

Memory Resources
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
DDC IP Cores
INPUT MULTIPLEXER

.

.

.

.
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
32 Memory Bank 1
32 Memory Bank 2
32 Memory Bank 3
32 Memory Bank 4
8X PCIe
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 56662
512 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory and capture space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock, or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.
AMC Interface

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Four 8-channel banks, one per acquisition module Decimation Range: 16x to 8192x in steps of 8x LO Tuning Freq. Resolution: 32 bits, 0 to s Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, >100 dB stopband attenuation
Model 56662 Description 4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - AMC XC6VLX240T XC6VSX315T LVDS FPGA I/O through front panel connector Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Options: -062 -064 -104 -155
-165
Contact Pentek for availability of ruged and conduction-cooled versions
Pentek, Inc.
www.pentek.com
! ew N
Model 56670
4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - AMC

General Information
Model 56670 is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6 FPGA. This 4-channel, high-speed data converter is suitable for connection to transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As, four digital upconverters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 56670 includes a front panel general-purpose connector for application-specific I/O. SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 56670 to operate as a complete turnkey solution, without the need to develop any FPGA IP.


Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 1.25 GHz 16-bit D/As Four digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-6 FPGA for custom I/O
RF Out
RF Out
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
Sync Bus A
Gate In Sync In
Sync Bus B
VCXO

GTX
LVDS
8X
IPMI CONTROLLER
40
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCIe
RS-232
AMC Ports 4 to 11
Front Panel
Pentek, Inc.
www.pentek.com
Model 56670

Memory Resources

AMC Interface

16
to D/A Ch 1 & 2
16
to D/A Ch 3 & 4
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 56670

The Model 56670 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the module. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connector Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin Sync bus connector includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.
Specifications
D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the D/A clock
Model 56670 Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through front panel connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required Description 4-Channel 1.25 GHz D/A with Virtex-6 FPGA - AMC
Pentek, Inc.
www.pentek.com
! ew N
Model 56671
4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - AMC
General Information
Model 56671 is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6 FPGA. This 4-channel, high-speed data converter is suitable for connection to transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As with a wide range of programmable interpolation factors, four digital upconverters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 56671 includes a front panel general-purpose connector for applicationspecific I/O. the D/A converters. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 56671 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 56671 factory-installed functions include four D/A waveform playback IP modules, to support waveform generation through

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 1.25 GHz 16-bit D/As Four digital upconverters Extended interpolation range from 2x to 1,048,576x Programmable output levels 250 MHz max. output bandwidth 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-6 FPGA for custom I/O
RF Out
RF Out
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
Sync Bus A
Gate In Sync In
Sync Bus B
VCXO

GTX
LVDS
8X
IPMI CONTROLLER
40
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCIe
RS-232
AMC Ports 4 to 11
Front Panel
Pentek, Inc.
www.pentek.com
Model 56671
Two Texas Instruments DAC3484s provide four DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals to a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs to a 16-bit D/A converter. If translation is disabled, each D/A acts as an interpolating 16-bit D/A with output sampling rates up to 1.25 GHz. In both modes, the D/A provides interpolation factors of 2x, 4x, 8x and 16x. In addition to the DAC3484, the 56671 features an FPGA-based interpolation engine which adds two additonal interpolation stages programmable from 2x to 256x. The combined interpolation results in a range from 2x to 1,048,576x for each D/A channel and is ideal for matching the digital downconversion and data reduction used on the receiving channels of many communications systems. Analog output is through four front panel SSMC connectors. on-board clock generator receives a sample clock either from the front panel SSMC connector or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this latter mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock to phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided by 2, 4, 8, or 16 to provide lower frequency D/A clocks. A pair of front panel Sync connectors allows multiple boards to be synchronized. They accept CML inputs that drive the boards sync and trigger/gate signals. The Pentek Models 5692 or 9192 Cobalt Synchronizers can drive multiple 56671 Sync connectors enabling large, multichannel synchronous configurations.
Memory Resources
The 56671 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the modules DMA and waveform playback capabilities. Waveform tables can be loaded into the memories with playback managed by the linked-list controllers. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

The Model 56671 factoryinstalled functions include a sophisticated D/A Waveform Playback IP module. Four linkedlist controllers support waveform generation to the four D/As from tables stored in either onboard memory or off-board host memory. Data for Channel 1 and Channel 2 are interleaved for delivery to a dual channel D/A device. For this reason, they must share a common trigger/ gate, sample rate, interpolation factor, and other parameters. The same rules apply to Channel 3 and Channel 4. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up to 64 individual link entries for each D/A channel can be chained together to create complex waveforms with a minimum of programming. An internal timing bus provides all required D/A clocking. The bus includes a clock, sync and a gate or trigger signal. An
16
to D/A Ch 1 & 2
16
to D/A Ch 3 & 4
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4

PCIe INTERFACE
8X PCIe
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 56671
AMC Interface
The Model 56671 complies with the AMC.1 specification by providing an x8 PCIe connection to AdvancedTCA carriers or TCA chassis. Module management is provided by an IPMI 2.0 MMC (Module Management Controller). Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connector Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin Sync bus connector includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Array: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.

The Model 56671 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the module.
Specifications
D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15
Model 56671 Description 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - AMC
Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through front panel connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
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Model 56690
L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - AMC

General Information
Model 56690 is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6 FPGA. A 2-Channel high-speed data converter, it is suitable for connection directly to the RF port of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes an L-Band RF tuner, two A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 56690 includes a front panel general-purpose connector for application-specific I/O. and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 56690 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 56690 factory-installed functions include two A/D acquisition IP modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking

Features

Accepts RF signals from 925 MHz to 2175 MHz Programmable LNA boosts LNB (low-noise block) antenna signal levels with up to 60 dB gain Programmable analog downconverter provides I + Q baseband signals with bandwidths ranging from 4 to 40 MHz Two 200 MHz 16-bit A/Ds digitize the I + Q signals synchronously Supports Xilinx Virtex-6 LXT and SXT FPGAs 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference Clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface, up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-6 FPGA for custom I/O
Ref In
RF In
MAX2112
Ref Out GC
12-BIT D/A
Ref A/D Clock/Sync
Control
16
16
IC
2
Timing Bus
VCXO

GTX
LVDS
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
Config FLASH 64 MB
8X
IPMI CONTROLLER
40
x8 PCIe
RS-232
AMC Ports 4 to 11
Front Panel
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
www.pentek.com
Model 56690

RF Tuner Stage


A/D Converter Stage

Memory Resources
from A/D (I)
from A/D (Q)
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 56690

8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. The factory-installed A/D acquisition modules use memory banks 1 & 2. Banks 3 & 4 can be optionally installed to support custom user-installed IP within the FPGA . A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board timing generator/synthesizer A/D Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, for the A/D clock Timing Generator External Clock Input Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 200 MHz (up to 800 MHz when Timing Generator divider is enabled) or PLL system reference Timing Generator Bus: 26-pin front panel connector LVPECL bus includes, clock/ sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Input Quantity: 2 Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8; Gen. 2 x4 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.
AMC Interface

Specifications
Model 56690 Description L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - AMC XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through front panel connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Options: -062 -064 -104 -150
-160
-155
-165
Pentek, Inc.
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Model 56720
General Information
Model 56720 is a member of the Onyx family of high-performance AMC modules based on the Xilinx Virtex-7 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture and playback features offer an ideal turnkey solution. It includes three A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 3 as a native interface, the Model 56720 includes a front panel general-purpose connector for applicationspecific I/O . playback IP modules for simplifying data capture and data transfer. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable the 56720 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 FPGAs from Xilinx. As the central feature of the board architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 56760 factory-installed functions include three A/D acquisition and a D/A waveform

The Virtex-7 FPGA site can be populated with one of two FPGAs to match the specific requirements of the processing task. Supported FPGAs are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 installs a front panel connector with 20 pairs of LVDS connections to the FPGA for custom I/O.
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Three 200 MHz 16-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-7 FPGA for custom I/O
RF In
RF In
RF In
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
16
Timing Bus
VCXO

GTX
LVDS
CONFIG FLASH 1 GB
FPGA Config Bus
PCIe Gen. 3 x8
IPMI CONTROLLER
48
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
RS-232 AMC
PCIe Gen. 3 x8
Ports 4 to 11
Front Panel
Pentek, Inc.
www.pentek.com
Model 56720
A/D Converter Stage

The front end accepts three full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-7 FPGA for signal processing, data capture or for routing to other module resources.

from A/D Ch 1
from A/D Ch 2

to D/A

INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
MEMORY CONTROL
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
FPGA GPIO
48
Pentek, Inc.
www.pentek.com
Model 56720
Memory Resources
The 56720 architecture supports four independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factoryinstalled functions, custom userinstalled IP within the FPGA can take advantage of the memories for many other purposes.
and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x. D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Gen. 3 available only with the VX330T-2 and VX690T-2 FPGAs AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.

Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 56720s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.
AMC Interface


Model 56720 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-7 FPGA AMC XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O through front panel connector
Options: -073 -076 -104
Pentek, Inc.
www.pentek.com
! w e N
Model 56760

General Information
Model 56760 is a member of the Onyx family of high-performance AMC modules based on the Xilinx Virtex-7 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes four A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 3 as a native interface, the Model 56760 includes a front panel general-purpose connector for applicationspecific I/O. modules for simplifying data capture and data transfer. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable the 56760 to operate as a complete turnkey solution without the need to develop any FPGA IP.

Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 FPGAs from Xilinx. As the central feature of the board architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 56760 factory-installed functions include four A/D acquisition IP

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Four 200 MHz 16-bit A/Ds 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-7 FPGA for custom I/O
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

GTX
LVDS
CONFIG FLASH 1 GB
FPGA Config Bus
PCIe Gen. 3 x8
IPMI CONTROLLER
48
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
RS-232 AMC
PCIe Gen. 3 x8
Ports 4 to 11
Front Panel
Pentek, Inc.
www.pentek.com
Model 56760

A/D Converter Stage



An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generator receives
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
FPGA GPIO
48
Pentek, Inc.
www.pentek.com
Model 56760

an external sample clock from the front
panel SSMC connector. This clock can be used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 56760s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Gen. 3 available only with the VX330T-2 and VX690T-2 FPGAs AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.
Memory Resources
The 56760 architecture supports four independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user- installed IP within the FPGA can take advantage of the memories for many other purposes.
AMC Interface

Model 56760 Options: -073 -076 -104 XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O through front panel connector Description 4-Channel 200 MHz A/D with Virtex-7 FPGA - AMC
Specifications
Pentek, Inc.
www.pentek.com
! ew N
Model 56730

General Information
Model 56730 is a member of the Onyx family of high performance AMC modules based on the Xilinx Virtex-7 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes 1 GHz A/D and D/A converters and four banks of memory. In addition to supporting PCI Express Gen.3 as a native interface, the Model 56730 includes a front panel general-purpose connector for application-specific I/O . form playback IP module for simplifying data capture and data transfer. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factoryinstalled functions and enable the 56730 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 FPGAs from Xilinx. As the central feature of the board architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 56730 factory-installed functions include an A/D acquisition and a D/A wave-

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe One 1 GHz 12-bit A/D One 1 GHz 16-bit D/A 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multiboard synchronization PCI Express (Gen. 1, 2 & 3) interface up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-7 FPGA for custom I/O
RF In
RF Out
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Sync In
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12
1 GHz 16-BIT D/A 16
D/A Sync Bus
VCXO
GTX

LVDS
CONFIG FLASH 1 GB
FPGA Config Bus
PCIe Gen. 3 x8
IPMI CONTROLLER
48
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
RS-232 AMC
PCIe Gen. 3 x8
Ports 4 to 11
Front Panel
Pentek, Inc.
www.pentek.com
Model 56730


A/D Converter Stage

D/A Converter Stage

to D/A

INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 56730

Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives a sample clock either from the front panel SSMC connector or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this latter mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock to phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or 16 to provide different lower frequency A/D and D/A clocks. A pair of front panel Sync connectors allows multiple modules to be synchronized. They accept CML inputs that drive the boards sync and gate/trigger signals. The Pentek Model 5692 and Model 9192 Cobalt Synchronizers can drive multiple 56730 Sync connectors enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connector. Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Installs a front panel connector with 24 LVDS pairs to the FPGA Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.
AMC Interface

Memory Resources
Specifications
Model 56730 Options: -073 -076 -104 XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O to front pannel connector Description 1 GHz A/D and D/A, Virtex-7 FPGA - AMC
Pentek, Inc.
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Model 8266

General Information
The Model 8266 is a fully-integrated PC development system for Pentek 786xx Cobalt and 787xx Onyx PCI Express software radio, data acquisition, and I/O boards. It was created to save engineers and system integrators the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. A fully-integrated system-level solution, the 8266 provides the user with a streamlined out-of-the-box experience. It comes preconfigured with Pentek hardware, drivers and software examples installed and tested to allow development engineers to run example applications out of the box. The 8266 uses a 19 4U rackmount chassis that is 21 deep. Enhanced forcedair ventilation assures adequate cooling for Pentek Cobalt and Onyx boards. The chassis is designed to draw cool air from the front and push warm air out the back. A 1000 W, 80+ Gold Power Supply guarantees more than enough power for additional boards.
Configuration
Pentek uses a variety of motherboards to provide the flexibility for operation and cooling of each system. Up to four Pentek Cobalt or Onyx boards in the 8266 can be supported. Please contact Pentek to configure a system that requires additional PCIe slots for 3rd party hardware.
ReadyFlow Software
Pentek ReadyFlow drivers and board support libraries are preinstalled and tested with the 8266. ReadyFlow includes example applications with full source code, a command line interface for custom control over hardware, and Penteks Signal Analyzer, a full-featured analysis tool that continuously displays live signals in both time and frequency domains.
Options
Options for high-end multicore CPUs and extended memory support applications that require additional horsepower. All necessary analog I/O cables are installed and tested, providing SMA connectivity for all analog I/O lines.
Features
4U 19-inch rackmount PC server chassis, 21-inch deep 64-bit Windows 7 Professional or Linux workstation Intel CoreTM i7 3.6 GHz processor 8 GB DDR3 SDRAM ReadyFlow drivers and board support libraries installed Out-of-the-box test examples All I/O cables included
Specifications
Operating System: 64-bit Windows 7 Professional or Linux Processor: Intel Core i7 processor Clock Speed: 3.6 GHz SDRAM: 8 GB Dimensions: 4U Chassis, 19" W x 21" D x 7" H Weight: 35 lb, approx. Operating Temp: 0 to +50 C Storage Temp: 40 to +85 C Relative Humidity: 5 to 95%, non-condensing Power Requirements: 100 to 240 VAC, 50 to 60 Hz, 1000 W max.
System Implementation
Built on a professional 4U rackmount workstation, the 8266 is equipped with the latest Intel processor, DDR3 SDRAM and a high-performance motherboard. These features accelerate application code development and provide unhindered access to the high-bandwidth data available with Cobalt and Onyx analog and digital interfaces. The 8266 can be configured with 64-bit Windows or Linux operating systems.
Model 8266 Description PC Development System for PCIe Cobalt and Onyx Boards 64-bit Linux OS 64-bit Windows 7 OS Upgrade to 64 GB DDR3 SDRAM
Options: -094 -095 -101
The addition of third-party PCIe cards may affect system performance. Please consult with us before doing so.
Pentek, Inc.
www.pentek.com
RAD AR & SDR I/O - 3U VPX - FORMA T 2 RADAR FORMAT

MODEL
Cobalt 52620 Cobalt 52621 Cobalt 52630 Cobalt 52640 Cobalt 52641 Cobalt 52650 Cobalt 52651 Cobalt 52660 Cobalt 52661 Cobalt 52662 Cobalt 52670 Cobalt 52671 Cobalt 52690 Onyx 52720 Onyx 52760 Onyx 52730
DESCRIPTION
3-Channel 200 MHz A/D, 2-Channel 800 MHz D/A, Virtex-6 FPGA - 3U VPX 3-Channel 200 MHz A/D with DDC, DUC, 2-Channel 800 MHz D/A, 3U VPX 1 GHz A/D and D/A, Virtex-6 FPGA - 3U VPX 1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D, Virtex-6 FPGA - 3U VPX 1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D, DDC, Virtex-6 FPGA - 3U VPX Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - 3U VPX 2-Chan 500 MHz A/D with DDC, DUC with 2-Chan 800 MHz D/A, Virtex-6 FPGA - 3U VPX 4-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - 3U VPX 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - 3U VPX 4-Channel 200 MHz A/D with 32-Channel DDC and Virtex-6 FPGA - 3U VPX 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - 3U VPX 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - 3U VPX L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - 3U VPX 3-Channel 200 MHz A/D, 2-Channel 800 MHz D/A, Virtex-7 FPGA - 3U VPX 4-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - 3U VPX 1 GHz A/D and D/A, Virtex-7 FPGA - 3U VPX Customer Information
& & & & & &
PMC/XMC CompactPCI PCI x 8 PCI Express AMC 3U VPX - FORMA T 1 FORMAT

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Model 52620
General Information
Model 52620 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture and playback features offer an ideal turnkey solution. The 52620 includes three A/Ds, one upconverter, two D/As and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. and a PCIe interface complete the factoryinstalled functions and enable the 52620 to operate as a complete turnkey solution, without the need to develop any FPGA IP.


Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Supports gigabit serial fabrics including PCI Express, Serial RapidIO and Xilinx Aurora Three 200 MHz 16-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF In
RF In
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
16
Timing Bus
VCXO

LVDS
GTX
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
40
4X
4X
4X
x4 PCIe
Memory Banks 1 & 2
Memory Banks 3 & 4
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52620
A/D Converter Stage
The front end accepts three full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an onboard programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 52620s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Memory Resources
to D/A D/A loopback

from A/D Ch 1
from A/D Ch 2
from A/D Ch 3

INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
MEMORY CONTROL
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 52620
FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O. Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols. Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz
Model 52620 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-6 FPGA 3U VPX XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 Gigabit serial FPGA I/O to VPX P1 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Options: -062 -064 -104 -105 -150
VPX Families
53xxx
-160
-155
-165
Pentek, Inc.
www.pentek.com
! ew N
Model 52621
General Information
Model 52621 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with a programmable DDC, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. The 52621 includes three A/Ds, one upconverter, two D/As and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. sition modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 52621 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Model 52621 COTS (left) and rugged version The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 52621 factory-installed functions include three A/D acquisition and a D/A waveform playback IP modules. Each of the three acquisition IP modules contains a powerful, programmable DDC IP core. The waveform playback IP module contains an intrepolation IP core, ideal for matching playback rates to the data and decimation rates of the acquiRF In

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three 200 MHz 16-bit A/Ds Three multiband DDCs (digital downconverters) One DUC (digital upconverter) Two 800 MHz 16-bit D/As Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference Optional LVPECL clock/sync bus for multiboard synchronization 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
16
Timing Bus
VCXO
VIRTEX-6 FPGA LX240T, or SX315T

LVDS

GTX
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
40
4X
4X
4X
Sum to next board

x4 PCIe
Memory Banks 1 & 2
Memory Banks 3 & 4
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52621
setting that ranges from DC to s, where s is the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as three different output bandwidths for the board. Decimations can be programmed from 2 to 65,536 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the three DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 52621s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the VPX P1 connector. This allows summation across channels on multiple boards.

Beamformer IP Core

The Model 52621 factory-installed functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users to easily play back to the dual D/As waveforms stored in either on-board memory or off-board host memory . Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 individual link entries can be chained together to create complex waveforms with a minimum of programming.
from A/D Ch 1
from A/D Ch 2
to D/A
INPUT MULTIPLEXER
DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all three DDCs or each of the three A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency
MEMORY CONTROL
MUX
DDC CORE
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
sum out sum in
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
FPGA GPIO
40
4X PCIe
Pentek, Inc.
www.pentek.com
Model 52621
A/D Converter Stage
The front end accepts three analog HF or IF inputs on front panel SSMC connectors with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other board resources. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 52621s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

A TI DAC5688 DUC (digital upconverter) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x. In addition to the DAC5688, an FPGA-based interpolator core provides additional interpolation from 2x to 65,536x. The two interpolators can be combined to crate a total range from 2x to 524,288x.
Memory Resources


Specifications
Pentek, Inc.
www.pentek.com
Model 52621
Digital Downconverters
Quantity: Three channels Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformer Summation: Three channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
VPX Families
Model 52621 Description 3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - 3U XMC XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
53xxx
Options: -062 -064 -104 -150
-160
-155
-165
Pentek, Inc.
www.pentek.com
! ew N
Model 52630

General Information


Features

RF In
RF Out
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Sync In
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12
1 GHz 16-BIT D/A 16
D/A Sync Bus
VCXO

LVDS
GTX
GTX GTX
16
16
16
16
40
4X
4X
4X

x4 PCIe
QDRII+ option 150
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52630

A/D Converter Stage

D/A Converter Stage

Memory Resources
to D/A



INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 52630

The Model 52630 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x4, the interface includes multiple DMA controllers for efficient transfers to and from the board. Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Option 150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Specifications
VPX Families
53xxx
Pentek, Inc.
www.pentek.com
! ew N
Model 52640
General Information

Model 52640 COTS (left) and rugged version The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 52640 factory-installed functions include an A/D acquisition IP module. In addition, IP modules for DDR3 memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factory-

Features

RF In
RF In
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus

12 12
Sync Bus

GTX
GTX
GTX
4X
4X
4X
Memory Banks 1 & 2
Memory Banks 3 & 4

x4 PCIe
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52640
A/D Converter Stage
Memory Resources



The 52640 accepts an 1.8 GHz dual-edge sample clock via a front panel SSMC connector. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multipin sync bus connector allows multiple boards to be
from A/D
from A/D

MEMORY CONTROLLER
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 52640
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Sample Clock Sources: Front panel SSMC connector Sync Bus: Multi-pin connectors, bus includes gate, reset and in and out reference clock External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm).
VPX Families
53xxx
Pentek, Inc.
www.pentek.com
! ew N
Model 52641
General Information
Model 52641 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A highspeed data converter with a programmable digital downconverter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. The 52641 includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. nization functions, a test signal generator and a PCIe interface complete the factoryinstalled functions and enable the 52641 to operate as a complete turnkey solution, without the need to develop any FPGA IP. For applications that require additional control and status signals, option -104 provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O.
A/D Converter Stage

The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the 52641 to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple boards. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources.

Features

Ideal radar and software radio interface solution One-channel mode with 3.6 GHz, 12-bit A/D Two-channel mode with 1.8 GHz, 12-bit A/Ds 2 GB of DDR3 SDRAM Programmable one- or twochannel DDC (Digital Downconverter) PCI Express (Gen. 1 & 2) interface, up to x4 Sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF In
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus

12 12
Sync Bus

GTX
40
4X
Memory Banks 1 & 2
Memory Banks 3 & 4
x4 PCIe
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52641
DDC IP Cores

The 52641 accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connector. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multipin sync bus connector allows multiple boards to be synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple 52641s can be synchronized using the Cobalt highspeed sync board to drive the sync bus.
Memory Resources
from A/D
from A/D

to Mem Bank 1
to Mem Bank 2
4X PCIe
FPGA GPIO
40
to Mem Bank 3
to Mem Bank 4
Pentek, Inc.
www.pentek.com
Model 52641
The Model 52641 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x4, the interface includes multiple DMA controllers for efficient transfers to and from the board. External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1or Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Digital Downconverters Modes: One or two channels, programmable Supported Sample Rate: One-channel mode: 3.6 GHz, two-channel mode: 1.8 GHz Decimation Range: One-channel mode: 8x, 16x or 32x, two-channel mode: 4x, 8x, or 16x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: User-programmable 18-bit coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation Sample Clock Sources: Front panel SSMC connector Sync Bus: Multipin connectors, bus includes gate, reset and in and out reference clock
VPX Families
53xxx
Model 52641 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, with Wideband DDC, Virtex-6 FPGA - 3U VPX
Options: -002* -064* -104 -2 FPGA speed grade XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
www.pentek.com
! ew N
Model 52650
General Information
Model 52650 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A twochannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture and playback features offer an ideal turnkey solution. The 52650 includes two A/Ds, one DUC (digital upconverter), two D/As and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. the factory-installed functions and enable the 52650 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 52650 factory-installed functions include two A/D acquisition and one D/A waveform playback IP modules. In addition, IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Supports gigabit serial fabrics including PCI Express, Serial RapidIO and Xilinx Aurora Two 500 MHz 12-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF In
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
500 MHz 12-BIT A/D
500 MHz 12-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
VCXO

LVDS
Timing Bus
GTX
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
40
4X
4X
4X
x4 PCIe
Memory Banks 1 & 2
Memory Banks 3 & 4
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52650
A/D Converter Stage


Memory Resources

from A/D Ch 1
to D/A
INPUT MULTIPLEXER

MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
MEMORY CONTROL
to Mem Bank 3
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 52650
FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (option 014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz, max. Output IF: DC to 400 MHz, max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz, max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock
Model 52650 Description Two 500 MHz A/Ds, one DUC, Two 800 MHz D/As with Virtex-6 FPGA - 3U VPX
Options: -002* -014 -062 -064 -104 -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 -105 Gigabit serial FPGA I/O to VPX P1 -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -160 Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required
External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
VPX Families
53xxx
Pentek, Inc.
www.pentek.com
! ew N
Model 52651
General Information
Model 52651 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A twochannel, high-speed data converter with a programmable DDC, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. The 52651 includes two A/Ds, two D/As and four banks of memory. It features builtin support for PCI Express over the 3U VPX backplane. or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 52651 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Model 52651 COTS (left) and rugged version The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 52651 factory installed functions include two A/D acquisition and a D/A waveform playback IP modules. Each of the two acquisition IP modules contains a powerful, programmable DDC IP core. The waveform playback IP module contains an intrepolation IP core, ideal for matching playback rates to the data and decimation rates of the acquisition modules. IP modules for either DDR3
RF In

RF In RF Out RF Out
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two 500 MHz 12-bit A/Ds Two multiband DDCs (digital downconverters) Two 800 MHz 16-bit D/As One DUC (digital upconverter) Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 16 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
500 MHz 12-BIT A/D
500 MHz 12-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
VCXO

LVDS
Timing Bus
GTX

GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
40
4X
4X
4X
QDRII+ option 160

x4 PCIe
Sum to next board
Memory Banks 1 & 2
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52651
frequency. Each DDC can have its own unique decimation setting, supporting as many as two different output bandwidths for the board. Decimations can be programmed from 2 to 131,072 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 16-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the two DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 52651s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the VPX P1 connector. This allows summation across channels on multiple boards.
Beamformer IP Core

from A/D Ch 1

INPUT MULTIPLEXER
to D/A

DDC IP Cores
MUX
DDC CORE
to Mem Bank 1
to Mem Bank 2
to Mem Bank 4
sum out sum in
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
4X PCIe
Pentek, Inc.
www.pentek.com
Model 52651
A/D Converter Stage
The front end accepts two analog HF or IF inputs on front panel SSMC connectors with transformer coupling into two Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 52651s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Memory Resources


Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits
Pentek, Inc.
www.pentek.com
Model 52651
A/D Converters (option -014)
Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits Digital Downconverters Quantity: Two channels Decimation Range: 2x to 131,072x in two programmable stages of 2x to 256x and one fixed 2x stage LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 16-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformer Summation: Two channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link over the VPX P1connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T-2 Optional: Xilinx Virtex-6 XC6VSX315T-T2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Memory Option -150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option -155 or -165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Model 52651 Description 2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - 3U VPX
VPX Families
Options: -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240 FPGA XC6VSX315 FPGA LVDS FPGA I/O through the VPX P2 connector -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required -002* -014 -062 -064 -104
53xxx
Pentek, Inc.
www.pentek.com
! ew N
Model 52660

General Information


Features

RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

LVDS GTX
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
4X 4X 4X
x4 PCIe
Memory Banks 1 & 2
Memory Banks 3 & 4
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52660

A/D Converter Stage
Memory Resources



from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
4X
Gigabit Serial I/O
4X 4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 52660

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector LVPECL bus includes, clock/sync/ gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
VPX Families
53xxx
Options: -062 -064 -104 -105 -150
-160
-155
-165
Pentek, Inc.
www.pentek.com
! ew N
Model 52661
General Information
Model 52661 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with a programmable DDC, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. The 52661 includes four A/Ds and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. nization functions, a test signal generator, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 52661 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 52661 factory-installed functions include four A/D acquisition IP modules. Each of the four acquisition IP modules contains a powerful, programmable DDC (digital downconverter) IP core. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchro-

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Four multiband DDCs (digital downconverters) Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

LVDS

GTX
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
4X 4X 4X
Sum to next board

x4 PCIe
Memory Banks 1 & 2
Memory Banks 3 & 4
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52661
providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 52661s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the VPX P1 connector. This allows summation across channels on multiple boards.
A/D Converter Stage

Beamformer IP Core

from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
DDC IP Cores
INPUT MULTIPLEXER
DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536

MUX
DDC CORE
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
sum out sum in
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
FPGA GPIO
40
4X PCIe
Pentek, Inc.
www.pentek.com
Model 52661
the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 52661s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O. Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

Memory Resources
The 52661 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Four channels Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation Beamformer Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus
Model 52661 Description 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - 3U VPX XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Options: -062 -064 -104 -150
VPX Families
-160
53xxx
-155
-165
Pentek, Inc.
www.pentek.com
! ew N
Model 52662
General Information
Model 52662 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. This fourchannel, high-speed data converter with programmable DDCs (digital downconverters) is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture feature offers an ideal turnkey solution. The 52662 includes four A/Ds and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. SDRAM memory controllers, and a PCIe interface complete the factory-installed functions and enable the 52662 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, and triggering. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 52662 factory-installed functions include four A/D acquisition IP modules. Each of the four acquisition IP modules contains a powerful, programmable 8-channel DDC IP core. IP modules for control of all data clocking, synchronization, gate and trigger functions, a test signal generator, voltage and temperature monitoring, DDR3

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Four multiband DDCs Up to 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

LVDS GTX
GTX
GTX
4X 4X 4X
x4 PCIe
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52662

A/D Converter Stage

from A/D Ch 1
Memory Resources
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
DDC IP Cores
INPUT MULTIPLEXER

.

.

.

.
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
32 Memory Bank 1
32 Memory Bank 2
32 Memory Bank 3
32 Memory Bank 4
4X PCIe
Gigabit Serial I/O
4X 4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 52662
512 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory and capture space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock, or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

The Model 52662 includes an industry standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x4, the interface includes multiple DMA controllers for efficient transfers to and from the module.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Four 8-channel banks, one per acquisition module Decimation Range: 16x to 8192x in steps of 8x LO Tuning Freq. Resolution: 32 bits, 0 to s Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user-programmable coefficients Default Filter Set: 80% bandwidth, >100 dB stopband attenuation Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock
VPX Families
Model 52662 Description 4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - 3U VPX XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through VPX P2 Gigabit serial FPGA I/O through VPX P1 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Options: -062 -064 -104 -105 -155
53xxx
-165
Pentek, Inc.
www.pentek.com
! ew N
Model 52670

General Information

RF Out

Features

RF Out
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO

LVDS
GTX
GTX
GTX
40
4X
4X
4X
Memory Banks 1 & 2
Memory Banks 3 & 4
x4 PCIe
VPX-P2
VPX-P1
Pentek, Inc.
www.pentek.com
Model 52670

Memory Resources



16
to D/A Ch 1 & 2
16
to D/A Ch 3 & 4
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 52670

Specifications
D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connector Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin Sync bus connector includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
VPX Families
53xxx
Pentek, Inc.
www.pentek.com
! ew N
Model 52671
General Information
Model 52671 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. This 4-channel, high-speed data converter is suitable for connection to transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As with a wide range of programmable interpolation factors, four digital upconverters and four banks of memory. In addition to supporting PCI Express Gen. 2 over the 3U VPX backplane, the Model 52671 includes optional generalpurpose and gigabit serial connectors for application-specific I/O . data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 52671 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 52671 factory-installed functions include four D/A waveform playback IP modules, to support waveform generation through the D/A converters. IP modules for DDR3 SDRAM memories, a controller for all
RF Out

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 1.25 GHz 16-bit D/As Four digital upconverters Programmable output levels Extended interpolation range from 2x to 1,048,576x 250 MHz max. output bandwidth 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multiboard synchronization Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO

LVDS
GTX
GTX
GTX
40
4X
4X
4X
Memory Banks 1 & 2
Memory Banks 3 & 4

x4 PCIe
VPX-P2
VPX-P1
Pentek, Inc.
www.pentek.com
Model 52671
Two Texas Instruments DAC3484s provide four DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals to a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs to a 16-bit D/A converter. If translation is disabled, each D/A acts as an interpolating 16-bit D/A with output sampling rates up to 1.25 GHz. In both modes, the D/A provides interpolation factors of 2x, 4x, 8x and 16x. In addition to the DAC3484, the 52671 features an FPGA-based interpolation engine which adds two additonal interpolation stages programmable from 2x to 256x. The combined interpolation results in a range from 2x to 1,048,576x for each D/A channel and is ideal for matching the digital downconversion and data reduction used on the receiving channels of many communications systems. Analog output is through four front panel SSMC connectors. on-board clock generator receives a sample clock either from the front panel SSMC connector or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this latter mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock to phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided by 2, 4, 8, or 16 to provide lower frequency D/A clocks. A pair of front panel Sync connectors allows multiple boards to be synchronized. They accept CML inputs that drive the boards sync and trigger/gate signals. The Pentek Models 5292 or 9192 Cobalt Synchronizers can drive multiple 52671 Sync connectors enabling large, multichannel synchronous configurations.
Memory Resources

An internal timing bus provides all required D/A clocking. The bus includes a clock, sync and a gate or trigger signal. An

The Model 52671 factoryinstalled functions include a sophisticated D/A Waveform Playback IP module. Four linked-list controllers support waveform generation to the four D/As from tables stored in either on-board memory or offboard host memory. Data for Channel 1 and Channel 2 are interleaved for delivery to a dual channel D/A device. For this reason, they must share a common trigger/ gate, sample rate, interpolation factor, and other parameters. The same rules apply to Channel 3 and Channel 4. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up to 64 individual link entries for each D/A channel can be chained together to create complex waveforms with a minimum of programming.
16
to D/A Ch 1 & 2
16
to D/A Ch 3 & 4
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4

PCIe INTERFACE
4X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 52671
The Model 52671 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x4 lane interface includes multiple DMA controllers for efficient transfers to and from the board. External Trigger Input Type: Front panel female SSMC connector Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin Sync bus connector includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Array: Standard: Xilinx Virtex-6 XC6VLX240T-2 Optional: Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Specifications
D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference
VPX Families
Model 52671 Description 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - 3U VPX
53xxx
Pentek, Inc.
www.pentek.com
! ew N
Model 52690

General Information


Features

Ref In
RF In
MAX2112
Ref Out GC
12-BIT D/A
Ref A/D Clock/Sync
Control
16
16
IC
2
Timing Bus
VCXO

LVDS GTX
GTX
GTX
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
4X 4X 4X

x4 PCIe
Memory Banks 1 & 2
Memory Banks 3 & 4
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52690

RF Tuner Stage


A/D Converter Stage

Memory Resources
from A/D (I)
from A/D (Q)
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
4X
Gigabit Serial I/O
4X 4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 52690

8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. The factory-installed A/D Acquisition Modules use memory banks 1 & 2. Banks 3 & 4 can be optionally installed to support custom user-installed IP within the FPGA . 50 ohms, accepts 10 to 200 MHz (up to 800 MHz when Timing Generator divider is enabled) or PLL system reference Timing Generator Bus: 26-pin front panel connector LVPECL bus includes, clock/ sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Input Quantity: 2 Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

Specifications
Front Panel Analog Signal Input Connector: Front panel female SSMC Impedance: 50 ohms L-Band Tuner Type: Maxim MAX2112 Input Frequency Range: 925 MHz to 2175 MHz Monolithic VCO Phase Noise: -97 dBc/Hz at 10 kHz Fractional-N PLL Synthesizer: freqVCO = (N.F) x freqREF where integer N = 19 to 251 and fractional F is a 20-bit binary value PLL Reference (freqREF): Front panel SSMC connector or on-board 27 MHz crystal (Option -100), 12 to 30 MHz LNA Gain: 0 to 65 dB, controlled by a programmable 12-bit D/A converter* Baseband Amplifier Gain: 0 to 15 dB, in 1 dB steps* *Usable Full-Scale Input Range: 50 dBm to +10 dBm Baseband Low Pass Filter: Cutoff frequency programmable from 4 to 40 MHz with 8-bit resolution A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board timing generator/synthesizer A/D Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, for the A/D clock Timing Generator External Clock Input Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled,
Options: -062 -064 -104 -105 -150
VPX Families
-160
53xxx
-155
-165
Pentek, Inc.
www.pentek.com
! ew N
Model 52720
General Information
Model 52720 is a member of the Onyx family of high-performance 3U VPX boards based on the Xilinx Virtex-7 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture and playback features offer an ideal turnkey solution. The 52720 includes three A/Ds, one upconverter, two D/As and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable the 52720 to operate as a complete turnkey solution without the need to develop any FPGA IP.


Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Three 200 MHz 16-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1 and 2) interface up to x4 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-7 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
800 MHz 16-BIT D/A
D/A Clock/Sync Bus
16
16
16
Timing Bus
VCXO

LVDS
GTX
GTX
GTX
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
FPGA Config Bus
PCIe Gen. 2 x4
4X
4X
PCIe Gen. 2 x4
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52720
A/D Converter Stage


A TI DAC5688 DUC (digital upconverter) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband
to D/A D/A loopback
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3

INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
MEMORY CONTROL
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 52720
input signals to any IF center frequency
up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x. front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O. Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols. Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Memory Resources

Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an onboard programmable VCXO. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the VCXO.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz),
VPX Families
Model 52720 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-7 FPGA 3U VPX XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O to VPX P2 Gigabit serial FPGA I/O to VPX P1
53xxx
Options: -073 -076 -104 -105
Pentek, Inc.
www.pentek.com
! ew N
Model 52760

General Information


Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Four 200 MHz 16-bit A/Ds 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-7 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D 16
200 MHz 16-BIT A/D 16
200 MHz 16-BIT A/D 16
200 MHz 16-BIT A/D 16

VCXO
LVDS
Timing Bus
GTX
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
FPGA Config Bus
PCIe Gen. 2 x4
4X
4X
PCIe Gen. 2 x4
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52760

A/D Converter Stage



from A/D Ch 1
from A/D Ch 2
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
4X
Gigabit Serial I/O
4X 4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 52760

used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 52760s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

Memory Resources
Specifications
VPX Families
53xxx
Options: -073 -076 -104 -105
Pentek, Inc.
www.pentek.com
! ew N
Model 52730

General Information

Model 52730 COTS (left) and rugged version Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 FPGAs from Xilinx. As the central feature of the board architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 52730 factory-installed functions include an A/D acquisition and a D/A waveform playback IP module for simplifying data capture and data transfer.

RF In RF Out
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe One 1 GHz 12-bit A/D One 1 GHz 16-bit D/A 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multiboard synchronization PCI Express (Gen. 1 and 2) interface up to x4 Optional LVDS connections to the Virtex-7 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Sync In
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12
1 GHz 16-BIT D/A 16
D/A Sync Bus
VCXO

LVDS
GTX
GTX
GTX
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
FPGA Config Bus
PCIe Gen. 2 x4
4X
4X
PCIe Gen. 2 x4
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52730


A/D Converter Stage

D/A Converter Stage


to D/A

INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 52730

Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives a sample clock either from the front panel SSMC connector or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this latter mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock to phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or 16 to provide different lower frequency A/D and D/A clocks. A pair of front panel Sync connectors allows multiple modules to be synchronized. They accept CML inputs that drive the boards sync and gate/trigger signals. The Pentek Model 5292 and Model 9192 Cobalt Synchronizers can drive multiple 52730 Sync connectors enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connector. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Memory Resources
The 52730 architecture supports four independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factoryinstalled functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

Specifications
VPX Families
53xxx
Pentek, Inc.
www.pentek.com
ANALOG & DIGIT AL I/O DIGITAL

MODEL
7150 7250, 7350 7650 7850 5350 Cobalt 71630 Cobalt 78630 Cobalt 53630 Cobalt 52630 Cobalt 72630, 73630, 74630 Cobalt 56630 Cobalt 71640 Cobalt 78640 Cobalt 53640 Cobalt 52640 Cobalt 72640, 73640, 74640 Cobalt 56640 Cobalt 71660 Cobalt 78660 Cobalt 53660 Cobalt 52660 Cobalt 72660, 73660, 74660 Cobalt 56660 Cobalt 71670 Cobalt 78670 Cobalt 53670 Cobalt 52670 Cobalt 72670, 73670, 74670 Cobalt 56670 Cobalt 71690 Cobalt 78690 Cobalt 53690 Cobalt 52690 Cobalt 72690, 73690, 74690 Cobalt 56690
DESCRIPTION
Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - PMC/XMC Quad or Octal 200 MHz, 16-bit A/D with Virtex-5 FPGAs - 6U/3U cPCI Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - PCI Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - x8 PCIe Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - 3U VPX 1 GHz A/D and D/A, Virtex-6 FPGA - XMC 1 GHz A/D and D/A, Virtex-6 FPGA - x8 PCIe 1 GHz A/D and D/A, Virtex-6 FPGA - 3U VPX - Format 1 1 GHz A/D and D/A, Virtex-6 FPGA - 3U VPX - Format 2 1-/2-Ch 1 GHz A/D and 1-/2-Ch 1 GHz D/A, Virtex-6 FPGA - 6U/3U cPCI 1 GHz A/D and D/A, Virtex-6 FPGA - AMC 1-Ch 3.6 GHz or 2-Ch 1.8 GHz 12-bit A/D, Virtex-6 FPGA - XMC 1-Ch 3.6 GHz or 2-Ch 1.8 GHz 12-bit A/D, Virtex-6 FPGA - x8 PCIe 1-Ch 3.6 GHz or 2-Ch 1.8 GHz 12-bit A/D, Virtex-6 FPGA - 3U VPX - Format 1 1-Ch 3.6 GHz or 2-Ch 1.8 GHz 12-bit A/D, Virtex-6 FPGA - 3U VPX - Format 2 1-/2-Ch 3.6 GHz or 2-/4-Ch 1.8 GHz 12-bit A/D, Virtex-6 FPGA - 6U/3U cPCI 1-Ch 3.6 GHz or 2-Ch 1.8 GHz 12-bit A/D, Virtex-6 FPGA - AMC 4-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - XMC 4-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - x8 PCIe 4-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - 3U VPX - Format 1 4-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - 3U VPX - Format 2 4-/8-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - 6U/3U cPCI 4-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - AMC 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - XMC 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - x8 PCIe 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - 3U VPX - Format 1 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - 3U VPX - Format 2 4-/8-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - 6U/3U cPCI 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - AMC L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - XMC L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - x8 PCIe L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - 3U VPX - Format 1 L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - 3U VPX - Format 2 1-/2-Ch L-Band RF Tuner, 2-/4-Ch 200 MHz A/D, Virtex-6 FPGA - 6U/3U cPCI L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - AMC More on next page

www.pentek.com
ANALOG & DIGIT AL I/O DIGITAL

MODEL
Onyx 71760 Onyx 78760 Onyx 53760 Onyx 52760 Onyx 72760, 73760, 74760 Onyx 56760Onyx 56760 Onyx 71730 Onyx 78730 Onyx 53730 Onyx 52730 Onyx 72730, 73730, 74730 Onyx 56730 6821, 6822 6826 Cobalt 71610 Cobalt 78610 Cobalt 53610 Cobalt 52610 Cobalt 72610, 73610, 74610 Cobalt 56610 Cobalt 7811 Cobalt 71611 Cobalt 78611 Cobalt 53611 Cobalt 52611 Cobalt 72611, 73611, 74611 Cobalt 56611 7120 7820 5220 7220, 7320, 7420 5620 8111 8266
DESCRIPTION
4-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - XMC 4-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - x8 PCIe 4-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - 3U VPX - Format 1 4-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - 3U VPX - Format 2 4-/8-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - 6U/3U cPCI 4-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - AMC 1 GHz A/D and D/A, Virtex-7 FPGA - XMC 1 GHz A/D and D/A, Virtex-7 FPGA - x8 PCIe 1 GHz A/D and D/A, Virtex-7 FPGA - 3U VPX - Format 1 1 GHz A/D and D/A, Virtex-7 FPGA - 3U VPX - Format 2 1-/2-Ch 1 GHz A/D and 1-/2-Ch 1 GHz D/A, Virtex-7 FPGAs - 6U/3U cPCI 1 GHz A/D and D/A, Virtex-7 FPGA - AMC Single or Dual 215 MHz, 12-bit A/Ds with Virtex-II Pro FPGAs - VME/VXS Dual 2 GHz, 10-bit A/D with Virtex-II Pro FPGA - VME/VXS LVDS Digital I/O with Virtex-6 FPGA - XMC LVDS Digital I/O with Virtex-6 FPGA - x8 PCIe LVDS Digital I/O with Virtex-6 FPGA - 3U VPX - Format 1 LVDS Digital I/O with Virtex-6 FPGA - 3U VPX - Format 2 Single or Dual LVDS Digital I/O with Virtex-6 FPGAs - 6U/3U cPCI LVDS Digital I/O with Virtex-6 FPGA - AMC Quad Serial FPDP Interface with Virtex-6 FPGA - x8 PCIe Quad Serial FPDP Interface with Virtex-6 FPGA - XMC Quad Serial FPDP Interface with Virtex-6 FPGA - x8 PCIe Quad Serial FPDP Interface with Virtex-6 FPGA - 3U VPX - Format 1 Quad Serial FPDP Interface with Virtex-6 FPGA - 3U VPX - Format 2 Quad or Octal Serial FPDP Interface with Virtex-6 FPGAs - 6U/3U cPCI Quad Serial FPDP Interface with Virtex-6 FPGA - AMC Bandit Two-Channel Analog RF Receiver - PMC/XMC Bandit Two-Channel Analog RF Receiver - PCIe Bandit Two-Channel Analog RF Receiver - 3U VPX Bandit Two/Four-Channel Analog RF Receiver - 6U/3U cPCI Bandit Two-Channel Analog RF Receiver - AMC Bandit Modular Analog RF Slot Downconverter Series
Model 7150

General Information
Model 7150 is a quad, high-speed data converter suitable for connection as the HF or IF input of a communications system. It features four 200 MHz, 16-bit A/Ds supported by an array of data processing and transport resources ideally matched to the requirements of high-performance systems. Model 7150 uses the popular PMC format and supports the emerging VITA 42 XMC standard for switched-fabric interfaces. DDR2 SDRAM memory, interface FPGA, programmable LVPECL I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T and FX100T. The SXT parts feature between 288 and 640 DSP48E Slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the Model 7150 can be optionally configured with an LX155T in the processing FPGA position for 155,648 logic cells. A second Virtex-5 FPGA provides board interfaces including PCI-X or PCI Express. Implementing the PCI interfaces in this second FPGA, keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT or an SXT family part, providing not only interface functionality, but processing resources up to an additional 640 DSP48E Slices. Option -104 installs the P4 PMC connector with 16 pairs of LVDS connections to the processing FPGA and 16 pairs of LVDS connections to the interface FPGA for custom I/O.
A/D Converter Stage

Virtex-5 FPGAs
The Model 7150 architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factoryshipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the A/D converters,
Features

Complete software radio interface solution VITA 42.0 XMC compatible with switched fabric interfaces Four 200 MHz 16-bit A/Ds Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Up to 2.56 seconds of data capture at 200 MHz LVPECL clock/sync bus for multimodule synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O

The Model 7150 architecture includes a flexible timing and synchronization circuit that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus.
RF In
RF XFORMR Sample Clk In PPS In TIMING BUS GENERATOR Clo k / Syn / Gate / PPS
RF In
RF XFORMR
RF In
RF XFORMR
RF In
RF XFORMR
Clo k/Syn Bus
TTL In
200 MH 16 bit A/D
200 MH 16 b t A/D
200 MH 16 bit A/D
200 MH 16 bit A/D
LVPECL Bus
XTL OSC To All Se tions Control/ PROCESSING FPGA VIRTEX 5 LX50T, SX50T, SX 5T, LX155T or FX100T
LVDS GTP GTP GTP
Timing Bus
Status
8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T

LVDS PCI X GTP
4X
GTP
4X
4X
PMC P4 FPGA I/O Option 104
32
32
PCI X BUS 64 Bits, 100 MH
64
4X
P15 XMC VITA 42 x Option 5xx
Pentek, Inc.
www.pentek.com
Model 7150

The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to three slave 7150s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. More modules can be synchronized with an external clock and sync generator.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VLX155T and XC5VFX100T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs P4 connector with 16 LVDS pairs to the processing FPGA and 16 pairs to the interface FPGA Memory DDR2 SDRAM: Up to 1 GB in two banks PCI Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard PMC module, 2.91 in. x 5.87 in.
XMC Interface
The Model 7150 complies with the VITA 42.0 XMC specification for carrier boards. This emerging standard provides serial data links with up to 3.125 GHz bit clock between the XMC module and the carrier board. With two 4X links, the 7150 achieves up to 2.5 GB/sec streaming data transfer rate independent of the PCI interface and supports switched fabric protocols such as Serial RapidIO and PCI Express.
Memory Resources
PCI-X Interface
The Model 7150 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the module. Data widths of 32 or 64 bits and data rates of 33, 66, 100 MHz are supported.

Model 7150 Description Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs PMC/XMC
Pentek, Inc.
www.pentek.com
Models 7250, 7250D and 7350
General Information
Models 7250 and 7350 are cPCI Quad 200 MHz A/Ds. They consist of one Model 7150 Quad A/D mounted on a cPCI carrier. The Model 7250 is a 6U cPCI board, while the Model 7350 is a 3U cPCI board. Model 7250D is the same as the Model 7250, except it contains two 7150s rather than one. different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T and FX100T. The SXT parts feature between 288 and 640 DSP48E Slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the Models 7250 and 7350 can be optionally configured with an LX155T in the processing FPGA position for 155,648 logic cells. A second Virtex-5 FPGA provides board interfaces including PCI-X or PCI Express. Implementing the PCI interfaces in this second FPGA, keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT or an SXT family part, providing not only interface functionality, but processing resources up to an additional 640 DSP48E Slices. Option -104 installs the J3 connector (Model 7250) or the J2 connector (Model 7350) with 16 pairs of LVDS connections to the processing FPGA and 16 pairs of LVDS connections to the interface FPGA for custom I/O. With Model 7250D, the option provides an additional 16 pairs of LVDS connections through the J5 connector to the processing FPGA and 16 pairs of LVDS connections to the interface FPGA.
A/D Converter Stage

Virtex-5 FPGAs
The architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory-shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the A/D converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of
Model 7350
Model 7250D

RF In
RF XFORMR
Features

Complete software radio interface solutions Four or eight 200 MHz, 16-bit A/Ds Up to 1 or 2 GB of DDR2 SDRAM Two or four Xilinx Virtex-5 FPGAs Up to 2.56 seconds of data capture at 200 MHz LVPECL clock/sync bus for multiboard synchronization 32 or 64 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR
RF In
RF XFORMR
RF In
RF XFORMR
Sample Clk In PPS In TIMING BUS GENERATOR Clo k / Syn / Gate / PPS 200 or 135 MH 16 BIT A/D 200 or 135 MH 16 BIT A/D 200 or 135 MH 16 BIT A/D 200 or 135 MH 16 BIT A/D
TTL In
Clo k/Syn Bus
LVPECL Bus
XTL OSC
To All Se tions
Timing Bus
Control/ Status
PROCESSING FPGA VIRTEX 5 LX50T, SX50T, SX 5T or LX155T LVDS 8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T LVDS 32 4X LVDS
PCI X INTERFACE
64
32
PCI-X BUS
PCI BUS
PCI-TO-PCI BRIDGE
Pentek, Inc.
www.pentek.com
Models 7250, 7250D and 7350
The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to two slave 7250Ds and three slave 7350s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.
Specifications
Model 7250 or Model 7350: 4 A/Ds Model 7250D: 8 A/Ds Model 7250D shown in the Specifications Front Panel Analog Signal Inputs (8) Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources (4): Selectable from onboard crystal oscillators, external or LVPECL clocks External Clocks (4) Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/PPS input TTL signal Field Programmable Gate Array (4) Processing FPGA: Two Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VLX155T and XCV5FX100T Interface FPGA: Two Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs the J3 and J5 cPCI connectors with 32 pairs of LVDS connections to the processing FPGA and 32 pairs of LVDS connections to the interface FPGA for custom I/O Memory DDR2 SDRAM: Up to 2 GB in four banks PCI Interface PCI Bus: 32- or 64-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U cPCI board
Memory Resources
PCI Interface
Both Models include an industry-standard interface fully compliant with PCI bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33, and 66 MHz are supported.
Model 7250 Description Quad 200 MHz, 16-bit A/D with two Virtex-5 FPGAs 6U cPCI Octal 200 MHz, 16-bit A/D with four Virtex-5 FPGAs 6U cPCI Quad 200 MHz, 16-bit A/D with two Virtex-5 FPGAs 3U cPCI FPGA I/O through cPCI J3 for 7250 or J2 for 7350; cPCI J3 and J5 for 7250D

For systems that require a PCI Express board interface, these Models can be optionally factory-configured with x4 PCI Express in the interface FPGA. Other serial protocols as well as different bus widths can be accommodated with custom IP cores.
7250D
7350
Options: -104
Pentek, Inc.
www.pentek.com
Model 7650

General Information
Model 7650 is a half-length PCI Quad 200 MHz A/D. It consists of one Model 7150 Quad A/D mounted on a PCI carrier board. The Model 7650 attaches directly to computer motherboards with PCI bus slots. Front panel connectors are brought out on the rear panel. programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T and FX100T. The SXT parts feature between 288 and 640 DSP48E Slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the Model 7650 can be optionally configured with an LX155T in the processing FPGA position for 155,648 logic cells. A second Virtex-5 FPGA provides board interfaces including PCI-X or PCI Express. Implementing the PCI interfaces in this second FPGA, keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT or an SXT family part, providing not only interface functionality, but additional processing resources up to an additional 640 DSP48E Slices. Option -104 installs a 64-pin DIN connector with 16 pairs of LVDS connections to the processing FPGA and 16 pairs of LVDS connections to the interface FPGA for custom I/O.
A/D Converter Stage

Virtex-5 FPGAs
The architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory-shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the A/D converters, DDR2 SDRAM memory, interface FPGA,

Features

Complete software radio interface solution Four or 200 MHz, 16-bit A/Ds Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Up to 2.56 seconds of data capture at 200 MHz LVPECL clock/sync bus for multiboard synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR Sample Clk In PPS In TIMING BUS GENERATOR Clo k / Syn / Gate / PPS 200 or 135 MH 16 BIT A/D
RF In
RF XFORMR
RF In
RF XFORMR
RF In
RF XFORMR
TTL In
Clo k/Syn Bus
200 or 135 MH 16 BIT A/D
200 or 135 MH 16 BIT A/D
200 or 135 MH 16 BIT A/D
LVPECL Bus
XTL OSC
To A l Se tions
Timing Bus
Control/ Status
PROCESSING FPGA VIRTEX 5 LX50T, SX50T, SX 5T or LX155T LVDS 8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T LVDS 32 4X LVDS
PCI X INTERFACE
64
LVDS 32 32
32
PCI-X BUS
64-pin DIN FPGA I/O (Option -104) PCI-X BUS
PCI-TO-PCI BRIDGE
Pentek, Inc.
www.pentek.com
Model 7650

The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to three slave 7650s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VLX155T and XC5VFX100T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs a 64-pin DIN connector with 16 pairs of LVDS connections to the processing FPGA and 16 pairs to the interface FPGA for custom I/O Memory DDR2 SDRAM: Up to 1 GB in two banks PCI Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard half-length PCI card
Memory Resources
PCI-X Interface

Model 7650 Description Quad 200 MHz, 16-bit A/D with two Virtex-5 FPGAs PCI FPGA I/O through a 64-pin DIN connector
Options: -104
Pentek, Inc.
www.pentek.com
Model 7850

General Information
Model 7850 is a high-speed data converter suitable for connection as the HF or IF input of a communications system. It features four 200 MHz, 16-bit A/Ds. These are supported by an array of data processing and transport resources ideally matched to requirements of high-performance systems. The 7850 attaches to motherboards with half-length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems. cessing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the A/D converters, DDR2 SDRAM memory, interface FPGA, programmable LVPECL I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T and FX100T. The SXT parts feature between 288 and 640 DSP48E Slices and are ideal for demodulation/modulation, decoding/ encoding, decryption/encryption, digital delay and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the Model 7150 can be optionally configured with an LX155T in the processing FPGA position for 155,648 logic cells. The interface FPGA provides board connections including PCI-X or PCI Express. Implementing the PCI interfaces in this FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT or an SXT family part, providing not only interface functionality, but processing resources up to an additional 640 DSP48E Slices. Option -104 installs a GPIO connector with 16 pairs of LVDS connections to the processing FPGA, and 16 pairs of LVDS connections to the interface FPGA for custom I/O.
RF In
RF XFORMR Sample Clk In PPS In TIMING BUS GENERATOR Clo k / Syn / Gate / PPS To All Se tions
A/D Converter Stage

The front end accepts four full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-5 FPGA for signal processing or for routing to other module resources.
Virtex-5 FPGAs
The Model 7850 architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory- shipped functions. There are two FPGA types on the 7850: processing and interface. The pro-
Features

Complete software radio interface solution PCI Express 2.0 (Gen. 2) Interface up to x8 wide Built-in fan for added cooling Four 200 MHz 16-bit A/Ds Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Up to 2.56 seconds of data capture at 200 MHz LVPECL clock/sync bus for multimodule synchronization Up to 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR
RF In
RF XFORMR
RF In
RF XFORMR
Clo k/Syn Bus
TTL In
200 MH 16 bit A/D
200 MH 16 bit A/D
200 MH 16 bit A D
200 MH 16 bit A/D
LVPECL Bus
XTL OSC
Control/ Status
PROCESSING FPGA VIRTEX 5 LX50T, SX50T, SX 5T, LX155T or FX100T

GTP GTP GTP LVDS
Timing Bus
8
4X 4X
4X
GTP
64
FLASH 32 MB

GTP PCI X LVDS
4X
64
32
PCI X BUS 1 64 Bits, 100 MH
32
4X Gbit Serial
4X Gbit Ser al 4X 4X
PCI TO PCIe BRIDGE
GPIO 1 (68-Pin)
x4 PCIe
x8 PCI Express
SER I/O A SER I/O B
Pentek, Inc.
www.pentek.com
Model 7850

The Model 7850 architecture includes a flexible timing and synchronization circuit for each bank of four A/D converters, allowing the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. Each timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/ Sync connector allows multiple boards to be synchronized. In the slave mode, each accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to three slave 7850s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VLX155T and XC5VFX100T Interface FPGA: Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Provides GPIO with 16 LVDS pairs to the processing FPGA and 16 pairs to the interface FPGA Memory DDR2 SDRAM: Up to 1 GB in two banks PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x8 width PCIe Ports: two x4 ports to processing FPGA; one can be alternately routed to interface FPGA one x4 port to PCI bus one x8 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe , 4.38 in. x 6.6 in.
Memory Resources

The 7850 includes a multiple port, 48-lane Gen. 2 PCI Express (PCIe) switch with integrated SerDes. The switch provides x8 wide connection to the PCIe interface, allowing high-speed data transfers to and from the motherboard. Switch ports each include buffer memory to minimize bottlenecks, with two x4 PCIe connections provided to the processing FPGA, as well as one x4 connection to the 64-bit PCI-X interface. Option -5xx adds two full duplex 4X gigabit serial paths on high-speed connectors, supporting PCIe or other gigabit protocols.
Model 7850 Description Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs Half-length x8 PCIe
Options: -104 FPGA I/O through the GPIO connector(s) -5xx Gigabit Serial I/O - two full duplex 4X paths
Pentek, Inc.
www.pentek.com
ew
Model 5350

General Information
Model 5350 is a high-speed data converter suitable for connection as the HF or IF input of a communications system. It features four 200 MHz, 16-bit A/Ds. These are supported by an array of data processing and transport resources ideally matched to requirements of high-performance systems. The 5350 features built-in support for PCI Express (PCIe) Gen. 2 over the 3U VPX backplane. A unique fabric-transparent crossbar switch configuration adds gigabit serial data paths for Xilinx Aurora or Serial RapidIO applications. There are two FPGA types on the 5350: processing and interface. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the onboard resources including the A/D converters, DDR2 SDRAM memory, interface FPGA, programmable LVPECL I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T and FX100T. The SXT parts feature between 288 and 640 DSP48E Slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the Model 5350 can be optionally configured with an LX155T in the processing FPGA position for 155,648 logic cells. The interface FPGA provides board connections including PCI-X or PCI Express, preserving the processing FPGA resources for signal processing. The interface FPGA can be configured as an LXT or an SXT family part, providing not only interface functionality, but processing resources up to an additional 640 DSP48E Slices. Option -104 provides general purpose I/O to VPX-P2 with 16 pairs of LVDS connections to the processing FPGA, and 16 pairs of LVDS connections to the interface FPGA for custom I/O.
RF In
RF XFORMR TIMING BUS GENERATOR Clo k / Syn / Gate / PPS To A l Se tions
A/D Converter Stage

Model 5350 commercial (left) and conduction-cooled version The front end accepts four full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-5 FPGA for signal processing or for routing to other board resources.
Virtex-5 FPGAs Features
Complete software radio interface solution for 3U VPX systems Supports Gigabit Serial Fabrics including PCI Express, Serial RapidIO and Xilinx Aurora Four 200 MHz 16-bit A/Ds Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Up to 2.56 seconds of data capture at 200 MHz LVPECL clock/sync bus for multiboard synchronization Up to 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46 (VPX Baseline Standard) VITA-48 (VPX REDI) VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
The Model 5350 architecture includes two Virtex-5 FPGAs. All data and control paths are accessible by the FPGAs, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP.
RF In
RF XFORMR
RF In
RF XFORMR
RF In
RF XFORMR
Clo k/Syn Bus
TTL In
200 MH 16 bit A/D
200 MH 16 bit A/D
200 MH 16 b t A/D
200 MH 16 bit A/D
LVPECL Bus
XTL OSC
Control/ Status
PROCESSING FPGA VIRTEX 5 LX50T, SX50T, SX 5T, LX155T or FX100T

GTP GTP GTP LVDS
8
4X 4X
Timing Bus
4X
GTP
64
FLASH 32 MB
NTERFACE FPGA VIRTEX 5 LX30T or SX50T

GTP PCI X LVDS
4X
64
PCI X BUS 1 64 Bits, 100 MH 32
32
XMC - P15
4X 4X
PMC - P14
x4 PCIe
24
64
CROSSBAR SWITCH
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 5350

The Model 5350 architecture includes a flexible timing and synchronization circuit for each bank of four A/D converters, allowing the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. Each timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, each accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to three slave 5350s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX50T standard; XC5VLX50T, XC5VSX95T, XC5VLX155T or XC5VFX100T, optional Interface FPGA: Xilinx Virtex-5 XC5VLX30T std.; XC5VSX50T optional Custom I/O Option -104: Provides GPIO to VPX-P2 with 16 LVDS pairs to processing FPGA (SX95T, LX155T or FX100T only) and 16 pairs to interface FPGA Memory DDR2 SDRAM: Up to 1 GB in two banks PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus Gigabit Serial I/O: Processing FPGA: Two 4X ports to Fabric-Transparent Switch; one can be alternately routed to interface FPGA VPX-P1: Four 4X ports to Fabric-Transparent Crossbar Switch PCI Express: Six ports to Fabric-Transparent Switch, each configurable as x1, x4, x8 or x16 lanes, 24 lanes total Environmental Operating Temperature: Forced-Air Cooled: 0 to 50 C std; -20 to 65 C (Level L2) Conduction-Cooled: -40 to 70 C (Level L3) Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGA. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering. Each memory bank can be easily accessed through the PCI interface using the on-board DMA controllers. Custom user-installed functions within the FPGA can take advantage of all three banks to support various applications.

Model 5350 Description Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs 3U VPX
Options: -104 FPGA I/O to VPX-P2 -5xx Gigabit Serial I/O to VPXP1- four full duplex 4X paths -703 Level L3 ConductionCooled Version
PCI Express Switch

Pentek, Inc.
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! ew N
Model 71630

General Information
Model 71630 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes 1 GHz A/D and D/A converters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71630 includes optional general purpose and gigabit serial card connectors for application-specific I/O. synchronization functions, a test signal generator and a PCIe interface complete the factory-installed functions and enable the 71630 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71630 factory-installed functions include an A/D acquisition and a D/A waveform playback IP module. In addition, IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and

RF In RF Out
Features

RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Sync In
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12
1 GHz 16-BIT D/A 16
D/A Sync Bus
VCXO

GTX
GTX
GTX
LVDS
16
16
16
16
8X
4X
4X
40
x8 PCIe
P15 XMC
QDRII+ option 150
Pentek, Inc.
www.pentek.com
Model 71630

A/D Converter Stage

D/A Converter Stage

Memory Resources
to D/A



INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 71630

XMC Interface
The Model 71630 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71630 supports x8 PCIe on the first XMC connector leaving the second connector free to support userinstalled transfer protocols specific to the target application. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Option 150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1: x4 or x8; Gen 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards (Models 78xxx). It was created to save engineers and system integrators the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. The Model 71630 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the module.
Specifications
Model 71630 Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector -105 Gigabit serial FPGA I/O through P16 connector -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required Description 1 GHz A/D and D/A, Virtex-6 FPGA - XMC

Pentek, Inc.
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! ew N
Model 78630

General Information
Model 78630 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes 1 GHz A/D and 1 GHz D/A converters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78630 includes optional general-purpose and gigabit serial card connectors for application specific I/O protocols. generator and a PCIe interface complete the factory-installed functions and enable the 78630 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory installed applications ideally matched to the boards analog interfaces. The 78630 factory-installed functions include an A/D acquisition and a D/A waveform playback IP module. In addition, IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal

RF In RF Out
Features

RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Sync In
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12
1 GHz 16-BIT D/A 16
D/A Sync Bus
VCXO

LVDS
GTX
GTX
GTX
16
16
16
16
8X
4X
4X
x8 PCIe
QDRII+ option 150
x8 PCI Express
Pentek, Inc.
www.pentek.com
Model 78630

A/D Converter Stage
The front end accepts an analog HF or IF input on a front panel SSMC connector with transformer coupling into a Texas Instruments ADS5400 1 GHz, 12-bit A/D converter. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources. Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or 16 to provide different lower frequency A/D and D/A clocks. A pair of front panel Sync connectors allows multiple boards to be synchronized. They accept CML inputs that drive the boards sync and gate/trigger signals. The Pentek Model 7892 and Model 9192 Cobalt Synchronizers can drive multiple 78630 Sync connectors enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connector.
D/A Converter Stage

Memory Resources
The 78630 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
to D/A


INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 78630

The Model 78630 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the board. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2, or XC6VSX315T-2 Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Option 150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1: x4 or x8 Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.
Specifications
Model 8266
Model 78630 Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T XC6VSX315T LVDS FPGA I/O through 68-pin ribbon cable connector -105 Gigabit serial FPGA I/O through two 4X top edge connectors -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required Model 8266 Description PC Development System See 8266 Datasheet for Options Description 1 GHz A/D and D/A, Virtex-6 FPGA - x8 PCIe
Pentek, Inc.
www.pentek.com
! ew N
Model 53630

General Information


Features

RF In
RF Out
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Sync In
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12
1 GHz 16-BIT D/A 16
D/A Sync Bus
VCXO

LVDS

GTX
GTX
GTX
16
16
16
16
40
8X x8 PCIe
4X
4X
CROSSBAR SWITCH
QDRII+ option 150
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 53630

A/D Converter Stage

D/A Converter Stage

Memory Resources
to D/A



INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 53630

The Model 53630 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the board. Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Option 150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1: x4 or x8; Gen 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

Specifications
VPX Families
53xxx
Pentek, Inc.
www.pentek.com
! ew N
Model 52630

General Information


Features

RF In
RF Out
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Sync In
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12
1 GHz 16-BIT D/A 16
D/A Sync Bus
VCXO

LVDS
GTX
GTX GTX
16
16
16
16
40
4X
4X
4X

x4 PCIe
QDRII+ option 150
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52630

A/D Converter Stage

D/A Converter Stage

Memory Resources
to D/A



INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 52630

Specifications
VPX Families
53xxx
Pentek, Inc.
www.pentek.com
! ew N
Model 52630

General Information


Features

RF In
RF Out
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Sync In
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12
1 GHz 16-BIT D/A 16
D/A Sync Bus
VCXO

LVDS
GTX
GTX GTX
16
16
16
16
40
4X
4X
4X

x4 PCIe
QDRII+ option 150
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52630

A/D Converter Stage

D/A Converter Stage

Memory Resources
to D/A



INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 52630

Specifications
VPX Families
53xxx
Pentek, Inc.
www.pentek.com
! ew N
Model 56630

General Information
Model 56630 is a member of the Cobalt family of high performance AMC modules based on the Xilinx Virtex-6 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes 1 GHz A/D and D/A converters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 56630 includes a front panel general-purpose connector for application-specific I/O . memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factory-installed functions and enable the 56630 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 56630 factory-installed functions include an A/D acquisition and a D/A waveform playback IP module. In addition, IP modules for either DDR3 or QDRII+

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One 1 GHz 12-bit A/D One 1 GHz 16-bit D/A Up to 2 GB of DDR3 SDRAM or 16 MB of QDRII+ SRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF Out
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Sync In
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12
1 GHz 16-BIT D/A 16
D/A Sync Bus
VCXO

GTX
LVDS
16
16
16
16
8X
IPMI CONTROLLER
40
x8 PCIe
RS-232
AMC Ports 4 to 11
Front Panel
QDRII+ option 150
Pentek, Inc.
www.pentek.com
Model 56630

A/D Converter Stage

D/A Converter Stage

Memory Resources

to D/A

INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 56630

AMC Interface
The Model 56630 complies with the AMC.1 specification by providing an x8 PCIe connection to AdvancedTCA carriers or TCA chassis. Module management is provided by an IPMI 2.0 MMC (Module Management Controller). External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory Option 150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1: x4 or x8; Gen 2: x4 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.

Specifications
Model 56630 Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through front panel connector -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required Description 1 GHz A/D and D/A, Virtex-6 FPGA - AMC
Pentek, Inc.
www.pentek.com
! w e N
Model 71640
General Information
Model 71640 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71640 includes optional general purpose and gigabit serial connectors for application-specific I/O. and a PCIe interface complete the factoryinstalled functions and enable the 71640 to operate as a complete turnkey solution, without the need to develop any FPGA IP.


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O. Option -105 installs the P16 XMC connector with dual 4X gigabit links to the FPGA to support other serial protocols.
Features

Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One-channel mode with 3.6 GHz, 12-bit A/D Two-channel mode with 1.8 GHz, 12-bit A/Ds 2 GB of DDR3 SDRAM Sync bus for multimodule synchronization PCI Express Gen. 2 interface x8 wide Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus

12 12
Sync Bus

GTX
GTX
GTX
LVDS
8X
4X
4X
40
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCIe
P15 XMC
Pentek, Inc.
www.pentek.com
Model 71640
A/D Converter Stage
The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the 71640 to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple modules. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple 71640s can be synchronized using the Cobalt high speed sync module to drive the sync bus.
Memory Resources

XMC Interface
The Model 71640 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 5 GHz bit clock. With dual XMC connectors, the 71640 supports x8 PCIe on the first XMC connector leaving the optional second connector free to support user-installed transfer protocols specific to the target application.

The 71640 accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connector. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multi-pin sync bus connector allows multiple modules to be synchronized, ideal for larger multichanel
from A/D
from A/D

MEMORY CONTROLLER
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 71640
The Model 71640 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the module. External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2, or XC6VSX315T-2 Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
Specifications
Model 8266
Model 71640 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - XMC
Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T XC6VSX315T LVDS FPGA I/O through P14 connector -105 Gigabit serial FPGA I/O through P16 connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required

Pentek, Inc.
www.pentek.com
! w e N
Model 78640
General Information
Model 78640 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. The 78640 includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78640 includes optional general-purpose and gigabit serial connectors for application-specific I/O protocols. and a PCIe interface complete the factoryinstalled functions and enable the 78640 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

RF In RF In

Features

Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One-channel mode with 3.6 GHz, 12-bit A/D Two-channel mode with 1.8 GHz, 12-bit A/Ds 2 GB of DDR3 SDRAM Sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface, up to x8 Clock/sync bus for multiboard synchronization Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus

12 12
Sync Bus

LVDS
GTX
GTX
GTX
40
8X
4X
4X
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCIe
x8 PCI Express
Pentek, Inc.
www.pentek.com
Model 78640
A/D Converter Stage
The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a National Semiconductor ADC12D1800 12-bit A/D. The converter operates in singlechannel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the 78640 to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple boards. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple 78640s can be synchronized using the Cobalt high speed sync board to drive the sync bus.
Memory Resources



The 78640 accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connector. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multi-pin sync bus connector allows multiple boards to be
from A/D
from A/D

T o hannel mode sho n INPUT MULTIPLEXER
DATA PACKING & FLO CONTROL MUX METADATA GENERATOR LINKED LIST DMA ENGINE A/D ACQUISITION IP MODULE to MEM CONTROL
DATA PACKING & FLO CONTROL MUX METADATA GENERATOR LINKED LIST DMA ENGINE A/D ACQUISITION IP MODULE
MEMORY CONTROLLER
supports user installed IP to Mem Bank 1 to Mem Bank 2 8X PCIe Gigabit Serial I/O 4X 4X 40 to Mem Bank 3 to Mem Bank 4
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 78640
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Sample Clock Sources: Front panel SSMC connector Sync Bus: Multi-pin connectors, bus includes gate, reset and in and out ref clock External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 XC6VSX315T-2 Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1or Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe card, 4.38 in. x 7.13 in.
Model 8266
Model 78640 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - x8 PCIe
Pentek, Inc.
www.pentek.com
! ew N
Model 53640
General Information

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 53640 factory-installed functions include an A/D acquisition IP module. In addition, IP modules for DDR3 memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factory-

Features

RF In
RF In
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus

12 12
Sync Bus

GTX

GTX
GTX
40
8X x8 PCIe
4X
4X
Memory Banks 1 & 2
Memory Banks 3 & 4
CROSSBAR SWITCH
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 53640
A/D Converter Stage
Memory Resources



The 53640 accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connector. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multipin sync bus connector allows multiple boards to be
from A/D
from A/D

MEMORY CONTROLLER
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 53640
The 53640 features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (4X). Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1or Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Sample Clock Sources: Front panel SSMC connector Sync Bus: Multi-pin connectors, bus includes gate, reset and in and out reference clock External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS
VPX Families
53xxx
Pentek, Inc.
www.pentek.com
! ew N
Model 52640
General Information

Model 52640 COTS (left) and rugged version The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 52640 factory-installed functions include an A/D acquisition IP module. In addition, IP modules for DDR3 memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factory-

Features

RF In
RF In
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus

12 12
Sync Bus

GTX
GTX
GTX
4X
4X
4X
Memory Banks 1 & 2
Memory Banks 3 & 4

x4 PCIe
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52640
A/D Converter Stage
Memory Resources



The 52640 accepts an 1.8 GHz dual-edge sample clock via a front panel SSMC connector. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multipin sync bus connector allows multiple boards to be
from A/D
from A/D

MEMORY CONTROLLER
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 52640
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Sample Clock Sources: Front panel SSMC connector Sync Bus: Multi-pin connectors, bus includes gate, reset and in and out reference clock External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm).
VPX Families
53xxx
Pentek, Inc.
www.pentek.com
! w e N
Models 72640, 73640 and 74640
General Information
Models 72640, 73640 and 74640 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71640 XMC modules mounted on a cPCI carrier board. Model 72640 is a 6U cPCI board while the Model 73640 is a 3U cPCI board; both are equipped with one Model 71640 XMC. Model 74640 is a 6U cPCI board with two XMC modules rather than one. These models include one or two 3.6 GHz, 12-bit A/D converters and four or eight banks of memory. generator and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions, without the need to develop any FPGA IP.

The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include one or two A/D acquisition IP modules. In addition, IP modules for DDR3 memories, controllers for all data clocking and synchronization functions, a test signal

Model 74640
Model 73640
Features

Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One or two 1-channel mode with 3.6 GHz, 12-bit A/Ds Two or four 2-channel mode with 1.8 GHz, 12-bit A/Ds 2 or 4 GB of DDR3 SDRAM Sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus

12 12
Sync Bus
VIRTEX-6 FPGA LX130T, LX240T or SX315T MODEL 73640 INTERFACES ONLY VIRTEX-6 FPGA
LVDS LVDS
GTX
40
GTX
x4 PCIe
4X
40
PCIe
Memory Banks 1 & 2
Memory Banks 3 & 4
PCIe to PCI BRIDGE
PCI to PCI BRIDGE
J2
Pentek, Inc.
www.pentek.com
Models 72640, 73640 and 74640
A/D Converter Stage
The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing these models to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple boards. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple boards can be synchronized using the Cobalt high speed sync board to drive the sync bus.
Memory Resources
The Cobalt architecture supports four or eight independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and data capture capabilities. Built-in memory functions include an A/D data transient capture mode for taking snapshots of data for transfer to a host computer. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

PCI-X Interface

These models accept a 1.8 GHz dualedge sample clock via front panel SSMC connectors. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multi-pin sync bus connector allows multiple boards to be
from A/D
from A/D

MEMORY CONTROLLER
(supports user installed IP) to Mem Bank 1 to Mem Bank 2 4X PCIe 40 FPGA I/O to Mem Bank 3 to Mem Bank 4
Pentek, Inc.
www.pentek.com
Models 72640, 73640 and 74640
Specifications
Model 72640 or Model 73640: One A/D Model 74640: Two A/Ds Front Panel Analog Signal Inputs (2 or 4) Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter (1 or 2) Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Sample Clock Sources (1 or 2) Front panel SSMC connector Sync Bus (1 or 2) Multi-pin connectors, bus includes gate, reset and in and out ref clock External Trigger Input (1 or 2) Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73640; J3 connector, Model 72640; J3 and J5 connectors, Model 74640 Memory Banks (1 or 2) Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73640: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
Model 72640 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - 6U cPCI 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - 3U cPCI 2-Ch. 3.6 GHz or 4-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - 6U cPCI
73640
74640
Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T XC6VSX315T LVDS I/O between the FPGA and J2 connector, Model 73640; J3 connector, Model 72640; J3 and J5 connectors, Model 74640 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
www.pentek.com
! w e N
Model 56640
General Information
Model 56640 is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 56640 includes a front panel general-purpose connector for application-specific I/O . controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factoryinstalled functions and enable the 56640 to operate as a complete turnkey solution, without the need to develop any FPGA IP.


Features

Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One-channel mode with 3.6 GHz, 12-bit A/D Two-channel mode with 1.8 GHz, 12-bit A/Ds 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus

12 12
Sync Bus

GTX
LVDS
8X
IPMI CONTROLLER
40
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCIe
RS-232
AMC Ports 4 to 11
Front Panel
Pentek, Inc.
www.pentek.com
Model 56640
A/D Converter Stage
The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the 56640 to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple modules. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple 56640s can be synchronized using the Cobalt high speed sync module to drive the sync bus.
Memory Resources

AMC Interface

The 56640 accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connector. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multi-pin sync bus connector allows multiple modules to be
from A/D
from A/D

MEMORY CONTROLLER
(supports user installed IP) to Mem Bank 1 to Mem Bank 2 8X PCIe 40 to Mem Bank 3 to Mem Bank 4
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 56640
The Model 56640 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the module. External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2, or XC6VSX315T-2 Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.
Specifications
Model 56640 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - AMC
Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T XC6VSX315T LVDS FPGA I/O through front panel connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
www.pentek.com
! w e N
Model 71660

General Information
Model 71660 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes four A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71660 includes general purpose and gigabit serial connectors for application-specific I/O . generator, and a PCIe interface complete the factory-installed functions and enable the 71660 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71660 factory-installed functions include four A/D acquisition IP modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 VITA 42.0 XMC compatible with switched fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

GTX
GTX
GTX
LVDS
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
8X
4X
4X
40
x8 PCIe
P15 XMC
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
www.pentek.com
Model 71660

A/D Converter Stage
Memory Resources


XMC Interface
The Model 71660 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71660
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 71660

supports x8 PCIe on the first XMC connector leaving the second connector free to support user-installed transfer protocols specific to the target application. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

Model 8266
Specifications
Model 71660 Options: -062 -064 -104 -105 -150 XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Description 4-Channel 200 MHz A/D with Virtex-6 FPGA - XMC
-160
-155
-165

Pentek, Inc.
www.pentek.com
! ew N
Model 78660

General Information
Model 78660 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. It includes four A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78660 includes optional general-purpose and gigabit serial connectors for applicationspecific I/O protocols. 78660 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory installed applications ideally matched to the boards analog interfaces. The 78660 factory-installed functions include four A/D acquisition IP modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factory- installed functions and enable the

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

LVDS
GTX
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
8X
4X
4X
x8 PCIe
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCI Express
Pentek, Inc.
www.pentek.com
Model 78660

A/D Converter Stage
The front end accepts four full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources. LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78660s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Memory Resources

An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the


from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 78660

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.
Model 8266
Model 78660 Options: -062 -064 -104 XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector Gigabit serial FPGA I/O through two 4X top edge connectors Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Description PC Development System See 8266 Datasheet for Options Description 4-Channel 200 MHz A/D with Virtex-6 FPGA - PCIe
-105
-150
-160
-155
-165
Model 8266
Pentek, Inc.
www.pentek.com
! ew N
Model 53660

General Information


Features

RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

LVDS GTX

GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
40
8X x8 PCIe
4X
4X
Memory Banks 1 & 2
Memory Banks 3 & 4
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 53660

A/D Converter Stage
Memory Resources



from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 53660

The 53660 features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (4X). External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector LVPECL bus includes, clock/sync/ gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs
VPX Families
Options: -062 -064 -104 -105 -150
53xxx
-160
-155
-165
Pentek, Inc.
www.pentek.com
! ew N
Model 52660

General Information


Features

RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

LVDS GTX
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
4X 4X 4X
x4 PCIe
Memory Banks 1 & 2
Memory Banks 3 & 4
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52660

A/D Converter Stage
Memory Resources



from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
4X
Gigabit Serial I/O
4X 4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 52660

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector LVPECL bus includes, clock/sync/ gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
VPX Families
53xxx
Options: -062 -064 -104 -105 -150
-160
-155
-165
Pentek, Inc.
www.pentek.com
! w e N
Models 72660, 73660 and 74660

General Information
Models 72660, 73660 and 74660 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71660 XMC modules mounted on a cPCI carrier board. Model 72660 is a 6U cPCI board while the Model 73660 is a 3U cPCI board; both are equipped with one Model 71660 XMC. Model 74660 is a 6U cPCI board with two XMC modules rather than one. These models include four or eight A/Ds and four or eight banks of memory. generator, and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions without the need to develop FPGA IP.

The Pentek Cobalt Architecture features Virtex-6 FPGAs. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factoryinstalled functions of these models include four or eight A/D acquisition IP modules. IP modules for either DDR3 or QDRII+ memories, controllers for all data clocking and synchronization functions, a test signal

Model 74660
Model 73660
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four or eight 200 MHz 16-bit A/Ds Up to 2 or 4 GB of DDR3 SDRAM; or: 32 or 64 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

LVDS

LVDS
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
40
4X
PCIe to PCI BRIDGE
GTX
PCI to PCI BRIDGE
J2
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
www.pentek.com
Models 72660, 73660 and 74660

A/D Converter Stage
The front end accepts four or eight full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into four or eight Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources. LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.


These models feature four or eight A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of four A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
PCI-X Interface
from A/D Ch 1
from A/D Ch 2
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
40 FPGA I/O
Pentek, Inc.
www.pentek.com
Models 72660, 73660 and 74660

Specifications
Model 72660 or Model 73660: 4 A/Ds Model 74660: 8 A/Ds Front Panel Analog Signal Inputs (4 or 8) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (4 or 8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources (1 or 2) On-board clock synthesizers Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus (1 or 2): 26-pin front panel connector; LVPECL bus includes, clock/ sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73660; J3 connector, Model 72660; J3 and J5 connectors, Model 74660 Memory Banks (1 or 2) Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73660: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
Model 72660 Description 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGA 6U cPCI 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGA 3U cPCI 8-Channel 200 MHz 16-bit A/D with two Virtex-6 FPGAs - 6U cPCI XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73660; J3 connector, Model 72660; J3 and J5 connectors, Model 74660 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
73660
74660
Options: -062 -064 -104
-150
-160
-155
-165
Pentek, Inc.
www.pentek.com
! w e N
Model 56660

General Information
Model 56660 is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes four A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 56660 includes a front panel general-purpose connector for applicationspecific I/O. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 56660 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 56660 factory-installed functions include four A/D acquisition IP modules.

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

GTX
LVDS
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
8X
IPMI CONTROLLER
40
x8 PCIe
RS-232
AMC Ports 4 to 11
Front Panel
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
www.pentek.com
Model 56660

A/D Converter Stage
Memory Resources


AMC Interface
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 56660

The Model 56660 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the module. Timing Bus: 26-pin front panel connector; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference
Model 56660 Options: -062 -064 -104 -150 XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through front panel connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Description 4-Channel 200 MHz A/D with Virtex-6 FPGA - AMC
-160
-155
-165
Pentek, Inc.
www.pentek.com
! ew N
Model 71670

General Information
Model 71670 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. This 4-channel, high-speed data converter is suitable for connection to transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As, four digital upconverters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71670 includes general purpose and gigabit serial connectors for application-specific I/O . a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 71670 to operate as a complete turnkey solution, without the need to develop any FPGA IP.


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O. Option -105 installs the P16 XMC connector with dual 4X gigabit links to the FPGA to support serial protocols.
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 1.25 GHz 16-bit D/As Four digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF Out
RF Out
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO

GTX
GTX
GTX
LVDS
8X
4X
4X
40
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCIe
P15 XMC
Pentek, Inc.
www.pentek.com
Model 71670

Two Texas Instruments DAC3484s provide four DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals to a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs to a 16-bit D/A converter. If translation is disabled, each D/A acts as an interpolating 16-bit D/A with output sampling rates up to 1.25 GHz. In both modes, the D/A provides interpolation factors of 2x, 4x, 8x and 16x. Analog output is through four front panel SSMC connectors. A pair of front panel Sync connectors allows multiple modules to be synchronized. They accept CML inputs that drive the boards sync and trigger/gate signals. The Pentek Models 7192 or 9192 Cobalt Synchronizers can drive multiple 71670 Sync connectors enabling large, multichannel synchronous configurations.
Memory Resources

An internal timing bus provides all required D/A clocking. The bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives a sample clock either from the front panel SSMC connector or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this latter mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock to phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided by 2, 4, 8, or 16 to provide lower frequency D/A clocks.
16
XMC Interface
The Model 71670 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 3.125 GHz bit clock. With dual XMC connectors, the 71670 supports x8 PCIe on the first XMC connector leaving the second connector free to support user-installed transfer protocols specific to the target application.

to D/A Ch 1 & 2
16
to D/A Ch 3 & 4
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 71670

The Model 71670 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the module. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connector Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as two 4X or one 8X gigabit serial links to the FPGA Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
Specifications Model 8266

The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards (Models 78xxx). It was created to save engineers and system integrators the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the D/A clock
Model 71670 Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector -105 Gigabit serial FPGA I/O through P16 connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required Description 4-Channel 1.25 GHz D/A with Virtex-6 FPGA - XMC

Pentek, Inc.
www.pentek.com
! ew N
Model 78670

General Information
Model 78670 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. This 4-channel, high-speed data converter is suitable for connection to transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As, four digital upconverters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78670 includes optional general purpose and gigabit serial connectors for application-specific I/O. complete the factory-installed functions and enable the 78670 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 78670 factory-installed functions include four D/A waveform playback IP modules, to support waveform generation through the D/A converters. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface
RF Out

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 1.25 GHz 16-bit D/As Four digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO

LVDS
GTX
GTX
GTX
40
8X
4X
4X
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCIe
x8 PCI Express
Pentek, Inc.
www.pentek.com
Model 78670

Memory Resources



16
to D/A Ch 1 & 2
16
to D/A Ch 3 & 4
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 78670

Specifications
D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connector Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.
Model 8266
Model 78670 Description 4-Channel 1.25 GHz D/A with Virtex-6 FPGA - x8 PCIe
Pentek, Inc.
www.pentek.com
! ew N
Model 53670

General Information

RF Out

Features

RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO

LVDS

GTX
GTX
GTX
40
8X x8 PCIe
4X
4X
Memory Banks 1 & 2
Memory Banks 3 & 4
CROSSBAR SWITCH
Pentek, Inc.
www.pentek.com
Model 53670

Memory Resources



16
to D/A Ch 1 & 2
16
to D/A Ch 3 & 4
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 53670

The 53670 features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (4X). External Trigger Input Type: Front panel female SSMC connector Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin Sync bus connector includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Specifications
D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference
VPX Families
53xxx
Pentek, Inc.
www.pentek.com
! ew N
Model 52670

General Information

RF Out

Features

RF Out
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO

LVDS
GTX
GTX
GTX
40
4X
4X
4X
Memory Banks 1 & 2
Memory Banks 3 & 4
x4 PCIe
VPX-P2
VPX-P1
Pentek, Inc.
www.pentek.com
Model 52670

Memory Resources



16
to D/A Ch 1 & 2
16
to D/A Ch 3 & 4
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 52670

Specifications
D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connector Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin Sync bus connector includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
VPX Families
53xxx
Pentek, Inc.
www.pentek.com
! ew N
Models 72670, 73670 and 74670

General Information
Models 72670, 73670 and 74670 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71670 XMC modules mounted on a cPCI carrier board. Model 72670 is a 6U cPCI board while the Model 73670 is a 3U cPCI board; both are equipped with one Model 71670 XMC. Model 74670 is a 6U cPCI board with two XMC modules rather than one. These models include four or eight D/As, four or eight DUCs, and four or eight banks of memory. controllers for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable these models to operate as complete turnkey solutions, without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions in these models include four or eightD/A waveform playback IP modules, to support waveform generation through the D/A converters. IP modules for DDR3 SDRAM memories,

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four or eight 1.25 GHz 16-bit D/As Four or eight digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 or 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-or Quad Sync clock/ sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF Out
RF Out
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO

LVDS

LVDS
GTX
40
x4 PCIe
4X
GTX
Memory Banks 3 & 4
PCIe to PCI BRIDGE
PCI to PCI BRIDGE
J2
Pentek, Inc.
www.pentek.com
Models 72670, 73670 and 74670

Two or four Texas Instruments DAC3484s provide four or eight DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals to a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs to a 16-bit D/A converter. If translation is disabled, each D/A acts as an interpolating 16-bit D/A with output sampling rates up to 1.25 GHz. In both modes, the D/A provides interpolation factors of 2x, 4x, 8x and 16x. Analog output is through four front panel SSMC connectors. 2, 4, 8, or 16 to provide lower frequency D/A clocks. A pair of front panel Sync connectors allows multiple boards to be synchronized. They accept CML inputs that drive the boards sync and trigger/gate signals. The Pentek Models 7292, 7392 and 7492 or the 9192 Cobalt Synchronizers can drive multiple Sync connectors enabling large, multichannel synchronous configurations.
Memory Resources
The architecture of these models supports four or eight independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and waveform playback capabilities. Waveform tables can be loaded into the memories with playback managed by the linked list controllers. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

PCI-X Interface

The factory-installed functions in these models include one or two sophisticated D/A Waveform Playback IP modules. Four or eight linked list controllers support waveform generation to the four or eight D/As from tables stored in either on-board memory or offboard host memory. Data for Channel 1 and Channel 2 are interleaved for delivery to a dual channel D/A device. For this reason, they must share a common trigger/ gate, sample rate, interpolation factor, and other parameters. The same rules apply to Channel 3 and Channel 4, as well as to the other four channels of Model 74670. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up to 64 or 128 individual link entries for each D/A channel can be chained together to create complex waveforms with a minimum of programming.
16
to D/A Ch 1 & 2
16
to D/A Ch 3 & 4
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
40 FPGA I/O
Pentek, Inc.
www.pentek.com
Models 72670, 73670 and 74670

Specifications
Models 72670 and 73670: 4-Channel DUC, 4-channel D/A Model 74670: 8-Channel DUC, 4-channel D/A D/A Converters (4 or8) Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Front Panel Analog Signal Outputs (4 or 8) Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the D/A clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus (1 or 2): 19-pin Sync bus connector includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73670; J3 connector, Model 72670; J3 and J5 connectors, Model 74670 Memory Banks (1 or 2) Four or eight 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73670: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
Model 72670 Description 4-Channel 1.25 GHz D/A with Virtex-6 FPGA - 6U cPCI 4-Channel 1.25 GHz D/A with Virtex-6 FPGA - 3U cPCI 8-Channel 1.25 GHz D/A with Virtex-6 FPGA - 6U cPCI
73670
74670
Pentek, Inc.
www.pentek.com
! ew N
Model 56670

General Information
Model 56670 is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6 FPGA. This 4-channel, high-speed data converter is suitable for connection to transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As, four digital upconverters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 56670 includes a front panel general-purpose connector for application-specific I/O. SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 56670 to operate as a complete turnkey solution, without the need to develop any FPGA IP.


Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 1.25 GHz 16-bit D/As Four digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-6 FPGA for custom I/O
RF Out
RF Out
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
Sync Bus A
Gate In Sync In
Sync Bus B
VCXO

GTX
LVDS
8X
IPMI CONTROLLER
40
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCIe
RS-232
AMC Ports 4 to 11
Front Panel
Pentek, Inc.
www.pentek.com
Model 56670

Memory Resources

AMC Interface

16
to D/A Ch 1 & 2
16
to D/A Ch 3 & 4
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 56670

The Model 56670 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the module. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connector Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin Sync bus connector includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.
Specifications
D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the D/A clock
Model 56670 Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through front panel connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required Description 4-Channel 1.25 GHz D/A with Virtex-6 FPGA - AMC
Pentek, Inc.
www.pentek.com
! w e N
Model 71690

General Information
Model 71690 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A 2-Channel high-speed data converter, it is suitable for connection directly to the RF port of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes an L-Band RF tuner, two A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71690 includes general purpose and gigabit serial connectors for application-specific I/O . generator, and a PCIe interface complete the factory-installed functions and enable the 71690 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71690 factory-installed functions include two A/D acquisition IP modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal
Ref In

RF In
MAX2112
Features

Accepts RF signals from 925 MHz to 2175 MHz Programmable LNA boosts LNB (low-noise block) antenna signal levels with up to 60 dB gain Programmable analog downconverter provides I + Q baseband signals with bandwidths ranging from 4 to 40 MHz Two 200 MHz 16-bit A/Ds digitize the I + Q signals synchronously Supports Xilinx Virtex-6 LXT and SXT FPGAs 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference PCI Express (Gen. 1 & 2) interface, up to x8 Clock/sync bus for multimodule synchronization VITA 42.0 XMC compatible with switched fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Ref Out GC
12-BIT D/A
Ref A/D Clock/Sync
Control
16
16
IC
2
Timing Bus
VCXO

GTX
GTX
GTX
LVDS
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
Config FLASH 64 MB
8X
4X
4X
40
x8 PCIe
P15 XMC
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
www.pentek.com
Model 71690

RF Tuner Stage


A/D Converter Stage

Memory Resources
from A/D (I)
from A/D (Q)
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 71690

8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. The factory-installed A/D acquisition modules use memory banks 1 & 2. Banks 3 & 4 can be optionally installed to support custom user-installed IP within the FPGA . A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board timing generator/synthesizer A/D Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, for the A/D clock Timing Generator External Clock Input Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 200 MHz (up to 800 MHz when Timing Generator divider is enabled) or PLL system reference Timing Generator Bus: 26-pin front panel connector LVPECL bus includes, clock/ sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Input Quantity: 2 Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8; Gen. 2 x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
Model 8266
XMC Interface

Model 71690 Description L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - XMC XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Options: -062 -064 -104 -105 -150
Specifications
-160
-155
-165

Pentek, Inc.
www.pentek.com
! w e N
Model 78690

General Information
Model 78690 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A 2-Channel high-speed data converter, it is suitable for connection directly to the RF port of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. It includes an L-Band RF tuner, two A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78690 includes optional general-purpose and gigabit serial connectors for application-specific I/O protocols. 78690 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 78690 factory-installed functions include two A/D acquisition IP modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable the
Ref In

RF In
MAX2112
Features

Accepts RF signals from 925 MHz to 2175 MHz Programmable LNA boosts LNB (low-noise block) antenna signal levels with up to 60 dB gain Programmable analog downconverter provides I + Q baseband signals with bandwidths ranging from 4 to 40 MHz Two 200 MHz 16-bit A/Ds Supports Xilinx Virtex-6 LXT and SXT FPGAs 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference PCI Express (Gen. 1 & 2) interface, up to x8 Clock/sync bus for multiboard synchronization Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Ref Out GC
12-BIT D/A
Ref A/D Clock/Sync
Control
Option 100
Q 200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
IC
2
Timing Bus
VCXO

LVDS
GTX
GTX
GTX
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
8X
4X
4X
x8 PCIe
Memory Banks 1 & 2
Memory Banks 3 & 4
x8 PCI Express
Pentek, Inc.
www.pentek.com
Model 78690

RF Tuner Stage


A/D Converter Stage

Memory Resources
from A/D (I)
from A/D (Q)
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 78690

8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. The factory-installed A/D Acquisition Modules use memory banks 1 & 2. Banks 3 & 4 can be optionally installed to support custom user-installed IP within the FPGA . Sample Clock Sources: On-board timing generator/synthesizer A/D Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, for the A/D clock Timing Generator External Clock Input Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 200 MHz (up to 800 MHz when Timing Generator divider is enabled) or PLL system reference Timing Generator Bus: 26-pin front panel connector LVPECL bus includes, clock/ sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Input Quantity: 2 Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8; Gen. 2 x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe card, 4.38 in. x 7.13 in.
Model 8266

Specifications
Front Panel Analog Signal Input Connector: Front panel female SSMC Impedance: 50 ohms L-Band Tuner Type: Maxim MAX2112 Input Frequency Range: 925 MHz to 2175 MHz Monolithic VCO Phase Noise: -97 dBc/Hz at 10 kHz Fractional-N PLL Synthesizer: freqVCO = (N.F) x freqREF where integer N = 19 to 251 and fractional F is a 20-bit binary value PLL Reference (freqREF): Front panel SSMC connector or on-board 27 MHz crystal (Option -100), 12 to 30 MHz LNA Gain: 0 to 65 dB, controlled by a programmable 12-bit D/A converter* Baseband Amplifier Gain: 0 to 15 dB, in 1 dB steps* *Usable Full-Scale Input Range: 50 dBm to +10 dBm Baseband Low Pass Filter: Cutoff frequency programmable from 4 to 40 MHz with 8-bit resolution A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits
Model 78690 Description L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - PCIe XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector Gigabit serial FPGA I/O through two 4X top edge connectors Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Description PC Development System See 8266 Datasheet for Options
Options: -062 -064 -104
-105
-150
-160
-155
-165
Model 8266
Pentek, Inc.
www.pentek.com
! ew N
Model 53690

General Information


Features

Ref In
RF In
MAX2112
Ref Out GC
12-BIT D/A
Ref A/D Clock/Sync
Control
16
16
IC
2
Timing Bus
VCXO

LVDS GTX

GTX
GTX
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
Config FLASH 64 MB
40
8X x8 PCIe
4X
4X
Memory Banks 1 & 2
Memory Banks 3 & 4
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 53690

RF Tuner Stage


A/D Converter Stage

Memory Resources
from A/D (I)
from A/D (Q)
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 53690
The Model 53690 includes an industry standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the board

8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. The factory-installed A/D Acquisition Modules use memory banks 1 & 2. Banks 3 & 4 can be optionally installed to support custom user-installed IP within the FPGA . 800 MHz when Timing Generator divider is enabled) or PLL system reference Timing Generator Bus: 26-pin front panel connector LVPECL bus includes, clock/ sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Input Quantity: 2 Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8; Gen. 2 x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

Specifications
Front Panel Analog Signal Input Connector: Front panel female SSMC Impedance: 50 ohms L-Band Tuner Type: Maxim MAX2112 Input Frequency Range: 925 MHz to 2175 MHz Monolithic VCO Phase Noise: -97 dBc/Hz at 10 kHz Fractional-N PLL Synthesizer: freqVCO = (N.F) x freqREF where integer N = 19 to 251 and fractional F is a 20-bit binary value PLL Reference (freqREF): Front panel SSMC connector or on-board 27 MHz crystal (Option -100), 12 to 30 MHz LNA Gain: 0 to 65 dB, controlled by a programmable 12-bit D/A converter* Baseband Amplifier Gain: 0 to 15 dB, in 1 dB steps* *Usable Full-Scale Input Range: 50 dBm to +10 dBm Baseband Low Pass Filter: Cutoff frequency programmable from 4 to 40 MHz with 8-bit resolution A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board timing generator/synthesizer A/D Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, for the A/D clock Timing Generator External Clock Input Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 200 MHz (up to
Options: -062 -064 -104 -105 -150
VPX Families
53xxx
-160
-155
-165
Pentek, Inc.
www.pentek.com
! ew N
Model 52690

General Information


Features

Ref In
RF In
MAX2112
Ref Out GC
12-BIT D/A
Ref A/D Clock/Sync
Control
16
16
IC
2
Timing Bus
VCXO

LVDS GTX
GTX
GTX
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
4X 4X 4X

x4 PCIe
Memory Banks 1 & 2
Memory Banks 3 & 4
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52690

RF Tuner Stage


A/D Converter Stage

Memory Resources
from A/D (I)
from A/D (Q)
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
4X
Gigabit Serial I/O
4X 4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 52690

8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. The factory-installed A/D Acquisition Modules use memory banks 1 & 2. Banks 3 & 4 can be optionally installed to support custom user-installed IP within the FPGA . 50 ohms, accepts 10 to 200 MHz (up to 800 MHz when Timing Generator divider is enabled) or PLL system reference Timing Generator Bus: 26-pin front panel connector LVPECL bus includes, clock/ sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Input Quantity: 2 Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

Specifications
Front Panel Analog Signal Input Connector: Front panel female SSMC Impedance: 50 ohms L-Band Tuner Type: Maxim MAX2112 Input Frequency Range: 925 MHz to 2175 MHz Monolithic VCO Phase Noise: -97 dBc/Hz at 10 kHz Fractional-N PLL Synthesizer: freqVCO = (N.F) x freqREF where integer N = 19 to 251 and fractional F is a 20-bit binary value PLL Reference (freqREF): Front panel SSMC connector or on-board 27 MHz crystal (Option -100), 12 to 30 MHz LNA Gain: 0 to 65 dB, controlled by a programmable 12-bit D/A converter* Baseband Amplifier Gain: 0 to 15 dB, in 1 dB steps* *Usable Full-Scale Input Range: 50 dBm to +10 dBm Baseband Low Pass Filter: Cutoff frequency programmable from 4 to 40 MHz with 8-bit resolution A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board timing generator/synthesizer A/D Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, for the A/D clock Timing Generator External Clock Input Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled,
Options: -062 -064 -104 -105 -150
VPX Families
-160
53xxx
-155
-165
Pentek, Inc.
www.pentek.com
! w e N
Models 72690, 73690 and 74690
General Information
Models 72690, 73690 and 74690 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71690 XMC modules mounted on a cPCI carrier board. Model 72690 is a 6U cPCI board while the Model 73690 is a 3U cPCI board; both are equipped with one Model 71690 XMC. Model 74690 is a 6U cPCI board with two XMC modules rather than one. These models include one ot two L-Band RF tuners, two or four A/Ds and four or eight banks of memory. test signal generator, and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions in these models include two or four A/D acquisition IP modules. IP modules for either DDR3 or QDRII+ memories, controllers for all data clocking and synchronization functions, a

Model 74690
Model 73690
Features
One or two L-Band tuners accept RF signals from 925 MHz to 2175 MHz One or two programmable LNAs boost LNB (low-noise block) antenna signal levels with up to 60 dB gain One or two programmable analog downconverters provide I + Q baseband signals with bandwidths ranging from 4 to 40 MHz Two or four 200 MHz 16-bit A/Ds Supports Xilinx Virtex-6 LXT and SXT FPGAs Up to 2 or 4 GB of DDR3 SDRAM; or: 32 MB or 64MB of QDRII+ SRAM Clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Ref In
RF In
MAX2112
Ref Out GC
12-BIT D/A
Ref A/D Clock/Sync
Control
16
16
IC
2
Timing Bus
VCXO

LVDS

LVDS
GTX
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
Config FLASH 64 MB
40
x4 PCIe
4X
GTX
PCIe to PCI BRIDGE
PCI to PCI BRIDGE
J2
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
www.pentek.com
Models 72690, 73690 and 74690
RF Tuner Stage
One or two front panel SSMC connectors accept L-Band signals between 925 MHz and 2175 MHz from the antenna LNBs (low noise blocks). The Maxim MAX2112 tuners directly convert these L-Band signals to baseband using broadband I/Q downconverters. The devices include RF variable-gain LNAs (low noise amplifiers), PLL (phaselocked loops) synthesized local oscillators, quadrature (I + Q) downconverting mixers, baseband lowpass filters with programmable cutoff frequency, and variable-gain baseband amplifiers. The fractional-N PLL synthesizers lock their VCOs to the timing generator output, or to an external reference input between 12 and 30 MHz. Together, the baseband amplifiers and the RF LNA offer a programmable linear gain range of 60 dB. The integrated lowpass filters with variable bandwidths provide bandwidths ranging from 4 to 40 MHz, programmable with 8 bits of resolution.

An internal timing generator provides all timing, gating, triggering and synchronization functions required by the A/D converters. It also serves as an optional source for the L-Band tuner reference. The front panel SSMC clock input can be used directly as the A/D sample clock. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (voltage-controlled crystal oscillator). In this mode, the front panel SSMC clock input connector accepts a 10 MHz reference signal for synchronizing the VCXO using a PLL. The timing generator uses a front panel LVPECL 26-pin clock/sync connector for one clock, two sync, and two gate/trigger signals. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate/ trigger signals within the bosrd. In the master mode, the LVPECL bus drives output timing signals to synchronize multiple slave bosrds, supporting synchronous sampling and sync functions across all connected boards.

These models feature two or fourA/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from either of the two A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
A/D Converter Stage

The analog baseband I and Q analog tuner outputs are then applied to two or four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources.
Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, all DDR3 SDRAM, or as combination of two banks of each type of memory.
from A/D (I)
from A/D (Q)
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
40 FPGA I/O
Pentek, Inc.
www.pentek.com
Models 72690, 73690 and 74690
Each QDRII+ SRAM bank can be up to 8
MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. The factory-installed A/D acquisition modules use memory banks 1 & 2. Banks 3 & 4 can be optionally installed to support custom user-installed IP within the FPGA . Sample Clock Sources (1 or 2) On-board timing generator/synthesizer A/D Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, for the A/D clock Timing Generator External Clock Inputs (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 200 MHz (up to 800 MHz when Timing Generator divider is enabled) or PLL system reference Timing Generator Bus (1 or 2): 26-pin front panel connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Inputs (2 or 4) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or2) Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73690; J3 connector, Model 72690; J3 and J5 connectors, Model 74950 Memory Banks (1 or 2) Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73690: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
PCI-X Interface
The models include an industry-standard interface compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73690: 32 bits only.
Specifications
Model 72690 or Model 73690: 1 RF tuner, 2 A/Ds Model 74690: 2 RF tuners, four A/Ds Front Panel Analog Signal Inputs (1 or 2) Connector: Front panel female SSMC Impedance: 50 ohms L-Band Tuners (1 or 2) Type: Maxim MAX2112 Input Frequency Range: 925 MHz to 2175 MHz Monolithic VCO Phase Noise: -97 dBc/Hz at 10 kHz Fractional-N PLL Synthesizer: freqVCO = (N.F) x freqREF where integer N = 19 to 251 and fractional F is a 20-bit binary value PLL Reference (freqREF): Front panel SSMC connector or on-board 27 MHz crystal (Option -100), 12 to 30 MHz LNA Gain: 0 to 65 dB, controlled by a programmable 12-bit D/A converter* Baseband Amplifier Gain: 0 to 15 dB, in 1 dB steps* *Usable Full-Scale Input Range: 50 dBm to +10 dBm Baseband Low Pass Filter: Cutoff frequency programmable from 4 to 40 MHz with 8-bit resolution A/D Converters (2 or 4) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits
Model 71690 Description L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - XMC XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73690; J3 connector, Model 72690; J3 and J5 connectors, Model 74690 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Options: -062 -064 -104
-150
-160
-155
-165
Pentek, Inc.
www.pentek.com
! w e N
Model 56690

General Information
Model 56690 is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6 FPGA. A 2-Channel high-speed data converter, it is suitable for connection directly to the RF port of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes an L-Band RF tuner, two A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 56690 includes a front panel general-purpose connector for application-specific I/O. and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 56690 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 56690 factory-installed functions include two A/D acquisition IP modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking

Features

Accepts RF signals from 925 MHz to 2175 MHz Programmable LNA boosts LNB (low-noise block) antenna signal levels with up to 60 dB gain Programmable analog downconverter provides I + Q baseband signals with bandwidths ranging from 4 to 40 MHz Two 200 MHz 16-bit A/Ds digitize the I + Q signals synchronously Supports Xilinx Virtex-6 LXT and SXT FPGAs 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference Clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface, up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-6 FPGA for custom I/O
Ref In
RF In
MAX2112
Ref Out GC
12-BIT D/A
Ref A/D Clock/Sync
Control
16
16
IC
2
Timing Bus
VCXO

GTX
LVDS
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
Config FLASH 64 MB
8X
IPMI CONTROLLER
40
x8 PCIe
RS-232
AMC Ports 4 to 11
Front Panel
Memory Banks 1 & 2
Memory Banks 3 & 4
Pentek, Inc.
www.pentek.com
Model 56690

RF Tuner Stage


A/D Converter Stage

Memory Resources
from A/D (I)
from A/D (Q)
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 56690

8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. The factory-installed A/D acquisition modules use memory banks 1 & 2. Banks 3 & 4 can be optionally installed to support custom user-installed IP within the FPGA . A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board timing generator/synthesizer A/D Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, for the A/D clock Timing Generator External Clock Input Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 200 MHz (up to 800 MHz when Timing Generator divider is enabled) or PLL system reference Timing Generator Bus: 26-pin front panel connector LVPECL bus includes, clock/ sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Input Quantity: 2 Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8; Gen. 2 x4 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.
AMC Interface

Specifications
Model 56690 Description L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - AMC XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through front panel connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Options: -062 -064 -104 -150
-160
-155
-165
Pentek, Inc.
www.pentek.com
! w e N
Model 71760

General Information
Model 71760 is a member of the Onyx family of high-performance XMC modules based on the Xilinx Virtex-7 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes four A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 3 as a native interface, the Model 71760 includes general-purpose and gigabitserial connectors for application-specific I/O. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable the 71760 to operate as a complete turnkey solution without the need to develop any FPGA IP.

Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 FPGAs from Xilinx. As the central feature of the board architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71760 factory-installed functions include four A/D acquisition IP modules for simplifying data capture and data transfer.

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Four 200 MHz 16-bit A/Ds 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up to x8 Advanced reconfigurability features VITA 42.0 XMC compatible with switched fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-7 FPGA for custom I/O
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

GTX
GTX
GTX
LVDS
CONFIG FLASH 1 GB
FPGA Config Bus
PCIe Gen. 3 x8
4X
4X
48
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
Pentek, Inc.
www.pentek.com
Model 71760

A/D Converter Stage



from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
Gigabit Serial I/O
4X
4X
FPGA GPIO
48
Pentek, Inc.
www.pentek.com
Model 71760

external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltagecontrolled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71760s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.
A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Installs the PMC P14 connector with 24 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Gen. 3 available only with the VX330T-2 and VX690T-2 FPGAs Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
Model 8266
Memory Resources
XMC Interface
The Model 71760 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to 10 Gb/sec per lane. With dual XMC connectors, the 71760 supports x8 PCIe on the first XMC connector leaving the second connector free to support userinstalled transfer protocols specific to the target application.
Model 71760 Options: -073 -076 -104 -105 XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector Description 4-Channel 200 MHz A/D with Virtex-7 FPGA - XMC


Specifications
Pentek, Inc.
www.pentek.com
! w e N
Model 78760

General Information
Model 78760 is a member of the Onyx family of high-performance PCIe boards based on the Xilinx Virtex-7 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes four A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 3 as a native interface, the Model 78760 includes optional general-purpose and gigabit-serial connectors for applicationspecific I/O protocols. and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 78760 to operate as a complete turnkey solution without the need to develop any FPGA IP.


Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Four 200 MHz 16-bit A/Ds 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1, 2 & 3) interface up to x8 Advanced reconfigurability features Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-7 FPGA for custom I/O
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

GTX
GTX
GTX
LVDS
CONFIG FLASH 1 GB
FPGA CONFIG BUS
PCIe Gen. 3 x8
4X
4X
48
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
FPGA - PCIe CONFIGURATION MANAGER
Pentek, Inc.
www.pentek.com
Model 78760

A/D Converter Stage



from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
Gigabit Serial I/O
4X
4X
FPGA GPIO
48
Pentek, Inc.
www.pentek.com
Model 78760

external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78760s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Connects 24 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Gen. 3 available only with the VX330T-2 and VX690T-2 FPGAs Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.
Model 8266
Memory Resources

The Model 78760 includes an industrystandard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the board.
Model 78760 Description 4-Channel 200 MHz A/D with Virtex-7 FPGA - x8 PCIe XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O through 68-pin ribbon cable connector Gigabit serial FPGA I/O through two 4X top edge connectors Description PC Development System See 8266 Datasheet for Options
Specifications
Options: -073 -076 -104
-105
Model 8266
Pentek, Inc.
www.pentek.com
! ew N
Model 53760

General Information


Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Four 200 MHz 16-bit A/Ds 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Advanced reconfigurability features Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-7 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D 16
200 MHz 16-BIT A/D 16
200 MHz 16-BIT A/D 16
200 MHz 16-BIT A/D 16

VCXO
LVDS
Timing Bus

GTX
GTX
GTX
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
FPGA Config Bus
PCIe Gen. 2 x8
4X
4X
PCIe Gen. 2 x8
CROSSBAR SWITCH
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 53760

A/D Converter Stage



from A/D Ch 1
from A/D Ch 2
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
Gigabit Serial I/O
4X
4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 53760

used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 53760s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8; Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)


Memory Resources
Specifications
VPX Families
53xxx
Options: -073 -076 -104 -105
Pentek, Inc.
www.pentek.com
! ew N
Model 52760

General Information


Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Four 200 MHz 16-bit A/Ds 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-7 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D 16
200 MHz 16-BIT A/D 16
200 MHz 16-BIT A/D 16
200 MHz 16-BIT A/D 16

VCXO
LVDS
Timing Bus
GTX
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
FPGA Config Bus
PCIe Gen. 2 x4
4X
4X
PCIe Gen. 2 x4
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52760

A/D Converter Stage



from A/D Ch 1
from A/D Ch 2
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
4X
Gigabit Serial I/O
4X 4X
FPGA GPIO
40
Pentek, Inc.
www.pentek.com
Model 52760

used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 52760s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

Memory Resources
Specifications
VPX Families
53xxx
Options: -073 -076 -104 -105
Pentek, Inc.
www.pentek.com
! w e N
Models 72760, 73760 and 74760

General Information
Models 72760, 73760 and 74760 are members of the Onyx family of high-performance CompactPCI boards based on the Xilinx Virtex-7 FPGA. They consist of one or two Model 71760 XMC modules mounted on a cPCI carrier board. Model 72760 is a 6U cPCI board while the Model 73760 is a 3U cPCI board; both are equipped with one Model 71760 XMC. Model 74760 is a 6U cPCI board with two XMC modules rather than one. These models include four or eight A/Ds and four or eight banks of memory. IP modules for DDR3 SDRAM memories, controllers for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable these models to operate as complete turnkey solutions without the need to develop FPGA IP.

The Pentek Onyx Architecture features Virtex-7 FPGAs. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include four or eight A/D acquisition IP modules for simplifying data capture and data transfer.

Model 74760
Model 73760
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCI/PCI-X bus Four or eight 200 MHz 16-bit A/Ds Four or eight GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-7 FPGA for custom I/O
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16 VCXO
16
16
16
Timing Bus

LVDS

LVDS
GTX
GTX
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
40
FPGA Config Bus

CONFIG FLASH 1 GB
x4 PCIe
FPGA Config Bus
x4 PCIe
x4 PCIe
PCIe to PCI BRIDGE
x4 PCIe
Pentek, Inc.
www.pentek.com
Models 72760, 73760 and 74760

A/D Converter Stage

The front end accepts four or eight fullscale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into four or eight Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-7 FPGA for signal processing, data capture or for routing to other board resources.

These models feature four or eight A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of four A/Ds or the test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
40 FPGA I/O
Pentek, Inc.
www.pentek.com
Models 72760, 73760 and 74760

An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An onboard clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. A/D Converters (4 or 8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: (1 or 2) On-board clock synthesizer Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus (1 or 2) 26-pin front panel connector; LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73760; J3 connector, Model 72760; J3 and J5 connectors, Model 74760 Memory Banks (1 or 2) Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73760: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
Memory Resources
Model 72760 Description 4-Channel 200 MHz 16-bit A/D with Virtex-7 FPGA 6U cPCI 4-Channel 200 MHz 16-bit A/D with Virtex-7 FPGA 3U cPCI 8-Channel 200 MHz 16-bit A/D with two Virtex-7 FPGAs - 6U cPCI XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS I/O between the FPGA and J2 connector, Model 73760; J3 connector, Model 72760; J3 and J5 connectors, Model 74760
PCI-X Interface
73760
74760
Specifications
Model 72760 or Model 73760: 4 A/Ds Model 74760: 8 A/Ds Front Panel Analog Signal Inputs (4 or 8) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz
Options: -073 -076 -104
Pentek, Inc.
www.pentek.com
! w e N
Model 56760

General Information
Model 56760 is a member of the Onyx family of high-performance AMC modules based on the Xilinx Virtex-7 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes four A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 3 as a native interface, the Model 56760 includes a front panel general-purpose connector for applicationspecific I/O. modules for simplifying data capture and data transfer. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable the 56760 to operate as a complete turnkey solution without the need to develop any FPGA IP.

Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 FPGAs from Xilinx. As the central feature of the board architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 56760 factory-installed functions include four A/D acquisition IP

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Four 200 MHz 16-bit A/Ds 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-7 FPGA for custom I/O
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
200 MHz 16-BIT A/D
16
16
16
16
Timing Bus
VCXO

GTX
LVDS
CONFIG FLASH 1 GB
FPGA Config Bus
PCIe Gen. 3 x8
IPMI CONTROLLER
48
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
RS-232 AMC
PCIe Gen. 3 x8
Ports 4 to 11
Front Panel
Pentek, Inc.
www.pentek.com
Model 56760

A/D Converter Stage



An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generator receives
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
FPGA GPIO
48
Pentek, Inc.
www.pentek.com
Model 56760

an external sample clock from the front
panel SSMC connector. This clock can be used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 56760s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Gen. 3 available only with the VX330T-2 and VX690T-2 FPGAs AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.
Memory Resources
AMC Interface

Model 56760 Options: -073 -076 -104 XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O through front panel connector Description 4-Channel 200 MHz A/D with Virtex-7 FPGA - AMC
Specifications
Pentek, Inc.
www.pentek.com
! ew N
Model 71730

General Information
Model 71730 is a member of the Onyx family of high performance XMC modules based on the Xilinx Virtex-7 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes 1 GHz A/D and D/A converters and four banks of memory. In addition to supporting PCI Express Gen. 3 as a native interface, the Model 71730 includes optional general purpose and gigabit serial card connectors for application-specific I/O. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factoryinstalled functions and enable the 71730 to operate as a complete turnkey solution, without the need to develop any FPGA IP.


Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe One 1 GHz 12-bit A/D One 1 GHz 16-bit D/A 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up to x8 VITA 42.0 XMC compatible with switched fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-7 FPGA for custom I/O
RF In
RF Out
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Sync In
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12
1 GHz 16-BIT D/A 16
D/A Sync Bus
VCXO
GTX
GTX

GTX
LVDS
CONFIG FLASH 1 GB
FPGA Config Bus
PCIe Gen. 3 x8
4X
4X
48
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
Pentek, Inc.
www.pentek.com
Model 71730

A/D Converter Stage

D/A Converter Stage

The 71730 features a TI DAC5681Z 1 GHz, 16-bit D/A. The converter has an input sample rate of 1 GS/sec, allowing it to accept full-rate data from the FPGA. Additionally, the D/A includes a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is through a front panel SSMC connector.
to D/A


INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 71730

Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Installs the PMC P14 connector with 24 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
XMC Interface
The Model 71730 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to 10 Gb/sec per lane. With dual XMC connectors, the 71730 supports x8 PCIe on the first XMC connector leaving the second connector free to support user-installed transfer protocols specific to the target application.

Model 8266
Memory Resources
Model 71730 Options: -073 -076 -104 -105 XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector Description 1 GHz A/D and D/A, Virtex-7 FPGA - XMC
Specifications

Pentek, Inc.
www.pentek.com
! ew N
Model 78730

General Information
Model 78730 is a member of the Onyx family of high-performance PCIe boards based on the Xilinx Virtex-7 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes 1 GHz A/D and 1 GHz D/A converters and four banks of memory. In addition to supporting PCI Express Gen. 3 as a native interface, the Model 78730 includes optional general-purpose and gigabit serial card connectors for application specific I/O. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factoryinstalled functions and enable the 78730 to operate as a complete turnkey solution, without the need to develop any FPGA IP.


RF In RF Out
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe One 1 GHz 12-bit A/D One 1 GHz 16-bit D/A 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Sync In
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12
1 GHz 16-BIT D/A 16
D/A Sync Bus
VCXO
GTX
GTX

GTX
LVDS
CONFIG FLASH 1 GB
FPGA Config Bus
PCIe Gen. 3 x8
4X
4X
48
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
Pentek, Inc.
www.pentek.com
Model 78730

A/D Converter Stage

The front end accepts an analog HF or IF input on a front panel SSMC connector with transformer coupling into a Texas Instruments ADS5400 1 GHz, 12-bit A/D converter. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources.
D/A Converter Stage

to D/A

INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 78730

Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives a sample clock either from the front panel SSMC connector or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this latter mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock to phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or 16 to provide different lower frequency A/D and D/A clocks. A pair of front panel Sync connectors allows multiple modules to be synchronized. They accept CML inputs that drive the boards sync and gate/trigger signals. The Pentek Model 7892 and Model 9192 Cobalt Synchronizers can drive multiple 78730 Sync connectors enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connector. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.
Model 8266
Memory Resources
Model 78730 Options: -073 -076 -104 XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O through 68-pin ribbon cable connector Gigabit serial FPGA I/O through two 4X top edge connectors Description 1 GHz A/D and D/A, Virtex-7 FPGA - x8 PCIe

-105
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz to 1 GHz Resolution: 12 bits D/A Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max.

Pentek, Inc.
www.pentek.com
! ew N
Model 53730

General Information


RF In RF Out
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe One 1 GHz 12-bit A/D One 1 GHz 16-bit D/A 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional LVDS connections to the Virtex-7 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Sync In
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12
1 GHz 16-BIT D/A 16
D/A Sync Bus
VCXO

LVDS

GTX
GTX
GTX
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
FPGA Config Bus
PCIe Gen. 2 x8
4X
4X
PCIe Gen. 2 x8
CROSSBAR SWITCH
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 53730


A/D Converter Stage

D/A Converter Stage

to D/A

INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 53730

External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8; Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Memory Resources

Crossbar Switch
Specifications
VPX Families
53xxx
Pentek, Inc.
www.pentek.com
! ew N
Model 52730

General Information

Model 52730 COTS (left) and rugged version Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 FPGAs from Xilinx. As the central feature of the board architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 52730 factory-installed functions include an A/D acquisition and a D/A waveform playback IP module for simplifying data capture and data transfer.

RF In RF Out
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe One 1 GHz 12-bit A/D One 1 GHz 16-bit D/A 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multiboard synchronization PCI Express (Gen. 1 and 2) interface up to x4 Optional LVDS connections to the Virtex-7 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Sync In
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12
1 GHz 16-BIT D/A 16
D/A Sync Bus
VCXO

LVDS
GTX
GTX
GTX
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
FPGA Config Bus
PCIe Gen. 2 x4
4X
4X
PCIe Gen. 2 x4
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52730


A/D Converter Stage

D/A Converter Stage


to D/A

INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 52730

Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives a sample clock either from the front panel SSMC connector or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this latter mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock to phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or 16 to provide different lower frequency A/D and D/A clocks. A pair of front panel Sync connectors allows multiple modules to be synchronized. They accept CML inputs that drive the boards sync and gate/trigger signals. The Pentek Model 5292 and Model 9192 Cobalt Synchronizers can drive multiple 52730 Sync connectors enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connector. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Memory Resources
The 52730 architecture supports four independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factoryinstalled functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

Specifications
VPX Families
53xxx
Pentek, Inc.
www.pentek.com
! ew N
Models 72730, 73730 and 74730
General Information
Models 72730, 73730 and 74730 are members of the Onyx family of high performance CompactPCI boards based on the Xilinx Virtex-7 FPGA. They consist of one or two Model 71730 XMC modules mounted on a cPCI carrier board. Model 72730 is a 6U cPCI board while the Model 73730 is a 3U cPCI board; both are equipped with one Model 71730 XMC. Model 74730 is a 6U cPCI board with two XMC modules rather than one. These models include one or two 1 GHz A/D and D/A converters and four or eight banks of memory IP modules for DDR3 SDRAM memories, controllers for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable these models to operate as complete turnkey solutions without the need to develop FPGA IP.

The Pentek Onyx Architecture features Virtex-7 FPGAs. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include ne or two A/D acquisition and one or two D/A waveform playback IP modules for simplifying data capture and data transfer.

Model 74730
Model 73730
Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCI/PCI-X bus One or two 1 GHz 12-bit A/D One or two 1 GHz 16-bit D/A Four or eight GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multimodule synchronization Optional LVDS connections to the Virtex-7 FPGA for custom I/O
RF In
RF Out
RF XFORMR
RF XFORMR
Gate In Sync In
A/D Clock/Sync Bus
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12 VCXO
1 GHz 16-BIT D/A 16
D/A Sync Bus

LVDS

LVDS
GTX
GTX
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
40
FPGA Config Bus

CONFIG FLASH 1 GB
x4 PCIe
FPGA Config Bus
x4 PCIe
x4 PCIe
PCIe to PCI BRIDGE
x4 PCIe
Pentek, Inc.
www.pentek.com
Models 72730, 73730 and 74730

The Onyx architecture includes GateXpress, a sophisticated FPGA configuration manager for loading and reloading the FPGA. At power up, GateXpress immediately presents a target for the host computer to discover, effectively giving the FPGA time to load from FLASH. This is especially important for larger FPGAs where the loading times can exceed the PCI-X discovery window, typically 100 msec on most PCs. The boards configuration FLASH can hold four FPGA images. Images can be factory-installed IP or custom IP created by the user, and programmed into the FLASH via JTAG using Xilinx iMPACT or through the boards PCI-X interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the FPGA with a new IP image. The first is the option to load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the FPGA image must be loaded directly through the PCI-X interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the FPGA IP may need to change many times during the course of a mission, images can be stored on the host computer and loaded as needed.
The third option, typically used during development, allows the user to directly load the FPGA through JTAG using Xilinx iMPACT. In all three FPGA loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the PCI-X configuration space allowing dynamic FPGA reconfiguration without needing to reset the host computer to rediscover the board. After the reload, the host simply continues to see the board with the expected device ID.
A/D Converter Stage

The front end accepts one or two analog HF or IF input on front panel SSMC connectors with transformer coupling into one or two Texas Instruments ADS5400 1 GHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-7 FPGA for signal processing, data capture or for routing to other module resources.
D/A Converter Stage

These models feature one or two TI DAC5681Z 1 GHz, 16-bit D/As. The converters have an input sample rate of 1 GSPS, allowing them to acept full rate data from the FPGA. Additionally, the D/As include a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is through front panel SSMC connectors.
to D/A

INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
Pentek, Inc.
www.pentek.com
Models 72730, 73730 and 74730
Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives a sample clock either from the front panel SSMC connector or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this latter mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock to phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or 16 to provide different lower frequency A/D and D/A clocks. A pair of front panel Sync connectors allows multiple modules to be synchronized. They accept CML inputs that drive the boards sync and gate/trigger signals. The Pentek Model 7192 and Model 9192 Cobalt Synchronizers can drive multiple 71630 Sync connectors enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connector. Front Panel Analog Signal Outputs (1 or 2) Output Type: Transformer-coupled, front panel female SSMC connectors Sample Clock Sources (1 or 2) On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73730; J3 connector, Model 72730; J3 and J5 connectors, Model 74730 Memory Banks (1 or 2) Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73730: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
PCI-X Interface
Memory Resources

Model 72730 73730 74730 Options: -073 -076 -104 XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS I/O between the FPGA and J2 connector, Model 73730; J3 connector, Model 72730; J3 and J5 connectors, Model 74730 Description 1 GHz A/D and D/A, Virtex-7 FPGA - 6U cPCI 1 GHz A/D and D/A, Virtex-7 FPGA - 3U cPCI Two 1 GHz A/D and D/A, Virtex-7 FPGA - 6U cPCI
Model 72730 or Model 73730: 1 A/D, 1 D/A Model 74730: 2 A/Ds, 2 D/As Front Panel Analog Signal Inputs (1 or 2) Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converters (1 or 2) Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz to 1 GHz Resolution: 12 bits D/A Converters (1 or 2) Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: 16 bits
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Model 56730

General Information
Model 56730 is a member of the Onyx family of high performance AMC modules based on the Xilinx Virtex-7 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes 1 GHz A/D and D/A converters and four banks of memory. In addition to supporting PCI Express Gen.3 as a native interface, the Model 56730 includes a front panel general-purpose connector for application-specific I/O . form playback IP module for simplifying data capture and data transfer. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factoryinstalled functions and enable the 56730 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 FPGAs from Xilinx. As the central feature of the board architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 56730 factory-installed functions include an A/D acquisition and a D/A wave-

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe One 1 GHz 12-bit A/D One 1 GHz 16-bit D/A 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multiboard synchronization PCI Express (Gen. 1, 2 & 3) interface up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-7 FPGA for custom I/O
RF In
RF Out
RF XFORMR
RF XFORMR
A/D Clock/Sync Bus
Gate In Sync In
1 GHz 12-BIT A/D
A/D Sync Bus

Gate In Sync In
D/A Clock/Sync Bus

12
1 GHz 16-BIT D/A 16
D/A Sync Bus
VCXO
GTX

LVDS
CONFIG FLASH 1 GB
FPGA Config Bus
PCIe Gen. 3 x8
IPMI CONTROLLER
48
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
RS-232 AMC
PCIe Gen. 3 x8
Ports 4 to 11
Front Panel
Pentek, Inc.
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Model 56730


A/D Converter Stage

D/A Converter Stage

to D/A

INPUT MULTIPLEXER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
www.pentek.com
Model 56730

Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives a sample clock either from the front panel SSMC connector or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this latter mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock to phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or 16 to provide different lower frequency A/D and D/A clocks. A pair of front panel Sync connectors allows multiple modules to be synchronized. They accept CML inputs that drive the boards sync and gate/trigger signals. The Pentek Model 5692 and Model 9192 Cobalt Synchronizers can drive multiple 56730 Sync connectors enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connector. Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz Synchronization: VCXO can be phaselocked to an external 4 to 200 MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin Sync bus connector includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Installs a front panel connector with 24 LVDS pairs to the FPGA Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.
AMC Interface

Memory Resources
Specifications
Model 56730 Options: -073 -076 -104 XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O to front pannel connector Description 1 GHz A/D and D/A, Virtex-7 FPGA - AMC
Pentek, Inc.
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215 MHz, 12-bit A/Ds with Virtex-II Pro FPGAs - VME/VXS

General Information
Models 6821 (single-channel) and 6822 (dual-channel) are complete high-frequency A/D converters in a 6U VMEbus form factor. They accept one or two front panel analog inputs and deliver digital output samples over two or four FPDP ports utilizing FPDP or FPDP II standards. These Models are ideal as high-speed data acquisition front ends for real-time recording, digital receivers, and DSP systems. equipped with 128 MB of SDRAM and 16 MB of FLASH memory. Each FPGA accepts 12-bit signals at the sampling frequency from the A/D converter. Several data packing modes are selectable across the multiple FPDP ports. The FPGAs also act as controllers for other board functions including gating and triggering. Optional LVDS I/O is available through either the VMEbus P2 connector or a second-slot front panel mezzanine.
Input Stage and A/D Converters

Front panel female SMA connectors accept analog RF inputs at a full scale level of +8 dBm or +2 dBm (software selectable) into the primary of RF transformers that present 50 ohm input impedance. The transformers offer low-distortion paths to the differential inputs of the Analog Devices AD9430 A/Ds, with flat frequency response from 400 kHz to 700 MHz (standard).
FIFOs and FPDP Outputs

Following each FPGA are two 32-bit wide FIFO buffers with standard depth of 32k words. These FIFOs are useful as elastic memory to support hard disk latencies in recording applications. A total of four FPDP output ports are available, two per FPGA, to support data transfers of 320 MB/sec each or greater. One port per FPGA is attached to the boards front panel, with the second attached to an optional second-slot front panel. A data demultiplexing mode splits the data stream between each pair of FPDP ports, reducing the output data rate by a factor of up to four (depending on the data packing mode and number of FPDP ports) to support slower FPDP devices.
Clocking, Gating and Triggering

Model 6822 standard single slot (left) and conduction-cooled version. The A/D converter sample clock can be sourced from an internal 210 MHz crystal oscillator or from an externally supplied sinusoidal clock of 215 MHz, maximum. This clock is accepted through a front panel SMA connector terminated in 50 ohms. An external LVDS bus supports synchronous data acquisition across multiple boards. This is ideal for applications such as multichannel radar systems.
Optional VXS Interface

Both Models provide optional full duplex VITA-41 VXS links to the VME P0 connector for both FPGAs. These links support 4X Serial RapidIO, or other switched fabrics such as PCI Express and Xilinx Aurora.
Virtex-II Pro FPGAs

Both Models utilize two Xilinx Virtex-II Pro Series FPGAs. Each FPGA is optionally
Features

One or two AD9430 12-bit, 215 MHz A/D converters Xilinx Virtex-II Pro FPGAs Dual 4X VXS links for Serial RapidIO I/F input up to 700 MHz Four FPDP or FPDP II front panel ports FIFO data buffering Multiboard synchronization Ruggedized and conductioncooled versions available
OPT ONAL LVDS /O RF In RF TRANSFORMER Fs Ext. Sample Clock In AD9430 215 MHz 12-Bit A/D
44 FLASH 16 MB SDRAM 128 MB 12 16 32 32 XIL NX V RTEX-II PRO PGA Data Packing Formatting 32 FIFO 32k x 36 32 PDP NTERFACE 32 Slot 1 FPDP Output A Slot 2 FPDP Output C
FIFO 32k x 36
32
PDP NTERFACE
32
Clock
Data
XTAL OSC Fs RF In AD9430 215 MHz 12-Bit A/D 12 FLASH 16 MB SDRAM 128 MB OPT ONAL LVDS /O 44 16 32
64
32 XIL NX V RTEX-II PRO PGA Data Packing Formatting 32
FIFO 32k x 36
32
PDP NTERFACE
32
RF TRANSFORMER
Slot 1 PDP Output B Slot 2 FPDP Output D
FIFO 32k x 36
32
PDP NTERFACE
32
Fs/2
Fs/2 LVDS Trigger

CLOCK AND SYNC BUS
Local Tr gger
CLOCK DISTRIBUT ON
PDP CLOCK SELECT
PROGRM OSC
VMEbus SLAVE NTERFACE
P0 - VXS (V TA 41)
VMEbus
VXS Switched Backplane
Pentek, Inc.
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215 MHz, 12-bit A/Ds with Virtex-II Pro FPGAs - VME/VXS

Switchless VXS Card Cage
A five-slot card cage with full fabric support for three payload cards without the need for a switch card is now available for developing and testing VXS cards. Size: 16 MB each (32 MB total) Bus Width: 16 bits Front Panel Data Port (FPDP) Outputs Quantity: 2 standard; 4 with option -224 (additional ports located on secondslot front panel) Output Type: non-inverted configuration, FPDP I or FPDP II Clock: Onboard programmable oscillator (up to 50 MHz), or sample clock with one line to each FPDP port FIFOs Quantity: 2 standard (one per FPDP port), 4 with option -224 Size: 32,768 x 36 Speed: Sample clock rate 2 VME Slave Interface Type: Slave A16/D16, A16/D32 (A32/D32 programmable) Control: Operating modes, gate/trigger, FIFO reset, data packing, FPDP I/II selection, FPDP framing, time sync command, status Power Default Configuration: 19 W Note: User FPGA designs will increase power consumption, normally within the following ranges: With XC2VP20 FPGAs: from 28 W to 38 W maximum With XC2VP50 FPGAs: from 41 W to 62 W maximum Environmental (Commercial version) Pentek Ruggedization Level: L0 Cooling Method: Forced air Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, noncondensing Environmental - Option -703 Pentek Ruggedization Level: L3 Cooling Method: Conduction cooling Operating Temp: 40 to 70 C Storage Temp: 50 to 100 C Relative Humidity: 0 to 95%, noncondensing Sine Vibration: 10 g, 202,000 Hz Random Vibration: 0.1 g2/Hz, 202,000 Hz Shock: 30 g, 11 ms Environmental - Option -720 Relative Humidity: 0 to 100% noncondensing with conformal coating Size: Standard 6U VMEbus board, single slot; board 160 mm (6.3 in.) x 233.5 mm (9.2 in.), panel 20.3 mm (0.8 in) wide; Option -222 or -224: 40.6 mm (1.6 in) wide Weight: 425 grams (15 oz.); 794 grams (28 oz.) conduction-cooled version
Specifications
Front Panel Analog Signal Inputs Quantity: Model 6821: 1, Model 6822: 2 Input Type: Transformer-coupled, front panel female SMA connector Full Scale Input: +8 dBm (1.59 V p-p) or + 2 dBm (0.796 V p-p), software selectable, into 50 ohms Input Bandwidth: 150 MHz Transformer 3 dB Passband: 400 kHz to 700 MHz (other values optionally available) A/D Converter Quantity: Model 6821: 1, Model 6822: 2 Type: Analog Devices AD9430-210 Sampling Rate: 60 MHz to 215 MHz Internal Clock: 210 MHz crystal osc. std.; 213.333 MHz crystal osc. optional External Clock: 60 to 215 MHz Resolution: 12 bits Bandwidth: 700 MHz at full power Clock Source: Onboard crystal oscillator, front panel external clock External Clock: Front panel female SMA connector, sine wave, 0 to +4 dBm, AC coupled, 50 ohms impedance Sync/Gate Bus: One 26-pin connector with one clock, one FPGA sync, and four gate input/output LVDS signals; one sync and one gate input TTL signals Field Programmable Gate Arrays Quantity: 2, both Models Type: Option -050: Virtex-II Pro XC2VP50-5 Option -020: Virtex-II Pro XC2VP20-5 FPGA I/O: Option -222: Adds one 68-pin connector per FPGA through a second-slot front panel; each connector provides thirty two LVDS data I/O differential pairs, two LVDS clock I/O pairs and four control I/O pairs Option -121: Provides twenty four LVDS differential data I/O pairs, two clock I/O pairs and four control pairs from FPGA2 to VMEbus P2 connector (not available with XC2VP20) Memory SDRAM: Quantity: 2 banks, 1 per FPGA Size: 128 MB per bank (256 MB total) Bus Width: 32 bits Speed: 133 MHz FLASH: Quantity: 2, 1 per FPGA
Model 6821 Description Single 215 MHz, 12-bit A/D with Virtex-II Pro FPGAs - VME/VXS Dual 215 MHz, 12-bit A/D with Virtex-II Pro FPGAs - VME/VXS XC2VP20 FPGAs XC2VP50 FPGAs LVDS I/O thru P2 213.333 MHz crystal oscillator 2nd Slot LVDS I/O 2nd Slot FPDP I/O FPDP for conductioncooled version 128 MB SDRAM and 16 MB FLASH per FPGA Wideband Ultra HighSpeed DDC IP Core factory-installed VXS Interface Ruggedized & conductioncooled versions
6822
Options: -020 -050 -121 -213 -222 -224 -234 -340 -422*
-5xx -70x
Pentek, Inc.
www.pentek.com
Model 6826
Dual 2 GHz, 10-bit A/D with Virtex-II Pro FPGA - VME/VXS

General Information
The Model 6826 is a high-frequency single or dual channel A/D converter in a 6U VMEbus form factor. It accepts one or two front panel analog inputs and delivers digital output samples over two or four FPDP connectors utilizing FPDP or FPDP II standards. The 6826 is an ideal high-speed data acquisition front end for real-time recorders, digital receivers and DSP systems. application of an S/8 clock to support multiboard synchronization.
Virtex-II Pro FPGA

The 6826 utilizes a Model XC2VP70 Xilinx Virtex-II Pro FPGA. The FPGA is equipped with 512 MB of DDR SDRAM (optionally expandable to 1 GB) and 16 MB of FLASH memory. Several data packing modes allow formatting output data across multiple FPDP ports. The FPGA also acts as a controller for board functions such as gate/trigger. Optional LVDS I/O is available through either the VMEbus P2 connector or a second-slot front panel mezzanine.
Input Stage and A/D Converter

The 6826 features one or two Atmel AT84AS008 2 GHz, 10-bit A/D converters driven from single-ended transformer- or DC-coupled RF signals applied through front panel MMCX female connectors at 2 dBm full-scale into 50 ohms. Although the standard transformer-coupled input circuitry accepts signals to 1 GHz, higher frequency input options are also available. An innovative dual-stage demultiplexer packs groups of eight data samples into 80-bit words for delivery to the FPGA at one eighth the sampling frequency (S/8). This advanced circuit features the Atmel AT84CS001 Demultiplexer that represents a significant improvement over previous technology.
FIFOs and FPDP Outputs

Following the FPGA, two or four 32-bit wide FIFO buffers with a depth of 32k words are useful as elastic memory to support hard disk latencies in recording applications. A total of four FPDP output ports are available, each supporting data transfers of up to 400 MB/sec. Two FPDP ports are attached to the 6826 front panel; optionally, two additional ports attach to a second slot front panel (not available in conduction-cooled units).
Clocking, Gating and Triggering

The A/D converter sample clock is an externally supplied sinusoidal clock at a frequency from 200 MHz to 2 GHz. This clock is accepted through a front panel MMCX connector with 50 ohm termination and distributed to both A/D converters (dual-channel version). Synchronization and triggering circuitry supports synchronous data acquisition across multiple boards. Additional front panel MMCX connectors are provided for the
Optional VXS Interface

The 6826 provides two optional 4X full duplex VITA-41 links to the VXS P0 connector, each capable of peak rates to 1.25 GB/sec. These links support Gigabit fabrics such as Xilinx Aurora, Serial RapidIO and PCI Express.
Features

One or two 10-bit, 2 GHz A/D converters Xilinx Virtex-II Pro FPGA Dual 4X full duplex VXS links Two or four front panel FPDP or FPDP II outputs Up to 1 GB DDR SDRAM Multiboard synchronization: up to eight dual-channel 6826s may be synchronized with the Model 6890 clock, sync and gate distribution board Ruggedized and conductioncooled versions available
Switchless VXS Card Cage

A five-slot card cage with full fabric support for three payload cards without the need for a switch card is available for developing and testing VXS cards.
DDR SDRAM 512 MB RF In RF IN CIRCUIT AT84AS008 2 GHz 10-Bit A D DEMUX CKT 1/8 8x10 Fs/8
64
80
OPT ONAL LVDS I/O

32 FIFO 32k x 36 32 PDP NTERFACE 32 Slot 1 PDP Output A Slot 1 PDP Output B
Fs In CLOCK DISTRIB Fs/8 AT84AS008 2 GHz 10-Bit A D DEMUX CKT 1/8 8x10 Fs/8 DDR SDRAM 512 MB FLASH 16 MB
16
XILINX VIRTEX-II PRO XC2VP70 Data Packing Formatting
32
FIFO 32k x 36
32
PDP NTERFACE
32
32
RF In RF IN CIRCUIT
FIFO 32k x 36
32
PDP NTERFACE
32
Slot 2 PDP Output C Slot 2 PDP Output D
64
Fs/8 FS/8 Out A D Sync Gate/Trigger A Gate/Trigger B TTL Gate In PHASE ADJUST CONTROL
32
FIFO 32k x 36
32
PDP NTERFACE
32
SYNC AND GATE CIRCU T
Sync and Gates
PROG OSC
VMEbus SLAVE INTERFACE
P0 - VXS (V TA 41)
VMEbus
VXS Switched Backplane
Pentek, Inc.
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Model 6826
Dual 2 GHz, 10-bit A/D with Virtex-II Pro FPGA - VME/VXS

Specifications
Front Panel Analog Signal Inputs Quantity: 1 or 2 Input Type: Transformer-coupled, front panel female MMCX connectors Full Scale Input: 2 dBm into 50 ohms Transformer 1 dB Passband: 50 MHz to 1 GHz A/D Converters Quantity: 1 or 2 Type: Atmel AT84AS008 Sampling Rate: 200 MHz to 2 GHz Internal Clock: None External Clock: 200 MHz to 2 GHz Resolution: 10 bits Bandwidth: 3.3 GHz at full power Digital Demultiplexer Circuit Quantity: 1 or 2 Overall Demux Ratio: 1:8 Initial Stage: Type: Atmel AT84CS001 Demux Ratio: 1:4 Tunable Delay: -250 ps to +250 ps Programmability: User-programmable Output Resolution: 10 bits Secondary Stage: Type: Xilinx XC2VP4 FPGA Demux Ratio: 1:2 Output Resolution: 10 bits Clock Source: Front panel external clock External Clock: Front panel female MMCX connector, sine wave, 0 to 2 dBm, AC coupled, 50 ohms impedance A/D Sync Input/Output: Front panel female MMCX connector, low voltage PECL Gate/Trigger Control: One or two front panel female MMCX connectors, low voltage PECL; one female MMCX connector , TTL Field Programmable Gate Array Quantity: 1 Type: Option -070: Virtex-II Pro XC2VP70-6 FPGA I/O: Option -121: Provides forty LVDS differential data I/O pairs, two clock I/O pairs and four control pairs from the FPGA to VMEbus P2 connector Option -222: Adds two 68-pin connectors through a second-slot front panel; each provides twenty LVDS data I/O differential pairs, one LVDS clock I/O pair and two control I/O pairs Memory DDR SDRAM: Quantity: Two banks Size: 256 MB per bank, 512 MB total standard; 512 MB per bank, 1 GB total with option -340 Bus Width: 64 bits Speed: 125 MHz; 250 MHz double data rate FLASH: Quantity: 1 Size: 16 MB Bus Width: 16 bits Front Panel Data Port (FPDP) Outputs Quantity: 2 standard; 4 with option -224 (additional ports located on second slot front panel) Output Type: non-inverted configuration, FPDP I or FPDP II Clock: Onboard programmable oscillator (up to 50 MHz) FIFOs Quantity: 2 standard, 4 with option -224 Size: 32,768 x 36 Speed: 133 MHz VME Slave Interface Type: Slave A16/D16, A16/D32, A24/D24 (A32/D32 programmable) Control: Operating modes, gate/trigger, FIFO reset, data packing, FPDP I/II selection, status Power Default Configuration: 50 W (one A/D) to 60 W (dual A/D) User FPGA designs will increase power consumption within the following ranges: With XC2VP70 FPGA: from 50 W to 75 W typical Environmental (Commercial version) Pentek Ruggedization Level: L0 Cooling Method: Forced air Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, noncondensing Environmental - Option -703 Pentek Ruggedization Level: L3 Cooling Method: Conduction cooling Operating Temp: 40 to 70 C Storage Temp: 50 to 100 C Relative Humidity: 0 to 95%, noncondensing Sine Vibration: 10 g, 202,000 Hz Random Vibration: 0.1 g2/Hz, 202,000 Hz Shock: 30 g, 11 ms Environmental - Option -720 Relative Humidity: 0 to 100% noncondensing with conformal coating Size: Standard 6U VMEbus board, single slot; board 160 mm (6.3 in.) x 233.5 mm (9.2 in.), panel 20.3 mm (0.8 in.) wide; Option -222 or -224: 40.6 mm (1.6 in.) wide Weight: 1025 grams (2.26 lbs.)
Model 6826 Description Dual 2 GHz, 10-bit A/D with Virtex-II Pro FPGA VME/VXS Single A/D Converter Dual A/D Converter XC2VP70 FPGA LVDS I/O through P2 2nd Slot LVDS I/O 2nd Slot FPDP I/O 1 GB DDR SDRAM VXS Interface Ruggedized & conductioncooled versions
Options: -001 -002 -070 -121 -222 -224 -340 -5xx -70x
Pentek, Inc.
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Model 71610
LVDS Digital I/O with Virtex-6 FPGA - XMC

General Information
Model 71610 is a member of the Cobalt family of high-performance XMC modules based on the Xilinx Virtex-6 FPGA. This digital I/O module provides 32 LVDS differential inputs or outputs plus LVDS clock, data valid, and data flow control on a front panel 80-pin connector. Its built-in data capture and data generation feature offers an ideal turnkey solution as well as a platform for developing and deploying custom FPGA-processing IP. In addition to supporting PCI Express Gen. 1 as a native interface, the Model 71610 includes a general-purpose connector for application-specific I/O. plete the factory-installed functions and enable the 71610 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Virtex-6 FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T LX240T, or SX315T. The SXT part features up to 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O to the carrier board. Option -105 installs the P16 XMC connector with one 8X or two 4X gigabit links to the FPGA to support serial protocols.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions for data flow and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an IP (intellectual property) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards interface. The 71610 factory-installed functions include 32-bit acquisition and generation IP modules, to support either input or output functions, respectively. IP modules for DDR3 SDRAM memories, a controller for all data clocking, a test signal generator, and a PCIe interface com-
Features

32 bits of LVDS digital I/O One LVDS clock One LVDS data valid One LVDS data suspend Supports LXT and SXT Virtex-6 FPGAS DMA controller moves data to and from system memory Up to 2 GB of DDR3 SDRAM PCI Express interface Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O to the carrier board
80-pin Front Panel Connector

32 Pairs LVDS Data LVDS Clock Data Valid Data Suspend

LVDS
GTX
GTX
GTX
40
8X
4X
4X
Memory Banks 1 & 2
Memory Banks 3 & 4 Option 165
Optional FPGA GPIO
x8 PCIe
Optional Gigabit Serial I/O
PMC P14
XMC P15
XMC P16
Pentek, Inc.
www.pentek.com
Model 71610
LVDS Digital I/O with Virtex-6 FPGA - XMC

Acquisition IP Module
The module can be configured for digital input mode by setting a jumper on the board. In this case, the module accepts input data Clock and input Data Valid signals. This supports a continuous input Clock with data accepted only when the Data Valid line is true. The module can optionally generate a Data Suspend output signal indicating that the 71610 is no longer capable of accepting data. The module accepts 32 bits from the front panel connector or from an on-board test signal generator. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. Memory banks are supported with DMA engines for easily moving input data through the PCIe interface.

The Model 71610 includes an industrystandard interface fully compliant with PCI Express Gen. 1 bus specifications. Supporting a PCIe x4 or x8 connection, the interface includes multiple DMA controllers for efficient transfers to and from the module.
Memory Resources
The 71610 hardware architecture supports up to four independent 512 MB memory banks of DDR3 SDRAM. The board is always configured with 1 GB of memory (Banks 1 and 2). In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. For customers who need more memory to support their IP, Banks 3 and 4 can be optionally added for a total of 2 GB of DDR3 SDRAM
Model 8266
Generation IP Module
The module can be configured for digital output mode by setting a jumper on the board. In this case, the module generates output data Clock and output Data Valid signals. This supports a continuous output Clock with data valid only when the Data Valid line is true. The module can optionally accept a Data Suspend input signal to halt data generation when the destination device is no longer capable of accepting data. A linked-list controller allows users to generate 32-bit digital words out through the front panel LVDS connector from tables stored in either on-board or off-board host memory. Parameters including length of table, delay from software trigger, table repetition, etc. can be programmed for entry. Up to 64 individual link entries can be chained together to create complex output patterns with minimum programming.
Specifications
Front Panel Input/Output Data Lines: 35 LVDS differential pairs (32 pairs supported in factory-installed functions), 2.5 V compliant Clock: One LVDS differential pair, 2.5 V compliant Data Valid: One LVDS differential pair, 2.5 V compliant Data Suspend: One LVDS differential pair, 2.5 V compliant Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Standard: Two 512 MB DDR3 SDRAM memory banks (1 and 2), 400 MHz DDR Option 165: Two 512 MB DDR3 SDRAM memory banks (3 and 4), 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
Model Description 71610 Options: -062 -064 -104 XC6VLX240T XC6VSX315T LVDS FPGA I/O through P14 connector -105 Gigabit serial FPGA I/O through P16 connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required LVDS Digital I/O with Virtex-6 FPGA - XMC
XMC Interface
The Model 71610 complies with the VITA 42.0 XMC specification. Each of two connectors provides multilane gigabit serial interfaces with up to a 6 GHz bit clock. With dual XMC connectors, the 71610 supports x4 or x8 PCIe on the primary P15 XMC connector. The secondary P16 XMC connector is used for dual 4X or single 8X user-installed gigabit serial interfaces, such as Aurora, PCIe and serial RapidIO.

Pentek, Inc.
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Model 78610
LVDS Digital I/O with Virtex-6 FPGA - x8 PCIe

General Information
Model 78610 is a member of the Cobalt family of high-performance PCIe boards based on the Xilinx Virtex-6 FPGA. This digital I/O board provides 32 LVDS differential inputs or outputs plus LVDS clock, data valid, and data flow control on a front panel 80-pin connector. Its built-in data capture and data generation feature offers an ideal turnkey solution as well as a platform for developing and deploying custom FPGA-processing IP. In addition to supporting PCI Express Gen. 1 as a native interface, the Model 78610 includes a general-purpose connector for application-specific I/O. plete the factory-installed functions and enable the 78610 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Virtex-6 FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T LX240T, or SX315T. The SXT part features up to 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105 connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions for data flow and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an IP (intellectual property) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards interface. The 78610 factory-installed functions include 32-bit acquisition and generation IP modules, to support either input or output functions, respectively. IP modules for DDR3 SDRAM memories, a controller for all data clocking, a test signal generator, and a PCIe interface com-
Features

32 bits of LVDS digital I/O One LVDS clock One LVDS data valid One LVDS data suspend Supports LXT and SXT Virtex-6 FPGAS DMA controller moves data to and from system memory Up to 2 GB of DDR3 SDRAM PCI Express interface Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O to the carrier board


LVDS
GTX
GTX
GTX
8X
4X
4X
Memory Banks 1 & 2
x8 PCIe
x8 PCI Express
Pentek, Inc.
www.pentek.com
Model 78610
LVDS Digital I/O with Virtex-6 FPGA - x8 PCIe

The board can be configured for digital input mode by the setting of a jumper. In this case, the board accepts input data Clock and input data Valid signals. This supports a continuous input Clock with data accepted only when the Data Valid line is true. The board can optionally generate a Data Suspend output signal indicating that the 78610 is no longer capable of accepting data. The board accepts 32 bits from the front panel connector or from an on-board test signal generator. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. Memory banks are supported with DMA engines for easily moving input data through the PCIe interface.
Memory Resources
Model 8266
Specifications
Front Panel Input/Output Data Lines: 35 LVDS differential pairs (32 pairs supported in factory-installed functions), 2.5 V compliant Clock: One LVDS differential pair, 2.5 V compliant Data Valid: One LVDS differential pair, 2.5 V compliant Data Suspend: One LVDS differential pair, 2.5 V compliant Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Standard: Two 512 MB DDR3 SDRAM memory banks (1 and 2), 400 MHz DDR Option 165: Two 512 MB DDR3 SDRAM memory banks (3 and 4), 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe card, 4.38 in. x 7.13 in.
The board can be configured for digital output mode by the setting of a jumper. In this case, the board generates output data Clock and output Data Valid signals. This supports a continuous output Clock with data valid only when the Data Valid line is true. The board can optionally accept a Data Suspend input signal to halt data generation when the destination device is no longer capable of accepting data. A linked-list controller allows users to generate 32-bit digital words out through the front panel LVDS connector from tables stored in either on-board or off-board host memory. Parameters including length of table, delay from software trigger, table repetition, etc. can be programmed for entry. Up to 64 individual link entries can be chained together to create complex output patterns with minimum programming.
Model Description 78610 Options: -062 -064 -104 XC6VLX240T XC6VSX315T LVDS FPGA I/O through 68-pin ribbon cable connector -105 Gigabit serial FPGA I/O through two 4X top edge connectors -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required Model 8266 Description PC Development System See 8266 Datasheet for Options LVDS Digital I/O with Virtex-6 FPGA - PCIe

The Model 78610 includes an industrystandard interface fully compliant with PCI Express Gen. 1 bus specifications. Supporting a PCIe x4 or x8 connection, the interface includes multiple DMA controllers for efficient transfers to and from the board.
Pentek, Inc.
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Model 53610
LVDS Digital I/O with Virtex-6 FPGA - 3U VPX

General Information
Model 53610 is a member of the Cobalt family of high-performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. This digital I/O board provides 32 LVDS differential inputs or outputs plus LVDS clock, data valid, and data flow control on a front panel 80-pin connector. Its built-in data capture and data generation feature offers an ideal turnkey solution as well as a platform for developing and deploying custom FPGA-processing IP. In addition to supporting PCI Express Gen. 1 as a native interface, the Model 53610 includes a general-purpose connector for application-specific I/O. signal generator, and a PCIe interface complete the factory-installed functions and enable the 53610 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions for data flow and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an IP (intellectual property) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards interface. The 53610 factory-installed functions include 32-bit acquisition and generation IP modules, to support either input or output functions, respectively. IP modules for DDR3 SDRAM memories, a controller for all data clocking, a test

The Virtex-6 FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T LX240T, or SX315T. The SXT part features up to 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O. Option -105 provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols.
Features

32 bits of LVDS digital I/O One LVDS clock One LVDS data valid One LVDS data suspend Supports LXT and SXT Virtex-6 FPGAS DMA controller moves data to and from system memory Up to 2 GB of DDR3 SDRAM PCI Express interface Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O to the carrier board 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available


LVDS

GTX
GTX
GTX
40
8X x8 PCIe
4X
4X
Memory Banks 1 & 2
CROSSBAR SWITCH
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 53610

The board can be configured for digital input mode by the setting of a jumper. In this case, the board accepts input data Clock and input data Valid signals. This supports a continuous input Clock with data accepted only when the Data Valid line is true. The board can optionally generate a Data Suspend output signal indicating that the 53610 is no longer capable of accepting data. The board accepts 32 bits from the front panel connector or from an on-board test signal generator. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. Memory banks are supported with DMA engines for easily moving input data through the PCIe interface. IP, Banks 3 and 4 can be optionally added for a total of 2 GB of DDR3 SDRAM
Specifications
Front Panel Input/Output Data Lines: 35 LVDS differential pairs (32 pairs supported in factory-installed functions), 2.5 V compliant Clock: One LVDS differential pair, 2.5 V compliant Data Valid: One LVDS differential pair, 2.5 V compliant Data Suspend: One LVDS differential pair, 2.5 V compliant Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O. Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols. Memory Standard: Two 512 MB DDR3 SDRAM memory banks (1 and 2), 400 MHz DDR Option 165: Two 512 MB DDR3 SDRAM memory banks (3 and 4), 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

Model Description 53610 Options: -062 -064 -104 XC6VLX240T XC6VSX315T LVDS FPGA I/O to VPX P2 -105 Gigabit serial FPGA I/O to VPX P1 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required LVDS Digital I/O with Virtex-6 FPGA - 3U VPX
VPX Families
52xxx Form Factor
3U VPX One XMC No VPX P1 x4 Yes VPX P1 or P2 x8

53xxx
Memory Resources
The 53610 hardware architecture supports up to four independent 512 MB memory banks of DDR3 SDRAM. The board is always configured with 1 GB of memory (Banks 1 and 2). In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. For customers who need more memory to support their
# of XMCs Crossbar Switch PCIe path PCIe width Option -104 path Option -105 path Lowest Power Lowest Price
Pentek, Inc.
www.pentek.com
! ew N
Model 52610

General Information
Model 52610 is a member of the Cobalt family of high-performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. This digital I/O board provides 32 LVDS differential inputs or outputs plus LVDS clock, data valid, and data flow control on a front panel 80-pin connector. Its built-in data capture and data generation feature offers an ideal turnkey solution as well as a platform for developing and deploying custom FPGA-processing IP. In addition to supporting PCI Express Gen. 1 as a native interface, the Model 52610 includes a general-purpose connector for application-specific I/O. signal generator, and a PCIe interface complete the factory-installed functions and enable the 52610 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions for data flow and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an IP (intellectual property) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards interface. The 52610 factory-installed functions include 32-bit acquisition and generation IP modules, to support either input or output functions, respectively. IP modules for DDR3 SDRAM memories, a controller for all data clocking, a test

The Virtex-6 FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T LX240T, or SX315T. The SXT part features up to 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O. Option -105 provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols.
Features

32 bits of LVDS digital I/O One LVDS clock One LVDS data valid One LVDS data suspend Supports LXT and SXT Virtex-6 FPGAS DMA controller moves data to and from system memory Up to 2 GB of DDR3 SDRAM PCI Express interface Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O to the carrier board 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available


LVDS
GTX
GTX
GTX
40
4X
4X
4X
Memory Banks 1 & 2
x4 PCIe
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52610

The board can be configured for digital input mode by the setting of a jumper. In this case, the board accepts input data Clock and input data Valid signals. This supports a continuous input Clock with data accepted only when the Data Valid line is true. The board can optionally generate a Data Suspend output signal indicating that the 52610 is no longer capable of accepting data. The board accepts 32 bits from the front panel connector or from an on-board test signal generator. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. Memory banks are supported with DMA engines for easily moving input data through the PCIe interface. Banks 3 and 4 can be optionally added for a total of 2 GB of DDR3 SDRAM
Specifications
Front Panel Input/Output Data Lines: 35 LVDS differential pairs (32 pairs supported in factory-installed functions), 2.5 V compliant Clock: One LVDS differential pair, 2.5 V compliant Data Valid: One LVDS differential pair, 2.5 V compliant Data Suspend: One LVDS differential pair, 2.5 V compliant Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O. Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols. Memory Standard: Two 512 MB DDR3 SDRAM memory banks (1 and 2), 400 MHz DDR Option 165: Two 512 MB DDR3 SDRAM memory banks (3 and 4), 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Model Description 52610 Options: -062 -064 -104 XC6VLX240T XC6VSX315T LVDS FPGA I/O to VPX P2 -105 Gigabit serial FPGA I/O to VPX P1 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required LVDS Digital I/O with Virtex-6 FPGA - 3U VPX
VPX Families
52xxx Form Factor
3U VPX One XMC No VPX P1 x4 Yes VPX P1 or P2 x8

The Model 52610 includes an industrystandard interface fully compliant with PCI Express Gen. 1 bus specifications. Supporting a PCIe x4 connection, the interface includes multiple DMA controllers for efficient transfers to and from the board.
53xxx
Memory Resources
The 52610 hardware architecture supports up to four independent 512 MB memory banks of DDR3 SDRAM. The board is always configured with 1 GB of memory (Banks 1 and 2). In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. For customers who need more memory to support their IP,
# of XMCs Crossbar Switch PCIe path PCIe width Option -104 path Option -105 path Lowest Power Lowest Price
Pentek, Inc.
www.pentek.com
! ew N
Models 72610, 73610 and 74610
Single or Dual LVDS Digital I/O with Virtex-6 FPGA - cPCI

General Information
Models 72610, 73610 and 74610 are members of the Cobalt family of high-performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71610 XMC modules mounted on a cPCI carrier board. Model 72610 is a 6U cPCI board while the Model 73610 is a 3U cPCI board; both are equipped with one Model 71610 XMC. Model 74610 is a 6U cPCI board with two XMC modules rather than one. These models include one or two general-purpose connectors for applicationspecific I/O. signal generator, and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features Virtex-6 FPGAs. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions for data flow and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an IP (intellectual property) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards interface. The factory-installed functions of these models include 32-bit acquisition and generation IP modules, to support either input or output functions, respectively. IP modules for DDR3 SDRAM memories, controllers for all data clocking, a test

The Virtex-6 FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T LX240T, or SX315T. The SXT part features up to 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73610; J3 connector, Model 72610; J3 and J5 connectors, Model 74610.
Model 74610
Model 73610
Features

32 or 64 bits of LVDS digital I/O One or two LVDS clocks One or two LVDS data valid One or two LVDS data suspend Supports LXT and SXT Virtex-6 FPGAS One or two DMA controllers move data to and from system memory Up to 2 or 4 GB of DDR3 SDRAM Optional LVDS connections to the Virtex-6 FPGA for custom I/O to the carrier board

VIRTEX-6 FPGA LX130T, LX240T or SX315T MODEL 73610 INTERFACES ONLY

32 32 DDR3 SDRAM 512 MB 32 DDR3 SDRAM 512 MB 32 DDR3 SDRAM 512 MB 16 Config FLASH 64 MB
LVDS
GTX
VIRTEX-6 FPGA
LVDS
40
GTX
DDR3 SDRAM 512 MB
x4 PCIe
4X
40
PCIe
Memory Banks 1 & 2
PCIe to PCI BRIDGE
PCI to PCI BRIDGE
J2
Pentek, Inc.
www.pentek.com
Models 72610, 73610 and 74610
Single or Dual LVDS Digital I/O with Virtex-6 FPGA - cPCI

These models can be configured for digital input mode by the setting of a jumper. In this case, the board accepts input data Clock and input data Valid signals. This supports a continuous input Clock with data accepted only when the Data Valid line is true. The board can optionally generate a Data Suspend output signal indicating that these models are no longer capable of accepting data. The board accepts 32 bits from the front panel connector or from an on-board test signal generator. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. Memory banks are supported with DMA engines for easily moving input data through the PCIe interface.
Memory Resources
The hardware architecture supports up to four or eight independent 512 MB memory banks of DDR3 SDRAM. The board is always configured with 1 GB of memory (Banks 1 and 2). In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. For customers who need more memory to support their IP, Banks 3 and 4 can be optionally added for a total of 2 GB of DDR3 SDRAM for Models 72610 and 73610 or a total of 4 GB for Model 74610.
Specifications
Model 72610 or Model 73610: Single LVDS Digital I/O Model 74610: Dual LVDS Digital I/O Front Panel Input/Output (1 or 2) Data Lines: 35 LVDS differential pairs (32 pairs supported in factory-installed functions), 2.5 V compliant Clock: One LVDS differential pair, 2.5 V compliant Data Valid: One LVDS differential pair, 2.5 V compliant Data Suspend: One LVDS differential pair, 2.5 V compliant Field Programmable Gate Array (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73610; J3 connector, Model 72610; J3 and J5 connectors, Model 74610 Memory Banks (1 or 2) Standard: Two 512 MB DDR3 SDRAM memory banks (1 and 2), 400 MHz DDR Option 165: Two 512 MB DDR3 SDRAM memory banks (3 and 4), 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73610: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
These models can be configured for digital output mode by the setting of a jumper. In this case, the board generates output data Clock and output Data Valid signals. This supports a continuous output Clock with data valid only when the Data Valid line is true. The board can optionally accept a Data Suspend input signal to halt data generation when the destination device is no longer capable of accepting data. A linked-list controller allows users to generate 32-bit digital words out through the front panel LVDS connector from tables stored in either on-board or off-board host memory. Parameters including length of table, delay from software trigger, table repetition, etc. can be programmed for entry. Up to 64 individual link entries can be chained together to create complex output patterns with minimum programming.
Model Description 72610 Single LVDS Digital I/O with Virtex-6 FPGA 6U cPCI Single LVDS Digital I/O with Virtex-6 FPGA 3U cPCI Dual LVDS Digital I/O with Virtex-6 FPGAs 6U cPCI
73610
PCI-X Interface
74610
Options: -062 -064 -104 XC6VLX240T XC6VSX315T LVDS I/O between the FPGA and J2 connector, Model 73610; J3 connector, Model 72610; J3 and J5 connectors, Model 74610 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required
Pentek, Inc.
www.pentek.com
! ew N
Model 56610
LVDS Digital I/O with Virtex-6 FPGA - AMC

General Information
Model 56610 is a member of the Cobalt family of high-performance AMC boards based on the Xilinx Virtex-6 FPGA. This digital I/O board provides 32 LVDS differential inputs or outputs plus LVDS clock, data valid, and data flow control on a front panel 80-pin connector. Its built-in data capture and data generation feature offers an ideal turnkey solution as well as a platform for developing and deploying custom FPGA-processing IP. In addition to supporting PCI Express Gen. 1 as a native interface, the Model 56610 includes a general-purpose connector for application-specific I/O. IP modules for DDR3 SDRAM memories, a controller for all data clocking, a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 56610 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions for data flow and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an IP (intellectual property) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards interface. The 56610 factory-installed functions include 32-bit acquisition and generation IP modules, to support either input or output functions, respectively.

The Virtex-6 FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T LX240T, or SX315T. The SXT part features up to 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 installs a front panel connector with 20 pairs of LVDS connections to the FPGA for custom I/O.
Features

32 bits of LVDS digital I/O One LVDS clock One LVDS data valid One LVDS data suspend Supports LXT and SXT Virtex-6 FPGAS DMA controller moves data to and from system memory Up to 2 GB of DDR3 SDRAM PCI Express interface AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional LVDS connections to the Virtex-6 FPGA for custom I/O to the carrier board


GTX
LVDS
8X
IPMI CONTROLLER
40
Memory Banks 1 & 2
x8 PCIe
RS-232
AMC Ports 4 to 11
Front Panel
Pentek, Inc.
www.pentek.com
Model 56610
LVDS Digital I/O with Virtex-6 FPGA - AMC

The board can be configured for digital input mode by the setting of a jumper. In this case, the board accepts input data Clock and input data Valid signals. This supports a continuous input Clock with data accepted only when the Data Valid line is true. The board can optionally generate a Data Suspend output signal indicating that the 56610 is no longer capable of accepting data. The board accepts 32 bits from the front panel connector or from an on-board test signal generator. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. Memory banks are supported with DMA engines for easily moving input data through the PCIe interface.

Memory Resources
Specifications
Front Panel Input/Output Data Lines: 35 LVDS differential pairs (32 pairs supported in factory-installed functions), 2.5 V compliant Clock: One LVDS differential pair, 2.5 V compliant Data Valid: One LVDS differential pair, 2.5 V compliant Data Suspend: One LVDS differential pair, 2.5 V compliant Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory Standard: Two 512 MB DDR3 SDRAM memory banks (1 and 2), 400 MHz DDR Option 165: Two 512 MB DDR3 SDRAM memory banks (3 and 4), 400 MHz DDR AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.
Model Description 56610 Options: -062 -064 -104 XC6VLX240T XC6VSX315T LVDS FPGA I/O through 68-pin ribbon cable connector -105 Gigabit serial FPGA I/O through two 4X top edge connectors -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required LVDS Digital I/O with Virtex-6 FPGA - PCIe
AMC Interface
Pentek, Inc.
www.pentek.com
! w e N
Model 7811
Quad Serial FPDP Interface with Virtex-6 FPGA - PCIe

General Information
Model 7811 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, gigabit serial interface, it is ideal for interfacing to serial FPDP data converter boards or as a chassis-to-chassis data link. The 7811 is fully compatible with the VITA 17.1 Serial FPDP specification. Its built-in data transfer features make it a complete turnkey solution. For users who require application-specific functions, the 7811 serves as a flexible platform for developing and deploying custom FPGA processing IP. factory-installed functions and enable the 7811 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data transfer and control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. IP modules for data routing and flow control, CRC support, advanced DMA engines, and a PCIe interface complete the

The Virtex-6 FPGA can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T or SX315T. The SX315T part features 1,344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LX130T FPGA can be installed.
Features

Complete serial FPDP solution Fully compliant with VITA 17.1specification Fibre optic or copper serial interfaces PCI Express interface up to x8
CH 1 RX TX
CH 2 RX TX
CH 3 RX TX
CH 4 RX TX
FIBER OPTIC or COPPER INTERFACE
GTX
GTX
GTX
GTX

GTX
8X
x8 PCIe
PCIe
Pentek, Inc.
www.pentek.com
Model 7811
Quad Serial FPDP Interface with Virtex-6 FPGA - PCIe

Serial FPDP Interface
The 7811 is fully compatible with the VITA 17.1 Serial FPDP specification. With the capability to support 1.0625, 2.125, 2.5, 3.125, and 4.25 Gbaud link rates and the option for multi-mode and single-mode optical interfaces or copper interfaces the board can work in virtually any system. Programmable modes include: flow control in both receive and transmit directions, CRC support, and copy/loop modes.
Specifications
Front Panel Serial FPDP Inputs/Outputs Number of Connectors: 4 Fiber Optic Connector Type: LC Laser: 850 nm (standard, other options available) Copper Connector Type: SFP+ Fiber Optic or Copper Link Rates: 1.0625, 2.125, 2.5, 3.125 or 4.25 Gbaud (copper rate depends on cable langth) Fiber Optic or Copper Data Transfer Rates: 105, 210, 247, 309 or 420 MB/sec (depending on link rate) per serial FPDP port Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe card, 4.38 in. x 7.13 in.

The Model 7811 includes an industrystandard interface fully compliant with PCI Express bus specifications. Supporting PCIe links up to x8, the interface includes eight DMA controllers. Each of the four sFPDP channels includes dedicated DMA engines for transmit and receive for efficient transfers to and from the board.
Model 8266
SERIAL FPDP RX ENGINE CH 1 RX PACKET DECONSTRUCT OPTIONAL CRC CHECK 2K x 32 RX FIFO
DMA ENGINE 32K x 32 FIFO
SERIAL FPDP TX ENGINE 64 x 32 COPY MODE RX FIFO OPTIONAL CRC GENERATOR PACKET CONSTRUCT RATE BALANCE IDLE INSERT/DELETE 2K x 32 TX FIFO
Copy mode data path
Model 7811 Description Quad Serial FPDP Interface with Virtex-6 FPGA - PCIe XC6VLX240T FPGA XC6VSX315T FPGA Copper serial interfaces Multi-mode optical serial interfaces Description PC Development System See 8266 Datasheet for Options
CH 1 TX
DISPARITY CALCULATE
M U X
SERIAL FPDP CHANNEL 1 PCIe INTERFACE RX CH 2 TX
8X
Options: -062 -064 -280 -281
SERIAL FPDP CHANNEL 2
RX CH 3 TX
Model 8266
RX CH 4 TX
Pentek, Inc.
www.pentek.com
! ew N
Model 71611
Quad Serial FPDP Interface with Virtex-6 FPGA - XMC

General Information
Model 71611 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, gigabit serial interface, it is ideal for interfacing to serial FPDP data converter boards or as a chassis-to-chassis data link. The 71611 is fully compatible with the VITA 17.1 Serial FPDP specification. Its built-in data transfer features make it a complete turnkey solution. For users who require application-specific functions, the 71611 serves as a flexible platform for developing and deploying custom FPGA processing IP. In addition to supporting PCI Express as a native interface, the Model 71611 includes a general purpose connector for applicationspecific I/O. CRC support, advanced DMA engines, and a PCIe interface complete the factory-installed functions and enable the 71611 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T, SX315T, or SX475T. The SXT parts feature up to 2016 DSP48E slices and are ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lowercost LXT FPGA can be installed. Option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O.
CH 3 RX TX CH 4 RX TX

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data transfer and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. IP modules for DDR3 SDRAM memories, controllers for data routing and flow control,
Features

Complete serial FPDP solution Fully compliant with VITA 17.1specification Fiber optic or copper serial interfaces Up to 2 GB of DDR3 SDRAM PCI Express interface up to x8 LVDS connections to the Virtex-6 FPGA for custom I/O
CH 1 RX TX
CH 2 RX TX
GTX
GTX
GTX
GTX
VIRTEX-6 FPGA LX240T, SX315T or SX475T

GTX
LVDS
8X
40
x8 PCIe
FPGA GPIO (option -104) P14 PMC
P15 XMC
Pentek, Inc.
www.pentek.com
Model 71611
Quad Serial FPDP Interface with Virtex-6 FPGA - XMC

The 71611 is fully compatible with the VITA 17.1 Serial FPDP specification. With the capability to support 1.0625, 2.125, 2.5, 3.125, and 4.25 Gbaud link rates and the option for multi-mode and single-mode optical interfaces, the board can work in virtually any system. Programmable modes include: flow control in both receive and transmit directions, CRC support, and copy/loop modes.
Specifications
Front Panel Serial FPDP Inputs/Outputs Number of Connectors: 4 Fiber Optic Connector Type: LC Laser: 850 nm (standard, other options available) Copper Connector Type: Micro Twinax Fiber Optic or Copper Link Rates: 1.0625, 2.125, 2.5, 3.125 or 4.25 Gbaud (copper rate depends on cable langth) Fiber Optic or Copper Data Transfer Rates: 105, 210, 247, 309 or 420 MB/sec (depending on link rate) per serial FPDP port Field Programmable Gate Array: Xilinx Virtex-6 XC6VLX240T, XC6VSX315T, or XC6VSX475T Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Memory Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
Model 8266
Memory Resources
The 71611 architecture supports up to four independent memory banks of DDR3 SDRAM. Each memory is 512 MB deep and an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

The Model 71611 includes an industrystandard interface fully compliant with PCI Express Gen. 1 bus specifications. Supporting PCIe links up to x8, the interface includes eight DMA controllers. Each of the four sFPDP channels includes dedicated DMA engines for transmit and receive for efficient transfers to and from the module.
Model 71611 Description Quad Serial FPDP Interface with Virtex-6 FPGA - XMC XC6VLX240T FPGA XC6VSX315T FPGA XC6VSX475T FPGA LVDS FPGA I/O through P14 connector Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Copper serial interfaces Multi-mode optical serial interfaces
to optional 512 MB SDRAM buffer

SERIAL FPDP RX ENGINE CH 1 RX PACKET DECONSTRUCT OPTIONAL CRC CHECK 2K x 32 RX FIFO DMA ENGINE 32K x 32 FIFO
Options: -062 -064 -065 -104 -155
Copy mode data path
CH 1 TX
DISPARITY CALCULATE
M U X
-165
-280 -281

RX CH 2 TX SERIAL FPDP CHANNEL 2
PCIe INTERFACE
8X



Pentek, Inc.
www.pentek.com
! w e N
Model 78611
Quad Serial FPDP Interface with Virtex-6 FPGA - x8 PCIe

General Information
Model 78611 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A multichannel, gigabit serial interface, it is ideal for interfacing to serial FPDP data converter boards or as a chassis-to-chassis data link. The 78611 is fully compatible with the VITA 17.1 Serial FPDP specification. Its built-in data transfer features make it a complete turnkey solution. For users who require application-specific functions, the 78611 serves as a flexible platform for developing and deploying custom FPGA processing IP. In addition to supporting PCI Express as a native interface, the Model 78611 includes a general purpose connector for applicationspecific I/O. a PCIe interface complete the factory-installed functions and enable the 78611 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T, SX315T, or SX475T. The SXT parts feature up to 2016 DSP48E slices and are ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lowercost LXT FPGA can be installed. Option -104 connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data transfer and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. IP modules for DDR3 SDRAM memories, controllers for data routing and flow control, CRC support, advanced DMA engines, and
Features

Complete serial FPDP solution Fully compliant with VITA 17.1specification Fiber optic or copper serial interfaces Up to 2 GB of DDR3 SDRAM PCI Express interface up to x8 LVDS connections to the Virtex-6 FPGA for custom I/O
GTX
GTX
GTX
GTX

LVDS
GTX
8X
x8 PCIe
x8 PCI Express
Pentek, Inc.
www.pentek.com
Model 78611
Quad Serial FPDP Interface with Virtex-6 FPGA - x8 PCIe

Specifications
Front Panel Serial FPDP Inputs/Outputs Number of Connectors: 4 Fiber Optic Connector Type: LC Laser: 850 nm (standard, other options available) Copper Connector Type: Micro Twinax Fiber Optic or Copper Link Rates: 1.0625, 2.125, 2.5, 3.125 or 4.25 Gbaud (copper rate depends on cable langth) Fiber Optic or Copper Data Transfer Rates: 105, 210, 247, 309 or 420 MB/sec (depending on link rate) per serial FPDP port Field Programmable Gate Array: Xilinx Virtex-6 XC6VLX240T, XC6VSX315T, or XC6VSX475T Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Memory Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe card, 4.38 in. x 7.13 in.
Memory Resources
The 78611 architecture supports up to four independent memory banks of DDR3 SDRAM. Each memory is 512 MB deep and an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
Model 8266

The Model 78611 includes an industrystandard interface fully compliant with PCI Express Gen. 1 bus specifications. Supporting PCIe links up to x8, the interface includes eight DMA controllers. Each of the four sFPDP channels includes dedicated DMA engines for transmit and receive for efficient transfers to and from the board.
Model 78611 Description Quad Serial FPDP Interface with Virtex-6 FPGA - PCIe XC6VLX240T FPGA XC6VSX315T FPGA XC6VSX475T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Copper serial interfaces Multi-mode optical serial interfaces Description PC Development System See 8266 Datasheet for Options
SERIAL FPDP RX ENGINE CH 1 RX PACKET DECONSTRUCT OPTIONAL CRC CHECK

DMA ENGINE 2K x 32 RX FIFO 32K x 32 FIFO
Options: -062 -064 -065 -104

Copy mode data path
CH 1 TX
DISPARITY CALCULATE
M U X
-155

PCIe INTERFACE
8X
-165
-280 -281

Model 8266

Pentek, Inc.
www.pentek.com
! ew N
Model 53611
Quad Serial FPDP Interface with Virtex-6 FPGA - 3U VPX

General Information
Model 53611 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A multichannel, gigabit serial interface, it is ideal for interfacing to serial FPDP data converter boards or as a chassis-to-chassis data link. The 53611 is fully compatible with the VITA 17.1 Serial FPDP specification. Its built-in data transfer features make it a complete turnkey solution. For users who require application-specific functions, the 53611 serves as a flexible platform for developing and deploying custom FPGA processing IP. In addition to supporting PCI Express over the 3U VPX backplane, the Model 53611 includes a general purpose connector for application-specific I/O. a PCIe interface complete the factory-installed functions and enable the 53611 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T, SX315T, or SX475T. The SXT parts feature up to 2016 DSP48E slices and are ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lowercost LXT FPGA can be installed. Option -104 provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O.

Features

Complete serial FPDP solution Fully compliant with VITA 17.1specification Fiber optic or copper serial interfaces Up to 2 GB of DDR3 SDRAM PCI Express interface up to x8 LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
CH 1 RX TX
CH 2 RX TX
GTX
GTX
GTX
GTX

LVDS
GTX
40
8X x8 PCIe
CROSSBAR SWITCH
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 53611
Memory Resources
The 53611 architecture supports up to four independent memory banks of DDR3 SDRAM. Each memory is 512 MB deep and an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets.

The 53611 is fully compatible with the VITA 17.1 Serial FPDP specification. With the capability to support 1.0625, 2.125, 2.5, 3.125, and 4.25 Gbaud link rates and the option for multi-mode and single-mode optical interfaces, the board can work in virtually any system. Programmable modes include: flow control in both receive and transmit directions, CRC support, and copy/loop modes. Memory Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

The Model 53611 includes an industry-standard interface fully compliant with PCI Express Gen. 1 bus specifications. Supporting PCIe links up to x8, the interface includes eight DMA controllers. Each of the four sFPDP channels includes dedicated DMA engines for transmit and receive for efficient transfers to and from the board.
Specifications
Front Panel Serial FPDP Inputs/Outputs Number of Connectors: 4 Fiber Optic Connector Type: LC Laser: 850 nm (standard, other options available) Copper Connector Type: Micro Twinax Fiber Optic or Copper Link Rates: 1.0625, 2.125, 2.5, 3.125 or 4.25 Gbaud (copper rate depends on cable langth) Fiber Optic or Copper Data Transfer Rates: 105, 210, 247, 309 or 420 MB/sec (depending on link rate) per serial FPDP port Field Programmable Gate Array: Xilinx Virtex-6 XC6VLX240T, XC6VSX315T, or XC6VSX475T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O
VPX Families
53xxx
Crossbar Switch
Model 53611 Description Quad Serial FPDP Interface with Virtex-6 FPGA - 3U VPX XC6VLX240T FPGA XC6VSX315T FPGA XC6VSX475T FPGA LVDS FPGA I/O to VPX P2 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Copper serial interfaces Multi-mode optical serial interfaces
CH 1 RX PACKET DECONSTRUCT SERIAL FPDP RX ENGINE OPTIONAL CRC CHECK

Options: -062 -064 -065 -104 -155

CH 1 TX DISPARITY CALCULATE M U X
Copy mode data path

PCIe INTERFACE
8X
-165

-280 -281

Pentek, Inc.
www.pentek.com
! ew N
Model 52611

General Information
Model 52611 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A multichannel, gigabit serial interface, it is ideal for interfacing to serial FPDP data converter boards or as a chassis-to-chassis data link. The 52611 is fully compatible with the VITA 17.1 Serial FPDP specification. Its built-in data transfer features make it a complete turnkey solution. For users who require application-specific functions, the 52611 serves as a flexible platform for developing and deploying custom FPGA processing IP. In addition to supporting PCI Express over the 3U VPX backplane, the Model 52611 includes a general-purpose connector for application-specific I/O. a PCIe interface complete the factory-installed functions and enable the 52611 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T, SX315T, or SX475T. The SXT parts feature up to 2016 DSP48E slices and are ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lowercost LXT FPGA can be installed. Option -104 provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O.

Features

Complete serial FPDP solution Fully compliant with VITA 17.1specification Fiber optic or copper serial interfaces Up to 2 GB of DDR3 SDRAM PCI Express interface up to x4 LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
CH 1 RX TX
CH 2 RX TX
GTX
GTX
GTX
GTX

LVDS
GTX
40
4X

x4 PCIe
VPX-P2
VPX-P1
VPX BACKPLANE
Pentek, Inc.
www.pentek.com
Model 52611

Memory Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Memory Resources
The 52611 architecture supports up to four independent memory banks of DDR3 SDRAM. Each memory is 512 MB deep and an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. In addition to the factoryinstalled functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
Specifications
Front Panel Serial FPDP Inputs/Outputs Number of Connectors: 4 Fiber Optic Connector Type: LC Laser: 850 nm (standard, other options available) Copper Connector Type: Micro Twinax Fiber Optic or Copper Link Rates: 1.0625, 2.125, 2.5, 3.125 or 4.25 Gbaud (copper rate depends on cable langth) Fiber Optic or Copper Data Transfer Rates: 105, 210, 247, 309 or 420 MB/sec (depending on link rate) per serial FPDP port Field Programmable Gate Array: Xilinx Virtex-6 XC6VLX240T, XC6VSX315T, or XC6VSX475T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O
VPX Families

The Model 52611 includes an industry-standard interface fully compliant with PCI Express Gen. 1 bus specifications. Supporting PCIe links up to x4, the interface includes eight DMA controllers. Each of the four sFPDP channels includes dedicated DMA engines for transmit and receive for efficient transfers to and from the board.
53xxx
Model 52611 Description Quad Serial FPDP Interface with Virtex-6 FPGA - 3U VPX XC6VLX240T FPGA XC6VSX315T FPGA XC6VSX475T FPGA LVDS FPGA I/O to VPX P2 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Copper serial interfaces Multi-mode optical serial interfaces

Options: -062 -064 -065 -104 -155

Copy mode data path

PCIe INTERFACE
4X
-165

-280 -281

Pentek, Inc.
www.pentek.com
! w e N
Models 72611, 73611 and 74611
Quad or Octal Serial FPDP Interface with Virtex-6 FPGA - cPCI

General Information
Models 72611, 73611 and 74611 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71611 XMC modules mounted on a cPCI carrier board. Model 72611 is a 6U cPCI board while the Model 73611 is a 3U cPCI board; both are equipped with one Model 71611 XMC. Model 74611 is a 6U cPCI board with two XMC modules rather than one. These models are fully compatible with the VITA 17.1 Serial FPDP specification. Their built-in data transfer features make them complete turnkey solutions. For users who require application-specific functions, they serve as flexible platforms for developing and deploying custom FPGA processing IP. a cPCI interface complete the factory-installed functions and enable these models to operate as a complete turnkey solutions without the need to develop any FPGA IP.

The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T, SX315T, or SX475T. The SXT parts feature up to 2016 DSP48E slices and are ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lowercost LXT FPGA can be installed. Option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73611; J3 connector, Model 72611; J3 and J5 connectors, Model 74611.

The Pentek Cobalt Architecture features one or two Virtex-6 FPGAs. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data transfer and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. IP modules for DDR3 SDRAM memories, controllers for data routing and flow control, CRC support, advanced DMA engines, and
Model 74611
Model 73611
CH 1 RX TX
CH 2 RX TX
CH 3 RX TX
CH 4 RX TX
Features

Four or eight channels of serial FPDP interface Fully compliant with VITA 17.1specification Fiber optic or copper serial interfaces One or two Virtex-6 FPGAs Up to 2 or 4 GB of DDR3 SDRAM LVDS connections to the Virtex-6 FPGA for custom I/O
GTX
GTX
GTX
GTX

LVDS

LVDS
GTX
GTX
40
x4 PCIe
4X
40
to PCI Optional BRIDGE FPGA I/O (option 104)
PCIe
PCIe to PCI BRIDGE
J2
PCI/PCI-X BUS 32-bit, 33/66 MHz J3
PCI to PCI BRIDGE
Pentek, Inc.
www.pentek.com
Models 72611, 73611 and 74611
Quad or Octal Serial FPDP Interface with Virtex-6 FPGA - cPCI

These models are fully compatible with the VITA 17.1 Serial FPDP specification. With the capability to support 1.0625, 2.125, 2.5, 3.125, and 4.25 Gbaud link rates and the option for multi-mode and single-mode optical interfaces, the boards can work in virtually any system. Programmable modes include: flow control in both receive and transmit directions, CRC support, and copy/loop modes.
Specifications
Front Panel Serial FPDP Inputs/Outputs Number of Connectors: 4 or 8 Fiber Optic Connector Type: LC Laser: 850 nm (standard, other options available) Copper Connector Type: Micro Twinax Fiber Optic or Copper Link Rates: 1.0625, 2.125, 2.5, 3.125 or 4.25 Gbaud (copper rate depends on cable langth) Fiber Optic or Copper Data Transfer Rates: 105, 210, 247, 309 or 420 MB/sec (depending on link rate) per serial FPDP port Field Programmable Gate Array: Xilinx Virtex-6 XC6VLX240T, XC6VSX315T, or XC6VSX475T Custom I/O Option -104: provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73611; J3 connector, Model 72611; J3 and J5 connectors, Model 74611 Memory Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32- or 64-bit at 33 or 66 MHz Model 73611: 32-bit at 33 or 66 MHz Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
Memory Resources
The architecture supports up to four or eight independent memory banks of DDR3 SDRAM. Each memory is 512 MB deep and an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits (32 bits only, Model 73611) and data rates of 33 and 66 MHz are supported.
Model 72611 Description Quad serial FPDP Interface with Virtex-6 FPGA - 6U cPCI Quad serial FPDP Interface with Virtex-6 FPGA - 3U cPCI Octal serial FPDP Interface with Virtex-6 FPGA - 6U cPCI XC6VLX240T FPGA XC6VSX315T FPGA XC6VSX475T FPGA LVDS I/O between the FPGA and J2 connector, Model 73611; J3 connector, Model 72611; J3 and J5 connectors, Model 74611 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Copper serial interfaces Multi-mode optical serial interfaces

SERIAL FPDP RX ENGINE CH 1 RX PACKET DECONSTRUCT OPTIONAL CRC CHECK 2K x 32 RX FIFO DMA ENGINE 32K x 32 FIFO
73611
74611
Options: -062 -064 -065 -104

Copy mode data path

PCIe INTERFACE
4X
-155

-165

-280 -281
Pentek, Inc.
www.pentek.com
! w e N
Model 56611
Quad Serial FPDP Interface with Virtex-6 FPGA - AMC

General Information
Model 56611 is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, gigabit serial interface, it is ideal for interfacing to serial FPDP data converter boards or as a chassis-to-chassis data link. The 56611 is fully compatible with the VITA 17.1 Serial FPDP specification. Its built-in data transfer features make it a complete turnkey solution. For users who require application-specific functions, the 56611 serves as a flexible platform for developing and deploying custom FPGA processing IP. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 56611 includes a front panel general-purpose connector for applicationspecific I/O. CRC support, advanced DMA engines, and a PCIe interface complete the factory-installed functions and enable the 56611 to operate as a complete turnkey solution without the need to develop any FPGA IP.

The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T, SX315T, or SX475T. The SXT parts feature up to 2016 DSP48E slices and are ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lowercost LXT FPGA can be installed. Option -104 installs a front panel connector with 20 pairs of LVDS connections to the FPGA for custom I/O.

The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data transfer and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. IP modules for DDR3 SDRAM memories, controllers for data routing and flow control,
Features

Complete serial FPDP solution Fully compliant with VITA 17.1specification Fiber optic or copper serial interfaces Up to 2 GB of DDR3 SDRAM PCI Express interface up to x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections to the Virtex-6 FPGA for custom I/O
CH 1 RX TX
CH 2 RX TX
GTX
GTX
GTX
GTX

GTX
LVDS
8X
IPMI CONTROLLER
40
x8 PCIe
RS-232
AMC Ports 4 to 11
Front Panel
Pentek, Inc.
www.pentek.com
Model 56611
Quad Serial FPDP Interface with Virtex-6 FPGA - AMC

Specifications
Front Panel Serial FPDP Inputs/Outputs Number of Connectors: 4 Fiber Optic Connector Type: LC Laser: 850 nm (standard, other options available) Copper Connector Type: Micro Twinax Fiber Optic or Copper Link Rates: 1.0625, 2.125, 2.5, 3.125 or 4.25 Gbaud (copper rate depends on cable langth) Fiber Optic or Copper Data Transfer Rates: 105, 210, 247, 309 or 420 MB/sec (depending on link rate) per serial FPDP port Field Programmable Gate Array: Xilinx Virtex-6 XC6VLX240T, XC6VSX315T, or XC6VSX475T Custom I/O Option -104: Installs a front panel connector with 20 LVDS pairs to the FPGA Memory Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.
AMC Interface
Memory Resources
The 56611 architecture supports up to four independent memory banks of DDR3 SDRAM. Each memory is 512 MB deep and an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

The Model 56611 includes an industrystandard interface fully compliant with PCI Express Gen. 1 bus specifications. Supporting PCIe links up to x8, the interface includes eight DMA controllers. Each of the four sFPDP channels includes dedicated DMA engines for transmit and receive for efficient transfers to and from the module.
Model 56611 Description Quad Serial FPDP Interface with Virtex-6 FPGA - AMC XC6VLX240T FPGA XC6VSX315T FPGA XC6VSX475T FPGA LVDS FPGA I/O through front panel connector Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Copper serial interfaces Multi-mode optical serial interfaces
Options: -062 -064 -065 -104 -155

Copy mode data path

PCIe INTERFACE
8X
-165

-280 -281

Pentek, Inc.
www.pentek.com
! w e N
Model 7120
Bandit Two-Channel Analog RF Receiver - PMC/XMC

General Information
The Bandit Model 7120 is a two-channel, high-performance, stand-alone analog RF receiver. Packaged in a small, shielded PMC/XMC module with front-panel connectors for easy integration into RF systems, the module offers programmable gain, high dynamic range and a low noise figure. With an input frequency range from 400 to 4000 MHz and a wide IF bandwidth of up to 390 MHz, the 7120 is an ideal solution for amplifying and downconverting antenna signals for communications, radar and signal intelligence systems. with amplitude and phase balances of ~0.07 dB and ~0.2, respectively.
Tuning Accuracy
The 7120 uses an Analog Devices ADF4351 low-noise, on-board frequency synthesizer as the LO (Local Oscillator). Locked to an external input reference for accuracy with a fractional-N phase-locked loop, its frequency is programmable across the 400 to the 4000 MHz band with a tuning resolution of better than 100 kHz.
On-board Reference Clock

In addition to accepting a 10 MHz reference signal on the front panel, the 7120 includes an on-board 10 MHz crystal oscillator which can be used as the reference to lock the internal LO frequency synthesizer. This reference is an OCXO (Oven Controlled Crystal Oscillator), which provides an exceptionally precise frequency standard with excellent phase noise characteristics.
Programmable Input Level

The 7120 accepts RF signals on two front-panel SSMC connectors. LNAs (Low Noise Amplifiers) are provided, along with two programmable attenuators allowing downconversion of input signals ranging from 60 dBm to 20 dBm in steps of 0.5 dB. Higher level signals can be attenuated prior to input.
Input Filter Options Features

Wide Output
Output is provided as baseband I and Q signals at bandwidths up to 390 MHz. Alternatively, either I or Q output can be used at some intermediate offset frequency convenient to the application. User-provided in-line output IF filters allow customizing the output bandwidth and offset frequency to the specific application requirements. This output is suitable for A/D conversion using Pentek high-performance signal acquisition products, such as those in the Cobalt and Onyx families.
Accepts RF signals from 400 MHz to 4000 MHz Accepts RF input levels from -60 dBm to -20 dBm Baseband IF output with up to 390 MHz bandwidth Internal OCXO or external 10 MHz frequency reference
An optional five-stage lowpass or bandpass input filter can be included with several available frequency and attenuation characteristics for RF image rejection and harmonic suppression.
Quadrature Mixers
The 7120 features a pair of Analog Devices ADL5380 quadrature mixers. The ADL5380s are capable of excellent accuracy
RF In
LOW NOISE AMP
LOWPASS OR BANDPASS FILTER (optional)
LOW NOISE AMP
I I/Q DOWNCONVERTER Q
LOW NOISE AMP
IF I Out IF Q Out
Gain 1 Control
Gain 2 Control
SYNTHESIZER
Tuning Control Ref In USB INTERFACE Gain 1 Control Gain 2 Control Tuning Control Tuning Control OVEN CONTROLLED REFERENCE OSCILLATOR (option 015)
Ref Out
USB
Gain 1 Control LOWPASS OR BANDPASS FILTER (optional)
Gain 2 Control
SYNTHESIZER
RF In
LOW NOISE AMP
LOW NOISE AMP
LOW NOISE AMP
IF I Out IF Q Out
Pentek, Inc.
www.pentek.com
Model 7120
Bandit Two-Channel Analog RF Receiver - PMC/XMC

Specifications
RF Input Connector Type: SSMC Input Impedance: 50 ohms Input Level Range: 60 dBm to 20 dBm Flatness: 2 dB from 400 MHz to 1 GHz, 3 dB from 1 GHz to 3 GHz, 5 dB from 3 GHz to 4 GHz RF Attenuator: Programmable from 0 to 63 dB in 0.5 dB steps LO Synthesizer Tuning Frequency range: 4004000 MHz, Resolution: < 10 kHz Tuning Speed: < 500 sec Phase-Locked Loop Bandwidth: 100 kHz Phase Noise 1 kHz: 90 dBc/Hz 100 kHz: 110 dBc/Hz 1 MHz: 130 dBc/Hz Noise Figure (referred to input) 60 dB gain: 2.6 dB Inband Output IP3 20 dB gain: +10 dBm 60 dB gain: +42 dBm Reference Input/Output Connector Type: SSMC Input/Output Impedence: 50 ohms Reference Input Signal Frequency: 10 MHz Level: 0 dBm, sine wave Reference Output Signal Frequency: 10 MHz Level: 0 dBm, sine wave OCXO Reference Center Frequency: 10 MHz Frequency Stability vs. Change in Temperature: 50.0 ppb Frequency Calibration: 1.0 ppm Aging Daily: 10 ppb/day First Year: 300 ppb Total Frequency Tolerance (20 years): 4.60 ppm Phase Noise 1 Hz Offset: 67 dBc/Hz 10 Hz Offset: 100 dBc/Hz 100 Hz Offset: 130 dBc/Hz 1 KHz Offset: 148 dBc/Hz 10 KHz Offset: 154 dBc/Hz 100 KHz Offset: 155 dBc/Hz IF Output Connector Type: SSMC Output Impedance: 50 ohms Center Frequency: User definable Output Level: 0 dBm, nominal Programming Functions: RF Atten, IF Atten, Int/Ext Reference Select, LO Synthesizer Frequency Interface: USB Connector Type: MicroUSB Power Voltage: +12 VDC Current: 1.5 A PMC/XMC Interface: Power only on PMC P11 (option -104) or XMC P15 (option -105) Size: Standard PMC module, 2.91 in. x 5.87 in.
Model 7120 Description Bandit Two-Channel Analog RF Receiver PMC/XMC Description Oven Controlled Refernece Oscillator PMC P11 Power XMC P15 Power PCIe 6-pin connector (Power only) 1.45 GHz lowpass input filter 2.80 GHz lowpass input filter
Option -015 -104 -105 -106 -145 -280
Pentek, Inc.
www.pentek.com
! w e N
Model 7820
Bandit Two-Channel Analog RF Receiver - PCIe

General Information
The Bandit Model 7820 is a two-channel, high-performance, stand-alone analog RF receiver. Packaged in a small, shielded PCIe board with front-panel connectors for easy integration into RF systems, the board offers programmable gain, high dynamic range and a low noise figure. With an input frequency range from 400 to 4000 MHz and a wide IF bandwidth of up to 390 MHz, the 7820 is an ideal solution for amplifying and downconverting antenna signals for communications, radar and signal intelligence systems. with amplitude and phase balances of ~0.07 dB and ~0.2, respectively.
Tuning Accuracy



Wide Output
Quadrature Mixers
RF In
LOW NOISE AMP
LOW NOISE AMP
LOW NOISE AMP
IF I Out IF Q Out
Gain 1 Control
Gain 2 Control
SYNTHESIZER
Ref Out
USB
Gain 2 Control
SYNTHESIZER
RF In
LOW NOISE AMP
LOW NOISE AMP
LOW NOISE AMP
IF I Out IF Q Out
Pentek, Inc.
www.pentek.com
Model 7820
Bandit Two-Channel Analog RF Receiver - PCIe

Specifications
RF Input Connector Type: SSMC Input Impedance: 50 ohms Input Level Range: 60 dBm to 20 dBm Flatness: 2 dB from 400 MHz to 1 GHz, 3 dB from 1 GHz to 3 GHz, 5 dB from 3 GHz to 4 GHz RF Attenuator: Programmable from 0 to 63 dB in 0.5 dB steps LO Synthesizer Tuning Frequency range: 4004000 MHz, Resolution: < 10 kHz Tuning Speed: < 500 sec Phase-Locked Loop Bandwidth: 100 kHz Phase Noise 1 kHz: 90 dBc/Hz 100 kHz: 110 dBc/Hz 1 MHz: 130 dBc/Hz Noise Figure (referred to input) 60 dB gain: 2.6 dB Inband Output IP3 20 dB gain: +10 dBm 60 dB gain: +42 dBm Reference Input/Output Connector Type: SSMC Input/Output Impedence: 50 ohms Reference Input Signal Frequency: 10 MHz Level: 0 dBm, sine wave Reference Output Signal Frequency: 10 MHz Level: 0 dBm, sine wave OCXO Reference Center Frequency: 10 MHz Frequency Stability vs. Change in Temperature: 50.0 ppb Frequency Calibration: 1.0 ppm Aging Daily: 10 ppb/day First Year: 300 ppb Total Frequency Tolerance (20 years): 4.60 ppm Phase Noise 1 Hz Offset: 67 dBc/Hz 10 Hz Offset: 100 dBc/Hz 100 Hz Offset: 130 dBc/Hz 1 KHz Offset: 148 dBc/Hz 10 KHz Offset: 154 dBc/Hz 100 KHz Offset: 155 dBc/Hz IF Output Connector Type: SSMC Output Impedance: 50 ohms Center Frequency: User definable Output Level: 0 dBm, nominal Programming Functions: RF Atten, IF Atten, Int/Ext Reference Select, LO Synthesizer Frequency Interface: USB Connector Type: MicroUSB Power Voltage: +12 VDC Current: 1.5 A PCI-Express Interface PCI Express Bus: x4 or x8, power only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.
Model 7820 Description Bandit Two-Channel Analog RF Receiver PCIe Description Oven Controlled Reference Oscillator 1.45 GHz lowpass input filter 2.80 GHz lowpass input filter
Option -015 -145 -280
Pentek, Inc.
www.pentek.com
! w e N
Model 5220
Bandit Two-Channel Analog RF Receiver - 3U VPX

General Information
The Bandit Model 5220 is a two-channel, high-performance, stand-alone analog RF receiver. Packaged in a small, shielded 3U VPX board with front-panel connectors for easy integration into RF systems, the board offers programmable gain, high dynamic range and a low noise figure. With an input frequency range from 400 to 4000 MHz and a wide IF bandwidth of up to 390 MHz, the 5220 is an ideal solution for amplifying and downconverting antenna signals for communications, radar and signal intelligence systems. with amplitude and phase balances of ~0.07 dB and ~0.2, respectively.
Tuning Accuracy



Wide Output
Quadrature Mixers
RF In
LOW NOISE AMP
LOW NOISE AMP
LOW NOISE AMP
IF I Out IF Q Out
Gain 1 Control
Gain 2 Control
SYNTHESIZER
Ref Out
USB
Gain 2 Control
SYNTHESIZER
RF In
LOW NOISE AMP
LOW NOISE AMP
LOW NOISE AMP
IF I Out IF Q Out
Pentek, Inc.
www.pentek.com
Model 5220
Bandit Two-Channel Analog RF Receiver - 3U VPX

Specifications
RF Input Connector Type: SSMC Input Impedance: 50 ohms Input Level Range: 60 dBm to 20 dBm Flatness: 2 dB from 400 MHz to 1 GHz, 3 dB from 1 GHz to 3 GHz, 5 dB from 3 GHz to 4 GHz RF Attenuator: Programmable from 0 to 63 dB in 0.5 dB steps LO Synthesizer Tuning Frequency range: 4004000 MHz, Resolution: < 10 kHz Tuning Speed: < 500 sec Phase-Locked Loop Bandwidth: 100 kHz Phase Noise 1 kHz: 90 dBc/Hz 100 kHz: 110 dBc/Hz 1 MHz: 130 dBc/Hz Noise Figure (referred to input) 60 dB gain: 2.6 dB Inband Output IP3 20 dB gain: +10 dBm 60 dB gain: +42 dBm Reference Input/Output Connector Type: SSMC Input/Output Impedence: 50 ohms Reference Input Signal Frequency: 10 MHz Level: 0 dBm, sine wave Reference Output Signal Frequency: 10 MHz Level: 0 dBm, sine wave OCXO Reference Center Frequency: 10 MHz Frequency Stability vs. Change in Temperature: 50.0 ppb Frequency Calibration: 1.0 ppm Aging Daily: 10 ppb/day First Year: 300 ppb Total Frequency Tolerance (20 years): 4.60 ppm Phase Noise 1 Hz Offset: 67 dBc/Hz 10 Hz Offset: 100 dBc/Hz 100 Hz Offset: 130 dBc/Hz 1 KHz Offset: 148 dBc/Hz 10 KHz Offset: 154 dBc/Hz 100 KHz Offset: 155 dBc/Hz IF Output Connector Type: SSMC Output Impedance: 50 ohms Center Frequency: User definable Output Level: 0 dBm, nominal Programming Functions: RF Atten, IF Atten, Int/Ext Reference Select, LO Synthesizer Frequency Interface: USB Connector Type: MicroUSB Power Voltage: +12 VDC Current: 1.5 A PCI Express Interface PCIe Bus: x4, power only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Model 5220 Description Bandit Two-Channel Analog RF Receiver 3U VPX Description Oven Controlled Reference Oscillator 1.45 GHz lowpass input filter 2.80 GHz lowpass input filter
Option -015 -145 -280
Pentek, Inc.
www.pentek.com
! w e N
Models 7220, 7420 and 7320
Bandit Two-Channel Analog RF Receiver - 6U/3U cPCI

General Information
These Bandit models are two-or fourchannel, high-performance, stand-alone analog RF receivers. Packaged in small, shielded cPCI boards with front-panel connectors for easy integration into RF systems, they offer programmable gain, high dynamic range and a low noise figure. Model 7320 is a 3U cPCI booard while Model 7220 is a 6U cPCI board; both provide two channels, while Model 7420 is a double-density 6U cPCI board that provides four channels. With an input frequency range from 400 to 4000 MHz and a wide IF bandwidth of up to 390 MHz, these models are ideal solutions for amplifying and downconverting antenna signals for communications, radar and signal intelligence systems. are capable of excellent accuracy with amplitude and phase balances of ~0.07 dB and ~0.2, respectively.
Tuning Accuracy
These models use the Analog Devices ADF4351 low-noise, on-board frequency synthesizer as the LO (Local Oscillator). Locked to an external input reference for accuracy with a fractional-N phase-locked loop, its frequency is programmable across the 400 to the 4000 MHz band with a tuning resolution of better than 100 kHz.

In addition to accepting a 10 MHz reference signal on the front panel, these models include on-board 10 MHz crystal oscillators which can be used as the reference to lock the internal LO frequency synthesizers. This reference is an OCXO (Oven Controlled Crystal Oscillator), which provides an exceptionally precise frequency standard with excellent phase noise characteristics.
Model 7420
Model 7320

The models accept RF signals on two or four front-panel SSMC connectors. LNAs (Low Noise Amplifiers) are provided, along with two programmable attenuators allowing downconversion of input signals ranging from 60 dBm to 20 dBm in steps of 0.5 dB.
Wide Output
Outputs are provided as baseband I and Q signals at bandwidths up to 390 MHz. Alternatively, either I or Q output can be used at some intermediate offset frequency convenient to the application. User-provided in-line output IF filters allow customizing the output bandwidth and offset frequency to the specific application requirements. This output is suitable for A/D conversion using Pentek high-performance signal acquisition products, such as those in the Cobalt and Onyx families.
Features

Input Filter Options

Accept RF signals from 400 MHz to 4000 MHz Accept RF input levels from -60 dBm to -20 dBm Baseband IF output with up to 390 MHz bandwidth Internal OCXO or external 10 MHz frequency reference
Quadrature Mixers
These models feature a Analog Devices ADL5380 quadrature mixers. The ADL5380s
RF In
LOW NOISE AMP
LOW NOISE AMP
LOW NOISE AMP
IF I Out IF Q Out
Gain 1 Control
Gain 2 Control
SYNTHESIZER
Ref Out
USB
Gain 2 Control
SYNTHESIZER
RF In
LOW NOISE AMP
LOW NOISE AMP
LOW NOISE AMP
IF I Out IF Q Out
Pentek, Inc.
www.pentek.com
Models 7220, 7420 and 7320
Bandit Two-Channel Analog RF Receiver - 6U/3U cPCI

Specifications
RF Input Connector Type: SSMC Input Impedance: 50 ohms Input Level Range: 60 dBm to 20 dBm Flatness: 2 dB from 400 MHz to 1 GHz, 3 dB from 1 GHz to 3 GHz, 5 dB from 3 GHz to 4 GHz RF Attenuator: Programmable from 0 to 63 dB in 0.5 dB steps LO Synthesizer Tuning Frequency range: 4004000 MHz, Resolution: < 10 kHz Tuning Speed: < 500 sec Phase-Locked Loop Bandwidth: 100 kHz Phase Noise 1 kHz: 90 dBc/Hz 100 kHz: 110 dBc/Hz 1 MHz: 130 dBc/Hz Noise Figure (referred to input) 60 dB gain: 2.6 dB Inband Output IP3 20 dB gain: +10 dBm 60 dB gain: +42 dBm Reference Input/Output Connector Type: SSMC Input/Output Impedence: 50 ohms Reference Input Signal Frequency: 10 MHz Level: 0 dBm, sine wave Reference Output Signal Frequency: 10 MHz Level: 0 dBm, sine wave OCXO Reference Center Frequency: 10 MHz Frequency Stability vs. Change in Temperature: 50.0 ppb Frequency Calibration: 1.0 ppm Aging Daily: 10 ppb/day First Year: 300 ppb Total Frequency Tolerance (20 years): 4.60 ppm Phase Noise 1 Hz Offset: 67 dBc/Hz 10 Hz Offset: 100 dBc/Hz 100 Hz Offset: 130 dBc/Hz 1 KHz Offset: 148 dBc/Hz 10 KHz Offset: 154 dBc/Hz 100 KHz Offset: 155 dBc/Hz IF Output Connector Type: SSMC Output Impedance: 50 ohms Center Frequency: User definable Output Level: 0 dBm, nominal Programming Functions: RF Atten, IF Atten, Int/Ext Reference Select, LO Synthesizer Frequency Interface: USB Connector Type: MicroUSB Power Voltage: +12 VDC Current: 1.5 A PCI Interface PCI Bus: 32-bit, 66 MHz (supports 33 MHz), power only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 3U or 6U cPCI board
Model 7220 Description Bandit Two-Channel Analog RF Receiver 6U cPCI Bandit Two-Channel Analog RF Receiver 3U cPCI Bandit Four-Channel Analog RF Receiver 6U cPCI Description Oven Controlled Reference Oscillator 1.45 GHz lowpass input filter 2.80 GHz lowpass input filter
7320
7420
Option -015 -145 -280
Pentek, Inc.
www.pentek.com
! w e N
Model 5620
Bandit Two-Channel Analog RF Receiver - AMC

General Information
The Bandit Model 5620 is a two-channel, high-performance, stand-alone analog RF receiver. Packaged in a small, shielded AMC board with front-panel connectors for easy integration into RF systems, the board offers programmable gain, high dynamic range and a low noise figure. With an input frequency range from 400 to 4000 MHz and a wide IF bandwidth of up to 390 MHz, the 5620 is an ideal solution for amplifying and downconverting antenna signals for communications, radar and signal intelligence systems. with amplitude and phase balances of ~0.07 dB and ~0.2, respectively.
Tuning Accuracy



Wide Output
Quadrature Mixers
RF In
LOW NOISE AMP
LOW NOISE AMP
LOW NOISE AMP
IF I Out IF Q Out
Gain 1 Control
Gain 2 Control
SYNTHESIZER
Ref Out
USB
Gain 2 Control
SYNTHESIZER
RF In
LOW NOISE AMP
LOW NOISE AMP
LOW NOISE AMP
IF I Out IF Q Out
Pentek, Inc.
www.pentek.com
Model 5620
Bandit Two-Channel Analog RF Receiver - AMC

Specifications
RF Input Connector Type: SSMC Input Impedance: 50 ohms Input Level Range: 60 dBm to 20 dBm Flatness: 2 dB from 400 MHz to 1 GHz, 3 dB from 1 GHz to 3 GHz, 5 dB from 3 GHz to 4 GHz RF Attenuator: Programmable from 0 to 63 dB in 0.5 dB steps LO Synthesizer Tuning Frequency range: 4004000 MHz, Resolution: < 10 kHz Tuning Speed: < 500 sec Phase-Locked Loop Bandwidth: 100 kHz Phase Noise 1 kHz: 90 dBc/Hz 100 kHz: 110 dBc/Hz 1 MHz: 130 dBc/Hz Noise Figure (referred to input) 60 dB gain: 2.6 dB Inband Output IP3 20 dB gain: +10 dBm 60 dB gain: +42 dBm Reference Input/Output Connector Type: SSMC Input/Output Impedence: 50 ohms Reference Input Signal Frequency: 10 MHz Level: 0 dBm, sine wave Reference Output Signal Frequency: 10 MHz Level: 0 dBm, sine wave OCXO Reference Center Frequency: 10 MHz Frequency Stability vs. Change in Temperature: 50.0 ppb Frequency Calibration: 1.0 ppm Aging Daily: 10 ppb/day First Year: 300 ppb Total Frequency Tolerance (20 years): 4.60 ppm Phase Noise 1 Hz Offset: 67 dBc/Hz 10 Hz Offset: 100 dBc/Hz 100 Hz Offset: 130 dBc/Hz 1 KHz Offset: 148 dBc/Hz 10 KHz Offset: 154 dBc/Hz 100 KHz Offset: 155 dBc/Hz IF Output Connector Type: SSMC Output Impedance: 50 ohms Center Frequency: User definable Output Level: 0 dBm, nominal Programming Functions: RF Atten, IF Atten, Int/Ext Reference Select, LO Synthesizer Frequency Interface: USB Connector Type: MicroUSB Power Voltage: +12 VDC Current: 1.5 A PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8, power only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.
Model 5620 Description Bandit Two-Channel Analog RF Receiver AMC Description Oven Controlled Reference Oscillator 1.45 GHz lowpass input filter 2.80 GHz lowpass input filter
Option -015 -145 -280
Pentek, Inc.
www.pentek.com
! w e N
Model 8111
Bandit Modular Analog RF Slot Downconverter Series

General Information
The Bandit Model 8111 provides a series of high-performance, stand-alone RF downconverter modules. Packaged in a small, shielded enclosure with connectors for easy integration into RF systems, the modules offer programmable gain, high dynamic range and a low noise figure. With input options to cover specific frequency bands of the RF spectrum, and an IF output optimized for A/D converters, the 8111 is an ideal solution for amplifying and downconverting antenna signals for communications, radar and signal intelligence systems. Option 001 002 003 004 005 006 007 Frequency Band 800-1200 MHz 1100-1500 MHz 1400-1800 MHz 1700-2100 MHz 2000-2400 MHz 2300-2700 MHz 2600-3000 MHz
Tuning Accuracy
The 8111 uses a low-noise, on-board frequency synthesizer as the LO (Local Oscillator). Locked to an external input reference for accuracy, its frequency is programmable across the 400 MHz band with a tuning resolution of 1 MHz. Alternatively, for applications demanding custom local oscillator characteristics, an external LO input signal can be accepted on a front panel connector and used instead of the on-board frequency synthesizer.

The 8111 accepts RF signals on a front panel SMA connector. An LNA (Low Noisefigure Amplifier) is provided along with two programmable attenuators allowing downconversion of input signals ranging from -60 dBm to -20 dBm in steps of 0.5 dB. Higher level signals can be attenuated prior to input.

In addition to accepting a reference signal on the front panel, the 8111 includes an on-board 10 MHz crystal oscillator which can be used as the reference to lock the internal LO frequency synthesizer. This reference is an OCXO (Oven Controlled Crystal Oscillator), which provides an exceptionally precise frequency standard with excellent phase noise characteristics.
Features
Accepts RF signals from 800 MHz to 3.000 GHz in seven different models Accepts RF input levels from -60 to -20 dBm 225 MHz IF output with 80 MHz output bandwidth Internal OCXO or external 10 MHz frequency reference
Preselector Options
Seven different input-frequency band options are offered, each tunable across a 400 MHz band, with an overlap of 100 MHz between adjacent bands. As a group, these seven options accommodate RF input signals from 800 MHz to 3.000 GHz as follows:
Wide IF Output
An 80 MHz wide IF output is provided at a 225 MHz center frequency . This output is suitable for A/D conversion using Pentek high-performance signal acquisition products, such as those in the Cobalt and Onyx families.
RF In
LOW NOISE AMP
BANDPASS FILTER
STEP ATTENUATOR
GAIN BLOCK
MIXER
GAIN BLOCK
IF FILTER
STEP ATTENUATOR
GAIN BLOCK
IF Out
Control In
USB INTERFACE
RF Attenuation IF Attenuation LO Select LO Synthesizer Tuning Frequency
GAIN BLOCK
RF SWITCH OVEN CONTROLLED CRYSTAL OSCILLATOR
LO
Ref In
Ext LO In
Ref Out
Pentek, Inc.
www.pentek.com
Model 8111
Bandit Modular Analog RF Slot Downconverter Series

Specifications
RF Input Connector Type: SMA Input Impedance: 50 ohms Input Level Range: -60 dBm to -20 dBm Flatness: 1 dB typical over each 400 MHz range RF Attenuator: Programmable from 0 to 31.5 dB in 0.5 dB steps LO Synthesizer Tuning Frequency range: 800-3000 MHz, across seven different options Resolution: 1 MHz Tuning Speed: < 500 sec PLL Loop Bandwidth: 100 kHz Phase Noise 1 kHz: -90 dBc/Hz 100 kHz: -110 dBc/Hz 1 MHz: -130 dBc/Hz Noise Figure (referred to input) 60 dB gain: 2.6 dB Inband Output IP3 20 dB gain: +10 dBm 60 dB gain: +42 dBm Reference / External LO Input Connector Type: SMA Input Impedence: 50 ohms Reference Input Signal Frequency: 10 MHz Level: 0 dBm to +20 dBm, sinewave External LO Input Signal Frequency: IN+225 MHz, where IN= RF input signal frequency Level: 0 dBm 2 dBm OCXO Reference Output Connector Type: SMA Center Frequency: 10 MHz Output Impedance: 50 ohms Output Level: +10 dBm, nominal, sine wave Frequency Stability vs. Change in Temperature: 50.0 ppb Frequency Calibration: 1.0 ppm Aging Daily: 10 ppb/day First Year: 300 ppb Total Frequency Tolerance (20 years): 4.60 ppm Phase Noise 1 Hz Offset: -67 dBc/Hz 10 Hz Offset: -100 dBc/Hz 100 Hz Offset: -130 dBc/Hz 1 KHz Offset: -148 dBc/Hz 10 KHz Offset: -154 dBc/Hz 100 KHz Offset: -155 dBc/Hz IF Attenuator: Programmable from 0 to 31.5 dB in 0.5 dB steps IF Output Connector Type: SMA Output Impedance: 50 ohms Center Frequency: 225 MHz Output Level: 0 dBm, nominal Programming Functions: RF Atten, IF Atten, Int/Ext LO Select, LO Synthezier Frequency Interface: USB Connector Type: MicroUSB Power Voltage: +12VDC Current: 1.5 A Connector Type: Micro DB-9, female Size: Module, 3.75 in x 7.5 in x 0.7 in
Model 8111 Description Bandit Modular RF Slot Downconverter Input Frequency Band 800-1200 MHz 1100-1500 MHz 1400-1800 MHz 1700-2100 MHz 2000-2400 MHz 2300-2700 MHz 2600-3000 MHz
Option 001 002 003 004 005 006 007
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Model 8266

General Information
The Model 8266 is a fully-integrated PC development system for Pentek 786xx Cobalt and 787xx Onyx PCI Express software radio, data acquisition, and I/O boards. It was created to save engineers and system integrators the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. A fully-integrated system-level solution, the 8266 provides the user with a streamlined out-of-the-box experience. It comes preconfigured with Pentek hardware, drivers and software examples installed and tested to allow development engineers to run example applications out of the box. The 8266 uses a 19 4U rackmount chassis that is 21 deep. Enhanced forcedair ventilation assures adequate cooling for Pentek Cobalt and Onyx boards. The chassis is designed to draw cool air from the front and push warm air out the back. A 1000 W, 80+ Gold Power Supply guarantees more than enough power for additional boards.
Configuration
Pentek uses a variety of motherboards to provide the flexibility for operation and cooling of each system. Up to four Pentek Cobalt or Onyx boards in the 8266 can be supported. Please contact Pentek to configure a system that requires additional PCIe slots for 3rd party hardware.
ReadyFlow Software
Pentek ReadyFlow drivers and board support libraries are preinstalled and tested with the 8266. ReadyFlow includes example applications with full source code, a command line interface for custom control over hardware, and Penteks Signal Analyzer, a full-featured analysis tool that continuously displays live signals in both time and frequency domains.
Options
Options for high-end multicore CPUs and extended memory support applications that require additional horsepower. All necessary analog I/O cables are installed and tested, providing SMA connectivity for all analog I/O lines.
Features
4U 19-inch rackmount PC server chassis, 21-inch deep 64-bit Windows 7 Professional or Linux workstation Intel CoreTM i7 3.6 GHz processor 8 GB DDR3 SDRAM ReadyFlow drivers and board support libraries installed Out-of-the-box test examples All I/O cables included
Specifications
Operating System: 64-bit Windows 7 Professional or Linux Processor: Intel Core i7 processor Clock Speed: 3.6 GHz SDRAM: 8 GB Dimensions: 4U Chassis, 19" W x 21" D x 7" H Weight: 35 lb, approx. Operating Temp: 0 to +50 C Storage Temp: 40 to +85 C Relative Humidity: 5 to 95%, non-condensing Power Requirements: 100 to 240 VAC, 50 to 60 Hz, 1000 W max.
System Implementation
Built on a professional 4U rackmount workstation, the 8266 is equipped with the latest Intel processor, DDR3 SDRAM and a high-performance motherboard. These features accelerate application code development and provide unhindered access to the high-bandwidth data available with Cobalt and Onyx analog and digital interfaces. The 8266 can be configured with 64-bit Windows or Linux operating systems.
Model 8266 Description PC Development System for PCIe Cobalt and Onyx Boards 64-bit Linux OS 64-bit Windows 7 OS Upgrade to 64 GB DDR3 SDRAM
Options: -094 -095 -101
The addition of third-party PCIe cards may affect system performance. Please consult with us before doing so.
Pentek, Inc.
www.pentek.com
PROCESSORS
MODEL
4207
DESCRIPTION
MPC 8641 PowerPC I/O Processor with Virtex-4 FPGA - VME/VXS
Last updated: June 2013

www.pentek.com
Model 4207
MPC8641 PowerPC I/O Processor with Virtex-4 FPGA -VME/VXS

General Information
The Pentek Model 4207 PowerPCTM VME/VXS I/O Processor board targets embedded applications that require high performance I/O and processing. With two PMC/XMC module sites, the 4207 offers powerful one-slot solutions with nearly unlimited high-speed connectivity. executes both fixed- and floating-point instructions. It is available with either a single or dual e600 PowerPC core with maximum clock frequency of 1.2 GHz. Built-in gigabit serial data ports provide 4X Serial RapidIO.
Zero Latency Crossbar Switch

The 4207 features a zero-latency fabrictransparent crossbar switch that bridges various board interfaces and resources via gigabit serial data paths. Programmable signal input equalization and output preemphasis settings enable optimization for each application. Gigabit serial paths include links to the processor that can be used for 4X Serial RapidIO. Other gigabit paths are not restricted to any protocol, and include two 4X links to each XMC module site, two 4X links (or four 2X links) to the FPGA RocketIO ports, and another pair of 4X links to the optional P0-VXS connector. The switch also provides high-speed connectivity to the optional Fibre Channel controller and front panel optical gigabit serial interface.
Uniquely Designed for Connectivity

The 4207 supports numerous interfaces including VME64x, Gigabit Ethernet, RS232 and dual 4 Gbit Fibre Channel. A unique crossbar switch architecture connects the XMC module sites, optical and VXS connectors, fibre channel interface, FPGA, and processor to high-speed gigabit serial data paths. All interfaces can be included without exceeding one VMEbus slot. Some processing-intensive applications may require two slots for optimized convection cooling.
MPC8641 AltiVec Processor

The Freescale MPC8641 utilizes the AltiVecTM engine to perform parallel processing of multiple data elements (SIMD) with 128-bit operations. The AltiVec processor
PCI-X
64
PCI-X
Front Panel I/O Front Panel I/O
PMC/XMC MEZZANINE MODULE SITE 1
PCI BR DGE
DUAL FIBRE CHANNEL CONTROLLER
DDR2 SDRAM 512 MB
4X Gbit Serial 4X Gbit Serial
VIRTEX-4 FPGA XC4VFX60 or XC4VFX100
64
DDR2 SDRAM 512 MB
16
FLASH 128 MB
Features
DUAL 10/100/1000Base-T ETHERNET I/O
64
64
MPC8641 SINGLE/DUAL CORE PROCESSOR PowerPC

16 FLASH 128 MB REAL TIME CLOCK 2
Dual 4X Gbit Serial 4X SRIO PCI EXPRESS to PCI-X BRIDGE

P0 - VXS (V TA 41)
P0
PowerPC
ZERO LATENCY CROSSBAR SWITCH WITH SIGNAL EQUALIZATION
Dual 1000Base-X E he net I/O
Front Panel I/O Front Panel I/O
QUAD RS-232 I/O
To PGA
FRONT PANEL DUAL OPTICAL I/O INTERFACE (Fibre Channel, SRIO...)
PCI-X BUS 0 (64 Bits, 100 MHz)
Front Panel I/O
4X Gbit Serial PMC/XMC MEZZANINE MODULE SITE 0 P4 4X Gbit Serial

PCI BR DGE Ts 148 VME64X INTERFACE 64
P1
64
P2
Pentek, Inc.
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VMEbus
VXS V TA 41
Freescale MPC8641 single or dual core PowerPC processor to 1.2 GHz Xilinx Virtex-4 FX Series FPGA Hosts two PMC or XMC modules On-board dual gigabit Ethernet interfaces Optional on-board 4-Gbit dual optical Fibre Channel controller Optional dual optical gigabit serial / Fibre Channel interface Up to 3 GB DDR2 SDRAM Two 64-bit PCI-X buses VME64x master/slave interface Optional VXS interface Ruggedized and conductioncooled versions
DDR2 SDRAM 1 GB
DDR2 SDRAM 1 GB
PCI-X BUS 1 (64 Bits, 100 MHz)
Dual 4X RocketIO Serial
Model 4207
Support Software
The Model 4207 is supported by world-class software for initialization, control and optimization. Pentek VxWorks BSPs provide software developers with a complete library of hardware initialization, control and application functions. Used in conjunction with Wind Rivers Workbench software development environment, it speeds application development. Pentek Linux BSPs and Drivers provide software developers with a complete open-source library of hardware initialization, control and application functions to be used in a real-time Linux operating environment. Pentek GateFlow Design Kits allow the onboard FPGA to be configured by the user for implementation of custom preprocessing functions. The kit is used in conjunction with the Xilinx ISE FoundationTM design tools. Verari Systems VSI/Pro is an implementation of VSIPL scientific and engineering functions optimized for the PowerPC.
MPC8641 PowerPC I/O Processor with Virtex-4 FPGA -VME/VXS

PMC/XMC Mezzanine Sites
Model 4207 includes two 64-bit PMC module sites which accept industry-standard modules up to 133 MHz for a wide variety of functions. The PMC modules are accessible from the MPC8641 processor and the VMEbus. A PCI bridge at each PMC site allows operation of slower 33 or 66 MHz modules while running the attached PCI-X bus at a higher speed. The 4207 PMC sites are also equipped to accept XMC (switched-fabric PMC) modules. Gigabit switched-fabric connectors are optionally provided to support two 4X fullduplex serial ports per XMC site. Each port allows high-speed data transfer to the crossbar switch using gigabit fabrics such as Xilinx Aurora or Serial RapidIO.
Dual Fibre Channel Interface

The 4207 features an optional dual Fibre Channel controller with optical front panel interface for high-speed data transfer to and from Fibre Channel storage devices. When installed, both optical interfaces are located on the 4207 front panel, along with the dual 10/100/1000Base-T Ethernet and the quad RS-232 interfaces. This allows Fibre Channel data transfer without sacrificing a PMC/XMC site, thus maintaining a single VMEbus slot.
VXS Interface
The 4207 provides two optional 4X fullduplex VITA-41 VXS links to the P0-VXS connector, each capable of peak rates up to 1.25 GB/sec. Each link is attached to the crossbar switch, and compatible with gigabit fabrics such as Xilinx Aurora and Serial RapidIO. The P0-VXS connector also features a dual 1000Base-X Ethernet interface per the VITA 41.6 draft standard.
FPGA Devices
The 4207 optionally includes a Xilinx Virtex-4 FX Series FPGA, the XC4VFX60 or XC4VFX100. Two 4X RocketIO ports provide a high-speed serial data path to and from the FPGA. These ports can also be configured as four 2X paths. Unused FPGA resources are available for the user to implement custom signalprocessing configurations and algorithms using Penteks GateFlow FPGA Design Kit and the high-performance IP Core Library.
Specifications
Processor Resources Processor: Freescale MPC8641 (Single Core) or MPC8641D (Dual Core) Processor clock: 1.2 GHz (-013 or -023) Level 2 cache: 1 MB for MPC8641, 2MB for MPC8641D DDR2 SDRAM: 1 GB or 2 GB (optional, one or two 1 GB banks, each 64 bits wide) FLASH: 128MB, 16 bits wide Node Control: Built into MPC8641 Mezzanines Two PMC/XMC sites Optional FPGA Type: Xilinx Virtex-4 Series (-11 speed) XC4VFX60 (-061) or FX100 (-101) DDR2 SDRAM: 1 GB (optional, two 512 MB banks, each 64 bits wide) FLASH: 128 MB, 16 bits wide (optional) PCI-X Bus #0 Width: 64 bits, Speed: 100 MHz PCI-X Bus #1 Width: 64 bits, Speed: 100 MHz Global Resources VME64x: Tundra Tsi148 master/slave, slot 1 controller, D64, A32 Serial I/O: Four RS232 front panel ports Ethernet: Two 10/100/1000Base-T front panel ports, two 1000Base-X ports on rear P0-VXS connector Optional Fibre Channel Controller: Dual Optical, 4 Gbit (Option -006) Size: standard 6U VMEbus board, single slot; board 160 mm (6.3 in.) x 233.5 mm (9.2 in.), panel 0.8 in. wide
Memory
The 4207 provides a wealth of memory resources with up to 3 Gigabytes of DDR2 SDRAM and 256 MB FLASH. The MPC8641 PowerPC is equipped with two 64-bit banks of DDR2 SDRAM at 512 MB or 1 GB each, for up to 2 GB program and data memory. A nonvolatile 128 MB FLASH memory is also provided for initialization, self-test and boot code. 1 MB on-chip L2 cache is available per processor core. The Virtex-4 FX Series FPGA is optionally equipped with another two 64-bit banks of DDR2 SDRAM at 512 MB each, and 128 MB FLASH memory.
Model 4207 Description MPC8641 PowerPC I/O Processor with Virtex-4 FPGA - VME/VXS
Options: -001 Front Panel Optical Connectors/Transceivers -006 Dual Fibre Channel interface, 4 Gbit/sec -013 Single core 1.2 GHz MPC8641 w/1 GB DDR2 -023 Dual core 1.2 GHz MPC8641D w/1 GB DDR2 -123 Dual core 1.2 GHz MPC8641D w/2 GB DDR2 -061 XC4VFX60-11 FPGA -101 XC4VXF100-11 FPGA -360 1 GB FPGA DDR2 SDRAM + 128 MB FLASH -5xx VXS interface -70x Ruggedized & conductioncooled versions
Two PCI-X Buses

The Model 4207 architecture includes two 64-bit PCI-X buses. PCI-X Bus 0 provides access to the VMEbus and its associated PMC/XMC mezzanine site. PCI-X Bus 1 provides access to its associated PMC/XMC mezzanine site, and the optional dual Fibre Channel interfaces.
Pentek, Inc.
www.pentek.com
HIGH-SPEED RECORDING SYSTEMS

MODEL
Talon RTS 2706 RTS 2707 RTS 2709 RTS 2715 RTS 2716 RTS 2718 RTR 2726 RTR 2727 RTR 2728 RTR 2736 RTR 2738 RTR 2746 RTR 2747 RTR 2748 RTR 2749 RTR 2755 RTR 2756 RTR 2758 RTX 2786
DESCRIPTION
Talon High-Speed Recording Systems: Flexible and Deployable Solutions Eight-Channel RF/IF, 200 MS/sec Rackmount Recorder Four-Channel RF/IF, 500 MS/sec Rackmount Recorder Ultra Wideband One- or Two-Channel RF/IF, 3.2 GS/sec Rackmount Recorder Two-Channel Ten-Gigabit Ethernet Rackmount Recorder Eight-Channel Serial FPDP Rackmount Recorder LVDS Digital I/O Rackmount Recorder Four-Channel RF/IF, 200 MS/sec Rugged Portable Recorder Two-Channel RF/IF, 500 MS/sec Rugged Portable Recorder One-Channel RF/IF, 1 GS/sec Rugged Portable Recorder Eight-Channel Serial FPDP Rugged Portable Recorder LVDS Digital I/O Rugged Portable Recorder Eight-Channel RF/IF, 200 MS/sec Rugged Rackmount Recorder Four-Channel RF/IF, 500 MS/sec Rugged Rackmount Recorder Two-Channel RF/IF, 1 GS/sec Rugged Rackmount Recorder Ultra Wideband One- or Two-Channel RF/IF, 3.2 GS/sec Rugged Rackmount Recorder Two-Channel Ten-Gigabit Ethernet Rugged Rackmount Recorder Eight-Channel Serial FPDP Rugged Rackmount Recorder LVDS Digital I/O Rugged Rackmount Recorder Four-Channel RF/IF, 200 MS/sec Extreme 3U VPX Recorder Customer Information
ANALOG RECORDING SYSTEMS
DIGIT AL RECORDING SYSTEMS DIGITAL
Last updated: December 2013

www.pentek.com
Talon High-Speed Recording Systems: Flexible and Deployable Solutions

High-Speed Recording Systems
Talon High-Speed Recording Systems eliminate the time and risk associated with new technology system development. With increasing pressure in both the defense and commercial arenas to get to the market first, todays system engineers are looking for more complete off-the-shelf system offerings. Out of the box, these systems arrive complete with a full-featured virtual operator control panel ready for immediate data recording and/or playback operation. Because they consist of modular COTS board-level products and flexible control software, they are easily scalable to larger multichannel data acquisition and recording applications requiring sustained, aggregate recording rates of up to 4.0 GB/sec. For example, they can be used as the data acquisition resource for embedded systems in real-time digital signal processing applications. A complete suite of software development tools simplifies custom system integration.
Recording Systems Form Factors

Penteks High-Speed Recording Systems are available as Lab Systems, Portable Systems, Rugged, and Extreme Systems. RTS Lab Systems are housed in a 19-in. rack-mountable chassis in a PC server configuration. They are designed for commercial applications in a lab or office environment.
Systems Include:
High-performance Windows workstation High-performance Intel Processor Pentek SystemFlow recording software with graphical user interface SystemFlow virtual oscilloscope and spectrum analyzer Supported RAID levels of up to 0, 1, 5, 6, 10 and 50 Time stamping support Detailed technical documentation
Ready-to-Run Recording Systems

Depending on model, the Pentek offerings are fully integrated systems featuring a range of A/D and D/A resources or digital I/O with high-speed disk arrays. Since these systems are built on a Windows workstation, users can easily install post-processing and analysis tools to operate on the recorded data. Pentek systems provide a flexible architecture that can be easily customized to meet user needs. Multiple RAID levels of up to 0, 1, 5, 6, 10 and 50, provide a choice for the required level of redundancy.
RTR Portable Systems are available in a small briefcase-sized enclosure with an integral LCD display and keyboard. They, too, provide a PC server configuration and are designed for commercial or harsh environment field applications where size and weight is of paramount importance.
Systems Benefits:

Complete turnkey systems Rack-mountable and portable form factors C-callable API for integration of recorder into application Aggregate recording rates of up to 4.0 GB/sec Recording to non-proprietary NTFS file system for easy and immediate data access Ideal for communications, radar, wireless, SIGINT, telecom and satcom They are easy to use right out-of-the-box Can be controlled over the Ethernet or over the Internet
RTR Rugged Systems are housed in a 19-in. rugged rack-mountable chassis or a briefcase-sized enclosure in a PC server configuration. They are built to survive shock and vibration and they target operation in harsh environments and remote locations that may be unsuitable for humans.
Pentek RTS High-Speed Recording Systems are designed for commercial applications. RTX Extreme Systems are housed in a ATR chassis and are designed to operate under extreme environmental conditions. They use conduction-cooling to draw heat from system components.
Pentek RTR High-Speed Recording Systems are designed for harsh environments.
Pentek RTX High-Speed Recording Systems are designed for extreme environments.
www.pentek.com
Pentek, Inc.
SystemFlow Architecture
Server/Client Architecture
As shown in the block diagram, the SystemFlow architecture provides for easy communication between the recording system Server on the right and the Client PC on the left.
SystemFlow Signal Viewer

SystemFlow also includes signal viewing and analysis tools that allow the user to monitor the signal prior to, during, and after a recording session. These tools include a virtual oscilloscope and a virtual spectrum analyzer. More information on the Signal Viewer is provided on the next page.
SystemFlow GUI
The SystemFlow architecture features a Windows-based GUI (Graphical User Interface) that provides a simple means to configure and control the system. Custom configurations can be stored as profiles and later loaded when needed, allowing the user to select preconfigured settings with a single click.
Server/Client Communication
Server and Client communicate through a standard socket connection. This arrangement enables the Server to provide real-time recording and playback functions that can be controlled from a local or a remote Client. It also allows Client and Server to run on different operating systems.
CLIENT Local or Remote Socket connection SERVER
SystemFlow JAVA Record/Play GUI Application
LabVIEW Signal Viewer Sockets SystemFlow Command Processor User Control Block User Proc. Block
Function Libraries
The function libraries and tools for controlling the recording and playback functions include the Application Programming Interface, the Graphical User Interface and the integrated Signal Viewer.
SystemFlow JAVA Client API
Sockets
API
SystemFlow Record/Play Server Application Windows Drivers
NTFS
NTFS
Client Operating System (Windows/Linux/Other)
Windows Operating System
SystemFlow API
The SystemFlow API allows developers to configure and customize the system interfaces and operation. Source code is supplied for all client API functions. A well-defined set of plugins allows the user to extend server API functions.
NTFS File System

The NTFS file management system provides immediate access to the recorded data, thereby eliminating time-consuming data conversion processes required with proprietary file management systems. It also eliminates the need for custom hardware and software platforms where the recorded data may need to be physically transported for conversion.
Pentek, Inc.
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SystemFlow Graphical User Interface
SystemFlow Recorder Interface

The Recorder Interface provides the user with a control interface for the recording system. It includes Configuration, Record, Playback and Status screens, each with intuitive controls and indicators. The user can easily move between screens to set configuration parameters, control and monitor a recording, play back a recorded signal and monitor board temperature and voltage levels. The signal viewer, integrated into the recording GUI, allows the user to monitor real-time signals or signals recorded on disk.
SystemFlow Hardware Configuration Interface

The Hardware Configuration Interface provides a simple and intuitive means for setting up the system parameters. The DDC configuration screen shown here, provides entries for input source, center frequency, decimation, as well as gate and trigger information. All parameters contain limitchecking and integrated help to provide an easier-to-use out-of-the-box experience.

The SystemFlow Signal Viewer includes a virtual oscilloscope and spectrum analyzer for signal monitoring in both the time and frequency domains. It is extremely useful for previewing live inputs prior to recording, and for monitoring signals as they are being recorded to help ensure successful recording sessions. The viewer can also be used to inspect and analyze the recorded files after the recording is complete. Advanced signal analysis capabilities include automatic calculators for signal amplitude and frequency, second and third harmonic components, THD (total harmonic distortion) and SINAD (signal to noise and distortion). With time and frequency zoom, panning modes and dual, annotated cursors to mark and measure points of interest, the SystemFlow Signal Viewer can often eliminate the need for a separate oscilloscope or spectrum analyzer in the field.
Pentek, Inc.
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Recording and Playback Dataflow

Recording Dataflow
Shown in this diagram is the dataflow during a typical recording session. The Pentek Transceiver Board contains a 2-channel 200 MHz A/D for digitizing two input analog channels. The digitized outputs are downconverted by the two DDCs (Digital Downconverters) and moved on to the PC system memory via the PCI Express interface. Both the DDCs and the PCIe interface are implemented in the boards FPGA. Data then moves from the system memory to the Recording System RAID Controller and is then recorded to disk via the SATA interface. DMA controllers conduct all data transfers, bypasssing the CPU for guaranteed real-time operation.
Sample Clk/Reference Clk In Gate/Trigger/Sync/PPS
Pentek Transceiver Board
TIMING BUS GENERATOR Clock / Sync / Gate / PPS A/D Clock/Sync Bus
DDC #1 DDC #2
Digital IF Channel # 1 Digital IF Channel # 2
200 MHZ 16-Bit A/D
RF/IF Analog Input Channel # 1 RF/IF Analog Input Channel # 2
200 MHZ 16-Bit A/D
2 Channels of Digital Data Being Transferred Over A PCI Express Interface
2 Channels of Digital Data Being Transferred Over A SATA Interface
System Memory CPU Recording System SBC/MB
RAID Controller
SATA Interface
Single Volume RAID 0 Storage Array
Recording System RAID Controller

This board also contains DUCs (Digital Upconverters) which upconvert the data to the original IF frequency bands. Two 800 MHz D/As convert the data to analog form and provide signals that are identical to the analog signals that were originally recorded. These can be further analyzed with any Windows-compatible analysis software.
Sample Clk/Reference Clk In Gate/Trigger/Sync/PPS
Playback Dataflow
During a playback session, data stored on disk moves through the SATA interface of the Playback System RAID Controller. From there, data is passed to the PC system memory through the PCIe interface and then to the Pentek Transceiver board through its PCIe interface, all via hardware DMA controllers for real-time operation.
Pentek Transceiver Board
TIMING BUS GENERATOR Clock / Sync / Gate / PPS D/A Clock/Sync Bus
DUC #1 DUC #2
Digital IF Channel # 1 Digital IF Channel # 2
800 MHZ 16-Bit D/A
RF/IF Analog Output Channel # 1 RF/IF Analog Output Channel # 2
800 MHZ 16-Bit D/A
2 Channels of Digital Data Being Transferred Over A PCI Express Interface
2 Channels of Digital Data Being Transferred Over A SATA Interface
System Memory CPU Playback System SBC/MB
RAID Controller
SATA Interface
Single Volume RAID 0 Storage Array
Playback System RAID Controller
Pentek, Inc.
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! ew N
Model RTS 2706
Eight-Channel RF/IF, 200 MS/sec Rackmount Recorder

General Information
The Talon RTS 2706 is a turnkey, multiband recording and playback system for recording and reproducing high-bandwidth signals. The RTS 2706 uses 16-bit, 200 MHz A/D converters and provides sustained recording rates up to 2 GB/sec in fourchannel configuration. The RTS 2706 uses Penteks high-powered Virtex-6-based Cobalt modules, that provide flexibility in channel count, with optional digital downconversion capabilities. Optional 16-bit, 1.25 GHz D/A converters with digital upconversion allow real-time reproduction of recorded signals. A/D sampling rates, DDC decimations and bandwidths, D/A sampling rates and DUC interpolations are among the GUIselectable system parameters, providing a fully-programmable system capable of recording and reproducing a wide range of signals. Optional GPS time and position stamping allows the user to record this critical signal information. SystemFlow also includes signal viewing and analysis tools, that allow the user to monitor the signal prior to, during, and after a recording session. These tools include a virtual oscilloscope and a virtual spectrum analyzer. Built on a Windows 7 Professional workstation, the RTS 2706 allows the user to install post processing and analysis tools to operate on the recorded data. The RTS 2706 records data to the native NTFS file system, providing immediate access to the recorded data. Data can be off-loaded via two gigabit Ethernet ports, six USB 2.0 ports or two eSATA ports. Additionally, data can be copied to optical disk, using the 8X double layer DVDR/RW drive.
Features
Complete multiband recording and playback system 4U 19-inch industrial rackmount PC server chassis Windows 7 Professional workstation with high-performance Intel CoreTM i7 processor 200 MHz max. 16-bit A/D sampling for recording, up to to eight channels 1.25 GHz max. 16-bit D/A sampling for playback, up to eight channels 80 MHz max. record and playback signal bandwidths Capable of record/playback of IF frequencies to 700 MHz Real-time sustained recording rates of up to 2 GB/sec Up to 20 terabytes of storage to NTFS RAID disk array RAID levels of 0 ,1, 5 , 6, 10 and 50 SystemFlow GUI with signal viewer analysis tool C-callable API for integration of recorder into application File headers include time stamping and recording parameters DDC decimation and DUC interpolation range from 2 to 65,536 Optional GPS time and position stamping
Flexible Architecture
The RTS 2706 is configured in a 4U 19" rack-mountable chassis, with hot-swappable data drives, front panel USB ports and I/O connectors on the rear panel. Systems are scalable to accommodate multiple chassis to increase channel counts and aggregate data rates. All recorder chassis are connected via Ethernet and can be controlled from a single GUI either locally or from a remote PC. Multiple RAID levels, including 0, 1, 5, 6, 10 and 50, provide a choice for the required level of redundancy. Up to 20 hot-swappable SATA drives are optionally available, allowing up to 20 terabytes of real-time data storage space in a single 4U chassis.
SystemFlow Software
The RTS 2706 includes the SystemFlow Recording Software. SystemFlow features a Windows-based GUI (Graphical User Interface) that provides a simple means to configure and control the system. Custom configurations can be stored as profiles and later loaded when needed, allowing the user to select preconfigured settings with a single click.
2 Channels In 200 MHz 16-bit A/D Up to 8 Channels DIGITAL DOWNCONVERTER Decimation: 2 to 65,536 6 INTEL PROCESSOR 2
Gigabit Ethernet USB 2.0 eSATA PS/2 Keyboard PS/2 Mouse Video Output GPS Antenna (Optional)
SYSTEM DRIVE Channels Out 800 MHz or 1.25 GHz 16-bit D/A Up to 8 Channels DIGITAL UPCONVERTER Decimation: 2 to 65,536
DDR SDRAM
HOST PROCESSOR RUNNING SYSTEMFLOW
DATA DRIVES
DATA DRIVES
DATA DRIVES
DATA DRIVES
Contact factory for options, number and type of analog channels, recording rates, and disk capacity.
UP TO 20 TB RAID
MODEL RTS 2706
Pentek, Inc.
www.pentek.com
Model RTS 2706

The RTS 2706 GUI provides the user with a control interface for the recording system. It includes Configuration, Record, Playback and Status screens, each with intuitive controls and indicators. The user can easily move between screens to set configuration parameters, control and monitor a recording, play back a recorded signal and monitor board temperature and voltage levels. The signal viewer, integrated into the recording GUI, allows the user to monitor real-time signals or signals recorded on disk.

The RTS 2706 configuration screens provide a simple and intuitive means for setting up the system parameters. The DDC configuration screen shown here, provides entries for input source, center frequency, decimation, as well as gate and trigger information. All parameters contain limitchecking and integrated help to provide an easier-to-use out-of-the-box experience.

Pentek, Inc.
www.pentek.com
Model RTS 2706

A/D Performance
Spurious Pick-up
Spurious Free Dynamic Range
fin = 70 MHz, fs = 200 MHz, Internal Clock Two-Tone SFDR
fs = 200 MHz, Internal Clock Two-Tone SFDR
f1 = 30 MHz, f2 = 70 MHz, fs = 200 MHz Adjacent Channel Crosstalk
f1 = 69 MHz, f2 = 71 MHz, fs = 200 MHz Input Frequency Response
fin Ch2 = 70 MHz, fs = 200 MHz, Ch 1 shown Spurious Free Dynamic Range
fs = 200 MHz, Internal Clock Spurious Free Dynamic Range
D/A Performance
fout = 70 MHz, fs = 200 MHz, Internal Clock
fout = 120 MHz, fs = 400 MHz, External Clock
Pentek, Inc.
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Model RTS 2706

Specifications

Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Digital Upconverter and D/As Type: TI DAC5688 and Pentek-installed interpolation IP core Interpolation: 2 to 65,536 in two stages of 2 to 256 Input Data Rate: 250 MHx max. Output IF: DC to 400 MHz Output Signal: Analog, real or quadrature Output Sampling Rate: 800 MHz max. with 2, 4 or 8 interpolation Resolution: 16 bits Clock Sources: Selectable from onboard programmable VCXO, external or LVDS clocks External Clocks Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, 10 to 200 MHz Multi-Recorder Sync/Gate Bus: 26-pin connector, dual clock/ sync/gate input/output LVDS buses; one sync/gate input TTL signal Physical and Environmental Size: 19" W x 26" D x 7" H Weight: 60-85 lb Operating Temp: +5 to +45 C Storage Temp: 40 to +85 C Relative Humidity: 5 to 95%, non-condensing Power Requirements: 100 to 240 VAC, 50 to 60 Hz, 500 W max.
PC Workstation (standard configuration) Operating System: Windows 7 Professional Processor: Intel Core i7 processor Clock Speed: 2.0 GHz or higher SDRAM: 6 GB RAID Storage: 220 TB Number of Drives: 120 Supported RAID Levels: 0, 1, 5, 6, 10 and 50 Analog Recording Input / Output Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverter Type: Virtex-6 installed DDC IP Core Decimation: 2 to 65,536 in two stages of 2 to 256 Bandwidth: Up to 80 MHz
Model RTS 2706 Order Information

Recording Options
Option 201 Option 202 Option 203 Option 204 Option 208 1-Channel recording 2-Channel recording 3-Channel recording 4-Channel recording 8-Channel recording
Storage Options
Option 240 Option 241 Option 242 Option 243 Option 244 Option 245 Option 246 2 TB Storage capacity 4 TB Storage capacity 6 TB Storage capacity 8 TB Storage capacity 12 TB Storage capacity 16 TB Storage capacity 20 TB Storage capacity
Playback Options
Option 221 Option 222 Option 224 Option 228 1-Channel playback 2-Channel playback 4-Channel playback 8-Channel playback
General Options
Option 260 Option 261 Digital downconversion & upconversion GPS time & position stamping
Contact Pentek for compatible Option combinations
Specifications are subject to change without notice
Pentek, Inc.
www.pentek.com
! ew N
Model RTS 2707
Four-Channel RF/IF, 500 MS/sec Rackmount Recorder

General Information
The Talon RTS 2707 is a turnkey, multiband recording and playback system for recording and reproducing high-bandwidth signals. The RTS 2707 uses 12-bit, 500 MHz A/D converters and provides sustained recording rates up to 1.6 GB/sec in twochannel configuration. The RTS 2707 uses Penteks high-powered Virtex-6-based Cobalt modules, that provide flexibility in channel count, with optional digital downconversion capabilities. Optional 16-bit, 800 MHz D/A converters with digital upconversion allow real-time reproduction of recorded signals. A/D sampling rates, DDC decimations and bandwidths, D/A sampling rates and DUC interpolations are among the GUIselectable system parameters, providing a fully-programmable system capable of recording and reproducing a wide range of signals. Optional GPS time and position stamping allows the user to record this critical signal information. SystemFlow also includes signal viewing and analysis tools, that allow the user to monitor the signal prior to, during, and after a recording session. These tools include a virtual oscilloscope and a virtual spectrum analyzer. Built on a Windows 7 Professional workstation, the RTS 2706 allows the user to install post processing and analysis tools to operate on the recorded data. The RTS 2706 records data to the native NTFS file system, providing immediate access to the recorded data. Data can be off-loaded via gigabit Ethernet ports or USB 2.0 ports. Additionally, data can be copied to optical disk, using the 8X double layer DVDR/RW drive.
The RTS 2707 is configured in a 4U 19" rack-mountable chassis, with hot-swappable data drives, front panel USB ports and I/O connectors on the rear panel. Systems are scalable to accommodate multiple chassis to increase channel counts and aggregate data rates. All recorder chassis are connected via Ethernet and can be controlled from a single GUI either locally or from a remote PC. Multiple RAID levels, including 0, 1, 5, 6, 10 and 50, provide a choice for the required level of redundancy. Up to 20 hot-swappable SATA drives are optionally available, allowing up to 20 terabytes of real-time data storage space in a single 4U chassis.
Features
Complete multiband recording and playback system 4U 19-inch industrial rackmount PC server chassis Windows 7 Professional workstation with high-performance Intel CoreTM i7 processor 500 MHz 12-bit A/Ds or 400 MHz 14-bit A/Ds 800 MHz 16-bit D/As Real-time aggregate recording rates of up to 1.6 GB/sec Capable of record/playback of IF frequencies to 700 MHz Up to 20 terabytes of storage to NTFS RAID disk array RAID levels of 0 ,1, 5 , 6, 10 and 50 SystemFlow GUI with signal viewer analysis tool C-callable API for integration of recorder into application File headers include time stamping and recording parameters DDC decimation and DUC interpolation range from 2 to 65,536 Optional GPS time and position stamping
SystemFlow Software
The RTS 2707 includes the SystemFlow Recording Software. SystemFlow features a Windows-based GUI (Graphical User Interface) that provides a simple means to configure and control the recorder. Custom configurations can be stored as profiles and later loaded when needed, allowing the user to select preconfigured settings with a single click.
Channels In
500 MHz 12-bit A/D or 400 MHz 14-bit A/D Up to 4 Channels
DIGITAL DOWNCONVERTER DEC: 2 to 64K
Gigabit Ethernet INTEL PROCESSOR USB 2.0 PS/2 Keyboard PS/2 Mouse Video Output GPS Antenna (Optional)
SYSTEM DRIVE
DDR SDRAM
Channels Out
800 MHz 16-bit D/A Up to 4 Channels
DIGITAL UPCONVERTER INT: 2 to 64K
DATA DRIVES
DATA DRIVES
DATA DRIVES
DATA DRIVES
MODEL RTS 2707
RAID DATA STORE
Pentek, Inc.
www.pentek.com
Model RTS 2707



Pentek, Inc.
www.pentek.com
Model RTS 2707

Specifications

Analog Playback Outputs Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Digital Upconverter and D/A Type: TI DAC5688 and Pentek-installed interpolation IP core Interpolation: 2 to 65,536 Input Data Rate to DAC5688: 250 MS/sec max. Output IF: 250 MHz max. Output Signal: Analog, real or quadrature Output Sampling Rate: 800 MHz max. Resolution: 16 bits Bandwidth Range: Matches recording bandwidths Clock Sources: Selectable from onboard programmable VCXO, external or LVDS clocks External Clock Type: Female SSMC connector, sine wave, 0 to +12 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz divider input clock or PLL system reference Internal Clock Type: Progammable VCXO from 10 to 810 MHz Physical and Environmental Size: 19" W x 26" D x 7" H Weight: 60-85 lb Operating Temp: +5 to +45 C Storage Temp: 40 to +85 C Relative Humidity: 5 to 95%, non-condensing Power Requirements: 100 to 240 VAC, 50 to 60 Hz, 500 W max.
PC Workstation (standard configuration) Operating System: Windows 7 Professional Processor: Intel Core i7 processor Clock Speed: 2.0 GHz or higher SDRAM: 8 GB RAID Storage: 220 TB Number of Drives: 120 Supported RAID Levels: 0, 1, 5, 6, 10 and 50 Analog Recording Inputs Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 or ADS5474 (Option -014) Sampling Rate (s): 20 MHz to 500 MHz or 20 MHz to 400 MHz (Option -014) Resolution: 12 bits or 14 bits (Option -014) A/D Recording Rate/Channel: 2s bytes/sec, (e.g., 800 MB/sec per channel at s = 400 MHz) Digital Downconverter Type: Virtex-6 installed DDC IP Core Decimation (D): 2 to 65,536 DDC Bandwidth: 0.8 s/D Bandwidth Range: 5 kHz to 160 MHz at s = 400 MHz DDC Recording Rate/Channel: 2s/D bytes/sec

Recording Options
Option -201 Option -202 Option -204 1-Channel recording 2-Channel recording 4-Channel recording
Storage Options
Option -240 Option -241 Option -242 Option -243 Option -244 Option -245 Option -246 2 TB Storage capacity 4 TB Storage capacity 6 TB Storage capacity 8 TB Storage capacity 12 TB Storage capacity 16 TB Storage capacity 20 TB Storage capacity
Playback Options
Option -221 Option -222 Option -224 1-Channel playback 2-Channel playback 4-Channel playback
General Options
Option -014 Option -261 400 MHz, 14-bit A/Ds GPS time & position stamping
Pentek, Inc.
www.pentek.com
! ew N
Model RTS 2709
Ultra Wideband One- or Two-Channel RF/IF, 3.2 GS/sec Rackmount Recorder

General Information
The Talon RTS 2709 is a turnkey system, used for recording high-bandwidth signals. The RTS 2709 uses 12-bit, 3.6 GHz A/D converters and can provide sustained recording rates up to 3.2 GB/sec. It can be configured as a one- or two-channel system and can record sampled data, packed as 8-bit-wide consecutive samples, or as 16-bit-wide consecutive samples (12-bit digitized samples residing in the 12 MSBs of the 16-bit word.) The RTS 2709 uses Penteks highpowered Virtex-6-based Cobalt boards that provide the data streaming engine for the high-speed A/D converters. Channel and packing modes as well as gate and trigger settings are among the GUI-selectable system parameters, providing complete control over this ultra wideband recording system. Optional GPS time and position stamping allows the user to capture this critical information in the header of each data file. SystemFlow also includes signal viewing and analysis tools that allow the user to monitor the signal prior to, during, and after a recording session. These tools include a virtual oscilloscope and a virtual spectrum analyzer. Built on a Windows 7 Professional workstation, the RTS 2709 allows the user to install post-processing and analysis tools to operate on the recorded data. The RTS 2709 records data to the native NTFS file system that provides immediate access to the recorded data. Data can be off-loaded via two gigabit Ethernet ports, six USB 2.0 ports or two eSATA ports. Additionally, data can be copied to optical disk, using the 8X double layer DVDR/RW drive.
Features
High-speed RF/IF recording system Sample rates up to 3.2 GHz in single-channel mode Sample rates up to 1.6 GHz in dual-channel mode Capable of recording RF/IF frequencies to 1.75 GHz in single-channel mode Capable of recording RF/IF frequencies to 2.8 GHz in dual-channel mode 12-bit A/D, with 12- and 8 bit packing modes Real-time sustained recording rates of up to 3.2 GB/sec 4U 19 inch industrial rackmount PC server chassis Windows 7 Professional workstation with high performance Intel CoreTM i7 processor Up to 20 terabytes of SSD storage to NTFS RAID disk array RAID levels of 0 ,1, 5 , 6, 10 and 50 N+1 redundant power supply SystemFlow GUI with signal viewer analysis tool C-callable API for integration of recorder into application File headers include time stamping and recording parameters Optional GPS time and position stamping
The RTS 2709 is configured in a 4U 19" rack-mountable chassis, with hot-swappable data drives, front panel USB ports and I/O connectors on the rear panel. Systems are scalable to accommodate multiple chassis to increase channel counts and aggregate data rates. All recorder chassis are connected via Ethernet and can be controlled from a single GUI either locally or from a remote PC. Multiple RAID levels, including 0, 1, 5, 6, 10 and 50 provide a choice for the required level of redundancy. Up to 40 hot-swappable SATA SSDs are optionally available, allowing up to 20 terabytes of real-time data storage space in a single 4U chassis.
SystemFlow Software
The RTS 2709 includes the SystemFlow Recording Software. SystemFlow features a Windows-based GUI (Graphical User Interface) that provides a simple means to configure and control the system. Custom configurations can be stored as profiles and later loaded when needed, allowing the user to select preconfigured settings with a single click.
Gigabit Ethernet Channel 1 In 3.6 GHz (1 Channel) or 1.8 GHz (2 Channel) 12-Bit A/D USB INTEL PROCESSOR eSATA
Channel 2 In
Keyboard SYSTEM DRIVE DDR SDRAM Mouse Video Output GPS Antenna (Optional)
DATA DRIVES
DATA DRIVES
DATA DRIVES
DATA DRIVES
Contact factory for options, for number and type of analog channels, recording rates, and disk capacity.
UP TO 20 TB RAID
MODEL RTS 2709
Pentek, Inc.
www.pentek.com
Model RTS 2709



Pentek, Inc.
www.pentek.com
Model RTS 2709

Specifications

A/D Converters Type: Texas Instruments ADC12D1800 Sampling Rate Single-channel mode: 500 MHz to 3.6 GHz Dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Maximum Usable Input Frequency Single-channel mode: 1.75 GHz Dual-channel mode: 2.8 GHz Sampling Clock Source: Internal fixed-frequency or programmable oscillator (selectable by option); in single-channel mode, the sample rate is 2x the clock frequency; in dual-channel mode, the sample rate equals the clock frequency Frequency Reference: Accepts external 10 MHz reference at 0 to +4 dBm to phase-lock the clock oscillator Physical and Environmental Size: 19" W x 26" D x 7" H Weight: 60 85 lb Operating Temp: +5 to +45 C Storage Temp: 40 to +85 C Relative Humidity: 5 to 95%, non-condensing Power Requirements: 100 to 240 VAC, 50 to 60 Hz, 500 W max.
PC Workstation (standard configuration) Operating System: Windows 7 Professional Processor: Intel Core i7 processor Clock Speed: 2.0 GHz or higher SDRAM: 8 GB RAID Storage: 220 TB Number of Drives: Up to 40 Drive Type: SATA III SSDs Supported RAID Levels: 0, 1, 5, 6, 10 and 50 Analog Signal Inputs Connectors: Two rear panel SSMC connectors, In 1 & In 2 Input Type: Single-ended, non-inverting Full Scale Input: +4 dBm into 50 ohms Coupling: Transformer coupled Analog Input Transformers Bandwidth: 4.5 kHz to 3.0 GHz Insertion Loss: 3.5 dB maximum
Specifications are subject to change without notice.
Model RTS 2709 Options

Sample Rate Options
Option 910 User-Programmable Sample Clock Dual-channel mode sample clock range 150 MHz 945 MHz 970 MHz 1134 MHz 1213 MHz 1417.5 MHz Single-channel mode sample clock range 500 MHz 1890 MHz 1940 MHz 2268 MHz 2426 MHz 2835 MHz Option 911 Fixed-frequency clock 1.5 / 3.0 GHz sample clock Fixed-frequency clock 1.6 / 3.2 GHz sample clock
Storage Options
Option 241 Option 242 Option 243 4.8 TB SSD Storage 9.6 TB SSD Storage 19.2 TB SSD Storage
General Options
Option 261 GPS Time & Position Stamping
Option 912
Sample rates are set up for dual-channel mode first and single-channel mode second: e.g. 1.5 / 3.0 is 1.5 in dualchannel mode and 3.0 in single-channel mode. Custom fixed-frequency sample clocks available upon request.
Pentek, Inc.
www.pentek.com
! ew N
Model RTS 2715
Two-Channel Ten-Gigabit Ethernet Rackmount Recorder

General Information
The Talon RTS 2715 is a complete turnkey recording system for storing one or two ten-gigabit Ethernet (10 GbE) streams. It is ideal for capturing any type of streaming sources including live transfers from sensors or data from other computers and supports both TCP and UDP protocols. Using highly-optimized disk storage technology, the system achieves aggregate recording rates up to 2 GB/sec. Two rear panel SFP+ LC connectors for 850 nm multi-mode or single-mode fibre cables, or CX4 connectors for copper twinax cables accommodate all popular 10 GbE interfaces. Optional GPS time and position stamping accurately identifies each record in the file header. Built on a server-class Windows 7 Professional workstation, the RTS 2715 allows the user to install post-processing and analysis tools to operate on the recorded data. The RTS 2715 records data to the native NTFS file system, providing immediate access to the recorded data. Data can be off-loaded via two gigabit Ethernet ports or six USB 2.0 ports. Additionally, data can be copied to optical disk, using the 8X double layer DVDR/RW drive.
The RTS 2715 is configured in a 4U or 5U 19" rack-mountable chassis, with hot-swap data drives, front panel USB ports and I/O connectors on the rear panel. Systems are scalable to accommodate multiple chassis to increase channel counts and aggregate data rates. All recorder chassis are connected via Ethernet and can be controlled from a single GUI either locally or from a remote PC. Multiple RAID levels, including 0, 1, 5, 6, 10 and 50, provide a choice for the required level of redundancy. Up to 24 hot-swappable SATA drives are optionally available, allowing up to 20 terabytes of real-time data storage space in a single chassis.
SystemFlow Software
The RTS 2715 includes the SystemFlow Recording Software. SystemFlow features a Windows-based GUI (Graphical User Interface) that provides a simple and intuitive means to configure and control the system. Custom configurations can be stored as profiles and later loaded as needed, allowing the user to select preconfigured settings with a single click.
Features
Records ten-gigabit Ethernet streams One or two channels TCP and UDP protocols Copper or optical 10 GbE interfaces Aggregate recording rates to 2 GB/sec 4U or 5U 19-inch industrial rackmount PC server chassis Windows 7 Professional workstation with a high performance Intel CoreTM i7 processor Up to 20 terabytes of storage to NTFS RAID disk array RAID levels of 0 ,1, 5 , 6, 10 and 50 SystemFlow GUI virtual instrumentation panel for fast, intuitive operation C-callable API for integration of recorder into applications File headers include time stamping and recording parameters Optional GPS time and position stamping
2 Ch 1 In / Out 6 10G Ethernet INTEL PROCESSOR 2
SYSTEM DRIVE Ch 2 In / Out
DDR SDRAM
10G Ethernet
DATA DRIVES
DATA DRIVES
DATA DRIVES
DATA DRIVES
UP TO 20 TB RAID
Contact factory for options, number of channels, recording rates, and disk capacity.
MODEL RTS 2715
Pentek, Inc.
www.pentek.com
Model RTS 2715

SystemFlow Graphical User
Interface
The RTS 2715 GUI provides the user with a control interface for the recording system. It includes Configuration, Record, Playback, and Status screens, each with intuitive controls and indicators. The user can easily move between screens to set configuration parameters, control and monitor a recording, and play back a recorded stream. All parameters contain limit-checking and integrated help to provide an easier-to-use out-of-the-box experience. The Configure Screen shows a block diagram of the system, and presents operational system parameters including temperature and voltages. Parameters are entered for each input or output channel specifying UDP or TCP protocol, client or server connection, the IP address and port number. The Record Screen allows you to browse a folder and enter a file name for the recording. The length of the recording for each channel can be specified in megabytes or in seconds. Intuitive buttons for Record, Pause and Stop simplify operation. Status indicators for each channel display the mode, the number of recorded bytes, and the average data rate. A Data Loss indicator alerts the user to any problem, such as a disk full condition. By checking the Master Record boxes, any combination of channels in the lower screen can be grouped for synchronous recording via the upper Master Record screen. The recording time can be specified, and monitoring functions inform the operator of recording progress.
Pentek, Inc.
www.pentek.com
Model RTS 2715

SystemFlow API

Ten-Gigabit Ethernet Interface Copper - Option 280 Quantity: 2 ports Cable: Twinax copper Connector Type: CX4 Max. Cable Length: 15 m Multi-mode Fibre Optical - Option 281 Quantity: 2 ports Cable: Multi-mode fibre, 850 nm Connector Type: LC Max. Cable Length: Up to 300 m Single-mode Fibre Optical - Option 282 Quantity: 2 ports Cable: Single-mode fibre Connector Type: LC Max. Cable Length: Up to 10 km Physical and Environmental Dimensions 4U Long Chassis: 19" W x 26" D x 7" H 5U Long Chassis: 19" W x 26" D x 8.75" H Weight: 5080 lb Operating Temp: +5 to +45 C Storage Temp: 40 to +85 C Relative Humidity: 5 to 95%, non-condensing Power Requirements: 100 to 240 VAC, 50 to 60 Hz, 500 W max.
SystemFlow includes a complete API (Application Programming Interface) supporting control and status queries of all operations of the RTS 2715 from a custom application. High-level C-language function calls and the supporting device drivers allow users to incorporate the RTS 2715 as a high-performance server front end to a larger system. This is supported using a socket interface through the Ethernet port, either to a local host or through an internet link for remote, stand-alone acquisition. Recorded NTFS files can be easily retrieved through the same connection.
Specifications
PC Workstation Operating System: Windows 7 Professional Processor: Intel Core i7 processor Clock Speed: 2.0 GHz or higher SDRAM: 6 GB RAID Storage: 520 TB Drive Type: Hard disk drives Number of Drives: 1224 Supported Levels: 0, 1, 5, 6, 10 and 50
Model RTS2715 Ordering Information and Options

Option 201 - Single Channel 10 GbE Recorders
Option 201-242 Storage capacity: 5 TB 12 ea. 1 TB, 3.5 hard disk drives 4U long chassis
Option 202 - Dual Channel 10 GbE Recorders

Option 202-244 Storage capacity: 10 TB 24 ea. 1 TB, 3.5 hard disk drives 5U long chassis Storage capacity: 20 TB 24 ea. 2 TB, 3.5 hard disk drives 5U long chassis
Option 202-246 Option 201-244 Storage capacity: 10 TB 12 ea. 2 TB, 3.5 hard disk drives 4U long chassis Storage capacity: 20 TB 24 ea. 2 TB, 3.5 hard disk drives 5U long chassis
10 GbE Interface (append to all options)s above)

Option 280 Copper , CX4 connectors Multi-mode optical, LC connectors Single-mode optical, LC connectors Option 281 Option 282
Option 201-246
General Options (append to all options)s a

Option 261 Contact Pentek for other configurations GPS time & position stamping
Pentek, Inc.
www.pentek.com
! w e N
Model RTS 2716
Eight-Channel Serial FPDP Rackmount Recorder

General Information
The Talon RTS 2716 is a complete turnkey recording system capable of recording and playing multiple serial FPDP data streams. It is ideal for capturing any type of streaming sources including live transfers from sensors or data from other computers and is fully compatible with the VITA 17.1 specification. Using highly-optimized disk storage technology, the system achieves aggregate recording rates up to 3.4 GB/sec. The RTS 2716 can be populated with up to eight SFP connectors supporting serial FPDP over copper, single-mode, or multimode fiber, to accommodate all popular serial FPDP interfaces. It is capable of both receiving and transmitting data over these links and supports real-time data storage to disk. Programmable modes include flow control in both receive and transmit directions, CRC support, and copy/loop modes. The system is capable of handling 1.0625, 2.125, 2.5, 3.125 and 4.25 GBaud link rates supporting data transfer rates of up to 425 MB/sec per serial FPDP link. Optional GPS time and position stamping allows the user to mark the beginning of a recording in the recording files header. Custom configurations can be stored as profiles and later loaded as needed, allowing the user to select preconfigured settings with a single click. Built on a server-class Windows 7 Professional workstation, the RTS 2716 allows the user to install post-processing and analysis tools to operate on the recorded data. The RTS 2716 records data to the native NTFS file system, providing immediate access to the recorded data. Data can be off-loaded via two gigabit Ethernet ports or six USB 2.0 ports. Additionally, data can be copied to optical disk, using the 8X double layer DVDR/RW drive.
The RTS 2716 is configured in a 4U or 5U 19" rack-mountable chassis, with hot-swap data drives, front panel USB ports and I/O connectors on the rear panel. Systems are scalable to accommodate multiple chassis to increase channel counts and aggregate data rates. All recorder chassis are connected via Ethernet and can be controlled from a single GUI either locally or from a remote PC. Multiple RAID levels, including 0, 1, 5, 6, 10 and 50, provide a choice for the required level of redundancy. Up to 24 hot-swappable SATA drives are optionally available, allowing up to 20 terabytes of real-time data storage space in a single chassis.
Features
Complete serial FPDP record and playback system Up to eight I/O channels in a single 4U or 5U 19 inch industrial rackmount PC server chassis Supports Flow Control, CRC, and Copy/Loop Mode as a receiver and transmitter Supports 1.0625, 2.125, 2.5, 3.125 and 4.25 GBaud link rates Copper, single-mode and multi-mode fiber interfaces available Real-time aggregate recording rates of up to 3.4 GB/sec in eight-channel configuration Up to 20 terabytes of storage to NTFS RAID disk array RAID levels of 0 ,1, 5 , 6, 10 and 50 SystemFlow GUI virtual instrumentation panel for fast, intuitive operation C-callable API for integration of recorder into application File headers include time stamping and recording parameters Optional GPS time and position stamping Windows 7 Professional workstation with high performance Intel CoreTM i7 processor
SystemFlow Software
The RTS 2716 includes the SystemFlow Recording Software. SystemFlow features a Windows-based GUI (Graphical User Interface) that provides a simple and intuitive means to configure and control the system.
2 Ch 1 In / Out Ch 2 In / Out Ch 3 In / Out Ch 4 In / Out Ch 5 In / Out Ch 6 In / Out Ch 7 In / Out Ch 8 In / Out Serial FPDP Serial FPDP Serial FPDP Serial FPDP Serial FPDP Serial FPDP Serial FPDP Serial FPDP DATA DRIVES DATA DRIVES HOST PROCESSOR RUNNING SYSTEMFLOW INTEL PROCESSOR 6 2
SYSTEM DRIVE
DDR SDRAM
DATA DRIVES
DATA DRIVES
UP TO 20 TB RAID
MODEL RTS 2716
Pentek, Inc.
www.pentek.com
Model RTS 2716

Interface
The RTS 2716 GUI provides the user with a control interface for the recording system. It includes Configuration, Record, Playback, and Status screens, each with intuitive controls and indicators. The user can easily move between screens to set configuration parameters, control and monitor a recording, and play back a recorded stream. All parameters contain limit-checking and integrated help to provide an easier-to-use out-of-the-box experience. The Configure Screen shows a block diagram of the system, and provides control for operational system parameters. These parameters are entered for each input or output channel, specifying the flow control settings and the recognition of a CRC in the data stream. Each channel can also be setup to utilize SFPDPs copy/loop mode. The Record Screen allows you to browse a folder and enter a file name for the recording. The length of the recording for each channel can be specified in megabytes or in seconds. Intuitive buttons for Record, Pause and Stop simplify operation. Status indicators for each channel display the mode, the number of recorded bytes, and the average data rate. A Data Loss indicator alerts the user to any problem, such as a disk full condition. By checking the Master Record boxes, any combination of channels in the lower screen can be grouped for synchronous recording via the upper Master Record screen. The recording time can be specified, and monitoring functions inform the operator of recording progress.
Pentek, Inc.
www.pentek.com
Model RTS 2716

SystemFlow API

Serial FPDP Interface Copper - Option 280 Cable: 100-ohm shielded twin-ax Connector Type: SFP+ Max. Cable Length: 20 m Multi-mode Fiber Optical - Option 281 Cable: Multi-mode fiber, 850 nm Connector Type: LC Max. Cable Length: Up to 300 m Single-mode Fiber Optical - Option 282 Cable: Single-mode fiber Connector Type: LC Max. Cable Length: Up to 10 km Physical and Environmental Dimensions Full 4U Chassis: 19" W x 26" D x 7" H Weight: 30 80 lb Operating Temp: +5 to +45 C Storage Temp: 40 to +85 C Relative Humidity: 5 to 95%, non-condensing Power Requirements: 100 to 240 VAC, 50 to 60 Hz, 500 W max.
SystemFlow includes a complete API (Application Programming Interface) that supports control and status queries of all operations of the RTS 2716 from a custom application. High-level C-language function calls and the supporting device drivers allow users to incorporate the RTS 2716 as a high-performance server front end to a larger system. This is supported using a socket interface through the Ethernet port, either to a local host or through an internet link for remote, stand-alone acquisition. Recorded NTFS files can be easily retrieved through the same connection.
Specifications
PC Workstation Operating System: Windows 7 Professional Processor: Intel Core i7 processor Clock Speed: 1.8 GHz or greater SDRAM: 6 GB RAID Storage: 520 TB Drive Type: 3.5 HDD Number of Drives: Options 041, 042 up to 16 removable drives; options 043, 082, 083 up to 20 removable drives Supported Levels: 0, 1, 5, 6, 10 and 50
Model RTS 2716 Ordering Information and Options

4-Channel Serial FPDP Recorders
Option 041 Option 042 Option 043 Storage capacity: 5 TB Maximum disk data rate: 988 MB/sec Storage capacity: 10 TB Maximum disk data rate: 988 MB/sec Storage capacity: 20 TB Maximum disk data rate: 988 MB/sec

Option 082 Option 083 Storage capacity: 10 TB Maximum disk data rate: 1976 MB/ssec Storage capacity: 20 TB Maximum disk data rate: 1976 MB/sec
Serial FPDP Interface (append to options above)s above)

Option 280 Option 281 Option 282 Copper, SFP+ connectors Multi-mode optical, LC connectors Single-mode optical, LC connectors

Option 261 GPS time & position stamping
Contact Pentek for other configurations
Pentek, Inc.
www.pentek.com
! w e N
Model RTS 2718
LVDS Digital I/O Rackmount Recorder

General Information
The Talon RTS 2718 is a complete turnkey system for recording and playing back digital data using the Pentek Model 78610 LVDS digital I/O board. Using highly optimized disk storage technology, the system achieves sustained recording rates of up to 1 GB/sec. The RTS 2718 utilizes a 32-bit LVDS interface that can be clocked at speeds up to 250 MHz. It includes Data Valid and Suspend signals and provides the ability to turn these signals on and off as well as control their polarity. Optional GPS time and position stamping accurately identifies each record in the file header. using the 8X double layer DVDR/RW drive.
The RTS 2718 is configured in a 4U 19" rack-mountable chassis, with hot-swap data drives, front panel USB ports and I/O connectors on the rear panel. Systems are scalable to accommodate multiple chassis to increase channel counts and aggregate data rates. All recorder chassis are connected via Ethernet and can be controlled from a single GUI either locally or from a remote PC. Multiple RAID levels, including 0, 1, 5, 6, 10 and 50, provide a choice for the required level of redundancy. Up to 16 hot-swappable SATA drives are optionally available, allowing up to 20 terabytes of real-time data storage space in a single 4U chassis.
SystemFlow Software
The RTS 2718 includes the SystemFlow Recording Software. SystemFlow features a Windows-based GUI (Graphical User Interface) that provides a simple means to configure and control the system. Custom configurations can be stored as profiles and later loaded when needed, allowing the user to select preconfigured settings with a single click. Built on a Windows 7 Professional workstation, the RTS 2718 allows the user to install post-processing and analysis tools to operate on the recorded data. The RTS 2718 records data to the native NTFS file system, providing immediate access to the recorded data. Data can be off-loaded via two gigabit Ethernet ports or eight USB ports. Additionally, data can be copied to optical disk
SystemFlow API
SystemFlow includes a complete API (Application Programming Interface) that supports control and status queries of all operations of the RTS 2718 from a custom application. High-level C-language function calls and the supporting device drivers allow users to incorporate the RTS 2718 as a highperformance server front end to a larger system. This is supported using a socket interface through the Ethernet port, either to a local host or through an internet link for remote, stand-alone acquisition. Recorded NTFS files can be easily retrieved through the same connection.
Features

32 bits of LVDS digital I/O LVDS clock, Data Valid and Data Suspend signals Supports clock rates up to 250 MHz Real-time aggregate recording rates up to 1 GB/s Up to 20 terabytes of storage to NTFS RAID disk array RAID levels of 0 ,1, 5 , 6, 10 and 50 SystemFlow GUI virtual instrumentation panel for fast, intuitive operation C-callable API for integration of recorder into application File headers include time stamping and recording parameters Optional GPS time and position stamping Windows 7 Professional workstation with high-performance Intel CoreTM i7 processor
2 32-bit Data In Clock Data Valid Data Suspend 8 INTEL PROCESSOR
Gigabit Ethernet USB
32-bit LVDS I/O Record Interface
32-bit Data Out Clock Data Valid Data Suspend
Optiional 32-bit LVDS I/O Playback Interface
DATA DRIVES
DATA DRIVES
DATA DRIVES
DATA DRIVES
Contact factory for options, recording rates, and disk capacity.
UP TO 20 TB RAID
MODEL RTS 2718
Pentek, Inc.
www.pentek.com
Model RTS 2718
SystemFlow Main Interface

The RTS 2718 GUI provides the user with a control interface for the recording system. It includes Configuration, Record, Playback, and Status screens, each with intuitive controls and indicators. The user can easily move between screens to set configuration parameters, control and monitor a recording, and play back a recorded stream. All parameters contain limit-checking and integrated help to provide an easier-to-use out-of-the-box experience.

The RTS 2718 configuration screen shows a block diagram of the system, and provides control for operational system parameters. These parameters include data valid and suspend enables, as well as polarity control for both signals.
SystemFlow Record Interface

The SystemFlow Record Screen allows you to browse a folder and enter a file name for the recording. The length of the recording for each channel can be specified in megabytes or in seconds. Intuitive buttons for Record, Pause and Stop simplify operation. Status indicators for each channel display the mode, the number of recorded bytes, and the average data rate. A Data Loss indicator alerts the user to any problem, such as a disk full condition. By checking the Master Record boxes, any combination of channels in the lower screen can be grouped for synchronous recording via the upper Master Record screen. The recording time can be specified, and monitoring functions inform the operator of recording progress.
Pentek, Inc.
www.pentek.com
Model RTS 2718

Specifications
PC Workstation Operating System: Windows 7 Professional Processor: Intel Core i7 processor Clock Speed: 3.0 GHz or higher SDRAM: 8 GB RAID Storage: 520 TB Drive Type: 3.5 HDD Supported RAID Levels: 0, 1, 5, 6, 10 and 50 LVDS Interface Cable: 80-pin ribbon cable Connector Type: 2x40 pin IDC Data Lines: 32 LVDS pairs, 2.5 V compliant Clock: One LVDS pair, 2.5 V compliant Data Valid: One LVDS pair, 2.5 V compliant Data Suspend: One LVDS pair, 2.5 V compliant
Physical and Environmental Dimensions 4U Long Chassis: 19" W x 26" D x 7" H Size: 19" W x 26" D x 7" H Weight: 50-80 lb Operating Temp: +5 to +45 C Storage Temp: 40 to +85 C Relative Humidity: 5 to 95%, non-condensing Power Requirements: 100 to 240 VAC, 50 to 60 Hz, 500 W max.

Storage Options
Option 242 Option 244 Option 246 5 TB Storage capacity 10 TB Storage capacity 20 TB Storage capacity
General Options
Interface Options
Option 221 Playback Interface
Pentek, Inc.
www.pentek.com
! ew N
Model RTR 2726
Four-Channel RF/IF, 200 MS/sec Rugged Portable Recorder

General Information
The Talon RTR 2726 is a turnkey, multiband recording and playback system that allows the user to record and reproduce high-bandwidth signals with a lightweight, portable and rugged package. The RTR 2726 provides sustained recording rates of up to 1.6 GB/sec in a four-channel system and is ideal for the user who requires both portability and solid performance in a compact recording system. The RTR 2726 is supplied in a small footprint portable package measuring only 16.9" W x 9.5" D x 13.4" H and weighing just 30 pounds. With measurements similar to a small briefcase, this portable workstation includes an Intel CoreTM i7 processor a high-resolution 17" LCD monitor, and a high-performance SATA RAID controller. At the heart of the RTR 2726 are Pentek Cobalt Series Virtex-6 software radio boards featuring A/D and D/A converters, DDCs (Digital Downconverters), DUCs (Digital Upconverters), and complementary FPGA IP cores. This architecture allows the system engineer to take full advantage of the latest technology in a turnkey system. Optional GPS time and position stamping allows the user to record this critical signal information. allowing the user to select preconfigured settings with a single click. SystemFlow also includes signal viewing and analysis tools, that allow the user to monitor the signal prior to, during, and after a recording session. These tools include a virtual oscilloscope and a virtual spectrum analyzer. Built on a Windows 7 Professional workstation, the RTR 2726 allows the user to install post-processing and analysis tools to operate on the recorded data. The RTR 2726 records data to the native NTFS file system, providing immediate access to the recorded data. Data can be off-loaded through two 1 Gb Ethernet ports, eight USB 2.0 ports or two eSATA ports. Additionally, data can be copied to optical disk, using the 8X double layer DVDR/RW drive.
Features
Designed to operate under conditions of shock and vibration Portable system measuring 16.9" W x 9.5" D x 13.4" H Lightweight: approximately 30 pounds Rugged aluminum alloy chassis Shock- and vibration-resistant SSDs perform well in vehicles, ships and aircraft Recording & playback of IF signals up to 700 MHz Signal bandwidths to 80 MHz 200 MHz 16-bit A/Ds 800 MHz 16-bit D/As SFDR > 80 dBFS Real-time sustained recording rates up to 1.6 GB/sec Up to of 3.8 TB storage with hot-swappable SSD drives NTFS file format SystemFlow GUI with Signal Viewer analysis tool File headers include time stamping and recording parameters Ideal for communications, radar, wireless, SIGINT, telecom and satcom Optional GPS time and position stamping Complete high-performance Windows workstation
Rugged & Flexible Architecture

The RTR 2726 is configured in a portable, lightweight chassis with eight hot-swap SSDs, front panel USB ports and I/O connections on the side panel. It is built on an extremely rugged, 100% aluminum alloy unit, reinforced with shock absorbing rubber corners and an impact-resistant protective glass. Using shock- and vibration-resistant SSDs, the RTR 2726 is designed to reliably operate as a portable field instrument. The eight hot-swappable SSDs provide storage capacities of up to 3.8 TB. Drives can be easily removed or exchanged during or after a mission to retrieve recorded data. Multiple RAID levels, including 0,1,5 and 6, provide a choice for the required level of redundancy.
SystemFlow Software
Included in this system is the Pentek SystemFlow recording software. SystemFlow features a Windows-based GUI (Graphical User Interface) that provides a simple means to configure and control the system. Custom configurations can be stored as profiles and later loaded when needed,
Channels In
200 MHz 16-bit A/D Up to 4 Channels
DIGITAL DOWN CONVERTER DEC: 2 to 64K
HIGH RESOLUTION VIDEO DISPLAY
Aux Video VGA Output 1x Gigabit Ethernet 8x USB 2.0 2x USB 3.0 2x eSATA 3
INTEL CORE i7 PROCESSOR DIGITAL UP CONVERTER INT: 2 to 512K
Channels Out
SSD SYSTEM DRIVE
DDR SDRAM
WINDOWS HOST PROCESSOR
SSD DRIVES
SSD DRIVES
Contact the factory for options, for number and type of analog channels, recording rates, and disk capacity.
MODEL RTR 2726
SSD DRIVES
SSD DRIVES
RAID DATA STORE
Pentek, Inc.
www.pentek.com
Model RTR 2726
SystemView Graphical User Interface

The RTR 2726 GUI provides the user with a control interface for the recording system. It includes Configuration, Record, Playback and Status screens, each with intuitive controls and indicators. The user can easily move between screens to set configuration parameters, control and monitor a recording, play back a recorded signal and monitor board temperature and voltage levels. The signal viewer, integrated into the recording GUI, allows the user to monitor real-time signals or recorded signals on disk.

The RTR 2726s configuration screens provide a simple and intuitive means for setting up the system parameters. The DDC configuration screen shown here, provides entries for input source, center frequency, decimation, as well as gate and trigger information. All parameters contain limitchecking and integrated help to provide an easier-to-use out-of-the-box experience.

The SystemFlow Signal Viewer includes a virtual oscilloscope and spectrum analyzer for signal monitoring in both the time and frequency domains. It is extremely useful for previewing live inputs prior to recording, and for monitoring signals as they are being recorded to help ensure successful recording sessions. The viewer can also be used to inspect and analyze the recorded files after the recording is complete. Advanced signal analysis capabilities include automatic calculators for signal amplitude and frequency, second and third harmonic components, THD (total harmonic distortion) and SINAD (signal to noise and distortion). With time and frequency zoom, panning modes and dual annotated cursors to mark and measure points of interest, the SystemFlow Signal Viewer can often eliminate the need for a separate oscilloscope or spectrum analyzer in the field.
Pentek, Inc.
www.pentek.com
Model RTR 2726

A/D Performance
Spurious Pick-up
D/A Performance
Pentek, Inc.
www.pentek.com
Model RTR 2726

Specifications

Analog Playback Outputs Analog Signal Outputs Quantity: 1 or 2 Output Type: Transformer-coupled, female SSMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Digital Upconverter, Interpolator and D/As D/A Resolution: 16 bits Output Signal: Analog, real or quadrature Type: TI DAC5688 and Pentek-installed IP core interpolator IP Core Interpolation: 2 to 65,536 in two stages of 2 to 256 DAC5688 Interpolation: 2, 4 or 8 Overall Interpolation: 2 to 524,288 Input Data Rate to DAC5688: 250 MS/sec max. Output Sampling Rate: 800 MHz max Output IF: DC to 400 MHz Bandwidth Range: Matches recording bandwidths Clock Sources: Selectable from onboard programmable VCXO, external or LVDS clocks External Clocks Type: Female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, 10 to 200 MHz Physical and Environmental Dimensions: 16.9" W x 9.5" D x 13.4" H Weight: 30 lb, approximately Power: 90 to 265 VAC, 50 - 60 Hz Operating Temp: 0 to +50 C Storage Temp: 40 to +85 C Relative Humidity: 5 to 95%, non-condensing Operating Shock: 15 g max. (11 msec, half sine wave) Operating Vibration: 10 to 20 Hz: 0.02 inch peak, 20 to 500 Hz: 1.4 g peak acceleration Power Requirements: 100 to 240 VAC, 50 to 60 Hz, 500 W max.
PC Workstation (standard configuration) Operating System: Windows 7 Professional Processor: Intel Core i7 processor Clock Speed: 2.0 GHz or higher Operating System Drive: 128 GB SSD SDRAM: 6 GB Monitor: Built-in 17 high-resolution LCD 1440 x 900 pixels, 200 nits RAID Total Storage: 0.96, 1.9 or 3.8 TB Number of Drives: 8 Supported RAID Levels: 0, 1, 5 and 6 Drive Bays: 8, hot-swap, removable, rear panel USB 2.0 Ports: Eight (8) left side, two (2) front panel USB 3.0 Ports: Two (2) left side 1 Gb Ethernet Port: One (1) left side eSATA 3 Ports: Two (2) left side Aux Video Output: 15-pin VGA left side Analog Recording Inputs Analog Signal Inputs Quantity: 1, 2, 3, or 4 Input Type: Transformer-coupled, female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate (s): 10 MHz to 200 MHz Resolution: 16 bits A/D Recording Rate/Channel: 2s bytes/sec, (e.g., 400 MB/sec per channel at s = 200 MHz) Digital Downconverter Type: Virtex-6 installed DDC IP Core Decimation (D): 2 to 65,536 in two stages of 2 to 256 DDC Bandwidth: 0.8 s/D Bandwidth Range: 2.5 kHz to 80 MHz at s = 200 MHz DDC Recording Rate/Channel: 2s/D bytes/sec
Model RTR 2726 Ordering Information and Options

Channel Configurations
Option 201, 221 Option 202, 222 Option 203, 221 Option 204 1-Channel record 1-Channel playback 2-Channel record 2-Channel playback 3-Channel record 1-Channel playback 4-Channel record only
Storage Options
Option 241 Option 242 Option 244 960 GB SSD storage capacity; eight 120 GB hot-swappable SSDs 1.9 TB SSD storage capacity; eight 240 GB hot-swappable SSDs 3.8 TB SSD storage capacity; eight 480 GB hot-swappable SSDs
General Options (append to all options)

Specifications subject to change without notice
Pentek, Inc.
www.pentek.com
! ew N
Model RTR 2727
Two-Channel RF/IF, 500 MS/sec Rugged Portable Recorder

General Information
The Talon RTR 2727 is a turnkey, multiband recording and playback system that allows the user to record and reproduce high-bandwidth signals with a lightweight, portable and rugged package. The RTR 2727 provides aggregate recording rates of up to 2.0 GB/sec in a two-channel system and is ideal for the user who requires both portability and solid performance in a compact recording system. The RTR 2727 is supplied in a small footprint portable package measuring only 16.9" W x 9.5" D x 13.4" H and weighing just 30 pounds. With measurements similar to a small briefcase, this portable workstation includes an Intel CoreTM i7 processor a high-resolution 17" LCD monitor, and a high-performance SATA RAID controller. At the heart of the RTR 2727 are Pentek Cobalt Series Virtex-6 software radio boards featuring A/D and D/A converters, DDCs (Digital Downconverters), DUCs (Digital Upconverters), and complementary FPGA IP cores. This architecture allows the system engineer to take full advantage of the latest technology in a turnkey system. Optional GPS time and position stamping allows the user to record this critical signal information. allowing the user to select preconfigured settings with a single click. SystemFlow also includes signal viewing and analysis tools, that allow the user to monitor the signal prior to, during, and after a recording session. These tools include a virtual oscilloscope and a virtual spectrum analyzer. Built on a Windows 7 Professional workstation, the RTR 2727 allows the user to install post-processing and analysis tools to operate on the recorded data. The RTR 2727 records data to the native NTFS file system, providing immediate access to the recorded data. Data can be off-loaded through two 1 Gb Ethernet ports, eight USB 2.0 ports or two eSATA ports. Additionally, data can be copied to optical disk, using the 8X double layer DVDR/RW drive.
Features
Designed to operate under conditions of shock and vibration Portable system measuring 16.9" W x 9.5" D x 13.4" H Lightweight: approximately 30 pounds Rugged aluminum alloy chassis Shock- and vibration-resistant SSDs perform well in vehicles, ships and aircraft Recording and playback of IF signals up to 700 MHz Signal bandwidths to 200 MHz 500 MHz 12-bit A/Ds or 400 MHz 14-bit A/Ds 800 MHz 16-bit D/A SFDR > 70 dBFS Real-time aggregate recording rates up to 2.0 GB/sec Up to of 3.8 TB storage with hot-swappable SSD drives NTFS file format SystemFlow GUI with Signal Viewer analysis tool File headers include time stamping and recording parameters Ideal for communications, radar, wireless, SIGINT, telecom and satcom Optional GPS time and position stamping Complete high-performance Windows workstation

The RTR 2727 is configured in a portable, lightweight chassis with eight hot-swap SSDs, front panel USB ports and I/O connections on the side panel. It is built on an extremely rugged, 100% aluminum alloy unit, reinforced with shock absorbing rubber corners and an impact-resistant protective glass. Using shock- and vibration-resistant SSDs, the RTR 2727 is designed to operate reliably as a portable field instrument. The eight hot-swappable SSDs provide storage capacities of up to 3.8 TB. Drives can be easily removed or exchanged during or after a mission to retrieve recorded data. Multiple RAID levels, including 0,1,5, and 6 provide a choice for the required level of redundancy.
SystemFlow Software
Included in this system is the Pentek SystemFlow recording software. SystemFlow features a Windows-based GUI (Graphical User Interface) that provides a simple means to configure and control the system. Custom configurations can be stored as profiles and later loaded when needed,
Channels In
HIGH RESOLUTION VIDEO DISPLAY
Aux Video VGA Output 1x Gigabit Ethernet 8x USB 2.0 2x USB 3.0 2x eSATA 3
INTEL CORE i7 PROCESSOR
Channel Out
800 MHz 16-bit D/A Up to 1 Channel
SSD SYSTEM DRIVE
DDR SDRAM
WINDOWS HOST PROCESSOR
SSD DRIVES
SSD DRIVES
MODEL RTR 2727
SSD DRIVES
SSD DRIVES
RAID DATA STORE
Pentek, Inc.
www.pentek.com
Model RTR 2727


The RTR 2727s configuration screens provide a simple and intuitive means for setting up the system parameters. The DDC configuration screen shown here, provides entries for input source, center frequency, decimation, as well as gate and trigger information. All parameters contain limitchecking and integrated help to provide an easier-to-use out-of-the-box experience.

The SystemFlow Signal Viewer includes a virtual oscilloscope and spectrum analyzer for signal monitoring in both the time and frequency domains. It is extremely useful for previewing live inputs prior to recording, and for monitoring signals as they are being recorded to help ensure successful recording sessions. The viewer can also be used to inspect and analyze the recorded files after the recording is complete. Advanced signal analysis capabilities include automatic calculators for signal amplitude and frequency, second and third harmonic components, THD (total harmonic distortion) and SINAD (signal to noise and distortion). With time and frequency zoom, panning modes and dual annotated cursors to mark and measure points of interest, the SystemFlow Signal Viewer can often eliminate the need for a separate oscilloscope or spectrum analyzer in the field.
Pentek, Inc.
www.pentek.com
Model RTR 2727

Specifications

Bandwidth Range: 5 kHz to 160 MHz at s = 400 MHz DDC Recording Rate/Channel: 2s/D bytes/sec Analog Playback Output Analog Signal Outputs Quantity: 1 Output Type: Transformer-coupled, female SSMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Digital Upconverter and D/A Output Signal: Analog, real or qudrature Type: TI DAC5688 and Pentek-installed interpolation IP core Interpolation: 2 to 65,536 Input Data Rate to DAC5688: 250 MS/sec max. Output Sampling Rate: 800 MHz, max. Output IF: 250 MHz, max. D/A Resolution: 16 bits Bandwidth Range: Matches recording bandwidths Clock Sources: Selectable from onboard programmable VCXO, external or LVDS clocks External Clock Type: Female SSMC connector, sine wave, 0 to +12 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz divider input clock or PLL system reference Internal Clock Type: Progammable VCXO from 10 to 810 MHz Physical and Environmental Dimensions: 16.9" W x 9.5" D x 13.4" H Weight: 30 lb, approximately Power: 90 to 265 VAC, 50 - 60 Hz Operating Temp: 5 to +45 C Storage Temp: 40 to +85 C Relative Humidity: 5 to 95%, non-condensing Operating Shock: 15 g max. (11 msec, half sine wave) Operating Vibration: 10 to 20 Hz: 0.02 inch peak, 20 to 500 Hz: 1.4 g peak acceleration Power Requirements: 100 to 240 VAC, 50 to 60 Hz, 500 W max.
PC Workstation (standard configuration) Operating System: 64-bit Windows 7 Professional Processor: Intel Core i7 processor Clock Speed: 2.0 GHz or higher Operating System Drive: 128 GB SSD SDRAM: 8 GB Monitor: Built-in 17 high-resolution LCD 1440 x 900 pixels, 200 nits RAID Total Storage: 1.9 or 3.8 TB Number of Drives: Eight Supported RAID Levels: 0, 1, 5, and 6 Drive Bays: Eight, hot-swap, removable, rear panel USB 2.0 Ports: Eight on left side, two on front panel USB 3.0 Ports: Two on left side 1 Gb Ethernet Port: Two on left side eSATA 3 Ports: Two on left side Aux Video Output: 15-pin VGA on left side Analog Recording Inputs Analog Signal Inputs Quantity: 1 or 2 Input Type: Transformer-coupled, female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 or ADS5474 (Option -014) Sampling Rate (s): 20 MHz to 500 MHz or 20 MHz to 400 MHz (Option -014) Resolution: 12 bits or 14 bits (Option -014) A/D Recording Rate/Channel: 2s bytes/sec, (e.g., 800 MB/sec per channel at s = 400 MHz or 1000 MB/sec per channel at s = 500 MHz and with Option -244, 3.8 TB SSD storage capacity) Digital Downconverter Type: Virtex-6 installed DDC IP Core Decimation (D): 2 to 65,536 DDC Bandwidth: 0.8 s/D

Option -201 Option -202 Option -221 1-Channel recording 2-Channel recording 1-Channel playback Option -244
Storage Options
Option -242 1.9 TB SSD storage capacity; eight 240 GB hot-swappable SSDs Up to 1.6 GB/sec aggregate recording rate 3.8 TB SSD storage capacity; eight 480 GB hot-swappable SSDs Up to 2.0 GB/sec aggregate recording rate
General Options (append to all other options)s a

Option -014 Option -261 Contact Pentek for other configurations 400 MHz, 14-bit A/Ds GPS time & position stamping
Specifications subject to change without notice
Pentek, Inc.
www.pentek.com
! w e N
Model RTR 2728
One-Channel RF/IF, 1 GS/sec Rugged Portable Recorder

General Information
The Talon RTR 2728 is a turnkey, multiband recording and playback system that allows the user to record and reproduce high-bandwidth signals with a lightweight, portable and rugged package. The RTR 2728 provides recording rates of up to 2.0 GB/sec and is ideal for the user who requires portability and solid performance in a compact recording system. The RTR 2728 is supplied in a small footprint portable package measuring only 16.9" W x 9.5" D x 13.4" H and weighing just 30 pounds. With measurements similar to a small briefcase, this portable workstation includes an Intel Core i7 processor a high-resolution 17" LCD monitor, and a high-performance SATA RAID controller. At the heart of the RTR 2728 are Pentek Cobalt Series Virtex-6 software radio boards featuring A/D and D/A converters. This architecture allows the system engineer to take full advantage of the latest technology in a turnkey system. GPS time and position stamping is optionally available. SystemFlow also includes signal viewing and analysis tools, that allow the user to monitor the signal prior to, during, and after a recording session. These tools include a virtual oscilloscope and a virtual spectrum analyzer. Built on a Windows 7 Professional workstation, the RTR 2728 allows the user to install post-processing and analysis tools to operate on the recorded data. The RTR 2728 records data to the native NTFS file format, providing immediate access to the recorded data. Data can be off-loaded through two 1 Gb Ethernet ports, eight USB 2.0 ports or two eSATA ports. Additionally, data can be copied to optical disk, using the 8X double layer DVDR/RW drive.

The RTR 2728 is configured in a portable, lightweight chassis with eight hot-swap SSDs, front panel USB ports and I/O connections on the side panel. It is built on an extremely rugged, 100% aluminum alloy unit, reinforced with shock absorbing rubber corners and an impact-resistant protective glass. Using shock- and vibration-resistant SSDs, the RTR 2728 is designed to operate reliably as a portable field instrument. The eight hot-swappable SSDs provide storage capacities of up to 7.6 TB. Drives can be easily removed or exchanged during or after a mission to retrieve recorded data. Multiple RAID levels including 0, 1, 5, and 6 provide a choice for the required level of redundancy.
Features
Portable system measuring 16.9" W x 9.5" D x 13.4" H Lightweight: approximately 30 pounds Rugged aluminum alloy chassis Shock- and vibration-resistant SSDs perform well in vehicles, ships and aircraft Recording of IF signals up to 2 GHz Signal bandwidths to 500 MHz 1 GHz 12-bit A/D 1 GHz 16-bit D/A Real-time aggregate recording rates up to 2.0 GB/sec Up to 7.6 TB storage with hot-swappable SSD drives NTFS file format Complete high-performance Windows workstation with Intel CoreTM i7 processor SystemFlow GUI with Signal Viewer analysis tool File headers include time stamping and recording parameters Ideal for communications, radar, wireless, SIGINT, telecom and satcom Optional GPS time and position stamping
SystemFlow Software
Included in this system is the Pentek SystemFlow recording software. SystemFlow features a Windows-based GUI (Graphical User Interface) that provides a simple means to configure and control the system. Custom configurations can be stored as profiles and later loaded when needed, allowing the user to select preconfigured settings with a single click.
Pentek, Inc.
www.pentek.com
Model RTR 2728


The RTR 2728s configuration screens provide a simple and intuitive means for setting up the system parameters. The ADC configuration screen shown here, provides entries for gate/trigger mode, gate/trigger polarity, and sync source. All parameters contain limit-checking and integrated help to provide an easier-to-use out-of-the-box experience.

The SystemFlow Signal Viewer includes a virtual oscilloscope and spectrum analyzer for signal monitoring in both the time and frequency domains. It is extremely useful for previewing live inputs prior to recording, and for monitoring signals as they are being recorded to help ensure successful recording sessions. This viewer can also be used to inspect and analyze the recorded files after the recording is complete. Advanced signal analysis capabilities include automatic calculators for signal amplitude and frequency, second and third harmonic components, THD (total harmonic distortion) and SINAD (signal to noise and distortion). With time and frequency zoom, panning modes and dual annotated cursors to mark and measure points of interest, the SystemFlow Signal Viewer can often eliminate the need for a separate oscilloscope or spectrum analyzer in the field.
Pentek, Inc.
www.pentek.com
Model RTR 2728

Specifications

Analog Playback Output Analog Signal Outputs Quantity: 1 Output Type: Transformer-coupled, female SSMC connector1 Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz D/A Converter Type: TI DAC5681Z Interpolation: 1x, 2x or 4x Input Data Rate to DAC5681Z: 500 MS/sec max. Output Sampling Rate: 1 GHz, max. Output IF: 700 MHz, max. D/A Resolution: 16 bits Clock Sources: Selectable from onboard programmable VCXO or external clock External Clock Type: Female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz input clock or 10 MHz system reference Internal Clock Type: Progammable VCXO VCXO Frequency Ranges: 100 to 945 MHz, 970 MHz to 1 GHz Physical and Environmental Dimensions: 16.9" W x 9.5" D x 13.4" H Weight: 30 lb, approximately Power: 90 to 265 VAC, 50 - 60 Hz Operating Temp: 5 to +45 C Storage Temp: 40 to +85 C Relative Humidity: 5 to 95%, non-condensing Operating Shock: 15 g max. (11 msec, half sine wave) Operating Vibration: 10 to 20 Hz: 0.02 inch peak, 20 to 500 Hz: 1.4 g peak acceleration Power Requirements: 100 to 240 VAC, 50 to 60 Hz, 500 W max.
PC Workstation (standard configuration) Operating System: 64-bit Windows 7 Professional Processor: Intel Core i7 processor Clock Speed: 3.0 GHz or higher Operating System Drive: 128 GB SSD SDRAM: 8 GB Monitor: Built-in 17 high-resolution LCD 1440 x 900 pixels, 200 nits RAID Total Storage: 1.9, 3.8 or 7.6 TB Number of Drives: Eight Supported RAID Levels: 0, 1, 5, and 6 Drive Bays: Eight, hot-swap, removable, rear panel USB 2.0 Ports: Eight on left side, two on front panel USB 3.0 Ports: Two on left side 1 Gb Ethernet Port: Two on left side eSATA 3 Ports: Two on left side Aux Video Output: 15-pin VGA on left side Analog Recording Inputs Analog Signal Inputs Quantity: 1 Input Type: Transformer-coupled, female SSMC connector Transformer Type: Macom ETC1-1-13TR Full Scale Input: +10 dBm into 50 ohms 3 dB Passband: 5 MHz to 2 GHz A/D Converter Type: Texas Instruments ADS5400 Sampling Rate (s): 100 MHz to 1 GHz Resolution: 12 bits

Option -201 Option -221 1-Channel recording 1-Channel playback Option -244 Option -246
Storage Options
Option -242 1.9 TB SSD storage capacity; eight 240 GB hot-swappable SSDs 3.8 TB SSD storage capacity; eight 480 GB hot-swappable SSDs 7.6 TB SSD storage capacity; eight 960 GB hot-swappable SSDs
General Options (append to all other options)s a

Option -261 GPS time & position stamping
Pentek, Inc.
www.pentek.com
! w e N
Model RTR 2736
Eight-Channel Serial FPDP Rugged Portable Recorder

General Information
The Talon RTR 2736 is a complete turnkey recording system capable of recording and playing back multiple serial FPDP data streams in a rugged, lightweight portable package. It is ideal for capturing any type of streaming sources including live transfers from sensors or data from other computers and is fully compatible with the VITA 17.1 specification. Using highly-optimized disk storage technology, the system achieves aggregate recording rates up to 1.6 GB/sec. The RTR 2736 can be populated with up to eight SFP connectors supporting serial FPDP over copper, single-mode, or multimode fiber, to accommodate all popular serial FPDP interfaces. It is capable of both receiving and transmitting data over these links and supports real-time data storage to disk. Programmable modes include flow control in both receive and transmit directions, CRC support, and copy/loop modes. The system is capable of handling 1.0625, 2.125, 2.5, 3.125 and 4.25 GBaud link rates supporting data transfer rates of up to 200 MB/sec per serial FPDP link. Optional GPS time and position stamping allows the user to mark the beginning of a recording in the recording files header. Custom configurations can be stored as profiles and later loaded as needed, allowing the user to select preconfigured settings with a single click. Built on a server-class Windows 7 Professional workstation, the RTR 2736 allows the user to install post-processing and analysis tools to operate on the recorded data. The RTR 2736 records data to the native NTFS file system, providing immediate access to the recorded data. Data can be off-loaded via a gigabit Ethernet port, eight USB 2.0 ports, two USB 3.0 ports or two eSATA 3 Ports. Additionally, data can be copied to optical disk, using the 8X double layer DVDR/RW drive.
Features
Designed to operate under conditions of shock and vibration Portable system measures 16.9 W x 9.5 D x 13.4 H Rugged aluminum alloy chassis Lightweight, approximately 30 pounds Shock- and vibration-resistant SSDs perform well in vehicles, ships and aircraft Up to eight I/O channels Supports Flow Control, CRC, and Copy/Loop Mode as a receiver and transmitter Supports 1.0625, 2.125, 2.5, 3.125 and 4.25 GBaud link rates Copper, single-mode and multi-mode fiber interfaces available Real-time aggregate recording rates of up to 1.6 GB/sec Up to 3.8 terabytes of storage to NTFS RAID disk array RAID levels of 0 ,1, 5 and 6 SystemFlow GUI virtual instrumentation panel for fast, intuitive operation C-callable API for integration of recorder into application File headers include time stamping and recording parameters Optional GPS time and position stamping Windows 7 Professional workstation with high-performance Intel CoreTM i7 processor
Rugged and Flexible Architecture

SystemFlow Software
The RTR 2736 includes the SystemFlow Recording Software. SystemFlow features a Windows-based GUI (Graphical User Interface) that provides a simple and intuitive means to configure and control the system.
1 Ch 1 In / Out Ch 2 In / Out Ch 3 In / Out Ch 4 In / Out Ch 5 In / Out Ch 6 In / Out Ch 7 In / Out Ch 8 In / Out Serial FPDP Serial FPDP Serial FPDP Serial FPDP Serial FPDP Serial FPDP Serial FPDP Serial FPDP DATA DRIVES DATA DRIVES HOST PROCESSOR RUNNING SYSTEMFLOW INTEL PROCESSOR 8 2 2
Gigabit Ethernet USB 2.0 USB 3.0 eSATA PS/2 Keyboard PS/2 Mouse Video Output GPS Antenna (Optional)
SYSTEM DRIVE
DDR SDRAM
DATA DRIVES
DATA DRIVES
UP TO 3.8 TB RAID
MODEL RTR 2736
Pentek, Inc.
www.pentek.com
Model RTR 2736

Interface
The RTR 2736 GUI provides the user with a control interface for the recording system. It includes Configuration, Record, Playback, and Status screens, each with intuitive controls and indicators. The user can easily move between screens to set configuration parameters, control and monitor a recording, and play back a recorded stream. All parameters contain limit-checking and integrated help to provide an easier-to-use out-of-the-box experience. The Configure Screen shows a block diagram of the system, and provides control for operational system parameters. These parameters are entered for each input or output channel, specifying the flow control settings and the recognition of a CRC in the data stream. Each channel can also be setup to utilize SFPDPs copy/loop mode. The Record Screen allows you to browse a folder and enter a file name for the recording. The length of the recording for each channel can be specified in megabytes or in seconds. Intuitive buttons for Record, Pause and Stop simplify operation. Status indicators for each channel display the mode, the number of recorded bytes, and the average data rate. A Data Loss indicator alerts the user to any problem, such as a disk full condition. By checking the Master Record boxes, any combination of channels in the lower screen can be grouped for synchronous recording via the upper Master Record screen. The recording time can be specified, and monitoring functions inform the operator of recording progress.
Pentek, Inc.
www.pentek.com
Model RTR 2736

SystemFlow API

Serial FPDP Interface Copper - Option 280 Cable: 100-ohm shielded twin-ax Connector Type: SFP+ Max. Cable Length: 20 m Multi-mode Fiber Optical - Option 281 Cable: Multi-mode fiber, 850 nm Connector Type: LC Max. Cable Length: Up to 300 m Single-mode Fiber Optical - Option 282 Cable: Single-mode fiber Connector Type: LC Max. Cable Length: Up to 10 km Physical and Environmental Dimensions: 16.9" W x 9.5" D x 13.4" H Weight: 30 lb, approximately Operating Temp: 0 to +50 C Storage Temp: 40 to +85 C Relative Humidity: 5 to 95%, non-condensing Operating Shock: 15 g max. (11 msec, half sine wave) Operating Vibration: 10 to 20 Hz: 0.02 inch peak, 20 to 500 Hz: 1.4 g peak acceleration Power Requirements: 100 to 240 VAC, 50 to 60 Hz, 500 W max.
SystemFlow includes a complete API (Application Programming Interface) supporting control and status queries of all operations of the RTR 2736 from a custom application. High-level C-language function calls and the supporting device drivers allow users to incorporate the RTR 2736 as a high-performance server front end to a larger system. This is supported using a socket interface through the Ethernet port, either to a local host or through an internet link for remote, stand-alone acquisition. Recorded NTFS files can be easily retrieved through the same connection.
Specifications
PC Workstation Operating System: Windows 7 Professional Processor: Intel Core i7 processor Clock Speed: 2.0 GHz or greater SDRAM: 6 GB Monitor: Built-in 17 high-resolution LCD, 1440 x 900 pixels, 200 nits RAID Storage: 0.96, 1.9 or 3.8 TB Number of Drives: 8 Supported RAID Levels: 0, 1, 5 and 6 Drive Bays: 8, hot-swap, removable, rear panel USB 2.0 Ports: 8 left side, 2 front panel USB 3.0 Ports: 2 left side 1 Gb Ethernet Port: 1 left side eSATA Ports: 2 left side Aux Video Output: 15-pin VGA left side


4-Channel Maximum Disk Data Rate: 988 MB/sec
8-Channel Maximum Disk Data Rate: 1.6 GB/sec
Serial FPDP Interface (append to all options)s above)

Option 280 Option 281 Option 282 Copper, SFP+ connectors Multi-mode optical, LC connectors Single-mode optical, LC connectors

Pentek, Inc.
www.pentek.com
! w e N
Model RTR 2738
LVDS Digital I/O Rugged Portable Recorder

General Information
The Talon RTR 2738 is a complete turnkey system for recording and playing back digital data using the Pentek Model 78610 LVDS digital I/O board. Using highly optimized disk storage technology, the rugged, lightweight portable package achieves sustained recording rates of up to 1 GB/sec. The RTR 2738 utilizes a 32-bit LVDS interface that can be clocked at speeds up to 250 MHz. It includes Data Valid and Suspend signals and provides the ability to turn these signals on and off as well as control their polarity. Optional GPS time and position stamping accurately identifies each record in the file header. data can be copied to optical disk, using the 8X double layer DVDR/RW drive.

SystemFlow Software Features
Designed to operate under conditions of shock and vibration Portable system measures 16.9 W x 9.5 D x 13.4 H Rugged aluminum alloy chassis Lightweight, approximately 30 pounds Shock- and vibration-resistant SSDs perform well in vehicles, ships and aircraft 32 bits of LVDS digital I/O LVDS clock, Data Valid and Data Suspend signals Supports clock rates up to 250 MHz Real-time aggregate recording rates up to 1 GB/s Up to 3.8 terabytes of storage to NTFS RAID disk array SystemFlow GUI virtual instrumentation panel for fast, intuitive operation C-callable API for integration of recorder into application File headers include time stamping and recording parameters Optional GPS time and position stamping Windows 7 Professional workstation with high-performance Intel CoreTM i7 processor
The RTR 2738 includes the SystemFlow Recording Software. SystemFlow features a Windows-based GUI (Graphical User Interface) that provides a simple means to configure and control the system. Custom configurations can be stored as profiles and later loaded when needed, allowing the user to select preconfigured settings with a single click. Built on a Windows 7 Professional workstation, the RTR 2738 allows the user to install post-processing and analysis tools to operate on the recorded data. The RTR 2738 records data to the native NTFS file system, providing immediate access to the recorded data. Data can be off-loaded via a gigabit Ethernet port, eight USB 2.0 ports, two USB 3.0 ports or two eSATA 3 Ports. Additionally,
SystemFlow API
SystemFlow includes a complete API (Application Programming Interface) that supports control and status queries of all operations of the RTR 2738 from a custom application. High-level C-language function calls and the supporting device drivers allow users to incorporate the RTR 2738 as a high-performance server front end to a larger system. This is supported using a socket interface through the Ethernet port, either to a local host or through an internet link for remote, stand-alone acquisition. Recorded NTFS files can be easily retrieved through the same connection.
1 32-bit Data In Clock Data Valid Data Suspend DDR SDRAM 8 INTEL PROCESSOR 2 2
Gigabit Ethernet USB 2.0 USB 3.0 eSATA Keyboard PS2 Mouse Video Output GPS Antenna (Optional)
SYSTEM DRIVE
DATA DRIVES
DATA DRIVES
DATA DRIVES
DATA DRIVES
UP TO 3.8 TB RAID
MODEL RTR 2738
Pentek, Inc.
www.pentek.com
Model RTR 2738

The RTR 2738 GUI provides the user with a control interface for the recording system. It includes Configuration, Record, Playback, and Status screens, each with intuitive controls and indicators. The user can easily move between screens to set configuration parameters, control and monitor a recording, and play back a recorded stream. All parameters contain limit-checking and integrated help to provide an easier-to-use out-of-the-box experience.

The RTR 2738 configuration screen shows a block diagram of the system, and provides control for operational system parameters. These parameters include data valid and suspend enables, as well as polarity control for both signals.

Pentek, Inc.
www.pentek.com
Model RTR 2738

Specifications
PC Workstation Operating System: Windows 7 Professional Processor: Intel Core i7 processor Clock Speed: 3.0 GHz or higher SDRAM: 8 GB Monitor: Built-in 17 high-resolution LCD, 1440 x 900 pixels, 200 nits RAID Storage: 1.9 or 3.8 TB Number of Drives: up to eight Supported RAID Levels: 0, 1, 5 and 6 Drive Bays: 8, hot-swap, removable, rear panel USB 2.0 Ports: 8 left side, 2 front panel USB 3.0 Ports: 2 left side 1 Gb Ethernet Port: 1 left side eSATA Ports: 2 left side Aux Video Output: 15-pin VGA left side LVDS Interface Cable: 80-pin ribbon cable Connector Type: 2x40 pin IDC Data Lines: 32 LVDS pairs, 2.5 V compliant Clock: One LVDS pair, 2.5 V compliant Data Valid: One LVDS pair, 2.5 V compliant Data Suspend: One LVDS pair, 2.5 V compliant
Physical and Environmental Dimensions: 16.9" W x 9.5" D x 13.4" H Weight: 30 lb, approximately Operating Temp: 0 to +50 C Storage Temp: 40 to +85 C Relative Humidity: 5 to 95%, non-condensing Operating Shock: 15 g max. (11 msec, half sine wave) Operating Vibration: 10 to 20 Hz: 0.02 inch peak, 20 to 500 Hz: 1.4 g peak acceleration Power Requirements: 100 to 240 VAC, 50 to 60 Hz, 500 W max.
Model RTR 2738 Order Information

Storage Options
Option 242 Option 244 1.9 TB SSD storage capacity 3.8 TB SSD storage capacity
Interface Options
General Options
Pentek, Inc.
www.pentek.com
! ew N
Model RTR 2746
Eight-Channel RF/IF, 200 MS/sec Rugged Rackmount Recorder

General Information
The Talon RTR 2746 is a turnkey, multiband record and playback system that is built to operate under harsh conditions. Designed to withstand high vibration and operating temperatures, the RTR 2746 is intended for military, airborne and UAV applications requiring a rugged system. With scalable A/Ds, D/As and SSD (Solid-State Drive) storage, the RTR 2746 can be configured to stream data to and from disk at rates as high as 2 GB/sec. The RTR 2746 uses Penteks high-powered Virtex-6-based Cobalt boards, that provide flexibility in channel count with optional digital downconversion capabilities. Optional 16-bit, 1.25 GHz D/A converters with digital upconversion allow real-time reproduction of recorded signals. A/D sampling rates, DDC decimations and bandwidths, D/A sampling rates, and DUC interpolations are among the GUI-selectable system parameters, providing a fully programmable system capable of recording and reproducing a wide range of signals. Optional GPS time and position stamping allows the user to record this critical signal information. SystemFlow also includes signal viewing and analysis tools, that allow the user to monitor the signal prior to, during, and after a recording session. These tools include a virtual oscilloscope and a virtual spectrum analyzer. Built on a Windows 7 Professional workstation, the RTR 2746 allows the user to install post-processing and analysis tools to operate on the recorded data. The RTR 2746 records data to the native NTFS file system, providing immediate access to the recorded data. Data can be off-loaded through two rear-access gigabit Ethernet ports or two USB 2.0 ports. Additionally, data can be copied to optical disk, using the 8X double layer DVDR/RW drive.
Features
Designed to operate under conditions of shock and vibration 4U 19-inch rugged rackmount PC server chassis Windows 7 Professional workstation with high-performance Intel CoreTM i7 processor 200 MHz max. 16-bit A/D sampling for recording, up to eight channels 1.25 GHz max. 16-bit D/A sampling for playback, up to eight channels 80 MHz max. record and playback signal bandwidths Capable of record/playback of IF frequencies to 700 MHz Real-time sustained recording rates of up to 2 GB/sec Removable SSD drives Up to 12 terabytes of storage to NTFS RAID disk array RAID levels of 0 ,1, 5 , 6, 10 and 50 SystemFlow GUI with signal viewer analysis tool C-callable API for integration of recorder into application File headers include time stamping and recording parameters DDC decimation and DUC interpolation range from 2 to 65,536 Optional GPS time and position stamping

Because SSDs operate reliably under conditions of shock and vibration, the RTR 2746 performs well in ground, shipborne and airborne environments. The 24 hotswappable SSDs provide storage capacity of up to 12 TB. The drives can be easily removed or exchanged during or after a mission to retrieve recorded data. The RTR 2746 is configured in a 4U 19" rack-mountable chassis, with hot-swap data drives, front panel USB ports and I/O connectors on the rear panel. Systems are scalable to accommodate multiple chassis to increase channel counts and aggregate data rates. All recorder chassis are connected via Ethernet and can be controlled from a single GUI either locally or from a remote PC. Multiple RAID levels, including 0, 1, 5, 6, 10 and 50, provide a choice for the required level of redundancy.
SystemFlow Software
The RTR 2746 includes the SystemFlow Recording Software. SystemFlow features a Windows-based GUI (Graphical User Interface) that provides a simple means to configure and control the system. Custom configurations can be stored as profiles and later loaded when needed, allowing the user to select preconfigured settings with a single click.
2 Channels In 200 MHz 16-bit A/D Up to 8 Channels DIGITAL DOWNCONVERTER Decimation: 2 to 65,536 6 INTEL PROCESSOR 2
SYSTEM DRIVE Channels Out 800 MHz or 1.25 GHz 16-bit D/A Up to 8 Channels DIGITAL UPCONVERTER Decimation: 2 to 65,536
DDR SDRAM
DATA DRIVES
DATA DRIVES
DATA DRIVES
DATA DRIVES
UP TO 12 TB RAID
MODEL RTR 2746
Pentek, Inc.
www.pentek.com
Model RTR 2746

The RTR 2746 GUI provides the user with a control interface for the recording system. It includes Configuration, Record, Playback and Status screens, each with intuitive controls and indicators. The user can easily move between screens to set configuration parameters, control and monitor a recording, play back a recorded signal and monitor board temperature and voltage levels. The signal viewer, integrated into the recording GUI, allows the user to monitor real-time signals or signals recorded on disk.

The RTR 2746 configuration screens provide a simple and intuitive means for setting up the system parameters. The DDC configuration screen shown here, provides entries for input source, center frequency, decimation, as well as gate and trigger information. All parameters contain limitchecking and integrated help to provide an easier-to-use out-of-the-box experience.

Pentek, Inc.
www.pentek.com
Model RTR 2746

A/D Performance
Spurious Pick-up
D/A Performance
Pentek, Inc.
www.pentek.com
Model RTR 2746

Specifications
PC Workstation (standard configuration) Operating System: Windows 7 Professional Processor: Intel Core i7 processor Clock Speed: 2.0 GHz or higher SDRAM: 6 GB RAID Storage: Up to 12 TB Number of Drives: up to 24 Supported Levels: 0, 1, 5, 6, 10 and 50 Analog Recording Input / Output Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverter Type: Virtex-6 FPGA, Pentek-installed DDC IP Core Decimation: 2 to 65,536 in two stages of 2 to 256 Bandwidth: Up to 80 MHz Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz
Digital Upconverter and D/As Type: TI DAC5688 and Pentek-installed interpolation IP core Interpolation: 2 to 65,536 in two stages of 2 to 256 Input Data Rate: 250 MHx max. Output IF: DC to 400 MHz Output Signal: Analog, real or quadrature Output Sampling Rate: 800 MHz max. with 2, 4 or 8 interpolation Resolution: 16 bits Clock Sources: Selectable from onboard programmable VCXO, external or LVDS clocks External Clocks Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, 10 to 200 MHz Multi-Recorder Sync/Gate Bus: 26-pin connector, dual clock/ sync/gate input/output LVDS buses; one sync/gate input TTL signal Physical and Environmental Dimensions 4U Short Chassis: 19" W x 21" D x 7" H Weight: 50 lb, approx. Operating Temp: 0 to +50 C Storage Temp: 40 to +85 C Relative Humidity: 5 to 95%, non-condensing Operating Shock: 15 g max. (11 msec, half sine wave) Operating Vibration: 10 to 20 Hz: 0.02 inch peak, 20 to 500 Hz: 1.4 g peak acceleration Power Requirements: 100 to 240 VAC, 50 to 60 Hz, 500 W max.

Recording Options
Option 201 Option 202 Option 203 Option 204 Option 208 1-Channel recording 2-Channel recording 3-Channel recording 4-Channel recording 8-Channel recording
Storage Options
Option 240 Option 241 Option 242 Option 243 Option 244 2 TB Storage capacity 4 TB Storage capacity 6 TB Storage capacity 8 TB Storage capacity 12 TB Storage capacity
Playback Options
Option 221 Option 222 Option 224 Option 228 1-Channel playback 2-Channel playback 4-Channel playback 8-Channel Playback
General Options
Option 260 Option 261 Digital downconversion & upconversion GPS time & position stamping
Pentek, Inc.
www.pentek.com
! ew N
Model RTR 2747
Four-Channel RF/IF, 500 MS/sec Rugged Rackmount Recorder

General Information
The Talon RTR 2747 is a turnkey, multiband record and playback system that is built to operate under harsh conditions. Designed to withstand high vibration and operating temperatures, the RTR 2747 is intended for military, airborne and UAV applications requiring a rugged system. With scalable A/Ds, D/As and SSD (Solid-State Drive) storage, the RTR 2747 can be configured to stream data to and from disk at aggregate rates as high as 4.0 GB/sec. The RTR 2747 uses Penteks high-powered Virtex-6-based Cobalt boards, that provide flexibility in channel count with optional digital downconversion and upconversion capabilities. A/D sampling rates, DDC decimations and bandwidths, D/A sampling rates, and DUC interpolations are among the selectable system parameters, that provide a fully programmable system capable of recording and reproducing a wide range of signals. Optional GPS time and position stamping allows the user to record this critical signal information. SystemFlow also includes signal viewing and analysis tools, that allow the user to monitor the signal prior to, during, and after a recording session. These tools include a virtual oscilloscope and a virtual spectrum analyzer. Built on a Windows 7 Professional workstation, the RTR 2747 allows the user to install post-processing and analysis tools to operate on the recorded data. The RTR 2747 records data to the native NTFS file system, providing immediate access to the recorded data. Data can be off-loaded through two rear-access gigabit Ethernet ports or two USB 2.0 ports. Additionally, data can be copied to optical disk, using the 8X double layer DVDR/RW drive.

Because SSDs operate reliably under conditions of shock and vibration, the RTR 2747 performs well in ground, shipborne and airborne environments. The hot-swappable SSDs provide storage capacity of up to 11.5 TB. The drives can be easily removed or exchanged during or after a mission to retrieve recorded data. The RTR 2747 is configured in a 4U 19" rack-mountable chassis, with hot-swap data drives, front panel USB ports and I/O connectors on the rear panel. Systems are scalable to accommodate multiple chassis to increase channel counts and aggregate data rates. All recorder chassis are connected via Ethernet and can be controlled from a single GUI either locally or from a remote PC. Multiple RAID levels, including 0, 1, 5, 6, 10 and 50, provide a choice for the required level of redundancy.
Features
Designed to operate under conditions of shock and vibration 4U 19-inch rugged rackmount PC server chassis Windows 7 Professional workstation with high-performance Intel CoreTM i7 processor Shock- and vibration-resistant SSDs perform well in vehicles, ships and aircraft Recording and playback of IF signals up to 700 MHz Signal bandwidths to 200 MHz 500 MHz 12-bit A/Ds or 400 MHz 14-bit A/Ds 800 MHz 16-bit D/As Real-time aggregate recording rates of up to 4.0 GB/sec Up to 11.5 terabytes of storage to NTFS RAID disk array RAID levels of 0 ,1, 5 , 6, 10 and 50 NTFS file format SystemFlow GUI with signal viewer analysis tool C-callable API for integration of recorder into application File headers include time stamping and recording parameters Optional GPS time and position stamping
SystemFlow Software
The RTR 2747 includes the SystemFlow Recording Software. SystemFlow features a Windows-based GUI (Graphical User Interface) that provides a simple means to configure and control the system. Custom configurations can be stored as profiles and later loaded when needed, allowing the user to select preconfigured settings with a single click.
Channels In
Gigabit Ethernet INTEL PROCESSOR USB 2.0 PS/2 Keyboard PS/2 Mouse Video Output GPS Antenna (Optional)
SYSTEM DRIVE
DDR SDRAM
Channels Out
SSD DRIVES
SSD DRIVES
SSD DRIVES
SSD DRIVES
MODEL RTR 2747
RAID DATA STORE
Pentek, Inc.
www.pentek.com
Model RTR 2747



Pentek, Inc.
www.pentek.com
Model RTR 2747

Specifications
PC Workstation (standard configuration) Operating System: 64-bit Windows 7 Professional Processor: Intel Core i7 processor Clock Speed: 2.0 GHz or higher SDRAM: 8 GB RAID Storage: Up to 11.5 TB Supported Levels: 0, 1, 5, 6, 10 and 50 Analog Recording Inputs Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 or ADS5474 (Option -014) Sampling Rate (s): 20 MHz to 500 MHz or 20 MHz to 400 MHz (Option -014) Resolution: 12 bits or 14 bits (Option -014) A/D Recording Rate/Channel: 2s bytes/sec, (e.g., 800 MB/sec per channel at s = 400 MHz) Digital Downconverter Type: Virtex-6 installed DDC IP Core Decimation (D): 2 to 65,536 DDC Bandwidth: 0.8 s/D Bandwidth Range: 5 kHz to 160 MHz at s = 400 MHz DDC Recording Rate/Channel: 2s/D bytes/sec
Analog Playback Outputs Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Digital Upconverter and D/A Type: TI DAC5688 and Pentek-installed interpolation IP core Interpolation: 2 to 65,536 Input Data Rate to DAC5688: 250 MS/sec max. Output IF: 250 MHz max. Output Signal: Analog, real or quadrature Output Sampling Rate: 800 MHz max. Resolution: 16 bits Bandwidth Range: Matches recording bandwidths Clock Sources: Selectable from onboard programmable VCXO, external or LVDS clocks External Clock Type: Female SSMC connector, sine wave, 0 to +12 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz divider input clock or PLL system reference Internal Clock Type: Progammable VCXO from 10 to 810 MHz Physical and Environmental Dimensions 4U Short Chassis: 19" W x 21" D x 7" H Weight: 50 lb, approx. Operating Temp: 0 to +50 C Storage Temp: 40 to +85 C Relative Humidity: 5 to 95%, non-condensing Operating Shock: 15 g max. (11 msec, half sine wave) Operating Vibration: 10 to 20 Hz: 0.02 inch peak, 20 to 500 Hz: 1.4 g peak acceleration Power Requirements: 100 to 240 VAC, 50 to 60 Hz, 500 W max.

Recording Options
Option -201 Option -202 Option -204 1-Channel recording 2-Channel recording 4-Channel recording
Storage Options
Option -242 Option -244 Option -246 Option -247 1.9 TB Storage capacity 3.8 TB Storage capacity 7.6 TB Storage capacity 11.5 TB Storage capacity
Playback Options
Option -221 Option -222 Option -224 1-Channel playback 2-Channel playback 4-Channel playback
General Options (append to all other options)

Option -014 Option -261 400 MHz, 14-bit A/Ds GPS time & position stamping
Pentek, Inc.
www.pentek.com
! w e N
Model RTR 2748
Two-Channel RF/IF, 1 GS/sec Rugged Rackmount Recorder

General Information
The Talon RTR 2748 is a turnkey recording and playback system that allows users to record and reproduce signals with bandwidths up to 500 MHz. The RTR 2748 can be configured as a one- or two-channel system to provide real-time recording and playback rates up to 4.0 GB/sec to an array of solid-state drives. The RTR 2748 uses Penteks highpowered Virtex-6-based Cobalt boards that provide the data streaming engine for the high-speed A/D converters. A built-in synchronization module is provided to allow for multichannel phasecoherent operation. GPS time and position stamping is optionally available. Built on a Windows 7 Professional workstation, the RTR 2748 allows the user to install post-processing and analysis tools to operate on the recorded data. The RTR 2748 records data to the native NTFS file system that provides immediate access to the recorded data. Data can be off-loaded via two gigabit Ethernet ports, six USB 2.0 ports or two eSATA ports. Additionally, data can be copied to optical disk, using the 8X double layer DVDR/RW drive.

Because SSDs operate reliably under conditions of shock and vibration, the RTR 2748 performs well in ground, shipborne and airborne environments. The drives can be easily removed or exchanged during or after a mission to retrieve recorded data. Available in a 21" deep, 24-bay chassis or a 26" deep, 40-bay chassis, the system can be populated with SSD storage up to 38.4 TB. The RTR 2748 is configured in a 4U 19" rugged rackmount chassis, with hot-swappable data drives, front panel USB ports and I/O connectors on the rear panel. Systems are scalable to accommodate multiple chassis to increase channel counts and aggregate data rates. All recorder chassis are connected via Ethernet and can be controlled from a single GUI either locally or from a remote PC. Multiple RAID levels, including 0, 1, 5, 6, 10, and 50 provide a choice for the required level of redundancy.
Features
SystemFlow Software
The RTR 2748 includes the SystemFlow Recording Software. SystemFlow features a Windows-based GUI (Graphical User Interface) that provides a simple means to configure and control the system. Custom configurations can be stored as profiles and later loaded when needed, allowing the user to select preconfigured settings with a single click. SystemFlow also includes signal viewing and analysis tools that allow the user to monitor the signal prior to, during, and after a recording session. These tools include a virtual oscilloscope and a virtual spectrum analyzer.
Designed to operate under conditions of shock and vibration Recording of IF signals up to 2 GHz. Signal bandwidths to 500 MHz 1 GHz 12-bit A/Ds 1 GHz 16-bit D/As Real-time aggregate recording rates up to 4 GB/sec 4U 19-inch rugged rackmount PC server chassis Available in 21" deep 24-bay rackmount chassis or 26" deep 40-bay rackmount chassis Up to 38.4 terabytes of SSD storage to NTFS RAID solid state disk array RAID levels of 0 ,1, 5 , 6, 10 and 50 Complete high-performance Windows workstation with Intel CoreTM i7 processor SystemFlow GUI with signal viewer analysis tool C-callable API for integration of recorder into application File headers include time stamping and recording parameters Optional GPS time and position stamping
Pentek, Inc.
www.pentek.com
Model RTR 2748


The RTR 2748 configuration screens provide a simple and intuitive means for setting up the system parameters. The A/D configuration screen shown here, provides entries for gate/trigger mode, gate/trigger polarity, and trigger source. All parameters contain limit-checking and integrated help to provide an easier-to-use out-of-the-box experience.

Pentek, Inc.
www.pentek.com
Model RTR 2748

Specifications

Analog Playback Output Analog Signal Outputs Quantity: 1 Output Type: Transformer-coupled, female SSMC connector Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz D/A Converter Type: TI DAC5681Z Interpolation: 1x, 2x or 4x Input Data Rate to DAC5681Z: 500 MS/sec max. Output Sampling Rate: 1 GHz, max. Output IF: 700 MHz, max. D/A Resolution: 16 bits Clock Sources: Selectable from onboard programmable VCXO or external clock External Clock Type: Female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz input clock or 10 MHz system reference Internal Clock Type: Progammable VCXO VCXO Frequency Ranges: 100 to 945 MHz, 970 MHz to 1 GHz Physical and Environmental Size Width: 19" Height: 7" Depth: 21" (24 drive chassis) Depth: 26" (40 drive chassis) Weight: 60-85 lb Operating Temp: 0 to +50 C Storage Temp: 40 to +85 C Relative Humidity: 5 to 95%, non-condensing Operating Shock: 15 g max. (11 msec, half sine wave) Operating Vibration: 10 to 20 Hz: 0.02 inch peak, 20 to 500 Hz: 1.4 g peak acceleration Power Requirements: 100 to 240 VAC, 50 to 60 Hz, 500 W max.
PC Workstation (standard configuration) Operating System: Windows 7 Professional Processor: Intel Core i7 processor Clock Speed: 3.0 GHz or higher SDRAM: 8 GB RAID Storage: 1.938.4 TB Number of Drives: Up to 40 Drive Type: SATA III SSDs Supported RAID Levels: 0, 1, 5, 6, 10 and 50 Analog Recording Inputs Analog Signal Inputs Quantity: 1 Input Type: Transformer-coupled, female SSMC connector Transformer Type: Macom ETC1-1-13TR Full Scale Input: +10 dBm into 50 ohms 3 dB Passband: 5 MHz to 2 GHz A/D Converter Type: Texas Instruments ADS5400 Sampling Rate (s): 100 MHz to 1 GHz Resolution: 12 bits

Option 201 Option 202 Option 221 Option 222 1-Channel recording 2-Channel recording 1-Channel playback 2-Channel playback
Storage Options
Option 241 Option 242 Option 244 Option 245 Option 247 Option 249 1.9 TB SSD Storage 3.8 TB SSD Storage 7.6 TB SSD Storage 11.5 TB SSD Storage 23 TB SSD Storage 38.4 TB SSD Storage
General Options (append to all other options)


Pentek, Inc.
www.pentek.com
! ew N
Model RTR 2749
Ultra Wideband One- or Two-Channel RF/IF, 3.2 GS/sec Rugged Rackmount Recorder
General Information
The Talon RTR 2749 is a turnkey system, used for recording high-bandwidth signals. The RTR 2749 uses 12-bit, 3.6 GHz A/D converters and can provide sustained recording rates up to 3.2 GB/sec. It can be configured as a one- or two-channel system and can record sampled data, packed as 8-bit-wide consecutive samples, or as 16-bit-wide consecutive samples (12-bit digitized samples residing in the 12 MSBs of the 16-bit word.) The RTR 2749 uses Penteks highpowered Virtex-6-based Cobalt boards that provide the data streaming engine for the high-speed A/D converters. Channel and packing modes as well as gate and trigger settings are among the GUI-selectable system parameters, providing complete control over this ultra wideband recording system. Optional GPS time and position stamping allows the user to capture this critical information in the header of each data file. after a recording session. These tools include a virtual oscilloscope and a virtual spectrum analyzer. Built on a Windows 7 Professional workstation, the RTR 2749 allows the user to install post-processing and analysis tools to operate on the recorded data. The RTR 2749 records data to the native NTFS file system that provides immediate access to the recorded data. Data can be off-loaded via two gigabit Ethernet ports, six USB 2.0 ports or two eSATA ports. Additionally, data can be copied to optical disk, using the 8X double layer DVDR/RW drive.
Features
Designed to operate under conditions of shock and vibration Sample rates up to 3.2 GHz in single-channel mode Sample rates up to 1.6 GHz in dual-channel mode Capable of recording RF/IF frequencies to 1.75 GHz in single-channel mode Capable of recording RF/IF frequencies to 2.8 GHz in dual-channel mode 12-bit A/D, with 12- and 8-bit packing modes Real-time sustained recording rates of up to 3.2 GB/sec 4U 19-inch rugged rackmount PC server chassis Windows 7 Professional workstation with-high performance Intel CoreTM i7 processor Up to 20 terabytes of SSD storage to NTFS RAID solid state disk array RAID levels of 0 ,1, 5 , 6, 10 and 50 N+1 redundant power supply SystemFlow GUI with signal viewer analysis tool C-callable API for integration of recorder into application File headers include time stamping and recording parameters Optional GPS time and position stamping

Because SSDs operate reliably under conditions of vibration and shock, the RTR 2749 performs well in ground, shipborne and airborne environments. The 40 hot-swappable SSDs provide storage capacity of up to 20 TB. The drives can be easily removed or exchanged during or after a mission to retrieve recorded data. The RTR 2749 is configured in a 4U 19" rugged rackmount chassis, with hot-swappable data drives, front panel USB ports and I/O connectors on the rear panel. Systems are scalable to accommodate multiple chassis to increase channel counts and aggregate data rates. All recorder chassis are connected via Ethernet and can be controlled from a single GUI either locally or from a remote PC. Multiple RAID levels, including 0, 1, 5, 6, 10 and 50 provide a choice for the required level of redundancy.
SystemFlow Software
The RTR 2749 includes the SystemFlow Recording Software. SystemFlow features a Windows-based GUI (Graphical User Interface) that provides a simple means to configure and control the system. Custom configurations can be stored as profiles and later loaded when needed, allowing the user to select preconfigured settings with a single click. SystemFlow also includes signal viewing and analysis tools that allow the user to monitor the signal prior to, during, and
Gigabit Ethernet Channel 1 In 3.6 GHz (1 Channel) or 1.8 GHz (2 Channel) 12-Bit A/D USB INTEL PROCESSOR eSATA
Channel 2 In
DATA DRIVES
DATA DRIVES
DATA DRIVES
DATA DRIVES
UP TO 20 TB RAID
MODEL RTR 2749
Pentek, Inc.
www.pentek.com
Model RTR 2749



Pentek, Inc.
www.pentek.com
Model RTR 2749

Specifications
A/D Converters Type: Texas Instruments ADC12D1800 Sampling Rate Single-channel mode: 500 MHz to 3.6 GHz Dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Maximum Usable Input Frequency Single-channel mode: 1.75 GHz Dual-channel mode: 2.8 GHz Sampling Clock Source: Internal fixed-frequency or programmable oscillator (selectable by option); in single-channel mode, the sample rate is 2x the clock frequency; in dual-channel mode, the sample rate equals the clock frequency Frequency Reference: Accepts external 10 MHz reference at 0 to +4 dBm to phase-lock the clock oscillator Physical and Environmental Size: 19" W x 26" D x 7" H Weight: 60-85 lb Operating Temp: 0 to +50 C Storage Temp: 40 to +85 C Relative Humidity: 5 to 95%, non-condensing Operating Shock: 15 g max. (11 msec, half sine wave) Operating Vibration: 10 to 20 Hz: 0.02 inch peak, 20 to 500 Hz: 1.4 g peak acceleration Power Requirements: 100 to 240 VAC, 50 to 60 Hz, 500 W max.
PC Workstation (standard configuration) Operating System: Windows 7 Professional Processor: Intel Core i7 processor Clock Speed: 2.0 GHz or higher SDRAM: 8 GB RAID Storage: 220 TB Number of Drives: Up to 40 Drive Type: SATA III SSDs Supported RAID Levels: 0, 1, 5, 6, 10 and 50 Analog Signal Inputs Connectors: Two rear panel SSMC connectors, In 1 & In 2 Input Type: Single-ended, non-inverting Full Scale Input: +4 dBm into 50 ohms Coupling: Transformer coupled Analog Input Transformers Bandwidth: 4.5 kHz to 3.0 GHz Insertion Loss: 3.5 dB maximum
Model RTR 2749 Options

Sample Rate Options
Option 910 User-Programmable Sample Clock Dual-channel mode sample clock range 150 MHz 945 MHz 970 MHz 1134 MHz 1213 MHz 1417.5 MHz Single-channel mode sample clock range 500 MHz 1890 MHz 1940 MHz 2268 MHz 2426 MHz 2835 MHz Option 911 Fixed-frequency clock 1.5 / 3.0 GHz sample clock Fixed-frequency clock 1.6 / 3.2 GHz sample clock
Storage Options
Option 241 Option 242 Option 243 4.8 TB SSD Storage 9.6 TB SSD Storage 19.2 TB SSD Storage
General Options
Option 912
Sample rates are set up for dual-channel mode first and single-channel mode second: e.g. 1.5 / 3.0 is 1.5 in dualchannel mode and 3.0 in single-channel mode. Custom fixed-frequency sample clocks available upon request.
Pentek, Inc.
www.pentek.com
! ew N
Model RTR 2755
Two-Channel Ten-Gigabit Ethernet Rugged Rackmount Recorder

General Information
The Talon RTR 2755 is a complete turnkey recording system for storing one or two ten-gigabit Ethernet (10 GbE) streams. It is ideal for capturing any type of streaming sources including live transfers from sensors or data from other computers and supports both TCP and UDP protocols. Using highly-optimized disk storage technology, the system guarantees loss-free performance at aggregate recording rates up to 2 GB/sec. Two rear panel SFP+ LC connectors for 850 nm multi-mode or single-mode fibre cables, or CX4 connectors for copper twinax cables accommodate all popular 10 GbE interfaces. Optional GPS time and position stamping accurately identifies each record in the file header. user to install post-processing and analysis tools to operate on the recorded data. The RTR 2755 records data to the native NTFS file system, providing immediate access to the recorded data. Data can be off-loaded via two gigabit Ethernet ports or six USB 2.0 ports. Additionally, data can be copied to optical disk, using the 8X double layer DVDR/RW drive.

Because SSDs operate reliably under conditions of shock and vibration, the RTR 2755 performs well in ground, shipborne and airborne environments. The 24 hotswappable SSDs provide storage capacity of up to 12 TB. The drives can be easily removed or exchanged during or after a mission to retrieve recorded data. The RTR 2755 is configured in a 4U 19" rack-mountable chassis, with hot-swap data drives, front panel USB ports and I/O connectors on the rear panel. Systems are scalable to accommodate multiple chassis to increase channel counts and aggregate data rates. All recorder chassis are connected via Ethernet and can be controlled from a single GUI either locally or from a remote PC. Multiple RAID levels, including 0, 1, 5, 6, 10 and 50, provide a choice for the required level of redundancy.
Features
SystemFlow Software
The RTR 2755 includes the SystemFlow Recording Software. SystemFlow features a Windows-based GUI (Graphical User Interface) that provides a simple and intuitive means to configure and control the system. Custom configurations can be stored as profiles and later loaded as needed, allowing the user to select preconfigured settings with a single click. Built on a server-class Windows 7 Professional workstation, the RTR 2755 allows the
Designed to operate under conditions of shock and vibration Records ten-gigabit Ethernet streams One or two channels TCP and UDP protocols Copper or optical 10 GbE interfaces Aggregate recording rates to 2 GB/sec Removable SSD drives 4U short 19-inch rugged rackmount PC server chassis Windows 7 Professional workstation with high-performance Intel Core TM i7 processor Up to 12 terabytes of storage to NTFS RAID solid state disk array RAID levels of 0 ,1, 5 , 6, 10 and 50 SystemFlow GUI virtual instrumentation panel for fast, intuitive operation C-callable API for integration of recorder into applications File headers include time stamping and recording parameters Optional GPS time and position stamping
2 Ch 1 In / Out 6 10G Ethernet INTEL PROCESSOR 2
SSD SYSTEM DRIVE Ch 2 In / Out
DDR SDRAM
10G Ethernet WINDOWS HOST PROCESSOR
SSD DRIVES
SSD DRIVES
SSD DRIVES
SSD DRIVES
RAID DATA STORE
MODEL RTR 2755
Pentek, Inc.
www.pentek.com
Model RTR 2755

Interface
The RTR 2755 GUI provides the user with a control interface for the recording system. It includes Configuration, Record, Playback, and Status screens, each with intuitive controls and indicators. The user can easily move between screens to set configuration parameters, control and monitor a recording, and play back a recorded stream. All parameters contain limit-checking and integrated help to provide an easier-to-use out-of-the-box experience. The Configure Screen shows a block diagram of the system, and presents operational system parameters including temperature and voltages. Parameters are entered for each input or output channel specifying UDP or TCP protocol, client or server connection, the IP address and port number. The Record Screen allows you to browse a folder and enter a file name for the recording. The length of the recording for each channel can be specified in megabytes or in seconds. Intuitive buttons for Record, Pause and Stop simplify operation. Status indicators for each channel display the mode, the number of recorded bytes, and the average data rate. A Data Loss indicator alerts the user to any problem, such as a disk full condition. By checking the Master Record boxes, any combination of channels in the lower screen can be grouped for synchronous recording via the upper Master Record screen. The recording time can be specified, and monitoring functions inform the operator of recording progress.
Pentek, Inc.
www.pentek.com
Model RTR 2755

SystemFlow API

Ten-Gigabit Ethernet Interface Copper - Option 280 Quantity: 2 ports Cable: Twinax copper Connector Type: CX4 Max. Cable Length: 15 m Multi-mode Fibre Optical - Option 281 Quantity: 2 ports Cable: Multi-mode fibre, 850 nm Connector Type: LC Max. Cable Length: Up to 300 m Single-mode Fibre Optical - Option 282 Quantity: 2 ports Cable: Single-mode fibre Connector Type: LC Max Cable Length: Up to 10 km Physical and Environmental Dimensions 4U Short Chassis: 19" W x 21" D x 7" H Weight: 50 lb, approx. Operating Temp: 0 to +50 C Storage Temp: 40 to +85 C Relative Humidity: 5 to 95%, non-condensing Operating Shock: 15 g max. (11 msec, half sine wave) Operating Vibration: 10 to 20 Hz: 0.02 inch peak, 20 to 500 Hz: 1.4 g peak acceleration Power Requirements: 100 to 240 VAC, 50 to 60 Hz, 500 W max.
Specifications
PC Workstation Operating System: Windows 7 Professional Processor: Intel Core i7 processor Clock Speed: 2.0 GHz or higher SDRAM: 6 GB RAID Storage: 612 TB Drive Type: Solid state drive Number of Drives: 1224 Supported Levels: 0, 1, 5, 6, 10 and 50

Option 201 - Single Channel 10 GbE Recorders
Option 201-240 Storage capacity: 6 TB 12 ea. 512 GB, 2.5 solid state drives 4U short chassis
10 GbE Interface (append to all previous options)s above)

Option 280 Option 281 Option 282 Copper , CX4 connectors Multi-mode optical, LC connectors Single-mode optical, LC connectors
Option 202 - Dual Channel 10 GbE Recorders

Option 202-241 Storage capacity: 12 TB 24 ea. 512 GB, 2.5 solid state drives 4U short chassis
General Options (append to all previous options)s a

Option 261 GPS tme & position stamping
Pentek, Inc.
www.pentek.com
! w e N
Model RTR 2756
Eight-Channel Serial FPDP Rugged Rackmount Recorder

General Information
The Talon RTR 2756 is a complete turnkey recording system capable of recording and playing back multiple serial FPDP data streams. It is ideal for capturing any type of streaming sources including live transfers from sensors or data from other computers and is fully compatible with the VITA 17.1 specification. Using highly-optimized disk storage technology, the system achieves aggregate recording rates up to 3.4 GB/sec. The RTR 2756 can be populated with up to eight SFP connectors supporting serial FPDP over copper, single-mode, or multimode fiber, to accommodate all popular serial FPDP interfaces. It is capable of both receiving and transmitting data over these links and supports real-time data storage to disk. Programmable modes include flow control in both receive and transmit directions, CRC support, and copy/loop modes. The system is capable of handling 1.0625, 2.125, 2.5, 3.125 and 4.25 GBaud link rates supporting data transfer rates of up to 425 MB/sec per serial FPDP link. Optional GPS time and position stamping allows the user to mark the beginning of a recording in the recording files header. Built on a server-class Windows 7 Professional workstation, the RTR 2756 allows the user to install post-processing and analysis tools to operate on the recorded data. The RTR 2756 records data to the native NTFS file system, providing immediate access to the recorded data. Data can be off-loaded via two gigabit Ethernet ports or six USB 2.0 ports. Additionally, data can be copied to optical disk, using the 8X double layer DVDR/RW drive.

Because SSDs operate reliably under conditions of shock and vibration, the RTR 2756 performs well in ground, shipborne and airborne environments. Configurable with as many as 40 hot-swappable SSDs, the RTR 2756 can provide storage capacities of up to 19 TB in a rugged 4U chassis. Drives can be easily removed or exchanged during or after a mission to retrieve recorded data. The RTR 2756 is configured in a 4U 19 rack-mountable chassis, with hot-swap data drives, front-panel USB ports and I/O connectors on the rear panel. Systems are scalable to accommodate multiple chassis to increase channel counts and aggregate data rates. All recorder chassis are connected via Ethernet and can be controlled from a single GUI either locally or from a remote PC Multiple RAID levels, including 0,1,5, 6, 10 and 50 provide a choice for the required level on redundancy. Redundant power supplies are optionally available to provide a robust and reliable high-performance recording system.
Features
Designed to operate under conditions of shock and vibration Complete serial FPDP record and playback system Up to eight I/O channels in a single 4U 19-inch rugged rackmount PC server chassis Removable SSDs Up to 20 terabytes of storage to NTFS RAID disk array Copper, single-mode and multi-mode fiber interfaces available Real-time aggregate recording rates of up to 3.4 GB/sec in eight-channel configuration Supports Flow Control, CRC, and Copy/Loop Mode as a receiver and transmitter Supports 1.0625, 2.125, 2.5, 3.125 and 4.25 GBaud link rates RAID levels of 0 ,1, 5 , 6, 10 and 50 Optional N+1 redundant power supply SystemFlow GUI virtual instrumentation panel for fast, intuitive operation C-callable API for integration of recorder into application File headers include time stamping and recording parameters Optional GPS time and position stamping Windows 7 Professional workstation with high-performance Intel CoreTM i7 processor
SystemFlow Software
The RTR 2756 includes the SystemFlow Recording Software. SystemFlow features a Windows-based GUI (Graphical User Interface) that provides a simple and intuitive means to configure and control the system. Custom configurations can be stored as profiles and later loaded as needed, allowing the user to select preconfigured settings with a single click.
2 Ch 1 In / Out Ch 2 In / Out Ch 3 In / Out Ch 4 In / Out Ch 5 In / Out Ch 6 In / Out Ch 7 In / Out Ch 8 In / Out Serial FPDP Serial FPDP Serial FPDP Serial FPDP Serial FPDP Serial FPDP Serial FPDP Serial FPDP DATA DRIVES DATA DRIVES HOST PROCESSOR RUNNING SYSTEMFLOW INTEL PROCESSOR 6 2
SYSTEM DRIVE
DDR SDRAM
DATA DRIVES
DATA DRIVES
Contact factory for options, for number and type of channels, recording rates, and disk capacity.
UP TO 20 TB RAID
MODEL RTR 2756
Pentek, Inc.
www.pentek.com
Model RTR 2756

Interface
The RTR 2756 GUI provides the user with a control interface for the recording system. It includes Configuration, Record, Playback, and Status screens, each with intuitive controls and indicators. The user can easily move between screens to set configuration parameters, control and monitor a recording, and play back a recorded stream. All parameters contain limit-checking and integrated help to provide an easier-to-use out-of-the-box experience. The Configure Screen shows a block diagram of the system, and provides control for operational system parameters. These parameters are entered for each input or output channel, specifying the flow control settings and the recognition of a CRC in the data stream. Each channel can also be setup to utilize SFPDPs copy/loop mode. The Record Screen allows you to browse a folder and enter a file name for the recording. The length of the recording for each channel can be specified in megabytes or in seconds. Intuitive buttons for Record, Pause and Stop simplify operation. Status indicators for each channel display the mode, the number of recorded bytes, and the average data rate. A Data Loss indicator alerts the user to any problem, such as a disk full condition. By checking the Master Record boxes, any combination of channels in the lower screen can be grouped for synchronous recording via the upper Master Record screen. The recording time can be specified, and monitoring functions inform the operator of recording progress.
Pentek, Inc.
www.pentek.com
Model RTR 2756

SystemFlow API

Serial FPDP Interface Copper - Option 280 Cable: 100-ohm shielded twin-ax Connector Type: SFP+ Max. Cable Length: 20 m Multi-mode Fiber Optical - Option 281 Cable: Multi-mode fiber, 850 nm Connector Type: LC Max. Cable Length: Up to 300 m Single-mode Fiber Optical - Option 282 Cable: Single-mode fiber Connector Type: LC Max. Cable Length: Up to 10 km Physical and Environmental Dimensions & Weights All options except 085: 19" W x 21" D x 7" (4U) H Weight: 50 lb, approx. Option 085: 19" W x 26" D x 7" (4U) H Weight: 65-90 lb Operating Temp: 0 to +50 C Storage Temp: 40 to +85 C Relative Humidity: 5 to 95%, non-condensing Operating Shock: 15 g max. (11 msec, half sine wave) Operating Vibration: 10 to 20 Hz: 0.02 inch peak, 20 to 500 Hz; 1.4 g peak acceleration
Specifications
PC Workstation Operating System: Windows 7 Professional Processor: Intel Core i7 processor Clock Speed: 2.0 GHz or greater SDRAM: 6 GB RAID Storage: 1.9-19.2 TB Drive Type: 2.5 SSD Number of Drives: All options except 085, up to 24; option 085 up to 40 Supported Levels: 0, 1, 5, 6, 10 and 50

Option 041 Storage capacity: 1.9 TB 4U short chassis

Option 042
Storage capacity: 3.8 TB 4U short chassis Storage capacity: 7.8 TB 4U short chassis Storage capacity: 11.5 TB 4U short chassis
Option 082
Storage capacity: 3.8 TB 4U short chassis Storage capacity: 7.8 TB 4U short chassis Storage capacity: 11.5 TB 4U short chassis Storage capacity: 19.2 TB Special chassis
Option 043
Option 083
Option 044
Option 084
4-Channel Maximum Disk Data Rate: 988 MB/sec
Option 085
Serial FPDP Interface (append to all options)sbove)

Option 280 Option 281 Option 282 Copper, SFP+ connectors Multi-mode optical, LC connectors Single-mode optical, LC connectors 8-Channel Maximum Disk Data Rate: 1976 MB/sec

Option 261 GPS time & position stamping Contact Pentek for other configurations
Pentek, Inc.
www.pentek.com
! w e N
Model RTR 2758
LVDS Digital I/O Rugged Rackmount Recorder

General Information
The Talon RTR 2758 is a complete turnkey system for recording and playing back digital data using the Pentek Model 78610 LVDS digital I/O board. Using highly optimized disk storage technology, the system achieves sustained recording rates of up to 1 GB/sec. The RTR 2758 utilizes a 32-bit LVDS interface that can be clocked at speeds up to 250 MHz. It includes Data Valid and Suspend signals and provides the ability to turn these signals on and off as well as control their polarity. Optional GPS time and position stamping accurately identifies each record in the file header. Data can be off-loaded via two gigabit Ethernet ports or six USB ports. Additionally, data can be copied to optical disk using the 8X double layer DVDR/RW drive.
Ruged and Flexible Architecture

Because SSDs operate reliably under conditions of shock and vibration, the RTR 2758 performs well in ground, shipborne and airborne environments. Configurable with as many as 40 hot-swappable SSDs, the RTR 2758 can provide storage capacities of up to 19.2 TB in a rugged 4U chassis. Drives can be easily removed or exchanged during or after a mission to retrieve recorded data. The RTR 2758 is configured in a 4U 19" rack-mountable chassis, with hot-swap data drives, front panel USB ports and I/O connectors on the rear panel. Systems are scalable to accommodate multiple chassis to increase channel counts and aggregate data rates. All recorder chassis are connected via Ethernet and can be controlled from a single GUI either locally or from a remote PC. Multiple RAID levels, including 0, 1, 5, 6, 10 and 50, provide a choice for the required level of redundancy. Up to 40 hot-swappable SATA drives are optionally available, allowing up to 19.2 terabytes of real-time data storage space in a single 4U chassis.
SystemFlow Software
The RTR 2758 includes the SystemFlow Recording Software. SystemFlow features a Windows-based GUI (Graphical User Interface) that provides a simple means to configure and control the system. Custom configurations can be stored as profiles and later loaded when needed, allowing the user to select preconfigured settings with a single click. Built on a Windows 7 Professional workstation, the RTR 2758 allows the user to install post-processing and analysis tools to operate on the recorded data. The RTR 2758 records data to the native NTFS file system, providing immediate access to the recorded data.
Features
Designed to operate under conditions of shock and vibration Removable SSDs 32 bits of LVDS digital I/O LVDS clock, Data Valid and Data Suspend signals Supports clock rates up to 250 MHz Real-time aggregate recording rates up to 1 GB/sec Up to 19.2 terabytes storage to NTFS RAID disk array RAID levels of 0 ,1, 5 , 6, 10 and 50 Optional N+1 redundant power supply SystemFlow GUI virtual instrumentation panel for fast, intuitive operation C-callable API for integration of recorder into application File headers include time stamping and recording parameters Optional GPS time and position stamping Windows 7 Professional workstation with high-performance Intel CoreTM i7 processor
2 32-bit Data In Clock Data Valid Data Suspend 6 INTEL PROCESSOR
Gigabit Ethernet USB eSATA Keyboard
SYSTEM DRIVE
DDR SDRAM Mouse Video Output GPS Antenna (Optional)
DATA DRIVES
DATA DRIVES
DATA DRIVES
DATA DRIVES
UP TO 19.2 TB RAID
MODEL RTR 2758
Pentek, Inc.
www.pentek.com
Model RTR 2758

The RTR 2758 GUI provides the user with a control interface for the recording system. It includes Configuration, Record, Playback, and Status screens, each with intuitive controls and indicators. The user can easily move between screens to set configuration parameters, control and monitor a recording, and play back a recorded stream. All parameters contain limit-checking and integrated help to provide an easier-to-use out-of-the-box experience.

The RTR 2758 configuration screen shows a block diagram of the system, and provides control for operational system parameters. These parameters include data valid and suspend enables, as well as polarity control for both signals.

Pentek, Inc.
www.pentek.com
Model RTR 2758

SystemFlow API
SystemFlow includes a complete API (Application Programming Interface) that supports control and status queries of all operations of the RTR 2758 from a custom application. High-level C-language function calls and the supporting device drivers allow users to incorporate the RTR 2758 as a high-performance server front end to a larger system. This is supported using a socket interface through the Ethernet port, either to a local host or through an internet link for remote, stand-alone acquisition. Recorded NTFS files can be easily retrieved through the same connection.
LVDS Interface Cable: 80-pin ribbon cable Connector Type: 2x40 pin IDC Data Lines: 32 LVDS pairs, 2.5 V compliant Clock: One LVDS pair, 2.5 V compliant Data Valid: One LVDS pair, 2.5 V compliant Data Suspend: One LVDS pair, 2.5 V compliant Physical and Environmental Dimensions & Weights Dimensions: 19" W x 21" D x 7" (4U) H Weight: 50 lb, approx. Operating Temp: 0 to +50 C Storage Temp: 40 to +85 C Relative Humidity: 5 to 95%, non-condensing Operating Shock: 15 g max. (11 msec, half sine wave) Operating Vibration: 10 to 20 Hz: 0.02 inch peak, 20 to 500 Hz; 1.4 g peak acceleration
Specifications
PC Workstation Operating System: Windows 7 Professional Processor: Intel Core i7 processor Clock Speed: 3.0 GHz or higher SDRAM: 8 GB RAID Storage: 3.819.5 TB Drive Type: 2.5 SSD Number of Drives: up to 40 Supported Levels: 0, 1, 5, 6, 10 and 50
Model RTR 2758 Order Information

Storage Options
Interface Options
General Options
Option 243
Storage capacity: 7.6 TB 4U short chassis Storage capacity: 11.5 TB 4U short chassis Storage capacity: 19.2 TB Special chassis
Option 244
Option 245
Pentek, Inc.
www.pentek.com
! w e N
Model RTX 2786
Four-Channel RF/IF, 200 MS/sec Extreme 3U VPX Recorder

General Information
The Talon RTX 2786 is a turnkey, RF/IF signal recorder designed to operate under extreme environmental conditions. Housed in a ATR chassis, the RTX 2786 leverages Penteks 3U VPX SDR modules to provide a rugged recording system with up to four 16-bit, 200 MHz A/D converters with builtin digital downconversion capabilities. Optionally, the RTX 2786 provides one 800 MHz, 16-bit D/A converter with a digital upconverter for signal playback or waveform generation. As shown in the block diagram below, the maximum number of record channels with this option is three. The RTX2786 can record and play back analog signals with bandwidths ranging from a few kHz up to 80 MHz, either as baseband signals or as IF signals with center frequencies tunable across a 700 MHz range. The RTX 2786 uses conduction cooling to draw heat from the system components allowing it to operate in reduced air environments. It includes 1.92 TB of solid-state data storage, that allows it to operate with no degradation under conditions of extreme shock and vibration. The system is hermetically sealed and provides five D38999 connectors for power and I/O. Four SMA connectors are used for analog I/O. The recorder includes a graphical user interface for quick and simple out-of-thebox operation. It also includes a user API (Application Programming Interface) to easily integrate the system into the users application.
SystemFlow Software
The RTX 2786 includes Penteks SystemFlow Recording Software. SystemFlow features a Windows-based GUI (Graphical User Interface) that provides a simple means to configure and control the system. Custom configurations can be stored as profiles and later loaded when needed, allowing the user to select preconfigured settings with a single click. SystemFlow also includes signal viewing and analysis tools, that allow the user to monitor the signal prior to, during, and after a recording session. These tools include a virtual oscilloscope and a virtual spectrum analyzer. The user API allows users to integrate the recorder as a subsystem of a larger system. The API is provided as a C-callable library and allows for the recorder to be controlled over Ethernet, thus providing the ability to remotely control the recorder from a custom interface. Built on a Windows 7 Professional workstation, the RTX 2786 allows the user to install post-processing and analysis tools on the system itself to operate on the recorded data. The RTX 2786 records data to the Windows native NTFS file system, providing immediate access to all recorded data. Data can be off-loaded via dual gigabit Ethernet ports or four USB 2.0 ports. Four built-in solid-state drives provide reliable, high-speed storage with a total capacity of 1.92 TB.
Features
Multiband recording and playback system ATR 3U VPX chassis Designed to MIL-STD-704F, 810F and 461F Windows 7 Professional workstation with high performance Intel CoreTM i7 processor 200 MHz 16-bit A/Ds for recording up to four channels 800 MHz 16-bit D/A for playback of one channel 80 MHz max. record and playback signal bandwidths DDC decimation and DUC interpolation ranges from 2 to 65,536 Capable of record/playback of IF frequencies to 700 MHz Real-time sustained recording rates of up to 500 MB/sec 1.92 TB of storage to NTFS RAID disk array RAID levels of 0 ,1, 5 and 6 SystemFlow GUI with signal viewer analysis tool which includes a virtual oscilloscope and spectrum analyzer C-callable API for integration of recorder into application File headers include time stamping and recording parameters
CH 1 In CH 2 In CH 3 In
200 MHz 16-bit A/D 200 MHz 16-bit A/D 200 MHz 16-bit A/D
DIGITAL DOWNCONVERTER DIGITAL DOWNCONVERTER DIGITAL DOWNCONVERTER INTEL PROCESSOR
2 4
Gigabit Ethernet USB 2.0
SYSTEM DRIVE
DDR SDRAM Video Output
Out
800 MHz 16-bit D/A
DIGITAL UPCONVERTER
HOST PROCESSOR
Sample Clk / Reference In
DATA DRIVES CLOCK & SYNC GENERATOR PROGRAM VCXO
DATA DRIVES
DATA DRIVES
DATA DRIVES
MODEL 53621
RAID
MODEL RTX 2786

Three Record Channels and One Playback Channel.
Pentek, Inc.
www.pentek.com
Model RTX 2786

The RTX 2786 GUI provides the user with a control interface for the recording system. It includes Configuration, Record, Playback and Status screens, each with intuitive controls and indicators. The user can easily move between screens to set configuration parameters, control and monitor a recording, play back a recorded signal and monitor board temperature and voltage levels. The signal viewer, integrated into the recording GUI, allows the user to monitor real-time signals or signals recorded on disk.

The RTX 2786 configuration screens provide a simple and intuitive means for setting up the system parameters. The DDC configuration screen shown here, provides entries for input source, center frequency, decimation, as well as gate and trigger information. All parameters contain limitchecking and integrated help to provide an easier-to-use out-of-the-box experience.

Pentek, Inc.
www.pentek.com
Model RTX 2786

A/D Performance
Spurious Pick-up
D/A Performance
Pentek, Inc.
www.pentek.com
Model RTX 2786

Specifications

Digital Upconverter and D/As Type: TI DAC5688 and FPGA interpolation IP core Overall Interpolation: 2x to 524,288x in two stages of 2x to 256x and one stage of 2x, 4x, or 8x Output Bandwidth: 200 MHz maximum Output IF Center Frequency: Up to 400 MHz Output Sampling Rate: 800 MHz maximum Resolution: 16 bits Sample Clock Selections: On-board programmable VCXO External 10 MHz reference for phase-locking VCXO External direct sample clock External Clock Input Connector: Bulkhead female SMA connector Clock Input Type: 10 MHz reference to lock VCXO or direct input sample clock Clock Signal: Sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, 10 to 200 MHz Physical and Environmental Size: 7.1" W x 16.5" D x 8.1" H Weight: 40 lb Environmentals: MIL-STD-810F EMC: MIL-STD-461F - CE101, CE102, CS101, RE101, RE102, and RS101 Operating Temperature: 40O C to +55O C Cooling Options: Conduction, to cold plate Conduction, to forced air side wall heat exchangers, four variable-speed rear fans Power Requirements: 24 to 32 VDC, per MIL-STD-704F with 50 msec transient holdup
Ruggedized Computer Operating System: Windows 7 Professional Processor: Intel Core i7 processor SDRAM: 4 GB I/O Connections Connectors: D38999 circular Ethernet: Dual 1 GbE Serial: Dual RS-232/422/485 USB: Four USB 2.0 Video: Hi-Res VGA Audio: In/Out Stereo Switch: Reboot RAID Storage: 1.92 TB Storage Type: Internal SSDs Analog Recording Input / Output Analog Signal Inputs Input Type: Transformer-coupled Connectors: Bulkhead SMA female Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverter Type: Virtex-6 installed DDC IP Core Decimation: 2x to 65,536x in two stages of 2x to 256x Bandwidth: Up to 80 MHz Analog Signal Outputs Output Type: Transformer-coupled Connectors: Bulkhead SMA female Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz
Model RTX 2786 Options

Recording/Playback Options
Option 201 Option 202 Option 203 Option 204 One-channel recording and one-channel playback Two-channel recording and one-channel playback Three-channel recording and one channel playback Four-channel recording and no playback
Pentek, Inc.
www.pentek.com
CLOCK & SYNC GENERA TORS GENERATORS

MODEL
6890 6891 7190 7290, 7390 7690 7890 5390 7191 7291, 7391 7691 7891 5391 7192 7292, 7392, 7492 7892 5292 5692 7893 7194 7294, 7394, 7494 7894 5294 5694 9190 9192
DESCRIPTION
2.2 GHz Clock, Sync and Gate Distribution Board - VME System Synchronizer and Distribution Board - VME Multifrequency Clock Synthesizer - PMC Multifrequency Clock Synthesizers - 3U/6U cPCI Multifrequency Clock Synthesizers - PCI Multifrequency Clock Synthesizer - x8 PCIe Multifrequency Clock Synthesizer - 3U VPX Programmable Multifrequency Clock Synthesizer - PMC Programmable Multifrequency Clock Synthesizers - 3U/6U cPCI Programmable Multifrequency Clock Synthesizers - PCI Programmable Multifrequency Clock Synthesizer - x8 PCIe Programmable Multifrequency Clock Synthesizer - 3U VPX High-Speed Synchronizer and Distribution Board - PMC/XMC High-Speed Synchronizer and Distribution Board - 3U/6U cPCI High-Speed Synchronizer and Distribution Board - x8 PCIe High-Speed Synchronizer and Distribution Board - 3U VPX High-Speed Synchronizer and Distribution Board - AMC System Synchronizer and Distribution Board - PCIe High-Speed Clock Generator - PMC/XMC High-Speed Clock Generator - 3U/6U cPCI High-Speed Clock Generator - PCIe High-Speed Clock Generator - 3U VPX High-Speed Clock Generator - AMC Clock and Sync Generator for I/O Modules Rack-mount High-Speed System Synchronizer Unit Customer Information

www.pentek.com
Model 6890
2.2 GHz Clock, Sync and Gate Distribution Board - VME

General Information
Model 6890 Clock, Sync and Gate Distribution Board synchronizes multiple Pentek I/O boards within a system. It enables synchronous sampling and timing for a wide range of multichannel high-speed data acquisition, DSP and software radio applications. Up to eight boards can be synchronized using the 6890, each receiving a common clock of up to 2.2 GHz along with timing signals that can be used for synchronizing, triggering and gating functions.
Gate and Synchronization Signals

The 6890 features separate inputs for gate/trigger and sync signals with userselectable polarity. Each of these inputs can be TTL or LVPECL. Separate Gate Enable and Sync Enable MMCX inputs allow the user to enable or disable these circuits using an external signal. A programmable delay allows the user to make timing adjustments on the gate and sync signals before they are sent to an LVPECL buffer. A bank of eight MMCX connectors at the output of each buffer delivers signals to up to eight boards. A 2:1 multiplexer in each circuit allows the gate/trigger and sync signals to be registered with the input clock signal before output, if desired.
Input Signals
Model 6890 provides three front panel connectors to accept input signals. One SMA connector is provided for clock signal input, one MMCX connector accepts gate or trigger signals, and another MMCX connector is provided for synchronization. Two additional MMCX connectors are provided for Gate and Sync Enable. Clock signals are applied from an external source such as a high performance sine wave generator. Gate and sync signals can come from an external source, or from one supported board set to act as the master.
Accessories
Model 2890 provides various cable sets with options -002 through -008 supporting synchronization of two to eight boards. Options for individual cables are also available under Model 2890.
Supported Products
The 6890 currently supports Model 6826 Dual 2 GHz, 10-bit A/D Converter VME Board. Contact the factory for an up-to-date list of supported boards and modules.
Features

Clock Signals
The 6890 accepts clock input at +10 dBm to +14 dBm with a frequency range from 800 MHz to 2.2 GHz and uses a 1:2 power splitter to distribute the clock. The first output of this power splitter sends the clock signal to a 1:8 splitter for distribution to up to eight boards using SMA connectors. The second output of the 1:2 power splitter feeds a 1:2 buffer which distributes the clock signal to both the gate and synchronization circuits.
Synchronizes up to eight separate boards Synchronizes sampling and data acquisition for multichannel systems Synchronizes gating and triggering functions Clock rates from 800 MHz to 2.2 GHz Front panel SMA connectors for clock input and outputs Front panel MMCX connectors for gate/trigger and sync signal inputs and outputs Single-slot 6U VME board configuration
Physical Characteristics
Model 6890 is a standard 6U VMEbus board occupying a single VMEbus slot. Dimensions are 160 mm (6.3 inches) deep by 233.5 mm (9.2 inches) high. The board uses an EMC front panel as specified in IEEE 1101.10. Front panel width is 20.3 mm (0.8 inches).
F ont Panel Gate Enable F ont Panel Gate Input
TTL / PECL SELECTOR GATE CONTROL TTL / PECL SELECTOR PROG DELAY BUFFER 1:2 REG MUX 2:1 LVPECL BUFFER 18
Ch 1 Ch 2 Ch 3 Front Ch 4 Panel Ch 5 Gate Ch 6 Output Ch 7 Ch 8
Model 6890 Description 2.2 GHz Clock, Sync and Gate Distribution Board VME Accessories Model Description 2890-00x Set of Input and Output Cables for two (-002) to eight (-008) boards
Front Panel Clock Input
POWER SPL TTER 12
POWER SPL TTER BUFFER 1:2 1:8
Ch 1 Ch 2 Ch 3 Front Ch 4 Panel Ch 5 Clock Ch 6 Output Ch 7 Ch 8
F ont Panel Sync Enable F ont Panel Sync Input
TTL / PECL SELECTOR SYNC CONTROL TTL / PECL SELECTOR REG PROG DELAY BUFFER 1:2 MUX 2:1 LVPECL BUFFER 18
Ch 1 Ch 2 Ch 3 Front Ch 4 Panel Ch 5 Sync Ch 6 Output Ch 7 Ch 8
Pentek, Inc.
www.pentek.com
Model 6891
System Synchronizer and Distribution Board - VME

General Information
Model 6891 System Synchronizer and Distribution Board synchronizes multiple Pentek I/O modules within a system. It enables synchronous sampling and timing for a wide range of multichannel highspeed data acquisition, DSP and software radio applications. Up to eight modules can be synchronized using the 6891, each receiving a common clock up to 500 MHz along with timing signals that can be used for synchronizing, triggering and gating functions. For larger systems, up to eight 6891s can be linked together to provide synchronization for up to 64 I/O modules producing systems with up to 256 channels.
Clock Signals
The 6891 accepts clock input at +4 dBm to +14 dBm with a frequency range from 1 kHz to 800 MHz. This clock is used to register all sync and gate/trigger signals as well as providing a sample clock to all connected I/O modules.

The 6891 features separate inputs for gate/trigger and sync signals. Each of these inputs can be TTL or LVPECL. Separate Gate Enable and Sync Enable SMA inputs allow the user to enable or disable these circuits using an external signal. A programmable delay allows the user to make timing adjustments on the gate and sync signals before they are sent to an LVPECL buffer for output through the Sync Bus connectors.
Input Signals
Model 6891 provides three front panel SMA connectors to accept TTL input signals from external sources: one for clock, one for gate or trigger and one for a synchronization signal. Two additional SMA connectors are provided for separate gate and sync enable signals. Clock signals can be applied from an external source such as a high performance sine-wave generator. Gate/trigger and sync signals can come from an external system source. Alternately, a front panel 26-pin Sync Bus connector accepts LVPECL inputs from any compatible Pentek products to drive the clock, sync and gate/trigger signals.
Cables
Model 2891 provides various cable kits to support the 6891. Options are available for a range of cable lengths and synchronization of two to eight modules. Options for individual cables are also available under Model 2890.
Features

Synchronizes up to eight separate I/O modules Up to eight 6891s can be linked together to synchronize up to 64 I/O modules Synchronizes sampling and data acquisition for multichannel systems Synchronizes gating and triggering functions Clock rates up to 500 MHz Front panel SMA connectors for input signals Front panel 26-pin Sync Bus connectors compatible with a wide range of Pentek I/O modules Single-slot 6U VME board configuration
Supported Products
The 6891 currently supports all models in the 715x family. Contact the factory for an up-to-date list of supported modules.
Output Signals
The 6891 provides eight front panel Sync Bus output connectors, compatible with a wide range of Pentek I/O modules. The Sync Bus is distributed through ribbon cables, simplifying system design.
Model 6890 is a standard 6U VMEbus board occupying a single VMEbus slot.
Gate Clock Sync Gate

to Sync Bus Outputs 2-8
Sync Bus Output 1
F ont Panel Gate Enable F ont Panel GateInput

GATE CONTROL MUX 21 PROG DELAY BUFFER 12 REG MUX 21
GATE LVPECL BUFFER 18
Ch 1 Ch 2 Ch 3 Ch 4 Ch 5 Ch 6 Ch 7 Ch 8
Clock Sync Gate Clock Sync Gate Clock Sync
Sync Bus Output 2
Sync Bus Output 3
Model 6891 Description System Synchronizer and Distribution Board VME
F ont Panel Clock Input
MUX 21
CLOCK LVPECL BUFFER 1 10
Sync Bus Output 4
Gate Clock Sync Gate Sync Bus Output 5
F ont Panel Sync Enable Front Panel Sync Input

SYNC CONTROL MUX 21 PROG DELAY BUFFER 12
REG MUX 21 SYNC LVPECL BUFFER 18
Accessories 2891-xxx Set of Input and Output Cables
Clock Sync Gate

Sync Bus Output 6
Clock Sync Gate Clock Sync
Sync Bus Output 7
Gate Sync Bus Input Clock Sync
Sync Bus Output 8
Pentek, Inc.
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Model 7190
Multifrequency Clock Synthesizer - PMC

General Information
Model 7190 generates up to eight synthesized clock signals suitable for driving A/D and D/A converters in high-performance real-time data acquisition and software radio systems. The clocks offer exceptionally low phase noise and jitter to preserve the signal quality of the data converters. These clocks are synthesized from on-board quad VCXOs (voltage controlled oscillators) and can be phase-locked to an external reference signal. range of clock configurations is possible. In systems where more than five different clock outputs are required simultaneously, multiple 7190s can be used and phase-locked with a 5 to 100 MHz system reference.
PCI Interface
The Model 7190 uses an industry-standard 32-bit, 33/66 MHz PCI interface fully compatible with PCI bus specifications. The interface allows reading and writing of status and control signals for setup, operation and monitoring of the module.
Clock Synthesizer Circuits

The 7190 uses four Texas Instruments CDC7005 clock synthesizer and jitter cleaner devices. Each CDC7005 is paired with a dedicated VCXO to provide the base frequency for the clock synthesizer. Each of the four VCXOs can be independently programmed to generate one of four frequencies between 50 and 700 MHz. The CDC7005 can output the selected frequency of its associated VCXO, or generate submultiples using divisors of 2, 4, 8 or 16. The four CDC7005s can output up to five frequencies each. The 7190 can be programmed to route any of these 20 frequencies to the modules five output drivers. The CDC7005 includes phase-locking circuitry that locks the frequency of its associated VCXO to an input reference clock. This reference is a 5 to 100 MHz signal supplied to a front panel SMC connector. Eight front panel SMC connectors supply synthesized clock outputs driven from the five clock output drivers, as shown in the block diagram. This supports a single identical clock to all eight outputs or up to five different clocks to various outputs. With four independent quadVCXOs and each CDC7005 capable of providing up to five different submultiple clocks, a wide
Specifications
Front Panel Reference Input Connector Type: SMC Input Impedance: 50 ohms Reference Frequency: 5 to 100 MHz Input Level: 6 dBm to +10 dBm PLL Clock Synthesizers & Jitter Cleaners Quantity: Four Type: Texas Instruments CDC7005 Frequency Dividers: 1, 2, 4, 8 and 16 Quad VCXOs (Quantity: Four) Frequencies per VCXO: 4*, softwareprogrammable Frequency Range: 50 to 700 MHz Unlocked Accuracy: +20 ppm Front Panel Clock Outputs (Quantity: Eight) Connector Type: SMC Output Impedance: 50 ohms Output Level: +3 dBm @ 700 MHz Typ. Phase Noise: 105 dBc/Hz @ 1 kHz (dependent on reference source stability) PCI Interface PCI Bus: 32-bit, 66 MHz (supports 33 MHz) Operation: control and status interface Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard PMC module, 2.91 in. x 5.87 in.
1 2 4 8 16
Out In C R O S S B A R S W I T C H
Clock Out 1 Clock Out 2
Features

Simultaneous synthesis of up to five different clocks Eight SMC clock outputs Ideal for A/D and D/A converter clock sources Typical phase noise: 105 dBc/Hz @ 1 kHz offset All clocks are phase-locked to input reference signal Input reference frequency of 5 to 100 MHz Four quad VCXOs allow selection from 16 different base frequencies Output clocks of 1, 2, 4, 8, or 16 submultiples of VCXO base frequencies Output clock frequencies between 50 and 700 MHz Control and status via PCI bus interface
Reference In QUAD VCXO A
CLOCK SYNTHESIZER AND JITTER CLEANER A
Model 7190 Options Specify frequencies of four factory-installed quad VCXOs between 50 and 700 MHz * Contact Pentek to order specific frequencies Description Multifrequency Clock Synthesizer - PMC
QUAD VCXO B
CLOCK SYNTHESIZER AND JITTER CLEANER B
1 2 4 8 16 1 2 4 8 16
Out
In
Out
QUAD VCXO C
CLOCK SYNTHESIZER AND JITTER CLEANER C
In
Out
Clock Out 7
QUAD VCXO D
CLOCK SYNTHESIZER AND JITTER CLEANER D
1 2 4 8 16
In Out
Clock Out 8
Control
PCI INTERFACE
32
PCI BUS (32 Bits / 66 MHz)
Pentek, Inc.
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Models 7290, 7290D and 7390
Multifrequency Clock Synthesizers - 3U/6U cPCI

General Information
These Models generate up to eight synthesized clock signals suitable for driving A/D and D/A converters in high-performance real-time data acquisition and software radio systems. The clocks offer exceptionally low phase noise and jitter to preserve the signal quality of the data converters. These clocks are synthesized from on-board quad VCXOs (voltage controlled oscillators) and can be phase-locked to an external reference signal. Models 7290 and 7390 generate eight clocks while Model 7290D generates sixteen. wide range of clock configurations is possible. In systems where even more different clock outputs are required simultaneously, multiple boards can be used and phase-locked with a 5 to 100 MHz system reference.
PCI Interface
These Models use an industry-standard 32-bit, 33/66 MHz PCI interface fully compatible with PCI bus specifications. The interface allows reading and writing of status and control signals for setup, operation and monitoring of the board.

These Models use the Texas Instruments CDC7005 clock synthesizer and jitter cleaner devices. Each CDC7005 is paired with a dedicated VCXO to provide the base frequency for the clock synthesizer. Each quad VCXO can be independently programmed to generate one of four frequencies between 50 and 700 MHz. The CDC7005 can output the selected frequency of its associated VCXO, or generate submultiples using divisors of 2, 4, 8 or 16. The CDC7005s can output up to five frequencies each. These Models can be programmed to route any of these 20 frequencies to the boards five output drivers. The CDC7005 includes phase-locking circuitry that locks the frequency of its associated VCXO to an input reference clock. This reference is a 5 to 100 MHz signal supplied to a front panel SMC connector. Eight or 16 front panel SMC connectors supply synthesized clock outputs driven from the five clock output drivers, as shown in the block diagram. This supports a single identical clock to all outputs or up to five or ten different clocks to various outputs. With four or eight independent quad VCXOs and each CDC7005 capable of providing up to five different submultiple clocks, a
Specifications
Front Panel Reference Input Connector Type: SMC Input Impedance: 50 ohms Reference Frequency: 5 to 100 MHz Input Level: 6 dBm to +10 dBm PLL Clock Synthesizers & Jitter Cleaners Quantity: Four or eight Type: Texas Instruments CDC7005 Frequency Dividers: 1, 2, 4, 8 and 16 Quad VCXOs (Quantity: Four or eight) Frequencies per VCXO: 4*, softwareprogrammable Frequency Range: 50 to 700 MHz Unlocked Accuracy: +20 ppm Front Panel Clock Outputs (Quantity: 8 or 16) Connector Type: SMC Output Impedance: 50 ohms Output Level: +3 dBm @ 700 MHz Typ. Phase Noise: 105 dBc/Hz @ 1 kHz (dependent on reference source stability) PCI Interface PCI Bus: 32-bit, 66 MHz (supports 33 MHz) Operation: control and status interface Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 3U or 6U cPCI board
1 2 4 8 16
Model 7390
Model 7290D
Features

Simultaneous synthesis of up to five different clocks Eight or 16 SMC clock outputs Typical phase noise: 105 dBc/Hz @ 1 kHz offset All clocks are phase-locked to input reference signal Input reference frequency of 5 to 100 MHz Quad VCXOs allow selection from different base frequencies Output clocks of 1, 2, 4, 8, or 16 submultiples of VCXO base frequencies Output clock frequencies between 50 and 700 MHz Control and status via PCI bus interface
Model 7290 7290D 7390 Options Specify frequencies of four factory-installed quad VCXOs between 50 and 700 MHz * Contact Pentek to order specific frequencies Description Multifrequency Clock Synthesizer - 6U cPCI Dual Multifrequency Clock Synthesizer - 6U cPCI Multifrequency Clock Synthesizer - 3U cPCI
QUAD VCXO B
1 2 4 8 16 1 2 4 8 16
Out
In
Out
QUAD VCXO C
In
Out
Clock Out 7
QUAD VCXO D
1 2 4 8 16
In Out
Clock Out 8
Control
PCI INTERFACE
32
PCI-TO-PCI BRIDGE
Pentek, Inc.
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Model 7690
Multifrequency Clock Synthesizer - PCI

General Information
PCI Interface
The Model 7690 uses an industry-standard 32-bit, 33/66 MHz PCI interface fully compatible with PCI bus specifications. It attaches directly to computer motherboards with PCI bus slots. Front panel connectors are brought out on the rear panel.

The 7690 uses four Texas Instruments CDC7005 clock synthesizer and jitter cleaner devices. Each CDC7005 is paired with a dedicated VCXO to provide the base frequency for the clock synthesizer. Each of the four VCXOs can be independently programmed to generate one of four frequencies between 50 and 700 MHz. The CDC7005 can output the selected frequency of its associated VCXO, or generate submultiples using divisors of 2, 4, 8 or 16. The four CDC7005s can output up to five frequencies each. The 7690 can be programmed to route any of these 20 frequencies to the boards five output drivers. The CDC7005 includes phase-locking circuitry that locks the frequency of its associated VCXO to an input reference clock. This reference is a 5 to 100 MHz signal supplied to a front panel SMC connector. Eight front panel SMC connectors supply synthesized clock outputs driven from the five clock output drivers, as shown in the block diagram. This supports a single identical clock to all eight outputs or up to five different clocks to various outputs. With four independent quadVCXOs and each CDC7005 capable of providing up to five different submultiple clocks, a wide
Specifications
Front Panel Reference Input Connector Type: SMC Input Impedance: 50 ohms Reference Frequency: 5 to 100 MHz Input Level: 6 dBm to +10 dBm PLL Clock Synthesizers & Jitter Cleaners Quantity: Four Type: Texas Instruments CDC7005 Frequency Dividers: 1, 2, 4, 8 and 16 Quad VCXOs (Quantity: 4) Frequencies per VCXO: 4*, softwareprogrammable Frequency Range: 50 to 700 MHz Unlocked Accuracy: +20 ppm Front Panel Clock Outputs (Quantity: Eight) Connector Type: SMC Output Impedance: 50 ohms Output Level: +3 dBm @ 700 MHz Typ. Phase Noise: 105 dBc/Hz @ 1 kHz (dependent on reference source stability) PCI Interface PCI Bus: 32-bit, 66 MHz (supports 33 MHz) Operation: control and status interface Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard half-length PCI board
1 2 4 8 16
Features

Simultaneous synthesis of up to five different clocks Eight SMC clock outputs Ideal for A/D and D/A converter clock sources Typical phase noise: 105 dBc/Hz @ 1 kHz offset All clocks are phase-locked to input reference signal Input reference frequency of 5 to 100 MHz Four quad VCXOs allow selection from 16 different base frequencies Output clocks of 1, 2, 4, 8, or 16 submultiples of VCXO base frequencies Output clock frequencies between 50 and 700 MHz Control and status via PCI bus interface
Model 7690 Options Specify frequencies of four factory-installed quad VCXOs between 50 and 700 MHz * Contact Pentek to order specific frequencies Description Multifrequency Clock Synthesizer - PCI
QUAD VCXO B
1 2 4 8 16 1 2 4 8 16
Out
In
Out
QUAD VCXO C
In
Out
Clock Out 7
QUAD VCXO D
1 2 4 8 16
In Out
Clock Out 8
Control
PCI INTERFACE
32
PCI-TO-PCI BRIDGE
Pentek, Inc.
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Model 7890
Multifrequency Clock Synthesizer - x8 PCIe

General Information

The Model 7890 includes a multiple port, 48-lane Gen. 2 PCIe switch with integrated SerDes. The switch provides x8 wide connection to the PCIe interface.

The 7890 uses four Texas Instruments CDC7005 clock synthesizer and jitter cleaner devices. Each CDC7005 is paired with a dedicated VCXO to provide the base frequency for the clock synthesizer. Each of the four VCXOs can be independently programmed to generate one of four frequencies between 50 and 700 MHz. The CDC7005 can output the selected frequency of its associated VCXO, or generate submultiples using divisors of 2, 4, 8 or 16. The four CDC7005s can output up to five frequencies each. The 7890 can be programmed to route any of these 20 frequencies to the boards five output drivers. The CDC7005 includes phase-locking circuitry that locks the frequency of its associated VCXO to an input reference clock. This reference is a 5 to 100 MHz signal supplied to a front panel SMC connector. Eight front panel SMC connectors supply synthesized clock outputs driven from the five clock output drivers, as shown in the block diagram. This supports a single identical clock to all eight outputs or up to five different clocks to various outputs. With four independent quadVCXOs and each CDC7005 capable of providing up to five different submultiple clocks, a wide
Specifications
Front Panel Reference Input Connector Type: SMC Input Impedance: 50 ohms Reference Frequency: 5 to 100 MHz Input Level: 6 dBm to +10 dBm PLL Clock Synthesizers & Jitter Cleaners Quantity: Four Type: Texas Instruments CDC7005 Frequency Dividers: 1, 2, 4, 8 and 16 Quad VCXOs (Quantity: Four) Frequencies per VCXO: 4*, softwareprogrammable Frequency Range: 50 to 700 MHz Unlocked Accuracy: +20 ppm Front Panel Clock Outputs (Quantity: Eight) Connector Type: SMC Output Impedance: 50 ohms Output Level: +3 dBm @ 700 MHz Typ. Phase Noise: 105 dBc/Hz @ 1 kHz (dependent on reference source stability) PCI to PCIe Interface PCIe Interface: Gen. 2, x8 width PCIe Ports: one x4 port to PCI bus, one x8 port to PCIe motherboard Operation: control and status interface Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe, 4.38 in. x 6.6 in
1 2 4 8 16
Features

Simultaneous synthesis of up to five different clocks Eight SMC clock outputs Ideal for A/D and D/A converter clock sources Typical phase noise: 105 dBc/Hz @ 1 kHz offset All clocks are phase-locked to input reference signal Input reference frequency of 5 to 100 MHz Four quad VCXOs allow selection from 16 different base frequencies Output clocks of 1, 2, 4, 8, or 16 submultiples of VCXO base frequencies Output clock frequencies between 50 and 700 MHz Control and status via PCIe bus interface
Model 7890 Description Multifrequency Clock Synthesizer - Half-length x8 PCIe Specify frequencies of four factory-installed quad VCXOs between 50 and 700 MHz * Contact Pentek to order specific frequencies
QUAD VCXO B
1 2 4 8 16 1 2 4 8 16
Out
In
Out
Options
QUAD VCXO C
In
Out
Clock Out 7
QUAD VCXO D
1 2 4 8 16
In Out
Clock Out 8
Control
PCI INTERFACE
32
PCI TO PCIe BRIDGE
x4 PCIe
x8 PCI Express
Pentek, Inc.
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Model 5390
Multifrequency Clock Synthesizer - 3U VPX

General Information
Model 5390 generates up to eight synthesized clock signals suitable for driving A/D and D/A converters in high-performance real-time data acquisition and software radio systems. The clocks offer exceptionally low phase noise and jitter to preserve the signal quality of the data converters. These clocks are synthesized from on-board quad VCXOs (voltage controlled oscillators) and can be phase-locked to an external reference signal. five different submultiple clocks, a wide range of clock configurations is possible. In systems where more than five different clock outputs are required simultaneously, multiple 5390s can be used and phase-locked with a 5 to 100 MHz system reference.
PCI Express Switch

Model 5390 includes a PCIe Gen. 2 switch. The switch provides a total of 24 PCIe lanes to the Fabric-Transparent Crossbar Switch on 6 ports. Dynamic lane width negotiation within the PCIe switch allows for x1, x4, x8 or x16 widths.

The 5390 uses four Texas Instruments CDC7005 clock synthesizer and jitter cleaner devices. Each CDC7005 is paired with a dedicated VCXO to provide the base frequency for the clock synthesizer. Each of the four VCXOs can be independently programmed to generate one of four frequencies between 50 and 700 MHz. The CDC7005 can output the selected frequency of its associated VCXO, or generate submultiples using divisors of 2, 4, 8 or 16. The four CDC7005s can output up to five frequencies each. The 5390 can be programmed to route any of these 20 frequencies to the boards five output drivers. The CDC7005 includes phase-locking circuitry that locks the frequency of its associated VCXO to an input reference clock. This reference is a 5 to 100 MHz signal supplied to a front panel SMC connector. Eight front panel SMC connectors supply synthesized clock outputs driven from the five clock output drivers, as shown in the block diagram. This supports a single identical clock to all eight outputs or up to five different clocks to various outputs. With four independent quadVCXOs and each CDC7005 capable of providing up to
Specifications
Front Panel Reference Input Connector Type: SMC Input Impedance: 50 ohms Reference Frequency: 5 to 100 MHz Input Level: 6 dBm to +10 dBm PLL Clock Synthesizers & Jitter Cleaners Quantity: Four Type: Texas Instruments CDC7005 Frequency Dividers: 1, 2, 4, 8 and 16 Quad VCXOs (Quantity: Four) Frequencies per VCXO: 4*, softwareprogrammable Frequency Range: 50 to 700 MHz Unlocked Accuracy: +20 ppm Front Panel Clock Outputs (Quantity: Eight) Connector Type: SMC Output Impedance: 50 ohms Output Level: +3 dBm @ 700 MHz Typ. Phase Noise: 105 dBc/Hz @ 1 kHz (dependent on reference source stability) Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Features

Simultaneous synthesis of up to five different clocks Eight SMC clock outputs Ideal for A/D and D/A converter clock sources Typical phase noise: 105 dBc/Hz @ 1 kHz offset All clocks are phase-locked to input reference signal Input reference frequency of 5 to 100 MHz Four quad VCXOs allow selection from 16 different base frequencies Output clocks of 1, 2, 4, 8, or 16 submultiples of VCXO base frequencies Output clock frequencies between 50 and 700 MHz Control and status over the VPX backplane
Reference In
QUAD VCXO A
1 2 4 8 16
QUAD VCXO B
1 2 4 8 16 1 2 4 8 16
Out
In
Model 5390 Options Specify frequencies of four factory-installed quad VCXOs between 50 and 700 MHz * Contact Pentek to order specific frequencies Description Multifrequency Clock Synthesizer - 3U VPX
QUAD VCXO C
Out
In
Out
Clock Out 7
QUAD VCXO D
1 2 4 8 16
In Out
Clock Out 8 24
Control
PCI INTERFACE
32
PCI TO PCIe BRIDGE
x4 PCIe PCI EXPRESS SWITCH PEX 8648

24 lanes / 6 ports each conf gurab e as x1/x4/x8/x16
CROSSBAR SWITCH
VPX BACKPLANE
Pentek, Inc.
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Model 7191
Programmable Multifrequency Clock Synthesizer - PMC

General Information
Model 7191 generates up to eight synthesized clock signals suitable for driving A/D and D/A converters in high-performance real-time data acquisition and software radio systems. The clocks offer exceptionally low phase noise and jitter to preserve the signal quality of the data converters. These clocks are synthesized from on-board programmable VCXOs (voltage controlled oscillators) and can be phase-locked to an external reference signal. wide range of clock configurations is possible. In systems where more than five different clock outputs are required simultaneously, multiple 7191s can be used and phase-locked with a 5 to 100 MHz system reference.
PCI Interface
The Model 7191 uses an industry-standard 32-bit, 33/66 MHz PCI interface fully compatible with PCI bus specifications. The interface allows reading and writing of status and control signals for setup, operation and monitoring of the module.

The 7191 uses four Texas Instruments CDC7005 clock synthesizer and jitter cleaner devices. Each CDC7005 is paired with a dedicated VCXO to provide the base frequency for the clock synthesizer. Each of the four VCXOs can be independently programmed to a desired frequency between 50 and 700 MHz with 32-bit tuning resolution. The CDC7005 can output the programmed frequency of its associated VCXO, or generate submultiples using divisors of 2, 4, 8 or 16. The four CDC7005s can output up to five frequencies each. The 7191 can be programmed to route any of these 20 frequencies to the modules five output drivers. The CDC7005 includes phase-locking circuitry that locks the frequency of its associated VCXO to an input reference clock. This reference is a 5 to 100 MHz signal supplied to a front panel SMC connector. Eight front panel SMC connectors supply synthesized clock outputs driven from the five clock output drivers, as shown in the block diagram. This supports a single identical clock to all eight outputs or up to five different clocks to various outputs. With four independently programmable VCXOs and each CDC7005 capable of providing up to five different submultiple clocks, a
Reference In PROGRAM VCXO A
Specifications
Front Panel Reference Input Connector Type: SMC Input Impedance: 50 ohms Reference Frequency: 5 to 100 MHz Input Level: 6 dBm to +10 dBm PLL Clock Synthesizers & Jitter Cleaners Quantity: Four Type: Texas Instruments CDC7005 Frequency Dividers: 1, 2, 4, 8 and 16 Programmable VCXOs (Quantity: Four) Frequency Range: 50 to 700 MHz Tuning Resolution: 32 bits Unlocked Accuracy: +20 ppm Front Panel Clock Outputs (Quantity: Eight) Connector Type: SMC Output Impedance: 50 ohms Output Level: +3 dBm @ 700 MHz Typ. Phase Noise: 105 dBc/Hz @ 1 kHz (dependent on reference source stability) PCI Interface PCI Bus: 32-bit, 66 MHz (supports 33 MHz) Operation: control and status interface Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard PMC module, 2.91 in. x 5.87 in.
1 2 4 8 16
Features

Simultaneous synthesis of up to five different clocks Eight SMC clock outputs Ideal for A/D and D/A converter clock sources Typical phase noise: 105 dBc/Hz @ 1 kHz offset All clocks are phase-locked to input reference signal Input reference frequency of 5 to 100 MHz Four programmable VCXOs with 32-bit tuning resolution Output clocks of 1, 2, 4, 8, or 16 submultiples of VCXO base frequencies Output clock frequencies between 50 and 700 MHz Control and status via PCI bus interface
PROGRAM VCXO B
1 2 4 8 16 1 2 4 8 16
Out
In
Out
PROGRAM VCXO C
In
Out
Clock Out 7
Model 7191 Description Programmable Multifrequency Clock Synthesizer - PMC
PROGRAM VCXO D
1 2 4 8 16
In Out
Clock Out 8
Control
PCI INTERFACE
32
Pentek, Inc.
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Models 7291, 7291D and 7391
Programmable Multifrequency Clock Synthesizers - 3U/6U cPCI

General Information
These Models generate up to 16 synthesized clock signals suitable for driving A/D and D/A converters in high-performance real-time data acquisition and software radio systems. The clocks offer exceptionally low phase noise and jitter to preserve the signal quality of the data converters. Models 7291 and 7391 generate eight clocks while Model 7291D generates sixteen. wide range of clock configurations is possible. In systems where more than ten different clock outputs are required simultaneously, multiple 7291Ds can be used and phaselocked with a 5 to 100 MHz system reference.
PCI Interface
These Models use an industry-standard 32-bit, 33/66 MHz PCI interface fully compatible with PCI bus specifications. The interface allows reading and writing of status and control signals for setup, operation and monitoring of the board.

These Models use fthe Texas Instruments CDC7005 clock synthesizer and jitter cleaner devices. Each CDC7005 is paired with a dedicated VCXO (Voltage Controlled Crystal Oscillator) to provide the base frequency for the clock synthesizer. Each of the VCXOs can be independently programmed to a desired frequency between 50 and 700 MHz with 32-bit tuning resolution. The CDC7005 can output the programmed frequency of its associated VCXO, or generate submultiples using divisors of 2, 4, 8 or 16. The CDC7005s can output up to five frequencies each. These Models can be programmed to route any of these 20 or 40 frequencies to the boards output drivers. The CDC7005 includes phase-locking circuitry that locks the frequency of its associated VCXO to an input reference clock. This reference is a 5 to 100 MHz signal supplied to a front panel SMC connector. Eight or 16 front panel SMC connectors supply synthesized clock outputs driven from the five or ten clock output drivers, as shown in the block diagram. This supports a single identical clock to all outputs or up to 16 different clocks to various outputs. With independently programmable VCXOs and each CDC7005 capable of providing up to five different submultiple clocks, a
Specifications
Front Panel Reference Input Connector Type: SMC Input Impedance: 50 ohms Reference Frequency: 5 to 100 MHz Input Level: 6 dBm to +10 dBm PLL Clock Synthesizers & Jitter Cleaners Quantity: Four or eight Type: Texas Instruments CDC7005 Frequency Dividers: 1, 2, 4, 8 and 16 Programmable VCXOs (Quantity: 4 or 8) Frequency Range: 50 to 700 MHz Tuning Resolution: 32 bits Unlocked Accuracy: +20 ppm Front Panel Clock Outputs (Quantity: 8 or 16) Connector Type: SMC Output Impedance: 50 ohms Output Level: +3 dBm @ 700 MHz Typ. Phase Noise: 105 dBc/Hz @ 1 kHz (dependent on reference source stability) PCI Interface PCI Bus: 32-bit, 66 MHz (supports 33 MHz) Operation: control and status interface Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 3U or 6U cPCI board.
1 2 4 8 16
Model 7391
Model 7291D
Features

Simultaneous synthesis of five or ten different clocks Eight or 16 SMC clock outputs Ideal for A/D and D/A converter clock sources Typical phase noise: 105 dBc/Hz @ 1 kHz offset All clocks are phase-locked to input reference signal Input reference frequency of 5 to 100 MHz Four or eight programmable VCXOs with 32-bit tuning resolution Output clocks of 1, 2, 4, 8, or 16 submultiples of VCXO base frequencies Output clock frequencies between 50 and 700 MHz Control and status via PCI bus interface
Model 7291 Description Programmable Multifrequency Clock Synthesizer - 6U cPCI Dual Programmable Multifrequency Clock Synthesizer - 6U cPCI Programmable Multifrequency Clock Synthesizer - 3U cPCI
PROGRAM VCXO B
1 2 4 8 16 1 2 4 8 16
Out
In
Out
PROGRAM VCXO C
In
Out
Clock Out 7
7291D
PROGRAM VCXO D
1 2 4 8 16
In Out
Clock Out 8
7391
Control
PCI INTERFACE
32
PCI-TO-PCI BRIDGE
Pentek, Inc.
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Model 7691
Programmable Multifrequency Clock Synthesizer - PCI

General Information
PCI Interface
The Model 7691 uses an industry-standard 32-bit, 33/66 MHz PCI interface fully compatible with PCI bus specifications. The interface allows reading and writing of status and control signals for setup, operation and monitoring of the board.

The 7691 uses four Texas Instruments CDC7005 clock synthesizer and jitter cleaner devices. Each CDC7005 is paired with a dedicated VCXO to provide the base frequency for the clock synthesizer. Each of the four VCXOs can be independently programmed to a desired frequency between 50 and 700 MHz with 32-bit tuning resolution. The CDC7005 can output the programmed frequency of its associated VCXO, or generate submultiples using divisors of 2, 4, 8 or 16. The four CDC7005s can output up to five frequencies each. The 7691 can be programmed to route any of these 20 frequencies to the boards five output drivers. The CDC7005 includes phase-locking circuitry that locks the frequency of its associated VCXO to an input reference clock. This reference is a 5 to 100 MHz signal supplied to a front panel SMC connector. Eight front panel SMC connectors supply synthesized clock outputs driven from the five clock output drivers, as shown in the block diagram. This supports a single identical clock to all eight outputs or up to five different clocks to various outputs. With four independently programmable VCXOs and each CDC7005 capable of providing up to five different submultiple clocks, a
Specifications
Front Panel Reference Input Connector Type: SMC Input Impedance: 50 ohms Reference Frequency: 5 to 100 MHz Input Level: 6 dBm to +10 dBm PLL Clock Synthesizers & Jitter Cleaners Quantity: Four Type: Texas Instruments CDC7005 Frequency Dividers: 1, 2, 4, 8 and 16 Programmable VCXOs (Quantity: Four) Frequency Range: 50 to 700 MHz Tuning Resolution: 32 bits Unlocked Accuracy: +20 ppm Front Panel Clock Outputs (Quantity: Eight) Connector Type: SMC Output Impedance: 50 ohms Output Level: +3 dBm @ 700 MHz Typ. Phase Noise: 105 dBc/Hz @ 1 kHz (dependent on reference source stability) PCI Interface PCI Bus: 32-bit, 66 MHz (supports 33 MHz) Operation: control and status interface Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard half-length PCI board
1 2 4 8 16
Features

Simultaneous synthesis of up to five different clocks Eight SMC clock outputs Ideal for A/D and D/A converter clock sources Typical phase noise: 105 dBc/Hz @ 1 kHz offset All clocks are phase-locked to input reference signal Input reference frequency of 5 to 100 MHz Four programmable VCXOs with 32-bit tuning resolution Output clocks of 1, 2, 4, 8, or 16 submultiples of VCXO base frequencies Output clock frequencies between 50 and 700 MHz Control and status via PCI bus interface
PROGRAM VCXO B
1 2 4 8 16 1 2 4 8 16
Out
In
Out
PROGRAM VCXO C
In
Out
Clock Out 7
Model 7691 Description Programmable Multifrequency Clock Synthesizer - PCI
PROGRAM VCXO D
1 2 4 8 16
In Out
Clock Out 8
Control
PCI INTERFACE
32
PCI-TO-PCI BRIDGE
Pentek, Inc.
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Model 7891
Programmable Mulrifrequency Clock Synthesizer - x8 PCIe

General Information

The Model 7891 includes a multiple port, 48-lane Gen. 2 PCIe switch with integrated SerDes. The switch provides x8 wide connection to the PCIe interface.

The 7891 uses four Texas Instruments CDC7005 clock synthesizer and jitter cleaner devices. Each CDC7005 is paired with a dedicated VCXO to provide the base frequency for the clock synthesizer. Each of the four VCXOs can be independently programmed to a desired frequency between 50 and 700 MHz with 32-bit tuning resolution. The CDC7005 can output the programmed frequency of its associated VCXO, or generate submultiples using divisors of 2, 4, 8 or 16. The four CDC7005s can output up to five frequencies each. The 7891 can be programmed to route any of these 20 frequencies to the boards five output drivers. The CDC7005 includes phase-locking circuitry that locks the frequency of its associated VCXO to an input reference clock. This reference is a 5 to 100 MHz signal supplied to a front panel SMC connector. Eight front panel SMC connectors supply synthesized clock outputs driven from the five clock output drivers, as shown in the block diagram. This supports a single identical clock to all eight outputs or up to five different clocks to various outputs. With four independently programmable VCXOs and each CDC7005 capable of providing up to five different submultiple clocks, a
Specifications
Front Panel Reference Input Connector Type: SMC Input Impedance: 50 ohms Reference Frequency: 5 to 100 MHz Input Level: 6 dBm to +10 dBm PLL Clock Synthesizers & Jitter Cleaners Quantity: Four Type: Texas Instruments CDC7005 Frequency Dividers: 1, 2, 4, 8 and 16 Programmable VCXOs (Quantity: Four) Frequency Range: 50 to 700 MHz Tuning Resolution: 32 bits Unlocked Accuracy: +20 ppm Front Panel Clock Outputs (Quantity: Eight) Connector Type: SMC Output Impedance: 50 ohms Output Level: +3 dBm @ 700 MHz Typ. Phase Noise: 105 dBc/Hz @ 1 kHz (dependent on reference source stability) PCI to PCIe Interface PCIe Interface: Gen. 2, x8 width PCIe Ports: one x4 port to PCI bus, one x8 port to PCIe motherboard Operation: control and status interface Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe, 4.38 in. x 6.6 in.
1 2 4 8 16
Features

Simultaneous synthesis of up to five different clocks Eight SMC clock outputs Ideal for A/D and D/A converter clock sources Typical phase noise: 105 dBc/Hz @ 1 kHz offset All clocks are phase-locked to input reference signal Input reference frequency of 5 to 100 MHz Four programmable VCXOs with 32-bit tuning resolution Output clocks of 1, 2, 4, 8, or 16 submultiples of VCXO base frequencies Output clock frequencies between 50 and 700 MHz Control and status via PCIe bus interface
PROGRAM VCXO B
1 2 4 8 16 1 2 4 8 16
Out
In
Out
PROGRAM VCXO C
In
Out
Clock Out 7
Model 7891 Description Programmable Multifrequency Clock Synthesizer - Half-length x8 PCIe
PROGRAM VCXO D
1 2 4 8 16
In Out
Clock Out 8
Control
PCI INTERFACE
32
PCI TO PCIe BRIDGE
x4 PCIe
x8 PCI Express
Pentek, Inc.
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Model 5391
Programmable Multifrequency Clock Synthesizer - 3U VPX

General Information
Model 5391 generates up to eight synthesized clock signals suitable for driving A/D and D/A converters in high-performance real-time data acquisition and software radio systems. The clocks offer exceptionally low phase noise and jitter to preserve the signal quality of the data converters. These clocks are synthesized from on-board programmable VCXOs (voltage controlled oscillators) and can be phase-locked to an external reference signal. ing up to five different submultiple clocks, a wide range of clock configurations is possible. In systems where more than five different clock outputs are required simultaneously, multiple 5391s can be used and phase-locked with a 5 to 100 MHz system reference.


The 5391 uses four Texas Instruments CDC7005 clock synthesizer and jitter cleaner devices. Each CDC7005 is paired with a dedicated VCXO to provide the base frequency for the clock synthesizer. Each of the four VCXOs can be independently programmed to a desired frequency between 50 and 700 MHz with 32-bit tuning resolution. The CDC7005 can output the programmed frequency of its associated VCXO, or generate submultiples using divisors of 2, 4, 8 or 16. The four CDC7005s can output up to five frequencies each. The 5391 can be programmed to route any of these 20 frequencies to the boards five output drivers. The CDC7005 includes phase-locking circuitry that locks the frequency of its associated VCXO to an input reference clock. This reference is a 5 to 100 MHz signal supplied to a front panel SMC connector. Eight front panel SMC connectors supply synthesized clock outputs driven from the five clock output drivers, as shown in the block diagram. This supports a single identical clock to all eight outputs or up to five different clocks to various outputs. With four independently programmable VCXOs and each CDC7005 capable of providCLOCK SYNTHESIZER AND JITTER CLEANER A
Specifications
Front Panel Reference Input Connector Type: SMC Input Impedance: 50 ohms Reference Frequency: 5 to 100 MHz Input Level: 6 dBm to +10 dBm PLL Clock Synthesizers & Jitter Cleaners Quantity: Four Type: Texas Instruments CDC7005 Frequency Dividers: 1, 2, 4, 8 and 16 Programmable VCXOs (Quantity: Four) Frequency Range: 50 to 700 MHz Tuning Resolution: 32 bits Unlocked Accuracy: +20 ppm Front Panel Clock Outputs (Quantity: Eight) Connector Type: SMC Output Impedance: 50 ohms Output Level: +3 dBm @ 700 MHz Typ. Phase Noise: 105 dBc/Hz @ 1 kHz (dependent on reference source stability) Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Features

Simultaneous synthesis of up to five different clocks Eight SMC clock outputs Ideal for A/D and D/A converter clock sources Typical phase noise: 105 dBc/Hz @ 1 kHz offset All clocks are phase-locked to input reference signal Input reference frequency of 5 to100 MHz Four progammable VCXOs with 32-bit tuning resolution Output clocks of 1, 2, 4, 8, or 16 submultiples of VCXO base frequencies Output clock frequencies between 50 and 700 MHz Control and status over the VPX backplane
Reference In
PROGRAM VCXO A
1 2 4 8 16
PROGRAM VCXO B
1 2 4 8 16 1 2 4 8 16
Out
In
Out
PROGRAM VCXO C
In
Out
Clock Out 7
PROGRAM VCXO D
1 2 4 8 16
In Out
Clock Out 8 24
Model 5391 Description Programmable Multifrequency Clock Synthesizer - 3U VPX
Control
PCI INTERFACE
32
PCI TO PCIe BRIDGE
x4 PCIe PCI EXPRESS SWITCH PEX 8648

CROSSBAR SWITCH
VPX BACKPLANE
Pentek, Inc.
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Model 7192
High-Speed Synchronizer and Distribution Board - PMC/XMC

General Information
The Model 7192 High-Speed Synchronizer and Distribution Board synchronizes multiple Pentek Cobalt or Onyx modules within a system. It enables synchronous sampling and timing for a wide range of multichannel high-speed data acquisition, DSP, and software radio applications. Up to four modules can be synchronized using the 7192, with each receiving a common clock along with timing signals that can be used for synchronizing, triggering and gating functions. Onyx modules. The Sync signals include a reference clock, gate/trigger and sync signals and are distributed through matched cables, simplifying system design.
Clock Signals
The 7192 can accept a user supplied external clock on its front panel MMCX connector. As an alternative to the external clock, the 7192 can use its on-board programmable voltage controlled crystal oscillator (VCXO) as the clock source. The VCXO can operate alone or be locked to a system reference clock signal delivered to the front panel reference clock input. The external or on-board clock can operate at full rate or be divided and is used to register all sync and gate/trigger signals as well as providing a reference clock to all connected modules. In addition, the clock is available at the Clock Out MMCX as a sample or reference clock for other boards in the system.
Input Signals
Model 7192 provides three front panel MMCX connectors to accept input signals from external sources: one for clock, one for gate or trigger and one for a synchronization signal. Clock signals can be applied from an external source such as a high performance sine-wave generator. Gate/trigger and sync signals can come from an external system source. In addition to the MMCX connector, a reference clock can be accepted through the first front panel Sync output connector, allowing a single Cobalt or Onyx board to generate the clock for all subsequent boards in the system.

The 7192 features separate inputs for gate/trigger and sync signals. A programmable delay allows the user to make timing adjustments on the gate/trigger and sync signals before they are sent to buffers for output through the Sync output connectors.
Features
Output Signals
The 7192 provides four front panel Sync output connectors, compatible with a range of high-speed Pentek Cobalt and
Synchronizes up to four separate high-speed Cobalt or Onyx I/O modules Synchronizes sampling and data acquisition for multichannel systems Synchronizes gating and triggering functions Clock rates up to 1.8 GHz Front panel MMCX connectors for input signals Front panel Sync connectors compatible with a range of Pentek Cobalt and Onyx modules
PROGRAMMABLE VCXO Sample Clk / Reference Clk In
MUX
Clk In
PLL :N & DIVIDER :N
Clock / Calibration Out
Ref In
mSync 1 Reference Clk In * TWSI Control In

TWSI CONTROL Gate / Trigger Out Sync Out Reference Clk Out
mSync 2
Gate / Trigger Out Sync Out Reference Clk Out BUFFER & PROGRAM DELAYS
MUX Gate / Trigger In Sync In
Clk/ Ref In Trig/ Gate In Sync In
mSync 3
Gate / Trigger Out Sync Out Reference Clk Out
mSync 4
* For 71640 A/D calibration
Pentek, Inc.
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Model 7192
High-Speed Synchronizer and Distribution Board - PMC/XMC

Calibration
The 7192 features a calibration output specifically designed to work with the 71640 or 71740 3.6 GHz A/D module and provide a signal reference for phase adjustment across multiple D/As.
Specifications
Front Panel Sample Clock/Reference Input Connector Type: MMCX Input Impedance: 50 ohms Input Level: 0 dBm to +10 dBm, sine wave Sample Clock Frequency: 100 MHz to 2 GHz Reference Frequency: 5 to 100 MHz Front Panel Gate/Trigger & Sync Inputs Connector Type: MMCX Input Level: LVTTL Front Panel Sync Inputs/Outputs Quantity: 4 Connector Type: 19-pin HDMI Signal Level: CML Signals (Sync connector 1): Reference Clock In, TWSI control In, Reference Clock Out, Gate/Trigger Out, Sync Out Signals (Sync connectors 24): Reference Clock Out, Gate/Trigger Out, Sync Out Front Panel Clock / Calibration Output Connector Type: MMCX Output Impedance: 50 ohms Output Level: +6 dBm nominal, sine wave Sample Clock Frequency: 100 MHz to 1.8 GHz Programmable VCXO: Frequency Ranges: 10-945 MHz, 970-1134 MHz, and 1213-1417.5 MHz Tuning Resolution: 32 bits Unlocked Accuracy: +20 ppm PLL, Divider & Jitter Cleaner Type: Texas Instruments CDCM7005 Frequency Dividers: 1, 2, 3, 4, 6, 8 and 16 PMC/XMC Interface: Power only on PMC P1 or XMC P15 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard PMC module, 2.91 in. x 5.87 in.
Programming
The 7192 allows programming of operating parameters including: VCXO frequency, clock dividers, and delays that allow the user to make timing adjustments on the gate and sync signals. These adjustments are made before they are sent to buffers for output through the Sync connectors. The 7192 is programmed via a TWSI control interface on the first Sync connector. The control interface is compatible with the front panel Sync connectors of all highspeed Cobalt and Onyx modules, thereby providing a single cable connection that carries both control and timing signals.
Supported Products
The 7192 supports all high-speed models in the Cobalt family including the 71630 1 GHz A/D and D/A XMC, the 71640 3.6 GHz A/D XMC and the 71670 Fourchannel 1.25 GHz, 16-bit D/A XMC. The 7192 will also support high-speed models in the Onyx family as they become available.
Model 7192 Description High-Speed Synchronizer and Distribution Board PMC/XMC
Accessories 4 ea. 18 Sync cables are supplied; additional cables may be ordered: 2192-018 Sync cable - 18 2192-036 Sync cable - 36
Pentek, Inc.
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Models 7292, 7492 and 7392
High-Speed Synchronizer and Distribution Board - 3U/6U cPCI

General Information
These High-Speed Synchronizer and Distribution cPCI Boards synchronize multiple Pentek Cobalt or Onyx boards within a system. Thsy enable synchronous sampling and timing for a wide range of multichannel high-speed data acquisition, DSP, and software radio applications. Up to eight boards can be synchronized using the 7492, with each receiving a common clock along with timing signals that can be used for synchronizing, triggering and gating functions. with a range of high-speed Pentek Cobalt and Onyx boards. The Sync signals include reference clocks, gate/triggers and sync signals and are distributed through matched cables, simplifying system design.
Clock Signals
These modles can accept one or two user supplied external clocks on front panel MMCX connectors. As an alternative to the external clock, they can use on-board programmable voltage controlled crystal oscillators(VCXOs) as the clock sources. The VCXOs can operate alone or be locked to a system reference clock signal delivered to the front panel reference clock inputs. The external or on-board clocks can operate at full rate or be divided and is used to register all sync and gate/trigger signals as well as providing reference clocks to all connected boards. In addition, the clocks are available at the Clock Out MMCX as sample or reference clocks for other boards in the system.
Input Signals
These models provide three or six front panel MMCX connectors to accept input signals from external sources: one or two for clock, one or two for gate or trigger and one or two for synchronization signals. Clock signals can be applied from an external source such as a high performance sine-wave generator. Gate/trigger and sync signals can come from an external system source. In addition to the MMCX connector, a reference clock can be accepted through the front panel Sync output connectors, allowing a single Cobalt or Onyx board to generate the clock for all subsequent boards in the system.
Model 7392
Model 7492

These models feature separate inputs for gate/trigger and sync signals. Programmable delays allow the user to make timing adjustments on the gate/trigger and sync signals before they are sent to buffers for output through the Sync output connectors.
Features
Output Signals
These models provide up to eight front panel Sync output connectors, compatible
Synchronizes four or eight separate high-speed Cobalt or Onyx I/O boards Synchronizes sampling and data acquisition for multichannel systems Synchronizes gating and triggering functions Clock rates up to 1.8 GHz Front panel MMCX connectors for input signals Front panel Sync connectors compatible with a range of Pentek Cobalt and Onyx boards
MUX
Clk In
PLL :N & DIVIDER :N
Ref In

mSync 2
mSync 3
mSync 4
Models 7392 and 7192 Block Diagram. Model 7492 Doubles all Resources. Pentek, Inc.
www.pentek.com
Models 7292, 7492 and 7392
High-Speed Synchronizer and Distribution Board - 3U/6U cPCI

Calibration
These models feature a calibration output specifically designed to work with the 72640, 74640 and 73640 or 72740, 74740 and 73740 3.6 GHz A/D board and provide a signal reference for phase adjustment across multiple D/As.
Specifications
Front Panel Sample Clock/Reference Input Connector Type: MMCX Input Impedance: 50 ohms Input Level: 0 dBm to +10 dBm, sine wave Sample Clock Frequency: 100 MHz to 2 GHz Reference Frequency: 5 to 100 MHz Front Panel Gate/Trigger & Sync Inputs Connector Type: MMCX Input Level: LVTTL Front Panel Sync Inputs/Outputs Quantity: 4 or 8 Connector Type: 19-pin HDMI Signal Level: CML Signals (Sync connector 1): Reference Clock In, TWSI control In, Reference Clock Out, Gate/Trigger Out, Sync Out Signals (Sync connectors 24): Reference Clock Out, Gate/Trigger Out, Sync Out Front Panel Clock / Calibration Output Connector Type: MMCX Output Impedance: 50 ohms Output Level: +6 dBm nominal, sine wave Sample Clock Frequency: 100 MHz to 1.8 GHz Programmable VCXOs: Frequency Ranges: 10-945 MHz, 970-1134 MHz, and 1213-1417.5 MHz Tuning Resolution: 32 bits Unlocked Accuracy: +20 ppm PLL, Divider & Jitter Cleaner Type: Texas Instruments CDCM7005 Frequency Dividers: 1, 2, 3, 4, 6, 8 and 16 PCI Interface PCI Bus: 32-bit, 66 MHz (supports 33 MHz), power only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 3U or 6U cPCI board
Programming
These models allow programming of operating parameters including: VCXO frequency, clock dividers, and delays that allow the user to make timing adjustments on the gate and sync signals. These adjustments are made before they are sent to buffers for output through the Sync connectors. These models are programmed via a TWSI control interface on the first Sync connector. The control interface is compatible with the front panel Sync connectors of all high-speed Cobalt and Onyx boards, thereby providing a single cable connection that carries both control and timing signals.
Supported Products
These models support all high-speed models in the Cobalt family including the 72630, 74630 and 73630 1 GHz A/D and D/A cPCI boards; the 72640, 74640 and 73640 3.6 GHz A/D cPCI boards; and the 72670, 74670 and 73670 Four-channel 1.25 GHz, 16-bit D/A cPCI boards. They will also support high-speed models in the Onyx family as they become available.
Model 7292 Description High-Speed Synchronizer and Distribution Board 6U cPCI 7492 High-Speed Synchronizer and Distribution Board 6U cPCI 7392 High-Speed Synchronizer and Distribution Board 3U cPCI Accessories 4 ea. 18 Sync cables are supplied with Models 7292 and 7392; 8 ea. 18 Sync cables are supplied with Model 7492; additional cables may be ordered: 2192-018 Sync cable - 18 2192-036 Sync cable - 36
Pentek, Inc.
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Model 7892
High-Speed Synchronizer and Distribution Board - PCIe

General Information
The Model 7892 High-Speed Synchronizer and Distribution PCIe Board synchronizes multiple Pentek Cobalt or Onyx boards within a system. It enables synchronous sampling and timing for a wide range of multichannel high-speed data acquisition, DSP, and software radio applications. Up to four boards can be synchronized using the 7892, with each receiving a common clock along with timing signals that can be used for synchronizing, triggering and gating functions. Onyx boards. The Sync signals include a reference clock, gate/trigger and sync signals and are distributed through matched cables, simplifying system design.
Clock Signals
The 7892 can accept a user supplied external clock on its front panel MMCX connector. As an alternative to the external clock, the 7892 can use its on-board programmable voltage controlled crystal oscillator (VCXO) as the clock source. The VCXO can operate alone or be locked to a system reference clock signal delivered to the front panel reference clock input. The external or on-board clock can operate at full rate or be divided and is used to register all sync and gate/trigger signals as well as providing a reference clock to all connected boards. In addition, the clock is available at the Clock Out MMCX as a sample or reference clock for other boards in the system.
Input Signals

Features
Output Signals
Synchronizes up to four separate high-speed Cobalt or Onyx I/O boards Synchronizes sampling and data acquisition for multichannel systems Synchronizes gating and triggering functions Clock rates up to 1.8 GHz Front panel MMCX connectors for input signals Front panel Sync connectors compatible with a range of Pentek Cobalt and Onyx boards
MUX
Clk In
PLL :N & DIVIDER :N
Ref In

mSync 2
mSync 3
mSync 4
Pentek, Inc.
www.pentek.com
Model 7892
High-Speed Synchronizer and Distribution Board - PCIe

Calibration
The 7892 features a calibration output specifically designed to work with the 78640 or 78740 3.6 GHz A/D board and provide a signal reference for phase adjustment across multiple D/As.
Specifications
Front Panel Sample Clock/Reference Input Connector Type: MMCX Input Impedance: 50 ohms Input Level: 0 dBm to +10 dBm, sine wave Sample Clock Frequency: 100 MHz to 2 GHz Reference Frequency: 5 to 100 MHz Front Panel Gate/Trigger & Sync Inputs Connector Type: MMCX Input Level: LVTTL Front Panel Sync Inputs/Outputs Quantity: 4 Connector Type: 19-pin HDMI Signal Level: CML Signals (Sync connector 1): Reference Clock In, TWSI control In, Reference Clock Out, Gate/Trigger Out, Sync Out Signals (Sync connectors 24): Reference Clock Out, Gate/Trigger Out, Sync Out Front Panel Clock / Calibration Output Connector Type: MMCX Output Impedance: 50 ohms Output Level: +6 dBm nominal, sine wave Sample Clock Frequency: 100 MHz to 1.8 GHz Programmable VCXO: Frequency Ranges: 10-945 MHz, 970-1134 MHz, and 1213-1417.5 MHz Tuning Resolution: 32 bits Unlocked Accuracy: +20 ppm PLL, Divider & Jitter Cleaner Type: Texas Instruments CDCM7005 Frequency Dividers: 1, 2, 3, 4, 6, 8 and 16 PCI Express Interface PCIe Bus: x4 or x8, power only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.
Programming
The 7892 allows programming of operating parameters including: VCXO frequency, clock dividers, and delays that allow the user to make timing adjustments on the gate and sync signals. These adjustments are made before they are sent to buffers for output through the Sync connectors. The 7892 is programmed via a TWSI control interface on the first Sync connector. The control interface is compatible with the front panel Sync connectors of all highspeed Cobalt and Onyx boards, thereby providing a single cable connection that carries both control and timing signals.
Supported Products
The 7892 supports all high-speed models in the Cobalt family including the 78630 1 GHz A/D and D/A x8 PCIe, the 78640 3.6 GHz A/D x8 PCIe and the 78670 Fourchannel 1.25 GHz, 16-bit D/A x8 PCIe. The 7892 will also support high-speed models in the Onyx family as they become available.
Model 7892 Description High-Speed Synchronizer and Distribution Board PCIe Accessories 4 ea. 18 Sync cables are supplied; additional cables may be ordered: 2192-018 Sync cable - 18 2192-036 Sync cable - 36
Pentek, Inc.
www.pentek.com
! ew N
Model 5292
High-Speed Synchronizer and Distribution Board - 3U VPX

General Information
The Model 5292 High-Speed Synchronizer and Distribution 3U VPX Board synchronizes multiple Pentek Cobalt or Onyx boards within a system. It enables synchronous sampling and timing for a wide range of multichannel high-speed data acquisition, DSP, and software radio applications. Up to four boards can be synchronized using the 5292, with each receiving a common clock along with timing signals that can be used for synchronizing, triggering and gating functions. Onyx boards. The Sync signals include a reference clock, gate/trigger and sync signals and are distributed through matched cables, simplifying system design.
Clock Signals
The 5292 can accept a user supplied external clock on its front panel MMCX connector. As an alternative to the external clock, the 5292 can use its on-board programmable voltage-controlled crystal oscillator (VCXO) as the clock source. The VCXO can operate alone or be locked to a system reference clock signal delivered to the front panel reference clock input. The external or on-board clock can operate at full rate or be divided and is used to register all sync and gate/trigger signals as well as providing a reference clock to all connected boards. In addition, the clock is available at the Clock Out MMCX as a sample or reference clock for other boards in the system.
Input Signals

Features
Output Signals
Synchronizes up to four separate high-speed Cobalt or Onyx I/O boards Synchronizes sampling and data acquisition for multichannel systems Synchronizes gating and triggering functions Clock rates up to 1.8 GHz Front panel MMCX connectors for input signals Front panel Sync connectors compatible with a range of Pentek Cobalt and Onyx boards
MUX
Clk In
PLL :N & DIVIDER :N
Ref In

mSync 2
mSync 3
mSync 4
Pentek, Inc.
www.pentek.com
Model 5292
High-Speed Synchronizer and Distribution Board - 3U VPX

Calibration
The 5292 features a calibration output specifically designed to work with the 52640 or 52740 3.6 GHz A/D board and provide a signal reference for phase adjustment across multiple D/As.
Specifications
Front Panel Sample Clock/Reference Input Connector Type: MMCX Input Impedance: 50 ohms Input Level: 0 dBm to +10 dBm, sine wave Sample Clock Frequency: 100 MHz to 2 GHz Reference Frequency: 5 to 100 MHz Front Panel Gate/Trigger & Sync Inputs Connector Type: MMCX Input Level: LVTTL Front Panel Sync Inputs/Outputs Quantity: 4 Connector Type: 19-pin HDMI Signal Level: CML Signals (Sync connector 1): Reference Clock In, TWSI control In, Reference Clock Out, Gate/Trigger Out, Sync Out Signals (Sync connectors 24): Reference Clock Out, Gate/Trigger Out, Sync Out Front Panel Clock / Calibration Output Connector Type: MMCX Output Impedance: 50 ohms Output Level: +6 dBm nominal, sine wave Sample Clock Frequency: 100 MHz to 1.8 GHz Programmable VCXO: Frequency Ranges: 10-945 MHz, 970-1134 MHz, and 1213-1417.5 MHz Tuning Resolution: 32 bits Unlocked Accuracy: +20 ppm PLL, Divider & Jitter Cleaner Type: Texas Instruments CDCM7005 Frequency Dividers: 1, 2, 3, 4, 6, 8 and 16 PCI Express Interface PCIe Bus: x4, power only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Programming
The 5292 allows programming of operating parameters including: VCXO frequency, clock dividers, and delays that allow the user to make timing adjustments on the gate and sync signals. These adjustments are made before they are sent to buffers for output through the Sync connectors. The 5292 is programmed via a TWSI control interface on the first Sync connector. The control interface is compatible with the front panel Sync connectors of all highspeed Cobalt and Onyx boards, thereby providing a single cable connection that carries both control and timing signals.
Supported Products
The 5292 supports all high-speed models in the Cobalt family including the 52630 1 GHz A/D and D/A 3U VPX, the 52640 3.6 GHz A/D x3U VPX and the 52670 Fourchannel 1.25 GHz, 16-bit D/A 3U VPX. The 5292 will also support high-speed models in the Onyx family as they become available.
Model 5292 Description High-Speed Synchronizer and Distribution Board 3U VPX Accessories 4 ea. 18 Sync cables are supplied; additional cables may be ordered: 2192-018 Sync cable - 18 2192-036 Sync cable - 36
Pentek, Inc.
www.pentek.com
! ew N
Model 5692
High-Speed Synchronizer and Distribution Board - AMC

General Information
The Model 5692 High-Speed Synchronizer and Distribution board synchronizes multiple Pentek Cobalt or Onyx modules within a system. It enables synchronous sampling and timing for a wide range of multichannel high-speed data acquisition, DSP, and software radio applications. Up to four modules can be synchronized using the 5692, with each receiving a common clock along with timing signals that can be used for synchronizing, triggering and gating functions. Onyx modules. The Sync signals include a reference clock, gate/trigger and sync signals and are distributed through matched cables, simplifying system design.
Clock Signals
The 5692 can accept a user supplied external clock on its front panel MMCX connector. As an alternative to the external clock, the 5692 can use its on-board programmable voltage controlled crystal oscillator (VCXO) as the clock source. The VCXO can operate alone or be locked to a system reference clock signal delivered to the front panel reference clock input. The external or on-board clock can operate at full rate or be divided and is used to register all sync and gate/trigger signals as well as providing a reference clock to all connected modules. In addition, the clock is available at the Clock Out MMCX as a sample or reference clock for other boards in the system.
Input Signals

Features
Output Signals
Synchronizes up to four separate high-speed Cobalt or Onyx I/O modules Synchronizes sampling and data acquisition for multichannel systems Synchronizes gating and triggering functions Clock rates up to 1.8 GHz Front panel MMCX connectors for input signals Front panel Sync connectors compatible with a range of Pentek Cobalt and Onyx modules
MUX
Clk In
PLL :N & DIVIDER :N
Ref In

mSync 2
mSync 3
mSync 4
Pentek, Inc.
www.pentek.com
Model 5692
High-Speed Synchronizer and Distribution Board - AMC

Calibration
The 5692 features a calibration output specifically designed to work with the 56640 or 56740 3.6 GHz A/D module and provide a signal reference for phase adjustment across multiple D/As.
Specifications
Front Panel Sample Clock/Reference Input Connector Type: MMCX Input Impedance: 50 ohms Input Level: 0 dBm to +10 dBm, sine wave Sample Clock Frequency: 100 MHz to 2 GHz Reference Frequency: 5 to 100 MHz Front Panel Gate/Trigger & Sync Inputs Connector Type: MMCX Input Level: LVTTL Front Panel Sync Inputs/Outputs Quantity: 4 Connector Type: 19-pin HDMI Signal Level: CML Signals (Sync connector 1): Reference Clock In, TWSI control In, Reference Clock Out, Gate/Trigger Out, Sync Out Signals (Sync connectors 24): Reference Clock Out, Gate/Trigger Out, Sync Out Front Panel Clock / Calibration Output Connector Type: MMCX Output Impedance: 50 ohms Output Level: +6 dBm nominal, sine wave Sample Clock Frequency: 100 MHz to 1.8 GHz Programmable VCXO: Frequency Ranges: 10-945 MHz, 970-1134 MHz, and 1213-1417.5 MHz Tuning Resolution: 32 bits Unlocked Accuracy: +20 ppm PLL, Divider & Jitter Cleaner Type: Texas Instruments CDCM7005 Frequency Dividers: 1, 2, 3, 4, 6, 8 and 16 PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8, power only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.
Programming
The 5692 allows programming of operating parameters including: VCXO frequency, clock dividers, and delays that allow the user to make timing adjustments on the gate and sync signals. These adjustments are made before they are sent to buffers for output through the Sync connectors. The 5692 is programmed via a TWSI control interface on the first Sync connector. The control interface is compatible with the front panel Sync connectors of all highspeed Cobalt and Onyx modules, thereby providing a single cable connection that carries both control and timing signals.
Supported Products
The 5692 supports all high-speed models in the Cobalt family including the 56630 1 GHz A/D and D/A AMC, the 56640 3.6 GHz A/D AMC and the 56670 Fourchannel 1.25 GHz, 16-bit D/A AMC. The 5692 will also support high-speed models in the Onyx family as they become available.
Model 5692 Description High-Speed Synchronizer and Distribution Board AMC
Pentek, Inc.
www.pentek.com
! w e
Model 7893
System Synchronizer and Distribution Board - PCIe

General Information
Model 7893 System Synchronizer and Distribution Board synchronizes multiple Pentek Cobalt and Onyx boards within a system. It enables synchronous sampling, playback and timing for a wide range of multichannel high-speed data acquisition, DSP and software radio applications. Up to eight boards can be synchronized using the 7893, each receiving a common clock up to 800 MHz along with timing signals that can be used for synchronizing, triggering and gating functions. For larger systems, up to eight 7893s can be linked together to provide synchronization for up to 64 Cobalt or Onyx boards.
Output Signals
The 7893 provides eight timing bus output connectors for distributing all needed timing and clock signals to the front panels of Cobalt and Onyx boards via ribbon cables. The 7893 locks the Gate/Trigger and Sync/ PPS signals to the systems sample clock. The 7893 also provides four front panel SMA connectors for distributing sample clocks to other boards in the system.
Clock Signals
The 7893 can accept a clock from either the front panel SMA connector or from the timing bus input connector. In addition, the board is equipped with a programmable on-board VCXO clock generator which can free run or be locked to a user supplied, 10 MHz typical, system reference. In all cases, the sample clock can be divided by 1, 2, 4, 8 or 16 prior to distribution to the Clock Out SMAs or the timing bus output connectors.
Input Signals
The Model 7893 provides four front panel SMA connectors to accept LVTTL input signals from external sources: two for Sync/PPS and one for Gate/Trigger. In addition to the synchronization signals, a front panel SMA connector accepts sample clocks up to 800 MHz or, in an alternate mode, accepts a 10 MHz reference clock to lock an on-board VCXO sample clock source. The 7893 also accepts the 26-pin Timing Bus connector used on Cobalt and Onyx boards. This input allows a single Cobalt or Onyx board to generate the timing and clock signals for the 7893 for distribution of up to eight additional boards. This input can also be used to link multiple 7893s for larger systems.
USB Interface
The 7893 is programmed via a USB interface. In addition to status and control, the USB interface can be used to generate Gate/Trigger and Sync/PPS signals for distribution to all connected boards.
Features
Synchronizes up to eight separate Cobalt or Onyx boards Up to eight 7893s can be linked together to synchronize up to 64 boards Synchronizes sampling, data acquisition and playback for multichannel systems Synchronizes gating and triggering functions On-board programmable sample clock generator Output clock rates up to 800 MHz Front panel SMA connectors for TTL input signals and clock outputs Single-slot PCIe format
The 7893 is a single-slot PCIe size board which can be mounted in any PCI or PCIe slot. The board receives power from a standard six-pin PCIe power connector and uses the PCI or PCIe slot solely for physical mounting, with no electrical connections.
Sample Clk A
Clock Out 1
Sample Clk / Reference Clk In MUX

CLK IN
PLL N & : DIVIDER N

N
CONTROL VOLTAGE
:N
Clock Out 2
Sample Clk B
Clock Out 3
Sample Clk A Sample C k B Gate / Trig A Gate / Trig B Sync / PPS A Sync / PPS B
REF CLK IN
PROGRAM VCXO
Clock Out 4
Timing Bus In Timing Bus Out 1

Control
USB USB INTERFACE
USB Gate / Trig USB Sync / PPS Sample Clk A Sample Clk B
Sample Clk A Sample Clk B Gate / Trig A Gate / Trig B Sync / PPS A Sync / PPS B
TTL Gate / Trig In
USB Gate / Trig
MUX MUX MUX
Gate / Trig A
Gate / Trig B
BUFFER & PROGRAM DELAYS
Timing Bus Out 2 through Timing Bus Out 7

Timing Bus Out 8
USB Sync / PPS

TTL Sync / PPS A In TTL Sync / PPS B In MUX
Sync / PPS A
MUX
Sync / PPS B
Sample Clk A Sample Clk B Gate / Trig A Gate / Trig B Sync / PPS A Sync / PPS B
Pentek, Inc.
www.pentek.com
Model 7893
System Synchronizer and Distribution Board - PCIe

Supported Products
The 7893 supports a wide range of products in the Cobalt family including the 78620 and 78621 three-channel A/D, 200 MHz transceivers, the 78650 and 78651 two-channel A/D, 500 MHz transceivers, the 78660, 78661 and 78662 four-channel 200 MHz A/Ds, and the 78690 L-Band RF Tuner. The 7893 also supports the Onyx 78760 four-channel 200 MHz A/D and will support all complementary models in the Onyx family as they become available. Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 800 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference (front panel Reference Clock Input), typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for each of five on-board clock buses. Sample Clock Output Type: Four front panel female SMC connectors, each can be independently divided Output Level: +9 dBm, nominal, sine wave Timing Bus Out Type: Eight rear 26-pin connectors Signals: LVPECL bus includes: Sample Clock A & B Out, Gate/Trigger A & B Out, and Sync/PPS A & B Out Control: Rear USB input for connecting to motherboard on-board USB 8-pin header Power: Rear 8-pin connector compatible with PCIe power connectors Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe card, 4.38 in. x 7.13 in.
Specifications
Sample Clock/Reference Clock Input Type: Front panel female SMC connector Signal: Sine wave, 0 to +10 dBm, ACcoupled, 50 ohms, accepts 10 to 800 MHz sample clock or 4 to 180 MHz PLL system reference, typically 10 MHz TTL Gate/Trigger Input Type: Front panel female SMC connector Signal: LVTTL Function: Programmable functions include gate and trigger TTL Sync/PPS Input A Type: Front panel female SMC connector Signal: LVTTL Function: Programmable functions include sync and PPS TTL Sync/PPS Input B Type: Front panel female SMC connector Signal: LVTTL Function: Programmable functions include sync and PPS Timing Bus In Type: One rear 26-pin connector Signals: LVPECL bus includes: Sample Clock A & B In, Gate/Trigger A & B In, and Sync/PPS A & B In
Model 7893 Description System Synchronizer and Distribution Board- PCIe
Accessories 2891 Timing Bus Cables
Pentek, Inc.
www.pentek.com
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Model 7194
High-Speed Clock Generator - PMC/XMC

General Information
Model 7194 High-Speed Clock Generator provides fixed-frequency sample clocks to Cobalt and Onyx modules in multiboard systems. It enables synchronous sampling, playback and timing for a wide range of multichannel high-speed data acquisition and software radio applications.
Specifications
Sample Clock Frequency: Fixed, 1.4 to 2.0 GHz by ordering option Sample Clock Outputs Type: Four front panel female SMA connectors Output Level: +10 dBm, nominal, sine wave Reference Clock In Type: Front panel female SMA connector Frequency: 10 MHz Input Impedance: 50 ohms Input Level: 0 dBm to +10 dBm, sine wave Reference Clock Out Type: Front panel female SMA connector Center Frequency: 10 MHz Output Impedance: 50 ohms Output Level: +10 dBm, nominal, sine wave Frequency Stability vs. Change in Temperature: 50.0 ppb Frequency Calibration: +1.0 ppm Aging Daily: +10 ppb/day First Year: +300 ppb Total Frequency Tolerance (20 years): +4.60 ppm Phase Noise 1 Hz Offset: -67 dBc/Hz 10 Hz Offset: -100 dBc/Hz 100 Hz Offset: -130 dBc/Hz 1 KHz Offset: -148 dBc/Hz 10 KHz Offset: -154 dBc/Hz 100 KHz Offset: -155 dBc/Hz PMC/XMC Interface: Power only on PMC P1 or XMC P15 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard PMC module, 2.91 in. x 5.87 in.
Sample Clock Synthesizer

The Model 7194 uses a high-precision, fixed-frequency, PLO (Phase-Locked Oscillator) to generate an output sample clock. The PLO accepts a 10 MHz reference clock through a front panel SMA connector. The PLO locks the output sample clock to the incoming reference. A power splitter then receives the sample clock and distributes it to four front panel SMA connectors. The 7194 is available with sample clock frequencies from 1.4 to 2.0 GHz.

In addition to accepting a reference clock on the front panel, the 7194 includes an on-board 10 MHz reference clock. The reference is an OCXO (Oven-Controlled Crystal Oscillator), which provides an exceptionally precise frequency standard with excellent phase noise characteristics.
Features
Provides sample clock for up to four separate XMC Cobalt or Onyx boards Locks to user-supplied 10 MHz reference clock or on-board reference. OCXO provides an exceptionally precise clock
The 7194 is a standard PMC/XMC module. The module does not require programming and the PMC P14 or XMC P15 connector is used solely for power. The module can be optionally configured with a PCIe-style 6-pin power connector allowing it to be used in virtually any chassis or enclosure.
Clock Out 1 FREQUENCY SYNTHESIZER Reference Clock In

REFERENCE CLOCK IN SAMPLE CLOCK OUT
Clock Out 2 POWER SPLITTER Clock Out 3
frequency set by board option
Clock Out 4
OVEN STABlLIZED OSCILLATOR
Reference Clock Out
Pentek, Inc.
www.pentek.com
Model 7194
Sample Clock Phase Noise
High-Speed Clock Generator - PMC/XMC
Phase Noise (1 Hz BW, typical)
Phase Noise 10.00 dB/Ref -20.00 dBc/Hz
Model 7194 Description High-speed Clock Generator - PMC/XMC Options Description 104 PMC P14 (Power only) 105 XMC P15 (Power only) 106 PCIe 6-pin connector (Power only) 150 1.500 GHz sample clock 180 1.800 GHz sample clock
Contact Pentek for additional sample clock options
Pentek, Inc.
www.pentek.com
! w e N
Models 7294, 7494 and 7394
High-Speed Clock Generator - 3U/6U cPCI

General Information
These High-Speed Clock Generators provide fixed-frequency sample clocks to cPCI Cobalt and Onyx boards in multiboard systems. They enable synchronous sampling, playback and timing for a wide range of multichannel high-speed data acquisition and software radio applications. Model 7394 is a 3U cPCI booard that generates four clocks. Model 7294 is a 6U cPCI board that generates four clocks, while Model 7494 is a double-density 6U cPCI board that generates eight clocks.
Specifications
Sample Clock Frequency: Fixed, 1.4 to 2.0 GHz by ordering option Sample Clock Outputs Type: Four or eight front panel female SMA connectors Output Level: +10 dBm, nominal, sine wave Reference Clock In Type: Front panel female SMA connector Frequency: 10 MHz Input Impedance: 50 ohms Input Level: 0 dBm to +10 dBm, sine wave Reference Clock Out Type: Front or eight front panel female SMA connectors Center Frequency: 10 MHz Output Impedance: 50 ohms Output Level: +10 dBm, nominal, sine wave Frequency Stability vs. Change in Temperature: 50.0 ppb Frequency Calibration: +1.0 ppm Aging Daily: +10 ppb/day First Year: +300 ppb Total Frequency Tolerance (20 years): +4.60 ppm Phase Noise 1 Hz Offset: -67 dBc/Hz 10 Hz Offset: -100 dBc/Hz 100 Hz Offset: -130 dBc/Hz 1 KHz Offset: -148 dBc/Hz 10 KHz Offset: -154 dBc/Hz 100 KHz Offset: -155 dBc/Hz PCI Interface PCI Bus: 32-bit, 66 MHz (supports 33 MHz), power only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 3U or 6U cPCI board

These models use one or two high-precision, fixed-frequency, PLOs (Phase-Locked Oscillators) to generate four or eight output sample clocks. The PLOs accept a 10 MHz reference clock through front panel SMA connectors. The PLOs lock the output sample clocks to the incoming reference. Power splitters then receive the sample clocks and distribute them to four or eight front panel SMA connectors. These models are available with sample clock frequencies from 1.4 to 2.0 GHz.
Model 7494
Model 7394
On-board Reference Clock Features
Provides sample clock for up to four or eight separate cPCI Cobalt or Onyx boards Locks to user-supplied 10 MHz reference clock or on-board reference. OCXO provides an exceptionally precise clock
In addition to accepting a reference clock on the front panel, these models include one or two on-board 10 MHz reference clocks. The reference clocks are OCXOs (Oven-Controlled Crystal Oscillators), which provide an exceptionally precise frequency standard with excellent phase noise characteristics.
These models are standard CompactPCI boards. They do not require programming and the interface connectors are used solely for power. The boards can be optionally configured with a PCIe-style 6-pin power connector allowing them to be used in virtually any chassis or enclosure.

Clock Out 4
Models 7294 and 7394 Block Diagram. Model 7494 Doubles all Resources.
OVEN STABlLIZED OSCILLATOR Reference Clock Out
Pentek, Inc.
www.pentek.com
Models 7294, 7494 and 7394

High-Speed Clock Generator - 3U/6U cPCI
Model 7294 Description High-Speed Clock Generator - 6U cPCI 7494 High-Speed Clock Generator - 6U cPCI 7394 High-Speed Clock Generator - 3U cPCI Options Description 106 PCIe 6-pin connector (Power only) 150 1.500 GHz sample clock 180 1.800 GHz sample clock
Pentek, Inc.
www.pentek.com
! w e N
Model 7894
High-Speed Clock Generator - PCIe

General Information
Model 7894 High-Speed Clock Generator provides fixed-frequency sample clocks to PCIe Cobalt and Onyx boards in multi-board systems. It enables synchronous sampling, playback and timing for a wide range of multichannel high-speed data acquisition and software radio applications.
Specifications
Sample Clock Frequency: Fixed, 1.4 to 2.0 GHz by ordering option Sample Clock Outputs Type: Four front panel female SMA connectors Output Level: +10 dBm, nominal, sine wave Reference Clock In Type: Front panel female SMA connector Frequency: 10 MHz Input Impedance: 50 ohms Input Level: 0 dBm to +10 dBm, sine wave Reference Clock Out Type: Front panel female SMA connector Center Frequency: 10 MHz Output Impedance: 50 ohms Output Level: +10 dBm, nominal, sine wave Frequency Stability vs. Change in Temperature: 50.0 ppb Frequency Calibration: +1.0 ppm Aging Daily: +10 ppb/day First Year: +300 ppb Total Frequency Tolerance (20 years): +4.60 ppm Phase Noise 1 Hz Offset: -67 dBc/Hz 10 Hz Offset: -100 dBc/Hz 100 Hz Offset: -130 dBc/Hz 1 KHz Offset: -148 dBc/Hz 10 KHz Offset: -154 dBc/Hz 100 KHz Offset: -155 dBc/Hz PCI Express Interface PCIe Bus: x4 or x8, power only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.

The Model 7894 uses a high-precision, fixed-frequency, PLO (Phase-Locked Oscillator) to generate an output sample clock. The PLO accepts a 10 MHz reference clock through a front panel SMA connector. The PLO locks the output sample clock to the incoming reference. A power splitter then receives the sample clock and distributes it to four front panel SMA connectors. The 7894 is available with sample clock frequencies from 1.4 to 2.0 GHz.

Features
The 7894 is a standard PCI Express board. The board does not require programming and the PCIe interface connector is used solely for power. The board can be optionally configured with a PCIe style 6-pin power connector allowing it to be used in virtually any chassis or enclosure.
Provides sample clock for up to four separate PCIe Cobalt or Onyx boards Locks to user-supplied 10 MHz reference clock or on-board reference. OCXO provides an exceptionally precise clock

Clock Out 4
Reference Clock Out
Pentek, Inc.
www.pentek.com
Model 7894
High-Speed Clock Generator - PCIe
Model 7894 Description High-speed Clock Generator - PCIe Options Description 106 PCIe 6-pin connector (Power only) 150 1.500 GHz sample clock 180 1.800 GHz sample clock
Pentek, Inc.
www.pentek.com
! w e N
Model 5294
High-Speed Clock Generator - 3U VPX

General Information
Model 5294 High-Speed Clock Generator provides fixed-frequency sample clocks to 3U VPX Cobalt and Onyx boards in multiboard systems. It enables synchronous sampling, playback and timing for a wide range of multichannel high-speed data acquisition and software radio applications.
Specifications
Sample Clock Frequency: Fixed, 1.4 to 2.0 GHz by ordering option Sample Clock Outputs Type: Four front panel female SMA connectors Output Level: +10 dBm, nominal, sine wave Reference Clock In Type: Front panel female SMA connector Frequency: 10 MHz Input Impedance: 50 ohms Input Level: 0 dBm to +10 dBm, sine wave Reference Clock Out Type: Front panel female SMA connector Center Frequency: 10 MHz Output Impedance: 50 ohms Output Level: +10 dBm, nominal, sine wave Frequency Stability vs. Change in Temperature: 50.0 ppb Frequency Calibration: +1.0 ppm Aging Daily: +10 ppb/day First Year: +300 ppb Total Frequency Tolerance (20 years): +4.60 ppm Phase Noise 1 Hz Offset: -67 dBc/Hz 10 Hz Offset: -100 dBc/Hz 100 Hz Offset: -130 dBc/Hz 1 KHz Offset: -148 dBc/Hz 10 KHz Offset: -154 dBc/Hz 100 KHz Offset: -155 dBc/Hz PCI Express Interface PCIe Bus: x4, power only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

The Model 5294 uses a high-precision, fixed-frequency, PLO (Phase-Locked Oscillator) to generate an output sample clock. The PLO accepts a 10 MHz reference clock through a front-panel SMA connector. The PLO locks the output sample clock to the incoming reference. A power splitter then receives the sample clock and distributes it to four front panel SMA connectors. The 5294 is available with sample clock frequencies from 1.4 to 2.0 GHz.

Features
The 5294 is a standard 3U VPX board. The board does not require programming and the PCIe interface connector is used solely for power. The board can be optionally configured with a PCIe-style 6-pin power connector allowing it to be used in virtually any chassis or enclosure.
Provides sample clock for up to four separate 3U VPX Cobalt or Onyx boards Locks to user-supplied 10 MHz reference clock or on-board reference. OCXO provides an exceptionally precise clock

Clock Out 4
Reference Clock Out
Pentek, Inc.
www.pentek.com
Model 5294
High-Speed Clock Generator - 3U VPX
Model 5294 Description High-speed Clock Generator - 3U VPX Options Description 106 PCIe 6-pin connector (Power only) 150 1.500 GHz sample clock 180 1.800 GHz sample clock
Pentek, Inc.
www.pentek.com
! w e N
Model 5694
High-Speed Clock Generator - AMC

General Information
Model 5694 High-Speed Clock Generator provides fixed-frequency sample clocks to AMC Cobalt and Onyx boards in multiboard systems. It enables synchronous sampling, playback and timing for a wide range of multichannel high-speed data acquisition and software radio applications.
Specifications
Sample Clock Frequency: Fixed, 1.4 to 2.0 GHz by ordering option Sample Clock Outputs Type: Four front panel female SMA connectors Output Level: +10 dBm, nominal, sine wave Reference Clock In Type: Front panel female SMA connector Frequency: 10 MHz Input Impedance: 50 ohms Input Level: 0 dBm to +10 dBm, sine wave Reference Clock Out Type: Front panel female SMA connector Center Frequency: 10 MHz Output Impedance: 50 ohms Output Level: +10 dBm, nominal, sine wave Frequency Stability vs. Change in Temperature: 50.0 ppb Frequency Calibration: +1.0 ppm Aging Daily: +10 ppb/day First Year: +300 ppb Total Frequency Tolerance (20 years): +4.60 ppm Phase Noise 1 Hz Offset: -67 dBc/Hz 10 Hz Offset: -100 dBc/Hz 100 Hz Offset: -130 dBc/Hz 1 KHz Offset: -148 dBc/Hz 10 KHz Offset: -154 dBc/Hz 100 KHz Offset: -155 dBc/Hz PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8, power only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.

The Model 5694 uses a high-precision, fixed-frequency, PLO (Phase-Locked Oscillator) to generate an output sample clock. The PLO accepts a 10 MHz reference clock through a front-panel SMA connector. The PLO locks the output sample clock to the incoming reference. A power splitter then receives the sample clock and distributes it to four front panel SMA connectors. The 5694 is available with sample clock frequencies from 1.4 to 2.0 GHz.

Features
The 5694 is a standard AMC board. The board does not require programming and the PCIe interface connector is used solely for power. The board can be optionally configured with a PCIe-style 6-pin power connector allowing it to be used in virtually any chassis or enclosure.
Provides sample clock for up to four separate AMC Cobalt or Onyx boards Locks to user-supplied 10 MHz reference clock or on-board reference. OCXO provides an exceptionally precise clock

Clock Out 4
Reference Clock Out
Pentek, Inc.
www.pentek.com
Model 5694
High-Speed Clock Generator - AMC
Model 5694 Description High-speed Clock Generator - AMC Options Description 106 PCIe 6-pin connector (Power only) 150 1.500 GHz sample clock 180 1.800 GHz sample clock
Pentek, Inc.
www.pentek.com
Model 9190
Clock and Sync Generator for I/O Modules

Output Signals
The front panel clock and sync connectors in the list of supported modules fall into two classes, thus requiring two types of front panel cable. The first type uses a 26-pin connector (for the 621x series, the 6229, the 7x31, 7x40 and 7x42 series) delivering the clock and four timing signals. The second type uses a 36-pin connector (for the 623x series) delivering the clock and five timing signals. Either cable type can be installed in any of the 80 positions of the Model 9190, however, systems with mixed types of I/O modules may not have all functions supported. Contact the factory for assistance with your specific configuration. Buffered versions of the clock and five timing signals are also available as outputs on the 9190s front panel SMA connectors.
General Information
Model 9190 Clock and Sync Generator synchronizes multiple Pentek I/O modules within a system to provide synchronous sampling and timing for a wide range of high-speed, multichannel data acquisition, DSP and software radio applications. Up to 80 I/O modules can be driven from the Model 9190, each receiving a common clock and up to five different timing signals which can be used for synchronizing, triggering and gating functions.
Features

Synchronizes up to 80 I/O modules Synchronizes sampling and data acquisition for multichannel systems Synchronizes gating and triggering functions Synchronizes local oscillator phase, decimation phase and frequency switching for multichannel digital receivers and upconverters Clock rates up to 105 MHz Supports most popular I/O modules Front panel SMA connectors for external clock and timing signal inputs and outputs 19-inch wide, 1.75 in. high rack-mount chassis with integral AC line power supply Flexible cable installation supports many different system configurations
Input Signals
Clock and timing signals can come from six front panel SMA user inputs or from one I/O module set to act as the timing signal master. (In this case, the master I/O module will not be synchronous with the slave modules due to delays through the 9190.) Alternately, the master clock can come from a socketed, user-replaceable crystal oscillator within the 9190.
Model 9190 is housed in a line-powered, 1.75 in. high metal chassis suitable for mounting in a standard 19 in. equipment rack, either above or below the cage holding the I/O modules. Separate cable assemblies extend from openings in the front panel of the 9190 to the front panel clock and sync connectors of each I/O module. Mounted between two standard rack-mount card cages, Model 9190 can drive a maximum of 80 clock and sync cables, 40 to the card cage above and 40 to the card cage below. Fewer cables may be installed for smaller systems. Due to the numerous configuration possibilities allowed by the 9190, Pentek configuration services are required with its purchase.
Supported Products
Model 9190 currently supports VIM Models 6210, 6211, 6216, 6228, 6229, 6230, 6231, 6232, 6235, 6236; the PMC Models 7131, 7140, 7141, 7142 and 7150; the PCI Models 7631A, 7640, 7641, 7642 and 7650; and the cPCI Models 7231, 7331, 7240, 7340, 7241, 7341, 7242, 7342 and 7350. Contact us for an up-to-date list of supported modules.
From Module Master Source Front Panel Input SMA Connectors
LVDS DIFF. RECEIVER
Timing Signals
LVDS DIFF. DRIVERS
To Module No. 1 To Module No. 2
Timing Signals
LVDS DIFF. DRIVERS
Timing Signals
LINE RCVRS
Model 9190 Description Clock and Sync Generator
Multiplexer Switches Clock
Ext. Clock
LVDS DIFF. DRIVERS
To Module No. 80
Options: -019 64 MHz internal oscillator -040 40-Channel version
OPTIONAL INTERNAL OSCILLATOR
LINE DRIVERS
Front Panel Output SMA Connectors
Pentek, Inc.
www.pentek.com
! w e N
Model 9192
Rackmount High-Speed System Synchronizer Unit

Output Signals
The 9192 provides four rear panel Sync output connectors, compatible with a range of high-speed Pentek Cobalt and Onyx boards. The Sync signals include a reference clock, gate/trigger and sync signals and are distributed through matched cables, simplifying system design.
General Information
Model 9192 Rackmount High-Speed System Synchronizer Unit synchronizes multiple Pentek Cobalt or Onyx modules within a system. It enables synchronous sampling and timing for a wide range of multichannel high-speed data acquisition, DSP, and software radio applications. Up to twelve boards can be synchronized using the 9192, each receiving a common clock along with timing signals that can be used for synchronizing, triggering and gating functions.
Clock Signals
The 9192 can accept a user supplied external clock on its rear panel SMA connector. As an alternative to the external clock, the 9192 can use its on-board programmable voltage controlled crystal oscillator (VCXO) as the clock source. The VCXO can operate alone or be locked to a system reference clock signal delivered to the rear panel reference clock input. The on-board or external clock can operate at full rate or can be divided and used to register all sync and gate/trigger signals as well as providing a reference clock to all connected boards. In addition, the clock is available at twelve Clock Out SMAs as a sample or reference clock for other boards in the system.
Input Signals
Model 9192 provides four rear panel SMA connectors to accept input signals from external sources: two for clock, one for gate or trigger and one for a synchronization signal. Clock signals can be applied from an external source such as a high performance sine-wave generator. Gate/trigger and sync signals can come from an external system source. In addition to the SMA connector, a reference clock can be accepted through the first rear panel Sync output connector, allowing a single Cobalt or Onyx board to generate the clock for all subsequent boards in the system.
Features
Synchronizes up to twelve separate high-speed Cobalt or Onyx I/O modules Synchronizes sampling and data acquisition for multichannel systems Synchronizes gating and triggering functions Clock rates up to 1.8 GHz Rear panel SMA connectors for input signals Rear panel Sync connectors compatible with a range of Pentek Cobalt and Onyx modules

External Clk In Clock Out 1 Clock Out 2 MUX MUX CLOCK SPLITTER
Clk In
PLL :N & DIVIDER :N
Clock Out 3 through Clock Out 11 Clock Out 12
Ref In

USB USB-TO-TWSI INTERFACE
mSync 2
Clk Ref In Trig/ Gate In Sync In
mSync 3 through mSync 11 mSync 12

Pentek, Inc.
www.pentek.com
Model 9192
Rackmount High-Speed System Synchronizer Unit

Calibration
The 9192 features twelve calibration outputs specifically designed to work with the 71640 or 71740 3.6 GHz A/D module and provide a signal reference for phase adjustment across multiple D/As
Specifications
Front Panel Sample Clock / Reference Input Connector Type: SMA Input Impedance: 50 ohms Input Level: 0 dBm to +10 dBm, sine wave Sample Clock Frequency: 100 MHz to 2 GHz Reference Frequency: 5 to 100 MHz Rear Panel Gate/Trigger & Sync Inputs Connector Type: SMA Input Level: LVTTL Rear Panel Sync Inputs/Outputs Quantity: 12 Connector Type: 19-pin HDMI Signal Level: CML Signals (Sync connector 1): Reference Clock In, TWSI control In, Reference Clock Out, Gate/Trigger Out, Sync Out Signals (Sync connectors 2-12): Reference Clock Out, Gate/Trigger Out, Sync Out Rear Panel Clock / Calibration Outputs Quantity: 12 Connector Type: SMA Output Impedance: 50 ohms Output Level: +6 dBm nominal at 1400 MHz, sine wave Sample Clock Frequency: 100 MHz to 1.8 GHz Programmable VCXO: Frequency Ranges: 10-945 MHz, 970-1134 MHz, and 1213-1417.5 MHz Tuning Resolution: 32 bits Unlocked Accuracy: +20 ppm PLL, Divider & Jitter Cleaner Type: Texas Instruments CDCM7005 Frequency Dividers: 1, 2, 3, 4, 6, 8 and 16 Power: 120VAC Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 1U Rackmount, 19 in. x 1.75 in.
Programming
The 9192 allows programming of operation parameters including: VCXO frequency, clock dividers, and delays that allow the user to make timing adjustments on the gate and sync signals. These adjustments are made before they are sent to buffers for output through the Sync connectors. The 9192 is programmed via a rear panel USB connector or a TWSI control interface on the first Sync connector. The control interface is compatible with the front panel Sync connectors of all high-speed Cobalt and Onyx modules, thereby providing a single cable connection that carries both control and timing signals.
Supported Products
The 9192 supports all high-speed models in the Cobalt family including the 71630 1 GHz A/D and D/A XMC, the 71640 3.6 GHz A/D XMC and the 71670 Fourchannel 1.25 GHz, 16-bit D/A XMC. The 9192 will also support high-speed models in the Onyx family as they become available.
Model 9192 Description Rackmount High-Speed System Synchronizer Unit
Pentek, Inc.
www.pentek.com
SOF TW ARE & FPGA TOOLS SOFTW TWARE

MODEL
4953 4994A 4995A 4996/4996A VxWorks 4986
DESCRIPTION
Pentek GateFlow FPGA Design Kit Pentek ReadyFlow BSPs for Linux Pentek ReadyFlow BSPs for Windows Pentek VxWorks BSPs and Drivers Wind River Workbench/VxWorks for PowerPC Pentek SystemFlow Recording Software Verari Systems Software VSI/Pro for PowerPC Customer Information
Last updated: July 2013

www.pentek.com
Model 4953
GateFlow FPGA Design Kit for Cobalt and Onyx Products

Using the FPGA Design Kit
The GateFlow FPGA Design Kit allows the user to modify, replace and extend the standard factory-installed functions in the FPGA to incorporate special modes of operation, new control structures, and specialized signal-processing algorithms. The Cobalt and Onyx architectures configure the FPGA with standard factorysupplied interfaces including memory controllers, DMA engines, A/D and D/A interfaces, timing and synchronization structures, triggering and gating logic, time stamping and header tagging, data formatting engines, and the PCIe interface. These resources are connected to the User Application Container using well-defined ports that present easy-to-use data and control signals, effectively abstracting the lower level details of the hardware.
The User Application Container

Shown below is the FPGA block diagram of a typical Cobalt or Onyx module. The User Application Container holds a collection of different factory-installed IP modules connected to the various interfaces through the standard ports surrounding the container. The specific IP modules for each product are described in further detail in the datasheet of that product. The GateFlow Design Kit provides a complete Xilinx ISE Foundation Tool project folder containing all the files necessary for the FPGA developer to recompile the entire project with or without any required changes. VHDL source code for each IP module provides excellent examples of how the IP modules work, how they might be modified, and how they might be replaced with custom IP to implement a specific function.
GateFlow is Penteks family of extendable FPGA products. The GateFlow product line includes the GateFlow FPGA Design Kit to ease custom algorithm development and the GateFlow Factory-installed IP Cores in Pentek FPGA board products. The Pentek Model 4953 GateFlow FPGA Design Kit provides the user with design information, software files and utilities for extending FPGA functions in these products. Users can implement a variety of custom preprocessing functions such as convolution, framing, pattern recognition, decompression, FFT, delay, decoding, time stamping, averaging, summation and many more. For the latest GateFlow information go to: pentek.com/fpga
Front Panel Interface
User Application Container Sync Bus Interface Clock Generator
Factory Installed Base Function Application A/D & D/A Control Data Packing & Formatting Meta Data Files Linked-List A/D Control Linked-List D/A Control
Timestamp Test Generator Memory Controller Memory Controller
Memory Controller Memory Controller
Board Registers
User Registers
DMAs
P14 LVDS
P16 MGTs
Global Registers PCI Express Backend FLASH Interface PCI Express Interface
Defined and documented interface signals
V-6 or V-7 FPGA
Pentek, Inc.
www.pentek.com
Model 4953
GateFlow FPGA Design Kit for Other Pentek Products

Using the FPGA Design Kit
The GateFlow FPGA Design Kit is intended for the programming of predefined user blocks located in the data flow path specifically reserved for custom applications. These predefined blocks protect users from inadvertently altering base functionality. Pentek recommends user programming be limited to the predefined user blocks to maintain base functionality. However, for more complex requirements, sufficient information is supplied in the kit for the user to modify, add to, or replace default board functions if necessary. Default configuration files are included with the Design Kit should it be necessary to restore standard factory configuration.
FPGA Design Kit User Block

Shown below is the block diagram of a typical software radio module. The diagram includes the FPGA and external hardware devices connected to it. The blocks inside the FPGA are VHDL code modules that handle the standard factory functions and interfaces. The User Block is a VHDL module that sits in the data path with pin definitions for input, output, status, control and clocks. In the standard Design Kit product, the User Block is configured as a straight wire between the input and output ports. By creating a custom algorithm inside the block that conforms to the pin definition, the user will have a low-risk experience in recompiling and installing the custom code. Since Pentek provides source code for all the modules, changes outside the user block can also be made by the user.
GateFlow is Penteks family of extendable FPGA products. The GateFlow product line includes the GateFlow FPGA Design Kit to ease custom algorithm development and the GateFlow Factory-installed IP Cores in Pentek FPGA board products. The Pentek Model 4953 GateFlow FPGA Design Kit provides the user with design information, software files and utilities for extending FPGA functions in these products. Users can implement a variety of custom preprocessing functions such as convolution, framing, pattern recognition, decompression, FFT, delay, decoding, time stamping, averaging, summation and many more. For the latest GateFlow information go to: pentek.com/fpga
DIGITAL INPUT ANALOG INPUT A/D
FPGA USER BLOCK

DATA SELECT INPUT DEFAULT BYPASS CONTROL STATUS DMA CONTROL & COUNTERS OUTPUT DATA FORMATTER
MEZZANINE INTERFACE
DIGITAL RECEIVER EXT CLK LVDS CLK & SYNC

XTAL OSC CLOCK & SYNC DRIVERS
CLOCK CONTROL SYNC / GATE / TRIGGER GENERATOR
STATUS & CONTROL
INTERRUPT GENERATOR
Pentek, Inc.
www.pentek.com
Model 4953
GateFlow FPGA Design Kit

Available FPGA Resources for Pentek Hardware
FPGAs in Pentek Products

These charts show the Xilinx FPGA families as used in the various Pentek board-level products. These products use some FPGA resources to implement standard factory functions as well as installed IP cores. These charts show the percentage of unused system slices and RAM available to the user for extending the FPGA to include custom algorithms.
Logic Cells CLB Slices CLB Flip-Flops Max. Block RAM (kb) Multipliers / DSP Blocks PowerPC Processor Blocks Pentek Model 4207 6821 6822 6826 7142* Board Type VME/VXS VME/VXS VME/VXS VME/VXS PMC/XMC No. of FPGAs 1 2 2 1 2
Xilinx Virtex-II Pro

-VP50 53,136 23,616 47,232 4,176 232 2 -VP70 74,448 33,088 66,176 5,904 328 2 -FX60 56,880 25,280 50,560 4,176 128 2 Slices RAM 38% 77% 71% 92%
Xilinx Virtex-4
-FX100 94,986 42,176 84,352 6,768 160 2 Slices RAM 61% 86% 82% 95% -SX55 55,296 24,576 49,152 5,760 512 -LX100 110,592 49,152 98,304 4,320 96
% Available to User
% Available to User
Slices RAM Slices RAM 98% 100% 98% 100% 75% 72%
Slices RAM Slices RAM 54% 78% 77% 71%
Available FPGA Resources for Pentek Hardware

Xilinx Virtex-5
-SX50T Logic Cells CLB Slices CLB Flip-Flops Max. Block RAM (kb) DSP48E Blocks PCI Express Support Pentek Model 7150* 7153* 7156* 7158* 71620** 71621** 71630** 71640** 71650** 71651** 71660** 71661** 71662** 71670** 71690** 71720*** 71760*** Board Type PMC/XMC PMC/XMC PMC/XMC PMC/XMC XMC XMC XMC XMC XMC XMC XMC XMC XMC XMC XMC XMC XMC No. of FPGAs 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 52,224 8,160 32,640 4,752 288 -SX95T 94,208 14,720 58,880 8,784 640
% Available to User
Xilinx Virtex-6
-LX155T 155,648 24,320 97,280 7,632 128 Slices RAM 64% N/A 69% 69% 84% N/A 74% 74% -LX130T 128,000 20,000 160,000 9,504 480 Gen 2, x8 Slices RAM 68% 55% 8% 66% 69% 24% 80% 75% 64% 64% 74% 75% 46% 87% -LX240T 241,152 37,680 301,440 14,976 768 Gen 2, x8
% Available to User
Xilinx Virtex-7
-SX315T 314,880 49,200 393,600 25,344 1,344 -VX330T 326,400 51,000 408,000 27,000 1120 Gen 3, x8 -VX690T 693,120 108,300 866,400 52,920 3,600 Gen 3, x8
Gen 2, x8
% Available to User
Slices RAM Slices RAM 7% N/A 16% 16% 75% N/A 59% 59% 36% 42% 50% 50% 86% 45% 78% 78%
Slices RAM Slices RAM
Slices RAM Slices RAM
83% 82% 66% 63% 76% 77% 46% 77% 82% 84% 47% 65% 76% 85% 43% 67% TBD TBD 58% 65% 89% 91%
TBD TBD TBD TBD 81% 86% 59% 86% 86% 90% 58% 79% 88% 92% TBD TBD 48% 62% 68% 80% 91% 95%
TBD TBD TBD TBD
TBD TBD TBD TBD
* Other form factors: 72xx = 6U cPCI; 73xx = 3U cPCI; 76xx = PCI; 77xx = Full-Length PCIe; 78xx = Half-Length PCIe; 53xx = 3U VPX **Cobalt form factors: 716xx = XMC; 726xx = 6U CPCI; 736xx = 3U cPCI; 746xx = 6U CPCI (Dual XMC); 786xx = Half-Length PCIe; 536XX = 3U VPX - Format 1; 526XX = 3U VPX - Format 2; 566xx = AMC ***Onyx form factors: 717xx = XMC; 727xx = 6U CPCI; 737xx = 3U cPCI; 747xx = 6U CPCI (Dual XMC); 787xx = Half-Length PCIe; 537XX = 3U VPX - Format 1; 527XX = 3U VPX - Format 2; 567xx = AMC %Available to User: Applies to the Processing FPGA(s) of certain products; % Available can vary slightly due to rounding
Pentek, Inc.
www.pentek.com
Model 4953
Model 4953 Description GateFlow FPGA Design Kit
GateFlow FPGA Design Kit
Options:
Supported Product w/ FPGA option 7142 w/ XC4VSX55 7142 w/ XC4VFX60 7142 w/ XC4VFX100 7142 w/ XC4VLX100 7150 w/ XC5VLX155T 7150 w/ XC5VSX50T 7150 w/ XC5VSX95T 7153 w/ XC5VSX95T 7156 w/ XC5VLX155T 7156 w/ XC5VSX50T 7156 w/ XC5VSX95T 7158 w/ XC5VLX155T 7158 w/ XC5VSX50T 7158 w/ XC5VSX95T 71620 w/ XC6VLX130T 71620 w/ XC6VLX240T 71620 w/ XC6VSX315T 71621 w/ XC6VLX240T 71621 w/ XC6VSX315T 71630 w/ XC6VLX130T 71630 w/ XC6VLX240T 71630 w/ XC6VSX315T 71640 w/ XC6VLX130T 71640 w/ XC6VLX240T 71640 w/ XC6VSX315T 71641 w/ XC6VSX315T 71650 w/ XC6VLX130T 71650 w/ XC6VLX240T 71650 w/ XC6VSX315T 71651 w/ XC6VLX240T 71651 w/ XC6VSX315T
Options:
Supported Product w/ FPGA option 71660 w/ XC6VLX130T 71660 w/ XC6VLX240T 71660 w/ XC6VSX315T 71661 w/ XC6VLX240T 71661 w/ XC6VSX315T 71662 w/ XC6VLX240T 71662 w/ XC6VSX315T 71670 w/ XC6VLX130T 71670 w/ XC6VLX240T 71670 w/ XC6VSX315T 71671 w/ XC6VLX240T 71671 w/ XC6VSX315T 71690 w/ XC6VLX130T 71690 w/ XC6VLX240T 71690 w/ XC6VSX315T 71720 w/ XC7VX330T 71720 w/ XC7VX690T 71760 w/ XC7VX330T 71760 w/ XC7VX690T 4207 w/ XC4VFX60 4207 w/ XC4VFX100 6821 w/ XC2VP20 6821 w/ XC2VP50 6822 w/ XC2VP20 6822 w/ XC2VP50 6826 w/ XC2VP70
-142-055* -142-060* -142-100* -142-110* -150-083* -150-084* -150-085* -153-085* -156-083* -156-084* -156-085* -158-083* -158-084* -158-085* -620-061** -620-062** -620-064** -621-062** -621-064** -630-061** -630-062** -630-064** -640-061** -640-062** -640-064** -641-064** -650-061** -650-062** -650-064** -651-062** -651-064**
-660-061** -660-062** -660-064** -661-062** -661-064** -662-062** -662-064** -670-061** -670-062** -670-064** -671-062** -671-064** -690-061** -690-062** -690-064** -720-073*** -720-076*** -760-073*** -760-076*** -207-060 -207-100 -821-022 -821-052 -822-022 -822-052 -826-072
* Other form factors: 72xx = 6U cPCI; 73xx = 3U cPCI; 76xx = PCI; 77xx = Full-Length PCIe; 78xx = Half-Length PCIe; 53xx = 3U VPX **Cobalt form factors: 716xx = XMC; 726xx = 6U CPCI; 736xx = 3U cPCI; 746xx = 6U CPCI (Dual XMC); 786xx = Half-Length PCIe; 536XX = 3U VPX - Format 1; 526XX = 3U VPX - Format 2; 566xx = AMC ***Onyx form factors: 717xx = XMC; 727xx = 6U CPCI; 737xx = 3U cPCI; 747xx = 6U CPCI (Dual XMC); 787xx = Half-Length PCIe; 537XX = 3U VPX - Format 1; 527XX = 3U VPX - Format 2; 567xx = AMC
Example: Model 71660 72660 73660 74660 78660 53660 52660 56660 Description Cobalt Quad 200 MHz, 16-bit A/D with Virtex-6 FPGA Cobalt Quad 200 MHz, 16-bit A/D with Virtex-6 FPGA Cobalt Quad 200 MHz, 16-bit A/D with Virtex-6 FPGA Cobalt Octal 200 MHz, 16-bit A/D with Virtex-6 FPGAs Cobalt Quad 200 MHz, 16-bit A/D with Virtex-6 FPGA Cobalt Quad 200 MHz, 16-bit A/D with Virtex-6 FPGA Cobalt Quad 200 MHz, 16-bit A/D with Virtex-6 FPGA Cobalt Quad 200 MHz, 16-bit A/D with Virtex-6 FPGA Form Factor XMC 6U cPCI 3U cPCI 6U cPCI w/ Two XMCs x8 PCIe 3U VPX - Format 1 3U VPX - Format 2 AMC
Contact Pentek for the latest products and FPGA options.
Pentek, Inc.
www.pentek.com
Model 4994A
Pentek ReadyFlow - Board Support Package for LinuxTM

General Information
Users of high-performance data acquisition and signal processing boards often find themselves frustrated by the fact that when their new devices are delivered, they are unable to put them to immediate use. Because these boards are largely software controlled and offer a flexible range of functionality, a certain amount of programming is generally necessary to put the new cards through their paces. Then, if something does not go as planned, there is no way of knowing for sure whether the problem lies with the new code, or with the hardware itself. To address this issue, Pentek has developed the ReadyFlow BSPs (Board Support Packages) for all its board-level products. These packages: Provide a path for quick start-up through application completion Allow programming at high, intermediate and low levels to meet various needs Are illustrated with numerous examples Include complete documentation and definitions of all functions Include library and example source code most of the questions that occur with firsttime users of Pentek products. These programming examples will also help you get an immediate start on writing your own application without having to reinvent the wheel. They provide sample code that is known to work, giving you, the new user, a means of verifying that your board set is operational. ReadyFlow Board Support Packages are designed to reduce development time not only during the initial stages, but any time new hardware is added to the system. All packages are built with a consistent style and function-naming convention. Similar parameters on different boards have similar function calls, thereby allowing immediate familiarity with new hardware as its added further shortening the learning curve.
Command Line Interface

The Command Line Interface is a precompiled executable that runs the hardware right out of the box, without the need to write any code. Specific to the hardware features of the supported board, it allows operating arguments to be entered on the command line for controlling parameters such as: number of channels to enable, clock select, data transfer size, rate divider, interpolation, clock frequency, reference clock source, number of iterations to run the program, etc. An example command line for a D/A capable hardware module would look like this:
C:> dacmode -chan 1 -xfersize 32768 -loop 100000 -ratediv 2 -interpolate 4
Whats Included in the Package

In general, functions appropriate to the board-level product, such as: A How to section Build object libraries Compile and link application programs C-callable functions Initialization and test Data movement and communications Backplane I/O Mezzanine peripheral I/O Control of board resources Utilities Flash memory program loaders The package contains C-language examples that can be used to demonstrate the capabilities of Pentek products. The examples included provide the answers to
The Command Line Interface can be called from within a larger user application providing a convenient way to control the hardware. Operating parameters can be dynamically changed while the application is running to address changing application conditions. For command line functions that control data acquisition, the captured data can be saved in a host file or routed to the Signal Analyzer.
For the latest list of boards supported with ReadyFlow, visit our website at: www.pentek.com/readyflow
Pentek, Inc.
www.pentek.com
Model 4994A
Pentek ReadyFlow - Board Support Package for LinuxTM
Signal Analyzer*
When used with the Command Line Interface, the Signal Analyzer allows users to immediately start acquiring and displaying A/D data. A full-featured analysis tool, the Signal Analyzer displays data in time and frequency domains. Built-in measurement functions display 2nd and 3rd harmonics, THD (total harmonic distortion), and SINAD ( signal to noise and distortion). Interactive cursors allow users to mark data points and instantly calculate amplitude and frequency of displayed signals
Example, Model 71620

As an example of XMC module support, the BSP for the Cobalt Model 71620 Transceiver with three 200 MHz A/Ds, DUC (Digital Upconverter), and two 800 MHz D/As includes data structures and routines to support the following: PCIe Bus interface and DMA controller Board control registers Timing bus control and clock selection Triggering, gate enable and polarity Data input device management for the 200 MHz A/D Data output device management for the DUC and the 800 MHz D/A Built-in A/D Data Acquisition IP Modules Built-in D/A Waveform Playback IP Modules Built-in test waveform generator Interrupt generation and handling FPGA configuration Test modes and hardware revision codes Hardware voltage and temperature monitor
Model Description 4994A ReadyFlow - Board Support Package for Linux
Signal Analyzer and Command Line Interface supported on Cobalt series XMC, PCIe, VPX, and cPCI boards
* The signal viewer can only be run on an Intel PC running 32-bit Linux.
PowerPC Linux and Intel 64-bit Linux users have to run the viewer remotely on an Intel 32-bit Linux PC or on a 32- or 64-bit Windows PC.
Pentek, Inc.
www.pentek.com
Model 4995A
Pentek ReadyFlow - Board Support Package for Windows

General Information
Users of high-performance data acquisition and signal processing boards often find themselves frustrated by the fact that when their new devices are delivered, they are unable to put them to immediate use. Because these boards are largely software controlled and offer a flexible range of functionality, a certain amount of programming is generally necessary to put the new cards through their paces. Then, if something does not go as planned, there is no way of knowing for sure whether the problem lies with the new code, or with the hardware itself. To address this issue, Pentek has developed the ReadyFlow BSPs (Board Support Packages) for all its board-level products. These packages: Provide a path for quick start-up through application completion Allow programming at high, intermediate and low levels to meet various needs Are illustrated with numerous examples Include complete documentation and definitions of all functions Include library and example source code most of the questions that occur with firsttime users of Pentek products. These programming examples will also help you get an immediate start on writing your own application without having to reinvent the wheel. They provide sample code that is known to work, giving you, the new user, a means of verifying that your board set is operational. ReadyFlow Board Support Packages are designed to reduce development time not only during the initial stages, but any time new hardware is added to the system. All packages are built with a consistent style and function-naming convention. Similar parameters on different boards have similar function calls, thereby allowing immediate familiarity with new hardware as its added further shortening the learning curve.
Command Line Interface

The Command Line Interface is a precompiled executable that runs the hardware right out of the box, without the need to write any code. Specific to the hardware features of the supported board, it allows operating arguments to be entered on the command line for controlling parameters such as: number of channels to enable, clock select, data transfer size, rate divider, interpolation, clock frequency, reference clock source, number of iterations to run the program, etc. An example command line for a D/A capable hardware module would look like this:
C:> dacmode -chan 1 -xfersize 32768 -loop 100000 -ratediv 2 -interpolate 4
Whats Included in the Package

In general, functions appropriate to the board-level product, such as: A How to section Build object libraries Compile and link application programs C-callable functions Initialization and test Data movement and communications Backplane I/O Mezzanine peripheral I/O Control of board resources Utilities Flash memory program loaders The package contains C-language examples that can be used to demonstrate the capabilities of Pentek products. The examples included provide the answers to
The Command Line Interface can be called from within a larger user application providing a convenient way to control the hardware. Operating parameters can be dynamically changed while the application is running to address changing application conditions. For command line functions that control data acquisition, the captured data can be saved in a host file or routed to the Signal Analyzer.
For the latest list of boards supported with ReadyFlow, visit our website at: www.pentek.com/readyflow
Pentek, Inc.
www.pentek.com
Model 4995A
Pentek ReadyFlow - Board Support Package for Windows
Signal Analyzer
When used with the Command Line Interface, the Signal Analyzer allows users to immediately start acquiring and displaying A/D data. A full-featured analysis tool, the Signal Analyzer displays data in time and frequency domains. Built-in measurement functions display 2nd and 3rd harmonics, THD (total harmonic distortion), and SINAD ( signal to noise and distortion). Interactive cursors allow users to mark data points and instantly calculate amplitude and frequency of displayed signals.
Example, Model 71620

As an example of XMC module support, the BSP for the Cobalt Model 71620 Transceiver with three 200 MHz A/Ds, DUC (Digital Upconverter), and two 800 MHz D/As includes data structures and routines to support the following: PCIe Bus interface and DMA controller Board control registers Timing bus control and clock selection Triggering, gate enable and polarity Data input device management for the 200 MHz A/D Data output device management for the DUC and the 800 MHz D/A Built-in A/D Data Acquisition IP Modules Built-in D/A Waveform Playback IP Modules Built-in test waveform generator Interrupt generation and handling FPGA configuration Test modes and hardware revision codes Hardware voltage and temperature monitor
Model Description 4995A ReadyFlow - Board Support Package for Windows
Signal Analyzer and Command Line Interface supported on Cobalt series XMC, PCIe, VPX, and cPCI boards
Pentek, Inc.
www.pentek.com
Models 4996/4996A
Pentek VxWorks BSPs and Hardware Drivers

The Models 4996/4996A VxWorks BSPs provide software developers with a complete library of hardware initialization, control and application functions for Pentek PowerPC/Power Architecture processor baseboards, VME/VXS, PMC/XMC, VIM, and cPCI boards and modules. Used in conjunction with Wind Rivers Workbench software development environment, they speed application development by providing a high-level API for accessing all of the processor boards memory and communication resources, and control of the boards I/O interfaces and I/O modules. Processor specific functions found in the baseboard BSPs include: cache, DMA, SDRAM, interrupt, serial port, and timer control. Some general board functions include: reading and writing to mezzanine board FIFOs, VME/VXS, PMC/XMC, cPCI, and VIM I/O control, interprocessor communication, programming DMA reads and writes, programming interrupts, using mailboxes, managing RS-232 and ethernet interfaces, and control of optional Fibre Channel interfaces. The VxWorks BSPs are designed to reduce development time not only during the initial stages of software development, but any time new I/O hardware is added to the system. Hardware Drivers, each designed to control the specific hardware features of the I/O interface being used, are built with a consistent style and function naming convention. Similar parameters on different I/O modules have similar driver calls, thereby allowing immediate familiarity with new I/O hardware as its added. This can greatly shorten the application development learning curve when a system is modified or expanded.
Model Description 4996/4996A Pentek VxWorks BSPs and Hardware Drivers Contact Pentek for availability
Pentek, Inc.
www.pentek.com
VxWorks
Wind River Workbench / VxWorks for PowerPC

Wind Rivers Workbench development platform has dramatically improved embedded developers time-to-productivity. A component of Workbench, Workbench Tools, comprises a comprehensive suite of core and optional cross-development tools and utilities. The other integrated components of Workbench consist of the VxWorks run-time system, a high-performance scalable real-time operating system that executes on the target processor and a full range of communications options for the target connection to the host. Workbench Tools provides a highly visual and automated environment that accelerates the development of even the most complex VxWorks-based applications. At the heart of the VxWorks run-time system is the highly efficient Wind microkernel which supports a full range of real-time features. These include fast multitasking, interrupt support, and both preemptive and round-robin scheduling. The microkernel design minimizes system overhead and enables fast, deterministic response to external events.
Contact Wind River Systems at: www.windriver.com
Pentek, Inc.
www.pentek.com
SystemFlow Recording Software

General Information
The Pentek SystemFlow Recording Software provides a rich set of function libraries and tools for controlling and building Penteks real-time recording and data acquisition systems. These libraries ensure a consistent look and feel for developers across system families. SystemFlow software allows developers to configure and customize system interfaces and behavior. It includes API functions not only for the real-time data acquisition and playback functions, but also for the user-control software running on the host PC including the GUI. These API functions allow developers to either modify the sample code to meet their needs or use it as a reference for custom software development.

The SystemFlow GUI provides the user with a control interface for recording data. It includes Configuration, Record, Playback and Status screens, each with intuitive controls and indicators. The user can easily move between screens to set configuration parameters, control and monitor a recording, play back a recorded signal and monitor board temperature and voltage levels. The signal viewer, integrated into the recording GUI, allows the user to monitor real-time signals or recorded signals on disk.
Features
Complete turnkey recording and/or playback system software Software API for controlling data acquisition and recorder functions Graphical user interface Windows or Linux host One-year support included
Hardware Configuration Interface

The SystemFlow configuration screens provide a simple and intuitive means for setting up the system parameters. The DDC configuration screen shown here, provides entries for input source, center frequency, decimation, as well as gate and trigger information. All parameters contain limitchecking and integrated help to provide an easier-to-use out-of-the-box experience.
API Library Components

SystemFlow is based on a flexible client/server architecture. The host client application runs on a Windows or Linux platform and communicates with the server target application via a standard socket connection. In this way, server real-time recording and/or playback operations can be controlled from a local or remote host client. All servers use PC hardware running under Windows. The server application includes scheduling, task management, full control of data from Pentek software radio hardware, and drivers for communication with the hard disk arrays.
Hardware Configuration Interface

Recorder Interface The SystemFlow Signal Viewer includes a virtual oscilloscope and spectrum analyzer for signal monitoring in both the time and frequency domains. It is extremely useful for previewing live inputs prior to recording, and for monitoring signals as they are being recorded to help ensure successful recording sessions. The viewer can also be used to inspect and analyze the recorded files after the recording is complete. Advanced signal analysis capabilities include automatic calculators for signal amplitude and frequency, second and third harmonic components, THD (total harmonic distortion) and SINAD (signal to noise and distortion). With time and frequency zoom, panning modes and dual annotated cursors to mark and measure points of interest, the SystemFlow Signal Viewer can often eliminate the need for a separate oscilloscope or spectrum analyzer in the field.
Signal Viewer More information on pentek.com
Pentek, Inc.
www.pentek.com
Model 4986
Verari Systems Software VSI/Pro for PowerPC

The VSIPL (Vector, Signal and Image Processing Library) standard consists of definitions of over 500 scientific and engineering functions. It supports portable, high performance applications programming. The standard is based upon existing libraries that have evolved and matured over decades of computing. These include functions for linear algebra, signal processing (FFTs, windowing, filtering and convolution routines), image processing, scalar functionality, and vector and matrix view functionalities (scalar, unary, binary and ternary operations). The Verari Systems Software VSI/Pro is an implementation of VSIPL functions optimized specifically for the PowerPC and AltiVec architectures and is designed to be fully compliant with the emerging VSIPL standard. As a commercial implementation, VSI/Pro is the immediate step between the VSIPL standard and your own specialized software application. The library is compatible with Wind Rivers VxWorks real-time operating system and supports the ANSI C and C++ languages.
Model 4986 Description Verari Systems Software VSI/Pro
Pentek, Inc.
www.pentek.com
Placing an Order
When placing a purchase order for Pentek products, please provide the model number and product description. You may place your orders by letter, telephone, email or fax; you should confirm a verbal order by mail, email or fax. All orders should specify a purchase order number, bill-to and ship-to address, method of shipment, and a contact name and telephone number. U.S. orders should be made out to Pentek, Inc. and may be placed directly at our office address, or c/o our authorized sales representative in your area. International orders may be placed with us, or with our authorized distributor in your country. They have pricing and availability information and they will be pleased to assist you. Pentek must be notified of the defect or nonconformity within the warranty period. The affected product must be returned with shipping charges and insurance prepaid. Pentek will pay shipping charges for the return of product to buyer, except for products returned from outside the USA.
Limitations of Warranty
This warranty does not apply to products which have been repaired or altered by anyone other than Pentek or its authorized representatives. The warranty does not extend to products that have been damaged by misuse, neglect, improper installation, unauthorized modification, or extreme environmental conditions, that fall outside of the scope of the products environmental specifications. Due to the normal, finite write-cycle limits of Solid State Drives (SSDs), Pentek shall not be liable for warranty coverage of SSDs caused by wear-related issues that arise as an SSD reaches its write-cycle limit. Pentek specifically disclaims merchantability or fitness for a particular purpose. Pentek shall not be held liable for incidental or consequential damages arising from the sale, use, or installation of any Pentek product. Regardless of circumstances, Penteks liability under this warranty shall not exceed the purchase price of the product.
Prices and Price Quotations

All prices are F.O.B. factory in U.S. dollars. Shipping charges and applicable import, federal, state or local taxes, are paid by the purchaser. Were glad to respond to your request for price quotation just contact the corporate office, or your local representative. Price and delivery quotations are valid for 30 days, unless otherwise stated. Quantity discounts for large orders are available and will be included in our price quotation, if applicable.
Terms
Terms are Net 30 days for accounts with established credit; until credit is established, we require prepayment, or will ship C.O.D.
Extended Warranty
You may purchase an extended warranty on our boardlevel products for a fee of 1% of the list price per month of coverage, or 10% of the list price per year of coverage. All Pentek software products (excluding 3rd-party products) include free maintenance and free upgrades for one year. Extended software maintenance is available for one, two, and three years, starting after the first year.
Shipping
For new orders, we normally ship UPS ground with shipping charges prepaid and added to our invoice. If you are in a hurry, we will ship UPS Red, UPS Blue, FedEx, or the carrier of your choice, as you request.
Service and Repair

You must obtain a Return Material Authorization (RMA) before returning any product to Pentek for service or repair. RMA requests must be submitted online at: Return Material Authorization Form After the form is completed in its entirety and submitted, Pentek shall email you a receipt and start processing your request. Once your request has been approved, Pentek shall e-mail you an RMA number, shipping instructions, and a quotation if the product is out of warranty. Carefully package the product in its original packaging, if it is still available, and ship it to Pentek prepaid (if within the US) or free domicile DDP (if outside the US). Pentek shall not be responsible for loss or damage in shipment to Pentek, so you are strongly encouraged to insure the shipment for its full replacement value. When the work is completed, we will return the product to you along with a statement of work performed. Customer Service phone: 201-818-5900 fax: 201-818-5697 email: custsrvc@pentek.com
Order Cancellation and Returns

All orders placed with Pentek are considered binding and are subject to cancellation charges. Hardware products may be returned within 30 days after receipt, subject to a restocking charge. Before returning a product, please call Customer Service to obtain a Return Material Authorization (RMA) number. Software purchases are final and we cannot allow returns.
Warranty
Pentek warrants its products to conform to published specifications and to be free from defects in materials and workmanship for a period of one year from the date of delivery, when used under normal operating conditions and within the service conditions for which they were furnished. The obligation of Pentek arising from a warranty claim shall be limited to repairing or, optionally, replacing without charge any product which proves to be defective within the term and scope of the warranty.
www.pentek.com

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Last Updated: December 2013

Mission Statement Pentek Strategies

High-Speed Real-Time Recording Systems

boards with Freescale PowerPC engines Virtex FPGAs

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PRODUCT CATALOG CONTENTS

Last updated: December 2013

RAD AR & SDR I/O - PMC/XMC RADAR

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SDR SDR SDR SDR SDR SDR

I/O I/O I/O I/O I/O I/O

Last updated: November 2013

Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - PMC/XMC

A/D Converter Stage

Clocking and Synchronization

200 MHz 16 bit A/D

200 MHz 16 b t A/D

200 MHz 16 bit A/D

200 MHz 16 bit A/D

32 DDR2 SDRAM 512 MB

32 DDR2 SDRAM 512 MB

8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T

PMC P4 FPGA I/O (Option -104)

PCI-X BUS (64 Bits, 100 MHz)

P15 XMC VITA 42.x (Option -5xx)

Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - PMC/XMC

Optional PCI Express Interface

Contact Pentek for additional available options.

256-Channel DDC with four 200 MHz, 16-bit A/Ds - PMC

Decimation and Filtering

A/D Converter Stage Features

DDC Input Selection and Tuning

Output Multiplexers and FIFOs

200 MHz 16-bit A/D

200 MHz 16-bit A/D

200 MHz 16-bit A/D

CH 1 TIMING BUS GENERATOR CH 2 CH 3 CH 4

PCI-X INTERFACE Xilinx XC5VLX30T

256-Channel DDC with four 200 MHz, 16-bit A/Ds - PMC

Options: -702 L2 Extended temperature operation -730 Two-slot heat sink

Contact Pentek for additional available options.

32-Channel DDC with four 200 MHz, 16-bit A/Ds - PMC

Decimation and Filtering

A/D Converter Stage

DDC Input Selection and Tuning

Power Meters and Threshold Detectors

200 MHz 16-bit A/D

200 MHz 16-bit A/D

200 MHz 16-bit A/D

DIGITAL DOWNCONVERTER BANK 2: CH 9-16 DEC: 16 - 8192

PCI-X INTERFACE Xilinx XC5VLX30T

32-Channel DDC with four 200 MHz, 16-bit A/Ds - PMC

Clocking and Synchronization

Options: -730 Two-slot heat sink

Contact Pentek for additional available options.

4/2-Ch. DDC, four 200 MHz 16-bit A/Ds, Beamformer - PMC/XMC

Decimation and Filtering

A/D Converter Stage Features

DDC Input Selection and Tuning

200 MHz 16-bit A/D

AURORA G GAB T SERIAL INTERFACE

200 MHz 16-bit A/D

200 MHz 16-bit A/D