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VHDL Programming.pdf
Ratings: (0)|Views: 292|Likes: 0 Published by A B Shinde VHDL Programming Lab Programs See More

Digital System Design Department of Electronics Engg.,

P.V.P.I.T., Budhgaon

XOR GateDevice utilization Summary:

-------------------------Number of Slices: 1

out of 1200 0%Nu mber of 4 input LU Ts: 2 out of 2400 0 %Number of bonde d IOBs: 4 out of 96 4%

Simulation Waveform

Digital System Design Department of Electronics Engg.,

P.V.P.I.T., Budhgaon

-------Full Adder (Structural)-----library IEEE;use IEEE.STD_LOGIC _1164.ALL;use IEEE.STD_LOGIC

_ARITH.ALL;use IEEE.STD_LOGIC _UNSIGNED.ALL; entity f_adder isPort ( a : in std_logic;b : in std_logic;cin : in std_logic;sum : out std_logic;carry : out std_logic);end

f_adder;architecture structural of f_adder issignal s1, c1, c2: std_logic;componen t ha_adder isPort ( a : in std_logic;b : in std_logic;s : out std_logic;c : out std_logic);end

component;beginu1 : ha_adder port map(a, b, s1, c1);u2: ha_adder port map(s1, cin, sum, c2);carry<= c1 or c2;end structural;

Entity Level Diagram

Digital System Design Department of Electronics Engg., P.V.P.I.T., Budhgaon

Architectural Level DiagramDevice utilization summary: -------------------------Number of Slices: 1

out of 1200 0%Nu mber of 4 input LU Ts: 2 out of 2400 0 %Number of bonde d IOBs: 5 out of 96 5% Simulation Waveform

Digital System Design Department of Electronics Engg.,

P.V.P.I.T., Budhgaon

-------4 bit Full Adder (Structural)-----library IEEE;use IEEE.STD_LOGIC _1164.ALL;use

IEEE.STD_LOGIC _ARITH.ALL;use IEEE.STD_LOGIC _UNSIGNED.ALL; entity adder_4bit isPort ( a : in std_logic_vector(3 downto 0);b : in std_logic_vector(3

downto 0);cin : in std_logic;Sum : out std_logic_vector(3 downto 0);Cy : out std_logic);end adder_4bit;architect ure Behavioral of adder_4bit iscomponent

f_adder isPort ( a : in std_logic;b : in std_logic;cin : in std_logic;sum : out std_logic;carry : out std_logic);end component;signal c1, c2, c3:std_logic;beginu

1:f_adder port map(a=>a(0),b=>b( 0),cin=>cin,sum=> Sum(0),carry=>c1); u2:f_adder port map(a=>a(1),b=>b( 1),cin=>c1,sum=>S um(1),carry=>c2);u 3:f_adder port

map(a=>a(2),b=>b( 2),cin=>c2,sum=>S um(2),carry=>c3);u 4:f_adder port map(a=>a(3),b=>b( 3),cin=>c3,sum=>S um(3),carry=>Cy);e nd Behavioral;

Digital System Design Department of Electronics Engg., P.V.P.I.T., Budhgaon

Entity Level Diagram

Architectural Level DiagramDevice utilization summary: -------------------------Number of Slices: 5 out of 1200 0%Nu

mber of 4 input LU Ts: 9 out of 2400 0 %Number of bonde d IOBs: 14 out of 9 6 14% Simulation Waveform

Activity (1)
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