Unit05.Flip Flops English

Flip-flops
Luis Entrena, Celia Lpez, Mario Garca, Enrique San Milln
Universidad Carlos III de Madrid
Digital circuits and microprocessors

Inputs Output Functions Outputs
State Functions
State
Microprocessor
ALU
Combinational Sequential
Registers Control
RAM Peripherals ROM
Luis Entrena, Celia Lpez, Mario Garca, Enrique San Milln. Universidad Carlos III de Madrid, 2008
Outline
!!
Introduction
! The flip-flop as the basic memory element ! Flip-flop classification
!! !! !! !! !! !! !!
Asynchronous flip-flops Synchronous flip-flops Synchronous flip-flops with asynchronous inputs Flip-flop control logic Timing characteristics Synchronous circuits Circuits with flip-flops: chronograms
3
1. Introductin: flip-flops
!!
Definition:
! ! !
Circuit storing an information bit. It has two stable states, logic 0 and logic 1. The state does not change until the control inputs allow it. Control logic: inputs determining the new state
!!
Classification
! D, T, SR, JK
Syncronism:
! Asynchronous: can change the state in response to any input, at !

any time Synchronous: they have a control input that states when the state can change
! !
Level-triggered Edge-triggered
4
2. Asynchronous flip-flop
!!
SR asynchronous flip-flop
! S= 1 ! R= 1 ! S=R=
=> Set => Reset 0 => Keep state
0 1 0 1
On Off
S Q R
!!
Characteristics
! Memory: it keeps the state if !
inputs are not active Asynchronous: the state changes inmediately if R or S are activated
Asynchronous flip-flop
!!
State keeping circuit

1 0 0 1 Q 1 Two stable states 0
!!
With control signals

R Q
S 0 1 R 0 0 1 1 Q Q 1 0 0 /Q /Q 0 1 0 Keep state Set Reset Forbidden state
/Q S
0 1
3. Level-triggered synchronous flip-flop

!!
!!
It has a control signal that allows the state to be changed Level-triggered synchonous D Flip-flop (D-latch)
! C= ! C=
0
1 => state changes to D value 0 => keep state
D C
Q /Q
Q /Q
D C
C 0 1 1
D X 0 1
Q Q 0 1
/Q /Q 1 0 Keep state Assign 0 Assign 1
Edge-triggered synchronous flipflop

!!
Edge-triggered synchonous D flip-flop

LATCH
Q /Q
Edge detector
D C
Q /Q
tp,inv Clk
Clk
Edge detector
Clk
/Clk C
Bad solution due to technology. Inverter delay is not controllable.
Master-Slave synchronous flipflop

!!
Two latches active with opposite levels

Clk
Master Slave Master Slave
MASTER
SLAVE
D C
QM
D C
QE = Q
Clk D QM QE
!!
!!
QE changes only in clock rising edges QE new value is D value just before the clock edge
9
Edge triggered synchonous D flipflop

!! !!
!!
!!
The one used most Only changes in clock edges (normally rising edges) The output change takes place just before the edge The output new value is taken from D input just before the edge
Clk D Q
Clk D Q
10
4. Synchronous flip-flops with asynchronous inputs

!!
Synchronous flip-flops with asynchronous inputs for initialization
preset
! ! !
Clear: asynchronous initialitation to 0 Preset: asynchronous initialitation to 1 Usually low-level active
Q /Q
clear
preset clear Clk D Q
11
5. Flip-flop control logic

!!
Flip-flop inputs control the way the state is changed
! Kinds of flip-flops depending on the inputs: ! Enable signal:

! D,T,JK,SR ! Allows/prevents the state to change ! In nof enabled, the state is kept ! Set to
0 ir 1 in a synchronous way
! Synchronous initialization
12
Flip-flop control logic

!!
Working tables
D flip-flop (Data) D 0 1 Q 0 1
! Describe functionality
T flip-flop (Toggle) T 0 1 Q Q /Q
SR flip-flop (Set-Reset) S 0 0 1 R 0 1 0 Q Q 0 1
JK flip-flop (Jump & Kill) J 0 0 1 1 D flip-flop K 0 1 0 1 Q Q 0 1 /Q T flip-flop T 0 0 1 1 Q 0 1 0 1 Q 0 1 1 0

13
!!
Transition tables
! Describes the new state in

terms of the present state and input values
D 0 0 1 1
Q 0 1 0 1
Q 0 0 1 1

!!
Flip-flops with enable

D Q E /Q
D flip-flop E 0 1 1 D X 0 1 Q Q 0 1 T flip-flop E 0 1 1 D X 0 1 Q Q Q /Q
Q E /Q
D E
0 1
Q /Q
T E
Q /Q
14

!!
Flip-flop with synchronous initialization
! Set: forces 1 ! Reset: forces
!!
Example: D flip-flop with Enable, Set and Reset
! Priority: Reset, Set, Enable

D E /S /R Q
D E /S /R
0 1
Q /Q
15
6. Timing characteristics
!!
Timing flip-flop restrictions
! Clock level length ! (t0min,t1min) ! Asynchronous signals length ! (treset min) ! Data insertion times! (tsetup,thold)
(treset mn) (tomn,t1mn)
clear clk D Q
(tsetup,thold)
16
7. Synchronous circuits
!!
Synchronous circuit
! ! !
Every flip-flop use the same clock Every flip-flop is triggered by the same clock edge (usually the rising edge) There is a common initialization signal called Reset
Q /Q
Q /Q
Q /Q
Clk Reset
17
Synchronous circuits: the clock cycle

!!
Critical path:
! Path between two flip-flops with the larger delay ! Slowest path between two flip-flops. It determines the
maximum allowable clock frequency for the circuit.
Clk tClk tClk > thold + tcrtico + tsetup fClk = 1 / tClk tClk = 1ns ! fClk = 1GHz
Luis Entrena, Celia Lpez, Mario Garca, Enrique San Milln. Universidad Carlos III de Madrid, 2008 18
thold
tcrtico
tsetup
7. Chronograms
!!
Edge detector
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Chronograms
!!
Counter
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Bibliography
!!
!!
!!
Circuitos y Sistemas Digitales. J. E. Garca Snchez, D. G. Toms, M. Martnez Iniesta. Ed. Tebar-Flores Electrnica Digital , L. Cuesta, E. Gil, F. Remiro, McGraw-Hill Fundamentos de Sistemas Digitales , T.L Floyd, Prentice-Hall
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Flip-flops

Luis Entrena, Celia Lpez, Mario Garca, Enrique San Milln

Universidad Carlos III de Madrid

Digital circuits and microprocessors

RAM Peripherals ROM

! The flip-flop as the basic memory element ! Flip-flop classification

! Asynchronous: can change the state in response to any input, at !

=> Set => Reset 0 => Keep state

! Memory: it keeps the state if !

State keeping circuit

With control signals

3. Level-triggered synchronous flip-flop

1 => state changes to D value 0 => keep state

/Q /Q 1 0 Keep state Assign 0 Assign 1

Edge-triggered synchronous flipflop

Edge-triggered synchonous D flip-flop

Bad solution due to technology. Inverter delay is not controllable.

Master-Slave synchronous flipflop

Two latches active with opposite levels

Edge triggered synchonous D flipflop

4. Synchronous flip-flops with asynchronous inputs

Synchronous flip-flops with asynchronous inputs for initialization

Clear: asynchronous initialitation to 0 Preset: asynchronous initialitation to 1 Usually low-level active

preset clear Clk D Q

5. Flip-flop control logic

Flip-flop inputs control the way the state is changed

! Kinds of flip-flops depending on the inputs: ! Enable signal:

Flip-flop control logic

JK flip-flop (Jump & Kill) J 0 0 1 1 D flip-flop K 0 1 0 1 Q Q 0 1 /Q T flip-flop T 0 0 1 1 Q 0 1 0 1 Q 0 1 1 0

! Describes the new state in

Flip-flop control logic

Flip-flops with enable

Flip-flop control logic

Flip-flop with synchronous initialization

! Set: forces 1 ! Reset: forces

Example: D flip-flop with Enable, Set and Reset

! Priority: Reset, Set, Enable

Timing flip-flop restrictions

Synchronous circuits: the clock cycle

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