Assignment 5 EE671(VLSI Design) Timing Analysis By Fadadu Jaydip Ramnikbhai Roll No.

133070045 (1) Flip-flop characterization

For flip-flop characterisation following type of data pulse is applied.

For set-up of 92 ps and hold time of 10 ps flip-flop is able to flip output from 1 to 0 as shown in below figure.

Set-up time = 92 ps Hold = 10 ps

However delay of flip-flop is more and flip-flop takes almost 500ps to reach steady state value. This is not acceptable so I kept increasing set up time till there was not significant improvement in delay. All cases are shown below

Set-up = 93 ps Hold=10 ps

Set-up = 94 ps Hold=10 ps

Set-up = 95 ps Hold=10 ps

Set-up = 96 ps Hold=10 ps As observed above as I increase set-up time further more delay is not improving significantly. So we can finalize set-up as 95-96 ps. Now if I decrease hold time we observe following scenario.

Set-up = 96 ps Hold =10 ps

Set-up = 96 ps Hold = 9 ps

Set-up = 96 ps Hold=8 ps Thus if I decrease hold time make less than 8 ps delay is increasing. So we can finalize hold time as 9-10 ps. Same procedure was applied for positive pulse and set-up and hold time were found to be 52 ps and 9 ps

Set-up = 52 ps Hold=9 ps Taking worst case set-up time of flip-flop is 96 ps and hold time is 9 ps.

(2)

Block diagram of carry look ahead adder

Fig. 1 Block diagram of carry look ahead adder Here objective here is to construct adder such that (1) (2) (3) (4) (5) (6) Input capacitance is less than 10fF Output capacitance that accumulator needs to drive is 20fF Output should be settled within 1ns of rising edge Circuit should be realized using 2 input NAND gates only Flipflop used should have input capacitance of 15 Multiplexer is tri-state mux.

Now logic inside each block is as shown below.

(1) Single bit p and g signal

Fig 2. Single bit propagate and generate

(2) Group generate

GG= G3 + P3G2 + P3.P2.G1. + P3.P2.P1.G0

Fig 3 Group generate using 2 input nand gate only

(3) Group Propogate

PG = P3.P2.P1.P0

Fig 4 group propogate

(4) Carry look ahead block C1 = G0 + P0.C0 C2 = G1 + P1C1 = G1 + P1G0 + P1P0C0 C3 = G2 + P2G1 + P2P1G0 + P2P1P0C0 Equation to generate is similar to that of GG. So circuit is same for both. To make delay equal of all pathes (to minimize hazards in circuit) C1 and C2 are also realised with same circuit topology by making input of 4 input NAND gate zero.

(3)

Critical path in circuit

Fig. 5 critical path Critical path is shown in fig. 5.

The circuit of critical path is shown below.

Fig 6. critical path As mentioned by sir in class all NAND gates are kept of same size. So all inverters are working with electrical effort of 1. Logical effort is also 1. So all inverters are adding fixed delay of (1+p) There are total 19 stages in critical path. Flip-flop is presenting capacitance of 15 , that is 3.64 fF. Now input capacitance is to be kept less than 10fF. Lets design for 1fF. So H=3.64 Total branching in ciruit, B=2*3*6*3*3*2*2=1296 G=( )

So F=GBH=1.67469e+6

So stage effort

Taking this stage effort input capacitance of all stage is shown in fig 7

Fig 7. Sizing in critical path Here maximum size of nand gate is 8.8 . So size of nand size is 4.4 Nearest integer to 4.4 is 4 . So size of nand gate is kept Input capacitance of inverter at maximum is 8 So size of inverter is 8/3 = 2.66 Nearest integer is 3 . So size of inverter is kept 3 in NGSPICE.

(6) Simulation in NGSPICE

Clock to Q delay is maximum of 650 ps for critical path as shown below.

Fig 8 clock and output 15 showing maximum delay

Minimum clock for which circuit works correctly is around 1.3 ns. Along critical path maximum delay is arround 1.1 ns so minimum clock period for which circuit works correctly is 1.1ns + set up time. So arround 1.2ns.

Fig 9 maximum delay in critical path

Accumulator gives correct output for different input as shown below. Different combinations of input A (1) For A=0x0010

Fig 10 out(0-7) and clock for A= 0x0010

Fig 11 out(8-15) and clock for A= 0x0010

(2) A=0x0100

Fig 12 out(0-7) and clock for A=0x0100

Fig 13 out(8-15) and clock for A=0x0100

(3) A=0x1000

Fig 14 out(0-7) and clock for A=0x1000

Fig 15 out(8-15) and clock A=0x1000

(4) A=0x000f

Fig 16 out(0-7) and clock for A=0x000f

Fig 17 out(8-15) and clock for A=0x000f

(9) FLOOR PLAN

Fig 18 floor plan of accumulator

(10) Realization of circuit in magic

This circuit is realized in magic layout tool as shown below. However this is only partially realized. All important blocks are realized and complete circuit can be made by just repeating these blocks. Block 1: single bit p and g

Fig 19 single bit p and g in magic

Block 2: Group propogate

Fig 20 group propogate

Block 3: Group generate (can be used to generate carry C3, C2 and C1 also)

Fig 21 group generate

Partially realized layout of accumulator is as shown below. Output is shown only for 4 bits. By repeating the same blocks 16 bits can be realized.

Fig 22 Accumulator in magic layout tool