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Solution to Assignment 3 EE671 (VLSI Design) By Roll No 133070045(Fadadu Jaydip Ramnikbhai)

1.
Here the value of delay for different K value is as follows K 2 4 6 8 Delay (ps) 57 83 108 132

So from above data if we plot the graph of delay vs K then it is as follows.

Fig 1 delay(fs) vs k In above figure the black part of graph is not based on experimental data it is just the stretched graph till k=0. Now from the data slope for different segments of k Slope between k=2 and k=4 is Slope between k=4 and k=6 is Slope between k=6 and k=8 is So, average slope is 12.5. = 13. = 12.5. = 12

Now intercept with Y-axis is P = 57-12.5*2 = 32 ps Thus in this case = 12.5ps and = 32ps. In terms of , is 2.56.

2.
Here at input side the list of capacitances that appears is as follows. 1. Oxide capacitance 2. Gate source overlap capacitance 3. Gate drain overlap capacitance Now as given in the model file Oxide thickness So = = 8.418 mF/ Given data for NMOS For PMOS We have W=28.8 L=180nm

So total input capacitance

So The simulated value is 233fF. thus calculated and simulated value matches to some extent.

3.
We can approximate from the transfer characteristics that there are two unity gain points. One point is when is greater than and vice versa.

For the first case as drain voltage of NMOS is less than gate voltage we can predict that NMOS is in triode region and as drain to source voltage of PMOS is very high, PMOS is in saturation region. Current through both the transistor is same so ( Now as It is given that So rewriting the equation ( ) ( )( ) ( ) ..(2) ) [ ( and ) , ](1)

Simplifying the above expression yields

So now to find ( ) (

in the equation (2) ) ( )

( So And

In the same way taking the NMOS in saturation and PMOS in triode region we can find another unity gain point . At this point is 0.9V less than input voltage (contrary to above case where is 0.9V greater than input). From above method we can easily derive that and

4.
Here we want H=1000/10=100 We will use xor and xnor gate as follows.

Fig 2. xor gate that is used in design. From above figure the logical effort is 2. Xnor gate topology is also same and logical effort for xnor gate is also 2. But to use above topology we require true and complement value of each input. We will use fork for that. Branching is happening at two places because xor and xnor gate needs same input. Because circuit is symmetric at both branching point effort is 2. So G=1 H=100 B=2 =4 =8

If we take N=6 then the stage effort

Thus stage effort is coming near to value of 4. So six stages are acceptable. So we have to add 2 inverters at end. Now circuit topology looks like below.

Fig 3 Circuit topology one path of interest only is shown Now we will decide the size of inverters. For that we need the input capacitance that should be presented at each node. We can find input capacitances from stage effort . For inverter 5

So inverter 5 should present 260 input capacitance. Now if inverter is of size then the input capacitance is 1.

In the same way for inverter 4

So size of inverter 4

For xor 3

Now for xor gate we are using NMOS of 2W and PMOS of 4W. Thus size of PMOS is two times that of NMOS. This is identical to inverter. So for same input capacitance the size of NMOS will be same 3 times that of input capacitance. So size of NMOS in xor 3 is

And

For xor 2

In the same way as above

Now the thing is not straight forward because there is branching so out capacitance that xor 1 has to drive is not same as input capacitance represented by the xor 2. Xor 2 gate is driving xor 3 as well as xnor 3 So So for xor 1 =2*18.23=36.46

So size of xor 1

Now we reached the fork network.

Fig 4 input capacitances at different nodes As discussed above the output capacitance that each leg of fork has to drive is 38 So total electrical effort of fork is = 2*38/10 = 7.6 So we can design fork as 2:1 fork. Now to decide As calculated in solution 1 =2.56

Solving above equation by putting this values we get =0.48 So input capacitance represented to leg with one inverter is

So now the diagram with input capacitances is as follows

Fig 5 fork network and input capacitances at different node Now in unit the total delay of our circuit is D=

= 6*3.84 + 2.56*16 = 64 Now as shown below simulated value of delay is comes out to be 634.16 ps So simulated value of delay in terms of unit is

Above circuit is realised in NGSPICE. The netlist is shown below

Parity bit generator * lambda parameter value for the 180nm technology .param lambda=90n * include the SPICE model. .include tsmc_spice_180nm.txt

* definition of a sub circuit for

a single inverter

.subckt inv INx OUTx VDDx VSSx W_inv=10 .param Wn={W_inv*lambda} .param Wp={2*W_inv*lambda} * The entire device description should be on one line. * NGSPICE seems to have a bug due to which this line * cannot be split. MP1 OUTx INx VDDx VDDx cmosp L={2*lambda} W={Wp} PD={2*Wp+10*lambda} PS={2*Wp+10*lambda} AD={5*lambda*Wp} AS={5*lambda*Wp} MN1 OUTx INx VSSx VSSx cmosn L={2*lambda} W={Wn} PD={2*Wn+10*lambda} PS={2*Wn+10*lambda} AD={5*lambda*Wn} AS={5*lambda*Wn} .ends inv *subcircuit of xnor .subckt xnor INx INbarx INy INbary OUTx VDDx VSSx W_xor=10 .param Wnxor={W_xor*lambda} .param Wpxor={2*W_xor*lambda} MP1 OUTx INbarx mid2x VDDx cmosp L={2*lambda} W={Wpxor} PD={2*Wpxor+10*lambda} PS={2*Wpxor+10*lambda} AD={5*lambda*Wpxor} AS={5*lambda*Wpxor}

MN1 OUTx INx mid1x VSSx cmosn L={2*lambda} W={Wnxnor} PD={2*Wnxnor+10*lambda} PS={2*Wnxnor+10*lambda} AD={5*lambda*Wnxnor} AS={5*lambda*Wnxnor} MN2 mid1x INy VSSx VSSx cmosn L={2*lambda} W={Wnxnor} PD={2*Wnxnor+10*lambda} PS={2*Wnxnor+10*lambda} AD={5*lambda*Wnxnor} AS={5*lambda*Wnxnor} MN3 OUTx INbarx mid1y VSSx cmosn L={2*lambda} W={Wnxnor} PD={2*Wnxnor+10*lambda} PS={2*Wnxnor+10*lambda} AD={5*lambda*Wnxnor} AS={5*lambda*Wnxnor} MN4 mid1y INbary VSSx VSSx cmosn L={2*lambda} W={Wnxnor} PD={2*Wnxnor+10*lambda} PS={2*Wnxnor+10*lambda} AD={5*lambda*Wnxnor} AS={5*lambda*Wnxnor} .ends xor *original inputs are in01 to in08 and true and complemented output *are named as in1 to in8 and inbar1 to inbar8 *fork for input 1 xinv111 in01 inbar1 Supply 0 inv W_inv=14.4 xinv121 in01 mid121 Supply 0 inv W_inv=15.6 xinv122 mid121 in1 Supply 0 inv W_inv=42

*fork for input 2 xinv211 in02 inbar2 Supply 0 inv W_inv=14.4 xinv221 in02 mid221 Supply 0 inv W_inv=15.6 xinv222 mid221 in2 Supply 0 inv W_inv=42

*fork for input 3 xinv311 in03 inbar3 Supply 0 inv W_inv=14.4 xinv321 in03 mid321 Supply 0 inv W_inv=15.6 xinv322 mid321 in3 Supply 0 inv W_inv=42

*fork for input 4

xinv411 in04 inbar4 Supply 0 inv W_inv=14.4 xinv421 in04 mid421 Supply 0 inv W_inv=15.6 xinv422 mid421 in4 Supply 0 inv W_inv=42

*fork for input 5 xinv511 in05 inbar5 Supply 0 inv W_inv=14.4 xinv521 in05 mid521 Supply 0 inv W_inv=15.6 xinv522 mid521 in5 Supply 0 inv W_inv=42

*fork for input 6 xinv611 in06 inbar6 Supply 0 inv W_inv=14.4 xinv621 in06 mid621 Supply 0 inv W_inv=15.6 xinv622 mid621 in6 Supply 0 inv W_inv=42

*fork for input 7 xinv711 in07 inbar7 Supply 0 inv W_inv=14.4 xinv721 in07 mid721 Supply 0 inv W_inv=15.6 xinv722 mid721 in7 Supply 0 inv W_inv=42

*fork for input 8 xinv811 in08 inbar8 Supply 0 inv W_inv=14.4 xinv821 in08 mid821 Supply 0 inv W_inv=15.6 xinv822 mid821 in8 Supply 0 inv W_inv=42

*stage of tree one xor11 in1 inbar1 in2 inbar2 in11 Supply 0 xor W_xnor=57

xnor11 in1 inbar1 in2 inbar2 inbar11 Supply 0 xnor W_xor=57

xor12 in3 inbar3 in4 inbar4 in12 Supply 0 xor W_xnor=57 xnor12 in3 inbar3 in4 inbar4 inbar12 Supply 0 xnor W_xor=57

xor13 in5 inbar5 in6 inbar6 in13 Supply 0 xor W_xnor=57 xnor13 in5 inbar5 in6 inbar6 inbar13 Supply 0 xnor W_xor=57

xor14 in7 inbar7 in8 inbar8 in14 Supply 0 xor W_xnor=57 xnor14 in7 inbar7 in8 inbar8 inbar14 Supply 0 xnor W_xor=57

*second stage of tree xor21 in11 inbar11 in12 inbar12 in21 Supply 0 xor W_xnor=54.69 xnor21 in11 inbar11 in12 inbar12 inbar21 Supply 0 xnor W_xor=54.69

xor22 in13 inbar13 in14 inbar14 in22 Supply 0 xor W_xnor=54.69 xnor22 in13 inbar13 in14 inbar14 inbar22 Supply 0 xnor W_xor=54.69

*final stage xor31 in21 inbar21 in22 inbar22 out1 Supply 0 xor W_xnor=105 *inverters xinvfinal1 out1 out2 Supply 0 inv W_inv=201 xinvfinal2 out2 out Supply 0 inv W_inv=780

coutcap out 0 2184f *load capacitance equivalent to 3000 units * the pulse waveform vinto1 in01 0 pwl(0 0v 450ps 0v 500ps 1.8v 2950ps 1.8v 3000ps 0v) vinto2 in02 0 dc 1.8v

vinto3 in03 0 dc 0v vinto4 in04 0 dc 0v vinto5 in05 0 dc 0v vinto6 in06 0 dc 0v vinto7 in07 0 dc 0v vinto8 in08 0 dc 0v

*ANALYSIS .tran 10p 7ns .control *give command plot v(out) v(in01) to observe the output .end