Lab Title

Lab Partner Names, Name 2, Name 3

Department of Electrical and Computer Engineering, University of Connecticut, Storrs, Connecticut 06269

Abstract. Introduction. Report goes heresince power consumption is proportional to the square of the supply voltage. However, decreasing the supply voltage results in undesirable effects such as greater propagation delays and noise levels4. In an effort to reduce these undesirable effects, as well as maintain high drive current, threshold voltages of MOSFETs have been lowered5. However, low threshold voltages result in significant subthreshold conduction in the MOSFETs, causing substantial power dissipation in the OFF state. Therefore, it is of interest to reduce leakage current in order to minimize standby power dissipation. Methods used to reduce leakage current have the drawback of also reducing the drive current, so a compromise must be made between the leakage and drive currents to achieve an optimum device. Procedure. In this work, we use Sentaurus simulation tools6 to improve the design of an n-channel MOSFET so that its leakage current decreases by at least two decades, drive current degrades by no more than 20%, and gate length is not varied by more than 10%. Table 1 indicates the target values for the improved device. [Figures go here, then Tables; labels and captions go below the graphic]
_1ine is for spacing /formatting purposes

also results in increased tunneling through the oxide from the substrate to the gate, so leakage current increases as well 7. Figure 3 shows the results of a simulation experiment in which oxide thickness is varied from 1 nm to 2 nm while all other parameters are kept constant. For a 40 $ decrease in oxide thickness, there is relatively large increase (~20%) in
this_1ine is for spacing /formatting purposes

0 &nerg' (meV)

saturati)n m)*e

90 nm

%250

50 nm

%500 %100

%50

0 ( (nm)

50

100

FIG. 1. Sentaurus simulation results showing conduction band edge versus distance along the channel for nMOSFETs with gate lengths 50 nm and 90 nm. VD = 1.2 V, VG = 0 V.

Leakage Current (nA) Original Device Target Values

121.0 1.21

Drive Current (mA)

Table 1. Design specifications

-D (A)

1.059 0.!"#

Discussion and Conclusions. MOSFETs with shorter gate length suffer from the effect known as drain induced barrier lowering (DIBL). A shorter gate length results in a thinner energy barrier at the source / substrate / drain interface, so the greater electric field from the drain bias causes the barrier to be lowered further7 (Fig. 1). Thus, it is easier for electrons to overcome this barrier, so there is more leakage current in MOSFETs with shorter gate lengths. However, MOSFETs with longer gate length have less drive current due to the increased channel length which results in higher channel resistance7. Figure 2 shows the results of a simulation experiment in which gate length is varied from 45 nm to 55 nm while all other parameters are kept constant. Increasing gate length by 5 nm results in a ~9x reduction in leakage current and only a ~9% decrease in drive current. From these results, we conclude that the benefits from increasing gate length outweigh the drawbacks, and thus it is beneficial to increase gate length. Oxide thickness has a significant effect on threshold voltage. Decreasing oxide thickness results in higher capacitive coupling between the gate and substrate, which yields better electrostatic control of the channel 7. This allows the channel to be inverted at lower voltages, which results in higher drive current. However, decreasing oxide thickness

1&%, 1&%" 1&%5 1&%+ 1&%# 1.2

L. / "5 nm

55 nm

-D (mA)

0.9 0.+ 0., 0.0 0.0 0.2

L. / "5 nm

55 nm

0." 0.+ V. (V)

0.!

1.0

FIG. 2. Sentaurus simulation results showing transfer characteristics in logarithmic (top) and linear (bottom) scales. Gate length is varied from 45 nm to 55 nm while all other parameters are kept constant.

[Dont forget conclusion paragraph!]