Mp&i Course File - Unit-I

Microprocessors & Interfacing
MICROPROCESSORS AND INTERFACING UNIT - I By Mr. R. VENKATESH [Asst. Prof, Dept. of Electronics & Communication Engineering]
DEPT. OF ECE, SITS, KHAMMAM
PREPARED BY VENKATESH RACHA
Microprocessors & Interfacing COURSE OBJECTIVE The course provides an in-depth understanding of the operation of
microprocessors and microcontrollers, machine language programming & interfacing techniques. This course is designed to impart professional training to the students engineering, objective of to interface course and is build to microprocessors students and Microcontroller and based of applications involving inter facing of 8255 with 8086 and serial communication. The this teach design interfacing microcontroller-based embedded systems. Further the students will be able to program in both assembly and C languages oriented and fashion understand so that the impact of have computer a basic hardware on of software various use the programming. The student will be taught the course in a realistic, real-worldthe students understanding how constraints in embedded systems. It teaches the students is to
microcontrollers as a means to integrate the curriculum so that our students gain a comprehensive view of various topics they have learned in their previous years. The new course blends the lectures and the labs together, and emphasizes hands-on, active learning with labs and projects. This approach allows all engineering students the opportunity to learn to use the microprocessor as a tool for solving engineering monitoring and control problems. The approach consists of shifting the focus of the course from the microprocessor itself to learning the design methodology by which the microprocessor could be used as a tool to solve practical engineering problems. This course is intended as a first level course for microprocessor and
microcontroller based system design. Designer of microprocessor system must have a thorough understanding of hardware, software and system integration. In view of this, various aspects of hardware design, such as interfacing of memory and different types of I/O devices, will be covered in details. As it is customary to write software in machine or assembly language for embedded system applications, laboratory assignments will be on assembly language programming of 8086 and 8051. The students will also learn to use development aids, such as a assembler and simulator to perform software development, hardware development and hardware-software integration. Finally, each batch of students will implement a
complete microcontroller-based system as part of the lab assignment.
Microprocessors & Interfacing SYLLABUS MICROPROCESSORS AND MICROCONTROLLERS UNIT-I 8086 Architecture: Introduction to 8085 Microprocessor, 8086 Architecture Functional diagram, Register organization, Memory segmentation, Programming model, Memory address, Physical Memory organization, Architecture of 8086, Signal description of 8086 common function signals, Minimum and Maximum mode signals, Timing diagrams, Interrupts of 8086. UNIT-II Instruction set and Assembly language programming of 8086: Instruction formats, addressing modes, Instruction set, assembler directives, macros, simple programs involving logical, branch and call instructions, sorting, evaluating arithmetic expressions, string manipulations. UNIT-III I/O Interface: 8255 PPI various modes of operation and interfacing to 8086. Interfacing Keyboard, Displays, 8279 Stepper Motor interfacing, D/A and A/D converter interfacing. UNIT-IV Interfacing with advanced devices: Memory interfacing to 8086, interrupt structure of 8086, Vector interrupt table, Interrupt service routines, Introduction to DOS and BIOS interrupts, interfacing of interrupt controller 8259, DMA controller 8257 to 8086 UNIT-V Communication Interface: serial communications standards, Serial data transfer schemes, 8251 USART architecture and interfacing, RS 232, IEEE-488, Prototyping and trouble shooting. UNIT-VI Introduction to Microcontrollers: Over view of 8051 Microcontroller, Architecture, I/O Ports, Memory organization, addressing modes and instruction set of 8051, simple programs. UNIT-VII 8051 Real Time Control: Interrupts, timer/counter and serial communication, Programming Timer interrupts, Programming external hardware interrupts, Programming serial communication interrupts, Programming 8051 Times and counters.
Microprocessors & Interfacing UNIT-VIII The AVR RISC microcontrollers architecture: Introduction, AVR family architecture, Register file, The ALU, memory access and instruction execution, I/O memory. EEPROM, I/O ports, Timers, UART and Interrupt Structure. TEXT BOOKS: 1. Kenneth J Ayala, The 8051 Micro Controller Architecture, and Applications, Thomson Publishers, 2 Edition. nd 2. D. V.Hall, Micro Processor and Interfacing , Tata McGraw-Hill. REFERENCE BOOKS: 1. Ajay V. Deshmukh, Microcontrollers theor y applications, Tata McGraw-Hill Companies 2005. 2. Ray and BulChandi, Advanced Micro Processors, Tata McGraw-Hill. 3. Kenneth J Ayala, The 8086 Micro Processors Architecture, Programming and Applications, Thomson Publishers, 2005. 4. Micr ocomputer Systems: The 8086/8088 Family: Architecture, Programming and Design, 2 4. ed., Liu & Gibson Programming
INTRODUCTION In December 1970, Gilbert Hyatt filed a patent application entitled Single Chip Integrated Circuit Computer Architecture, the first basic patent on the microprocessor. The microprocessor was invented in the year 1971 in the Intel labs. The first processor was a 4 bit processor and was called 4004.The following table gives chronologically the microprocessor revolution. Microproces sors 4004 8008 8080 8085 8086 Year of Introduc tion 1971 1972 1973 1976 1978 Word Length 4 bits 8 bits 8 bits 8 bits 16 bits 8/16 bits 16 bits 16 bits 32 bits 16/32 bits 32 bits Memory Addressi ng 1KB 16KB 64KB 64KB 1 MB
Pins 16 18 40 40 40
Clock 750KHz 800KHz 2 MHz 3-6 MHz 5-10 MHz
Remarks Intels 1st P Mark-8 used this; 1st computer for the home. 6000trs, Altair1st PC Popular IBM PC, Intel became one of fortune 500 companies. PC/XT More a Microcontroller PC/AT, 15 million PCs sold in 6 years 2,75,000 transistors 32b int 16b ext Flaot pt cop, Command line to point and click 2 intr. At a time, Process real world data like sound, hand written and photo images. Speedy CAD
8088 80186 80286 80386DX 80386SX
1980 1982 1982 1985 1988
1MB 1 MB 16 MB real, 4GBv 4GB real, 64TBv 16MB real, 64TBv 4 GB real, 64TBv
40 68 68 132 PGA 100 168 PGA
5-8MHz 5-8MHz 60-12.5MHz 20-33MHz 20MHz
80486DX
1989
25-66MHz
Pentium
1993
64 bits
4 GB, 16 KB cache 64Gb, 256K/512 K L2 Cache
237 PGA
60-200 MHz
Pentium Pro
1995
64 bits
387 PGA
150MHz
Microprocessors & Interfacing Capture, edit & share digital photos via Internet Workstations thriving on business applications
Pentium II
1997
64 bits
64Gb
242
400MHz
Pentium II Xeon
1998
64 bits
512k/1M/ 2M L2 cache 16 k L1 data + 16 k L1 instr; 512 kB/1 MB/2 MB L2 514,864 KB 8 MB iL3 cache 2MB/ 4MB L3 cache 1.5 9MB L3 cache
528 pins LGA
400MHz
Pentium III Xeon
1999
64 bits
370 PGA
1GHz
e-commerce applications
Pentium 4
2000
64 bits
423 PGA
1.3 - 2GHz
Xeon
2001
64 bits
3.33 GHz 418 pins FCPGA 611 pins FCPGA
Itanium
2001
64 bits
800 MHz
1.5 GHz, Professional quality movies, rendering 3D graphics. Choice of operating system Enabling ecommerce security transactions Business applications Mobile specific, increased battery life. Hyper threading technology, games 90nm,2MB L2 cache400MHz power-system optimized system bus
Itanium 2 Centrino mobile Pentium 4 processor extreme Centrino M (mobile)
2002
64 bits
200 MHz
2003
64 bits 2 MB L2 cache 423 pins PGA
2003
64 bits
3.80 GHz
2004
64 bits
COMPUTER AND ITS ORGANIZATION A Computer is a programmable machine. It responds to a specific set of instructions in a well-defined manner. It can execute a prerecorded list of instructions (a program ).Modern computers are electronic and digital. The actual machinery wires, transistors, and circuits is called hardware. The instructions and data are called software. All general-purpose computers require the following hardware components: Memory: Enables a computer to store, at least temporarily, data and programs. Mass storage device: Allows a computer to permanently retain large amounts of data. Common mass storage devices include disk drives and tape drives. Input device: Usually a keyboard and mouse are the input device through which data and instructions enter a computer. Output device: A display screen, printer, or other device that lets you see what the computer has accomplished. Central processing unit (CPU): The heart of the computer, this is the component that actually executes instructions. In addition to these components, many others make it possible for the basic components to work together efficiently. For example, every computer requires a bus that transmits data from one part of the computer to another. Computers can be generally classified by size and power as follows, though there is considerable overlap: Personal computer: A small, single-user computer based on a microprocessor. In addition to the microprocessor, a personal computer has a keyboard for entering data, a monitor for displaying information, and a storage device for saving data. Working station: A powerful, single-user computer. A workstation is like a personal computer, but it has a more powerful microprocessor and a higher quality monitor. Minicomputer: A multi-user computer capable of supporting from 10 to hundreds of users simultaneously. Mainframe: A powerful multi-user computer capable of supporting many hundreds or thousands of users simultaneously. Supercomputer: An extremely fast computer that can perform hundreds of millions of instructions per second. Minicomputer: A midsized computer. In size and power, minicomputers lie between workstations and mainframes.
Microprocessors & Interfacing A minicomputer, a term no longer much used, is a computer of a size intermediate between a microcomputer and a mainframe. Typically, minicomputers have been stand-alone computers (computer systems with attached terminals and other devices) sold to small and mid-size businesses for general business applications and to large enterprises for department-level operations. Workstation: A type of computer used for engineering applications (CAD/CAM), desktop publishing, software development, and other types of applications that require a moderate amount of computing power and relatively high quality graphics capabilities. Workstations generally come with a large, high- resolution graphics screen, at least 64 MB (mega bytes) of RAM, built-in network support, and a graphical user interface. Microcomputer: The term microcomputer is generally synonymous with personal computer, or a computer that depends on a microprocessor. Microcomputers are designed to be used by individuals, whether in the form of PCs, workstations or notebook computers. A microcomputer contains a CPU on a microchip (the microprocessor), a memory system (typically ROM and RAM), a bus system and I/O ports, typically housed in a motherboard.
INTRODUCTION TO MICROPROCESSOR Microprocessor: A silicon chip that contains a CPU. In the world of personal Computers, the terms microprocessor and CPU are used interchangeably. A microprocessor (sometimes abbreviated P) is a digital electronic component with miniaturized transistors on a single semiconductor integrated circuit (IC).One or more microprocessors typically serves as a central processing unit (CPU) in a computer system or handheld device. Microprocessors made possible the advent of the microcomputer. At the heart of all personal computers and most working stations sits a microprocessor. Microprocessors also control the logic of almost all digital devices, from clock radios to fuel-injection systems for automobiles. Three basic characteristics differentiate microprocessors: Instruction set: The set of instructions that the microprocessor can execute. Bandwidth: The number of bits processed in a single instruction. Clock speed: Given in megahertz (MHz), the clock speed determines how many instructions per second the processor can execute. Microcontroller: A highly integrated chip that contains all the components comprising a controller. Typically this includes a CPU, RAM, some form of ROM, I/O ports, and timers. Unlike a general-purpose computer, which also includes all of these components, a microcontroller is designed for a very specific task - to control a particular system. A microcontroller differs from a microprocessor, which is a general-purpose chip that is used to create a multi-function computer or device and requires multiple chips to handle various tasks. A microcontroller is meant to be more self-contained and independent, and functions as a tiny, dedicated computer. The great advantage of microcontrollers, as opposed to using larger microprocessors, is that the parts-count and design costs of the item being controlled can be kept to a minimum. They are typically designed using CMOS (complementary metal oxide semiconductor) technology, an efficient fabrication technique that uses less power and is more immune to power spikes than other techniques. Microcontrollers are sometimes called embedded microcontrollers, which just means that they are part of an embedded system that is, one part of a larger device or system Embedded system: An Embedded System is a specialized computer system that is part of a larger system or machine. Typically, an embedded system is housed on a single microprocessor board with the programs stored in ROM. Virtually all appliances that have a digital Interfacewatches, microwaves, VCRs, cars -utilize embedded systems. Some embedded systems include an operating system, but many are so specialized that the entire logic can be implemented as a single program.
Address Bus, Data Bus and Control Bus The preferred method for data/information transfer between system components is
by a common data bus. Where point-to-point data transfer is required, the digital
format is the preferred method Control Bus The control bus is used by the CPU to direct and monitor the actions of the other functional areas of the computer. It is used to transmit a variety of individual signals (read, write, interrupt, acknowledge, and so forth) necessary to control and coordinate the operations of the computer. The individual signals transmitted over the control bus and their functions are covered in the appropriate functional area description. Address Bus The address bus consists of all the signals necessary to define any of the possible memory address locations within the computer, or for modular memories any of the possible memory addresses locations within a module. An address is defined as a label, symbol, or other set of characters used to designate a location or register where information is stored. Before data or instructions can be written into or read from memory by the CPU or I/O sections, an address must be transmitted to memory over the address bus. Data Bus The bidirectional data bus, sometimes called the memory bus, handles the transfer of all data and instructions between functional areas of the computer. The bi directional data bus can only transmit in one direction at a time. The data bus is used to transfer instructions from memory to the CPU for execution. It carries data (operands) to and from the CPU and memory as required by instruction translation. The data bus is also used to transfer data between memory and the I/O section during input/output operations Tristate bus Three-state, tri-state, or 3-state logic allows an output port to assume a high impedance state in addition to the 0 and 1 logic levels, effectively removing the output from the circuit. This allows multiple circuits to share the same output line or lines (such as a bus). Three-state outputs are implemented in many registers, bus drivers, and flip-flops in the 7400 and 4000 series as well as in other types, but also internally in many integrated circuits. Other typical uses are internal and external buses in microprocessors, memories, and peripherals. Many devices are controlled by an active-low input called OE (Output Enable) which dictates whether the outputs should be held in a high-impedance state or drive their respective loads (to either 0- or 1-level). Clock generation DEPT. OF ECE, SITS, KHAMMAM PREPARED BY VENKATESH RACHA
Microprocessors & Interfacing A clock generator is a circuit that produces a timing signal (known as a clock signal and behaves as such) for use in synchronizing a circuit's operation. The signal can range from a simple symmetrical square wave to more complex arrangements. The basic parts that all clock generators share are a resonant circuit and an amplifier. The resonant circuit is usually a quartz piezo-electric oscillator, although simpler tank circuits and even RC circuits may be used. The amplifier circuit usually inverts the signal from the oscillator and feeds a portion back into the oscillator to maintain oscillation. The generator may have additional sections to modify the basic signal. The 8088 for example, used a 2/3 duty cycle clock, which required the clock generator to incorporate logic to convert the 50/50 duty cycle which is typical of raw oscillators. Other such optional sections include frequency divider or clock multiplier sections. Programmable clock generators allow the number used in the divider or multiplier to be changed, allowing any of a wide variety of output frequencies to be selected without modifying the hardware. The clock generator in a motherboard is often changed by computer enthusiasts to control the speed of their CPU, FSB, GPU and RAM. Typically the programmable clock generator is set by the BIOS at boot time to the value selected by the enthusiast; although some systems have dynamic frequency scaling that frequently re-program the clock generator.
UNIT-I 8085 Microprocessor Introduction to 8085 It was introduced in 1977. It is 8-bit microprocessor. Its actual name is 8085 A. It is single NMOS device. It contains 6200 transistors approx. Its dimensions are 164 mm x 222 mm. It is having 40 pins Dual-In line-Package (DIP). It has three advanced versions: 8085 AH 8085 AH2 8085 AH1 These advanced versions are designed using HMOS technology. The advanced versions consume 20% less power supply. The clock frequencies of 8085 are: 8085 A 3 MHz 8085 AH 3 MHz 8085 AH2 5 MHz 8085 AH1 6 MHz Pin Diagram of 8085
X1 & X2 (Pin 1 and Pin 2 (Input)) These are also called Crystal Input Pins. 8085 can generate clock signals internally. To generate clock signals internally, 8085 requires external inputs from X1 and X2. RESET IN and RESET OUT (Pin 36 (Input) and Pin 3 (Output)) RESET IN: It is used to reset the microprocessor. It is active low signal. When the signal on this pin is low for at least 3 clocking cycles, it forces the microprocessor to reset itself.
Resetting the microprocessor means: Clearing the PC and IR. Disabling all interrupts (except TRAP). Disabling the SOD pin. All the buses (data, address, control) are tri-stated. Gives HIGH output to RESET OUT pin.
RESET OUT: It is used to reset the peripheral devices and other ICs on the circuit. It is an output signal. It is an active high signal. The output on this pin goes high whenever RESET IN is given low signal. The output remains high as long as RESET IN is kept low.
SID and SOD (Pin 4 (Input) and Pin 5 (Output)) SID (Serial Input Data): It takes 1 bit input from serial port of 8085. Stores the bit at the 8th position (MSB) of the Accumulator. RIM (Read Interrupt Mask) instruction is used to transfer the bit.
SOD (Serial Output Data): It takes 1 bit from Accumulator to serial port of 8085. Takes the bit from the 8th position (MSB) of the Accumulator. SIM (Set Interrupt Mask) instruction is used to transfer the bit.
Interrupt Pins Interrupt: It means interrupting the normal execution of the microprocessor. When microprocessor receives interrupt signal, it discontinues whatever it was executing. It starts executing new program indicated by the interrupt signal. Interrupt signals are generated by external peripheral devices. After execution of the new program, microprocessor goes back to the previous program. PREPARED BY VENKATESH RACHA
Microprocessors & Interfacing Sequence of Steps Whenever There is an Interrupt Microprocessor completes execution of current instruction of the program. PC contents are stored in stack. PC is loaded with address of the new program. After executing the new program, the microprocessor returns back to the previous program. It goes to the previous program by reading the top value of stack.
Five Hardware Interrupts in 8085 TRAP RST 7.5 RST 6.5 RST 5.5 INTR
Classification of Interrupts Maskable and Non-Maskable Vectored and Non-Vectored Edge Triggered and Level Triggered Priority Based Interrupts
Maskable Interrupts Maskable interrupts are those interrupts which can be enabled or disabled. Enabling and Disabling is done by software instructions. List of Maskable Interrupts: RST 7.5 RST 6.5 RST 5.5 INTR
Non-Maskable Interrupts The interrupts which are always in enabled mode are called non-maskable interrupts. These interrupts can never be disabled by any software instruction. TRAP is a non-maskable interrupt.
Vectored Interrupts The interrupts which have fixed memory location for transfer of control from normal execution. Each vectored interrupt points to the particular location in memory. List of vectored interrupts: RST 7.5 RST 6.5 RST 5.5 TRAP The addresses to which program control goes:
Absolute address is calculated by multiplying the RST value with 0008 H.
Non-Vectored Interrupts The interrupts which don't have fixed memory location for transfer of control from normal execution. The address of the memory location is sent along with the interrupt. INTR is a non-vectored interrupt.
Edge Triggered Interrupts The interrupts which are triggered at leading or trailing edge are called edge triggered interrupts. RST 7.5 is an edge triggered interrupt. It is triggered during the leading (positive) edge.
Level Triggered Interrupts The interrupts which are triggered at high or low level are called level triggered interrupts. RST 6.5 RST 5.5 INTR TRAP is edge and level triggered interrupt.
Priority Based Interrupts Whenever there exists a simultaneous request at two or more pins then the pin with higher priority is selected by the microprocessor. Priority is considered only when there are simultaneous requests. Priority of interrupts:
TRAP (Pin 6 (Input)) It is an non-maskable interrupt. It has the highest priority. It cannot be disabled. It is both edge and level triggered. It means TRAP signal must go from low to high. And must remain high for a certain period of time. TRAP is usually used for power failure and emergency shutoff. PREPARED BY VENKATESH RACHA
Microprocessors & Interfacing RST 7.5 (Pin 7 (Input)) It is a Maskable interrupt. It has the second highest priority. It is positive edge triggered only. The internal flip-flop is triggered by the rising edge. The flip-flop remains high until it is cleared by RESET IN.
RST 6.5 (Pin 8 (Input)) It is a Maskable interrupt. It has the third highest priority. It is level triggered only. The pin has to be held high for a specific period of time. RST 6.5 can be enabled by EI instruction. It can be disabled by DI instruction.
RST 5.5 (Pin 9 (Input)) It is a Maskable interrupt. It has the fourth highest priority. It is also level triggered. The pin has to be held high for a specific period of time. This interrupt is very similar to RST 6.5.
INTR (Pin 10 (Input)) It is a maskable interrupt. It has the lowest priority. It is also level triggered. It is a general purpose interrupt. By general purpose we mean that it can be used to vector microprocessor to any specific subroutine having any address.
INTA (Pin 11 (Output)) It stands for interrupt acknowledge. It is an outgoing signal. It is an active low signal. Low output on this pin indicates that microprocessor has acknowledged the INTR request.
Address and Data Pins Address Bus: The address bus is used to send address to memory. It selects one of the many locations in memory. Its size is 16-bit. Data Bus: It is used to transfer data between microprocessor and memory. Data bus is of 8-bit. PREPARED BY VENKATESH RACHA
Microprocessors & Interfacing AD0 AD7 (Pin 19-12 (Bidirectional)) These pins serve the dual purpose of transmitting lower order address and data byte. During 1st clock cycle, these pins act as lower half of address. In remaining clock cycles, these pins act as data bus. The separation of lower order address and data is done by address latch.
A8 A15 (Pin 21-28 (Unidirectional)) These pins carry the higher order of address bus. The address is sent from microprocessor to memory. These 8 pins are switched to high impedance state during HOLD and RESET mode.
ALE (Pin 30 (Output)) It is used to enable Address Latch. It indicates whether bus functions as address bus or data bus. If ALE = 1 then Bus functions as address bus. If ALE = 0 then Bus functions as data bus.
S0 and S1 (Pin 29 (Output) and Pin 33 (Output)) S0 and S1 are called Status Pins. They tell the current operation which is in progress in 8085.
IO/M (Pin 34 (Output)) This pin tells whether I/O or memory operation is being performed. If IO/M = 1 then I/O operation is being performed. If IO/M = 0 then Memory operation is being performed. The operation being performed is indicated by S0 and S1. If S0 = 0 and S1 = 1 then It indicates WRITE operation. If IO/M = 0 then It indicates Memory operation. Combining these two we get Memory Write Operation.
Table Showing IO/M, S0, S1 and Corresponding Operations
RD (Pin 32 (Output)) RD stands for Read. It is an active low signal. It is a control signal used for Read operation either from memory or from Input device. A low signal indicates that data on the data bus must be placed either from selected memory location or from input device.
WR (Pin 31 (Output)) WR stands for Write. It is also active low signal. It is a control signal used for Write operation either into memory or into output device. A low signal indicates that data on the data bus must be written into selected memory location or into output device.
READY (Pin 35 (Input)) This pin is used to synchronize slower peripheral devices with fast microprocessor. A low value causes the microprocessor to enter into wait state. The microprocessor remains in wait state until the input at this pin goes high.
HOLD (Pin 38 (Input)) HOLD pin is used to request the microprocessor for DMA transfer. A high signal on this pin is a request to microprocessor to relinquish the hold on buses. This request is sent by DMA controller. Intel 8257 and Intel 8237 are two DMA controllers.
HLDA (Pin 39 (Output)) HLDA stands for Hold Acknowledge. The microprocessor uses this pin to acknowledge the receipt of HOLD signal. When HLDA signal goes high, address bus, data bus, RD, WR, IO/M pins are tristated. This means they are cut-off from external environment. The control of these buses goes to DMA Controller. Control remains at DMA Controller until HOLD is held high. When HOLD goes low, HLDA also goes low and the microprocessor takes control of the buses. PREPARED BY VENKATESH RACHA
Microprocessors & Interfacing VSS and VCC (Pin 20 (Input) and Pin 40 (Input)) +5V power supply is connected to VCC. Ground signal is connected to VSS.
Block Diagram of 8085
Three Units of 8085
Microprocessors & Interfacing Processing Unit Instruction Unit Storage and Interface Unit
Processing Unit Arithmetic and Logic Unit Accumulator Status Flags Temporary Register
Instruction Unit Instruction Register Instruction Decoder Timing and Control Unit Storage and Interface Unit General Purpose Registers Stack Pointer Program Counter Increment/Decrement Register Address Latch Address/Data Latch
Three Other Units Interrupt Controller Serial I/O Controller Power Supply
Accumulator It the main register of microprocessor. It is also called register A. It is an 8-bit register. It is used in the arithmetic and logic operations. It always contains one of the operands on which arithmetic/logic has to be performed. After the arithmetic/logic operation, the contents of accumulator are replaced by the result.
Arithmetic & Logic Unit (ALU) It performs various arithmetic and logic operations. The data is available in accumulator and temporary/general purpose registers.
Arithmetic Operations: Addition, Subtraction, Increment, Decrement etc.
Logic Operations: AND, OR, X-OR, Complement etc.
Temporary Register DEPT. OF ECE, SITS, KHAMMAM PREPARED BY VENKATESH RACHA
Microprocessors & Interfacing It is an 8-bit register. It is used to store temporary 8-bit operand from general purpose register. It is also used to store intermediate results.
Status Flags Status Flags are set of flip-flops which are used to check the status of Accumulator after the operation is performed.
S = Sign Flag Z = Zero Flag AC = Auxiliary Carry Flag P = Parity Flag CY = Carry Flag
Sign Flag (S): It tells the sign of result stored in Accumulator after the operation is performed. If result is ve, sign flag is set (1). If result is +ve, sign flag is reset (0).
Zero Flag (Z): It tells whether the result stored in Accumulator is zero or not after the operation is performed. If result is zero, zero flag is set (1). If result is not zero, zero flag is reset (0).
Auxiliary Carry Flag (AC): It is used in BCD operations. When there is carry in BCD addition, we add 0110 (6) to the result. If there is carry in BCD addition, auxiliary carry is set (1). If there is no carry, auxiliary carry is reset (0).
Parity Flag (P): It tells the parity of data stored in Accumulator. If parity is even, parity flag is set (1). If parity is odd, parity flag is reset (0).
Program Status Word (PSW) The contents of Accumulator and Status Flags clubbed together is known as Program Status Word (PSW). It is a 16-bit word.
Instruction Register It is used to hold the current instruction which the microprocessor is about to execute. PREPARED BY VENKATESH RACHA
Microprocessors & Interfacing It is an 8-bit register.
Instruction Decoder It interprets the instruction stored in instruction register. It generates various machine cycles depending upon the instruction. The machine cycles are then given to the Timing and Control Unit.
Timing and Control Unit It controls all the operations of microprocessor and peripheral devices. Depending upon the machine cycles received from Instruction Decoder, it generates 12 control signals: S0 and S1 (Status Signals). ALE (Address Latch Enable).
Timing and Control Unit RD (Read, active low). WR (Write, active low). IO/M (Input-Output/Memory). READY RESET IN RESET OUT CLK OUT HOLD and HLDA
General Purpose Registers There are 6 general purpose registers, namely B, C, D, E, H, L. Each of them is 8-bit register. They are used to hold data and results. To hold 16-bit data, combination of two 8-bit registers can be used. This combination is known as Register Pair. The valid register pairs are: B C, D E, H L.
Program Counter It is used to hold the address of next instruction to be executed. It is a 16-bit register. The microprocessor increments the value of Program Counter after the execution of the current instruction, so that, it always points to the next instruction.
Stack Pointer It holds the address of top most item in the stack. It is also 16-bit register. Any portion of memory can be used as stack.
Increment/Decrement Register This register is used to increment or decrement the value of Stack Pointer. During PUSH operation, the value of Stack Pointer is incremented. During POP operation, the value of Stack Pointer is decremented. PREPARED BY VENKATESH RACHA
Address Latch It is group of 8 buffers. The upper-byte of 16-bit address is stored in this latch. And then it is made available to the peripheral devices.
Address/Data Latch The lower-byte of address and 8-bit of data are multiplexed. It holds either lower-byte of address or 8-bits of data. This is decided by ALE (Address Latch Enable) signal. If ALE = 1 then Address/Data Latch contains lower-byte of address. If ALE = 0 then It contains 8-bit data.
Serial I/O Controller It is used to convert serial data into parallel and parallel data into serial. Microprocessor works with 8-bit parallel data. Serial I/O devices works with serial transfer of data. Therefore, this unit is the interface between microprocessor and serial I/O devices.
Interrupt Controller It is used to handle the interrupts. There are 5 interrupt signals in 8085: TRAP RST 7.5 RST 6.5 RST 5.5 INTR
Interrupt Controller Interrupt controller receives these interrupts according to their priority and applies them to the microprocessor. There is one outgoing signal INTA which is called Interrupt Acknowledge.
Power Supply This unit provides +5V power supply to the microprocessor. The microprocessor needs +5V power supply for its operation.
Addressing Modes of 8085 To perform any operation, we have to give the corresponding instructions to the microprocessor. In each instruction, programmer has to specify 3 things: Operation to be performed. Address of source of data. Address of destination of result. PREPARED BY VENKATESH RACHA
Microprocessors & Interfacing The method by which the address of source of data or the address of destination of result is given in the instruction is called Addressing Modes. The term addressing mode refers to the way in which the operand of the instruction is specified.
Types of Addressing Modes Intel 8085 uses the following addressing modes: 1. 2. 3. 4. 5. Direct Addressing Mode Register Addressing Mode Register Indirect Addressing Mode Immediate Addressing Mode Implicit Addressing Mode
Direct Addressing Mode In this mode, the address of the operand is given in the instruction itself. LDA 2500H --- Load the contents of memory location 2500H in accumulator. LDA is the operation. 2500 H is the address of source. Accumulator is the destination.
Register Addressing Mode In this mode, the operand is in general purpose register. MOV A, B ---- Move the contents of register B to A MOV is the operation. B is the source of data. A is the destination.
Register Indirect Addressing Mode In this mode, the address of operand is specified by a register pair. MOV A, M ---- Move data from memory location specified by H-L pair to accumulator. MOV is the operation. M is the memory location specified by H-L register pair. A is the destination.
Immediate Addressing Mode In this mode, the operand is specified within the instruction itself. MVI A, 05H ---- Move 05H in accumulator. MVI is the operation. 05 H is the immediate data (source). PREPARED BY VENKATESH RACHA
Microprocessors & Interfacing A is the destination.
Implicit Addressing Mode If address of source of data as well as address of destination of result is fixed, then there is no need to give any operand along with the instruction. CMA --- Complement accumulator. CMA is the operation. A is the source. A is the destination.
Architecture of 8086 8086 has two blocks BIU and EU. The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. EU executes instructions from the instruction system byte queue. Both units operate asynchronously to give t he 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus a system performance. BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder. EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register.
Fig. 1: Block Diagram of Intel 8086
BUS INTERFACR UNIT: It provides a full 16 bit bidirectional data bus and 20 bit address bus. The bus interface unit is responsible for performing all external bus operations. Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control. The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture. This queue permits pre-fetch of up to six bytes of instruction code. Whenever the queue of the BIU is not full, it has room for at least two more bytes and at the same time the EU is not requesting it to read or write operands from memory, the BIU is free to look ahead in the program by prefetching the next sequential instruction. These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle. After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to the empty location nearest the output. The EU accesses the queue from the output end. It reads one instruction byte after the other from the output of the queue. If the queue is full and the EU is not requesting access to operand in memory. These intervals of no bus activity, which may occur between bus cycles are known as Idle state. If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle. The BIU also contains a dedicated adder which is used to generate the 20bit physical address that is output on the address bus. This address is formed med by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register. The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write. EXECUTION UNIT The Execution unit is responsible for decoding and executing all instructions. The EU extracts instructions from the top of the queue in the BIU, decodes them, generates operands if necessary, passes them to the BIU and requests it to perform the read or write by cycles to memory or I/O and perform the operation specified by the instruction on the operands. During the execution of the instruction, the EU tests the status and control flags an updates them based on the results of executing the instruction. If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the queue. When the EU executes a branch or jump instruction, it transfers control to a location corresponding to another set of sequential instructions. Whenever this happens, the BIU automatically resets the queue and then begins to fetch instructions from this new location to refill the queue. Register Organization: DEPT. OF ECE, SITS, KHAMMAM Prepared by VENKATESH RACHA
General Purpose Registers of 8086: These registers can be used as 8-bit registers individually or can be used as 16-bit in pair to have AX, BX, CX, and DX. All general registers of the 8086 microprocessor can be used for arithmetic and logic operations. The general registers are:
Accumulator Register (AX) consists of 2 8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX. AL in this case contains the loworder byte of the word, and AH contains the high-order byte. Accumulator can be used for I/O operations and string manipulation. Base Register (BX) consists of 2 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the high-order byte. BX register usually contains a data pointer used for based, based indexed or register indirect addressing. Count Register (CX) consists of 2 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX. When combined, CL register contains the low-order byte of the word, and CH contains the high-order byte. Count register can be used as a counter in string manipulation and shift/rotate instructions. Data Register (DX) consists of 2 8-bit registers DL and DH, which can be combined together and used as a 16-bit register DX. When combined, DL register contains the low-order byte of the word, and DH contains the high-order byte. Data register can be used as a port number in I/O operations. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number. Different registers and their operations are listed below: Register AX AL AH BX CX CL DX Operations Word multiply, Word divide, word I/O Byte Multiply, Byte Divide, Byte I/O, translate, Decimal Arithmetic Byte Multiply, Byte Divide Translate String Operations, Loops Variable Shift and Rotate Word Multiply, word Divide, Indirect I/O
The following registers are both pointer and index registers: Stack Pointer (SP) is a 16-bit register pointing to program stack. Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing.
Prepared by VENKATESH RACHA
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data addresses in string manipulation instructions. Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data addresses in string manipulation instructions. Instruction Pointer Register This is a crucially important register which is used to control which instruction the CPU executes. The IP, or program counter, is used to store the memory location of the next instruction to be executed. The CPU checks the program counter to ascertain which instruction to carry out next. It then updates the program counter to point to the next instruction. Thus the program counter will always point to the next instruction to be executed. Segment Registers: Additional registers called segment registers generate memory address when combined with other in the microprocessor. In 8086 microprocessor, memory is divided into 4 segments as follow:
Fig. 2: Memory Segments of 8086
There are four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1 MB of processor memory these 4 segments are located the processor uses four segment registers: Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions. Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack
pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP instruction.
Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS instructions. Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with program data. By default, the processor assumes that the DI register references the ES segment in string manipulation instructions. ES register can be changed directly using POP and LES instructions. It is possible to change default segments used by general and index registers by prefixing instructions with a CS, SS, DS or ES prefix. Segment Register CS DS SS ES Default Offset IP (Instruction Pointer) SI, DI SP, BP DI
Flag Registers of 8086 (or) Program status word (PSW): Flag register in EU is of 16-bit and is shown in fig. 3:
Fig. 3: Flag Register of 8086 Flags Register determines the current state of the processor. They are modified automatically by CPU after mathematical operations, this allows to determine the type of the result, and to determine conditions to transfer control to other parts of the program. 8086 has 9 flags and they are divided into two categories: 1. Conditional Flags 2. Control Flags 1. Conditional Flags: Conditional flags represent result of last arithmetic or logical instruction executed. Conditional flags are as follows: DEPT. OF ECE, SITS, KHAMMAM Prepared by VENKATESH RACHA
Carry Flag (CF): This flag indicates an overflow condition for unsigned integer arithmetic. It is also used in multiple-precision arithmetic. Auxiliary Flag (AF): If an lower nibble (i.e. D0 D3) given by D3 bit to D4 is AF by the processor to perform operation performed in ALU generates a carry/barrow from to upper nibble (i.e. D4 D7), the AF flag is set i.e. carry flag. This is not a general-purpose flag, it is used internally Binary to BCD conversion.
Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits of the result contains even number of 1s, the Parity Flag is set and for odd number o f 1s, the Parity Flag is reset. Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is reset. Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If the result of operation is negative, sign flag is set. Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An OF indicates that the result has exceeded the capacity of machine. 2. Control Flags: Control flags are set or reset deliberately to control the operations of the execution unit. Control flags are as follows: Trap Flag (TP): a. It is used for single step control. b. It allows user to execute one instruction of a program at a time for debugging. c. When trap flag is set, program can be run in single step mode. Interrupt Flag (IF): a. It is an interrupt enable/disable flag. b. If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the interrupt is disabled. c. It can be set by executing instruction sit and can be cleared by executing CLI instruction. Direction Flag (DF): a. It is used in string operation. b. If it is set, string bytes are accessed from higher memory address to lower memory address. c. When it is reset, the string bytes are accessed from lower memory address to higher memory address.
MEMORY SEGMENTATION: Since address registers and address operands are only 16 bits they can only address 64k bytes. In order to address the 20-bit address range of the 8086, physical addresses (those that are put on the address bus) are always formed by adding the values of one of the instruction are executed? The use of segment registers reduces the size of pointers to 16 bits. This reduces the code size but also restricts the addressing range of a pointer to 64k bytes. Performing address arithmetic within data structures larger than 64k is awkward. This is the biggest drawback of the 8086 architecture. We will restrict ourselves to short programs where all of the code, data and stack are placed into thesame 64k segment (i.e. CS=DS=SS). Most of the registers contain data/instruction offsets within 64 KB memory segment. There are four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1 MB of processor memory these 4 segments are located the processor uses four segment registers: Memory Program, data and stack memories occupy the same memory space. As the most of the processor instructions use 16-bit pointers the processor can effectively address only 64KB of memory. To access memory outside of 64 KB the CPU uses special segment registers to specify where the code, stack and data 64 KB segments are positioned within 1 MB of memory (see the "Registers" section below). 16-bit pointers and data are stored as: address: low-order byte address+1: high-order byte Program memory - program can be located anywhere in memory. Jump and call instructions can be used for short jumps within currently selected 64 KB code segment, as well as for far jumps anywhere within 1 MB of memory. All conditional jump instructions can be used to jump within approximately +127 to 127 bytes from current instruction. Data memory - the processor can access data in any one out of 4 available segments, which limits the size of accessible memory to 256 KB (if all four segments point to different 64 KB blocks). Accessing data from the Data, Code, Stack or Extra segments can be usually done by prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions by default may use the ES or SS segments instead of DS segment). Word data can be located at odd or even byte boundaries. The processor uses two memory accesses to read 16-bit word located at odd byte boundaries. Reading word data from even byte boundaries requires only one memory access. Stack memory can be placed anywhere in memory. The stack can be located at odd DEPT. OF ECE, SITS, KHAMMAM Prepared by VENKATESH RACHA
memory addresses, but it is not recommended for performance reasons (see "Data Memory" above).
Reserved locations: 0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer in format segment: offset. FFFF0h - FFFFFh - after RESET the processor always starts program execution at the FFFF0h address. Segment registers to the 16-bit address to form a 20-bit address. The segment registers themselves only contain the most-significant 16 bits of the 20-bit value that is contributed by the segment registers. The least significant four bits of the segment address are always zero. By default, the DS (data segment) is used for data transfer instructions (e.g. MOV), CS(code segment) is used with control transfer instructions(e.g. JMP or CALL), and SS is used with the stack pointer (e.g. PUSH or to save/restore addresses during CALL/RET or INT instructions). Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions. Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP instruction. Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS instructions. Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with program data. By default, the processor assumes that the DI registers references the ES segment in string manipulation instructions. ES register can be changed directly using POP and LES instructions. It is possible to change default segments used by general and index registers by prefixing instructions with a CS, SS, DS or ES prefix. Generation of 20-bit Physical Address:
LOGICAL ADDRESS
SEGMENT REGISTER
0000
ADDER
20 BIT PHYSICAL MEMORY ADDRESS
Fig: One way four 64-Kbyte segment might be positioned within the 1-Mbyte address space of an 8086
PHYSICAL ADDRESS FFFFFH 7FFFFH
MEMORY
HIGHEST ADDRESS TOP OF EXTRA SEGMENT
64K EXTRA SEGMENT BASE ES=7000H TOP OF STACK SEGMENT
70000H 5FFFFH
64K
50000H
STACK SEGMENT BASE SS = 5000H
4489FH
TOP OF CODE SEGMENT
64K CODE SEGMENT BASE CS=348AH TOP OF DATA SEGMENT
348A0H 2FFFFH
64K
20000H
BOTTOM OF DATA SEGMENT
Fig: Addition of IP to CS to produce the physical address of the code byte
PHYSICAL ADDRESS 4489FH
MEMORY TOP OF CODE SEGMENT
38AB4H IP=4214H 348A0H
CODE BYTE
START OF CODE SEGMENT CS=348AH
(a) Diagram CS IP PHYSICAL ADDRESS (b) Computation + 3 4 8 A 0 4 2 1 4 3 8 A B 4 HARDWIRED ZERO
Addressing modes of 8086

DEPT. OF ECE, SITS, KHAMMAM Prepared by VENKATESH RACHA
When 8086 executes an instruction, it performs the specified function on data. These data are called its operands and may be part of the instruction, reside in one of the internal registers of the microprocessor, stored at an address in memory or held at an I/O port, to access these different types of operands, the 8086 is provided with various addressing modes (Data Addressing Modes). Data Addressing Modes of 8086 The 8086 has 12 addressing modes. The various 8086 addressing modes can be classified into five groups. A. Addressing modes for accessing immediate and register data (register and immediate modes). B. Addressing modes for accessing data in memory (memory modes) C. Addressing modes for accessing I/O ports (I/O modes) D. Relative addressing mode E. Implied addressing mode 8086 ADDRESSING MODES
A. Immediate addressing mode: In this mode, 8 or 16 bit data can be specified as part of the instruction. OP Code Immediate Operand Example 1 : MOV CL, 03 H Moves the 8 bit data 03 H into CL Example 2 : MOV DX, 0525 H Moves the 16 bit data 0525 H into DX In the above two examples, the source operand is in immediate mode and the destination operand is in register mode. A constant such as VALUE can be defined by the assembler EQUATE directive such as VALUE EQU 35H Example : MOV BH, VALUE Used to load 35 H into BH Register addressing mode : The operand to be accessed is specified as residing in an internal register of 8086. Fig. below shows internal registers, any one can be used as a source or destination operand, however only the data registers can be accessed as either a byte or word. Register Accumulator Base Count Data Stack pointer Base pointer Operand sizes Byte (Reg 8) Word AL, AH BL, BH CL, CH DL, DH -
(Reg 16) Ax Bx Cx Dx SP BP
Source index Destination index Code Segment Data Segment Stack Segment Extra Segment
SI DI CS DS SS ES
Example 1 : MOV DX (Destination Register) , CX (Source Register) Which moves 16 bit content of CS into DX. Example 2 : MOV CL, DL Moves 8 bit contents of DL into CL MOV BX, CH is an illegal instruction. * The register sizes must be the same. B. Direct addressing mode : The instruction Opcode is followed by an affective address, this effective address is directly used as the 16 bit offset of the storage location of the operand from the location specified by the current value in the selected segment register. The default segment is always DS. The 20 bit physical address of the operand in memory is normally obtained as PA = DS : EA But by using a segment override prefix (SOP) in the instruction, any of the four segment registers can be referenced, PA = CS DS : Direct Address SS ES The Execution Unit (EU) has direct access to all registers and data for register and immediate operands. However the EU cannot directly access the memory operands. It must use the BIU, in order to access memory operands. In the direct addressing mode, the 16 bit effective address (EA) is taken directly from the displacement field of the instruction. Example 1 : MOV CX, START If the 16 bit value assigned to the offset START by the programmer using an assembler pseudo instruction such as DW is 0040 and [DS] = 3050. Then BIU generates the 20 bit physical address 30540 H. The content of 30540 is moved to CL The content of 30541 is moved to CH Example 2 : MOV CH, START If [DS] = 3050 and START = 0040 8 bit content of memory location 30540 is moved to CH. Example 3 : MOV START, BX With [DS] = 3050, the value of START is 0040. Physical address : 30540 MOV instruction moves (BL) and (BH) to locations 30540 and 30541 respectively. Register indirect addressing mode : DEPT. OF ECE, SITS, KHAMMAM Prepared by VENKATESH RACHA
The EA is specified in either pointer (BX) register or an index (SI or DI) register. The 20 bit physical address is computed using DS and EA. Example : MOV [DI], BX register indirect If [DS] = 5004, [DI] = 0020, [Bx] = 2456 The content of BX(2456) is moved CS PA = DS SS = ES Based addressing mode: CS DS BX SS : or + displacement ES BP when memory is accessed PA is computed from BX and DS when the stack is accessed PA is computed from BP and SS. Example : MOV AL, START [BX] or MOV AL, [START + BX] based mode EA : [START] + [BX] PA : [DS] + [EA] The 8 bit content of this memory location is moved to AL. PA = Indexed addressing mode: CS DS SI SS : or + 8 or 16bit displacement ES DI Example : MOV BH, START [SI] PA : [SART] + [SI] + [DS] The content of this memory is moved into BH. PA = Based Indexed addressing mode: CS DS BX SI SS : or + or + 8 or 16bit displacement ES BP DI : MOV ALPHA [SI] [BX], CL If [BX] = 0200, ALPHA 08, [SI] = 1000 H and [DS] = 3000
PA=50060.
to memory locations 50060 H and 50061 H. BX SI DI
PA =
Example
Physical address (PA) = 31208 DEPT. OF ECE, SITS, KHAMMAM Prepared by VENKATESH RACHA
8 bit content of CL is moved to 31208 memory address. String addressing mode: The string instructions automatically assume SI to point to the first byte or word of the source operand and DI to point to the first byte or word of the destination operand. The contents of SI and DI are automatically incremented (by clearing DF to 0 by CLD instruction) to point to the next byte or word. Example : MOV S BYTE If [DF] = 0, [DS] = 2000 H, [SI] = 0500, [ES] = 4000, [DI] = 0300 Source address : 20500, assume it contains 38 PA : [DS] + [SI] Destination address : [ES] + [DI] = 40300, assume it contains 45 After executing MOV S BYTE, [40300] = 38 [SI] = 0501 incremented [DI] = 0301 C. I/O mode (direct) :
Port number is an 8 bit immediate operand. Example : OUT 05 H, AL Outputs [AL] to 8 bit port 05 H I/O mode (indirect): The port number is taken from DX. Example 1 : INAL, DX If [DX] = 5040 8 bit content by port 5040 is moved into AL. Example 2 : IN AX, DX Inputs 8 bit content of ports 5040 and 5041 into AL and AH respectively. D. Relative addessing mode:
Example : JNC START If CY=O, then PC is loaded with current PC contents plus 8 bit signed value of START, otherwise the next instruction is executed. E. Implied addressing mode:
Instruction using this mode have no operands. Example : CLC which clears carry flag to zero.
INSTRUCTION SET OF 8086 DEPT. OF ECE, SITS, KHAMMAM Prepared by VENKATESH RACHA
Data Transfer Instructions: The MOV instruction is used to transfer a byte or a word of data from a source operand to a destination operand. These operands can be internal registers of the 8086 and storage locations in memory. Mnemonic MOV Meaning Move Format MOV D, S Operation (S) (D) Flags affected None Example MOV TEMP, AL MOV AX, TEMP MOV AX, BX MOV BP, Stack top MOV COUNT [DI], CX MOV CL, 04 MOV MASK [BX] [SI], 2F MOV ES, CX MOV DS, Seg base MOV BP SS MOV [BX], CS
Destination Memory Accumulator Register Register Memory Register Memory Seg. Register Seg. Register (Word Operation) Reg 16 (Word Operation) Memory 16
Source Accumulator Memory Register Memory Register Immediate Immediate Reg 16 Mem 16 Seg Reg Seg Reg
MOV instruction cannot transfer data directly between a source and a destination that both reside in external memory. INPUT/OUTPUT INSTRUCTIONS: IN acc, port: In transfers a byte or a word from input port to the AL register or the AX register respectively. The port number my be specified either with an immediate byte constant, allowing access to ports numbered 0 through 255 or with a number previously placed in the DX register allowing variable access (by changing the value in DX) to ports numbered from 0 through 65,535. In Operands acc, immB acc, DX Example IN AL, 0E2H (OR) IN AX, PORT IN AX, DX (OR) IN AL, DX
OUT port, acc : Out transfers a byte or a word from the AL register or the AX register respectively to an output port. The port numbers may be specified either with an immediate byte or with a number previously placed in the register DX allowing variable access. No flags are affected.
In Operands DEPT. OF ECE, SITS, KHAMMAM
Example Prepared by VENKATESH RACHA
Imm 8, acc DX, acc XCHG D, S : Mnemonic XCHG Destination Accumulator Memory Register
OUT 32, AX (OR) OUT PORT, AL OUT DX, AL (OR) OUT DX, AX
Meaning Exchange
Format XCHGD,S Source Reg 16 Register Register
Operation (D) (S)
Flags affected None Example XCHG, AX, BX XCHG TEMP, AX XCHG AL, BL
In the above table register cannot be a segment register Example: For the data given, what is the result of executing the instruction. XCHG [SUM], BX ((DS) + SUM) (BX) if (DS) = 0200, SUM = 1234 PA = 02000 + 1234 = 03234 ASSUME (03234) = FF [BX] = 11AA (03235) = 00 (03234) (BL) (03235) (BH) We get (BX) = 00FF (SUM) = 11AA XLAT (translate): This instruction is useful for translating characters from one code such as ASCII to another such as EBCDIC, this is no operand instruction and is called an instruction with implied addressing mode. The instruction loads AL with the contents of a 20 bit physical address computed from DS, BX and AL. This instruction can be used to read the elements in a table where BX can be loaded with a 16 bit value to point to the starting address (offset from DS) and AL can be loaded with the element number (0 being the first element number) no flags are affected. XLAT instruction is equivalent to MOV AL, [AL] [BX] AL [(AL) + (BX) + (DS)] Example: Write a program to convert binary to gray code for the numbers 0 to F using translate instruction. Let the binary number is stored at 0350 and its equivalent gray code is stored at 0351 after the program execution. Look up table is as follows. Memory 0300 0301: Data 00 01 Data in look up table Exampe: If (0350) = 03
0302 0303 . . 030F MOV BX, 0300 table. MOV SI, 0350 LOD SB XLAT MOV [SJ+1], AL INT20 Flag Control Instructions: Mnemonic LAHF SAHF CLC STC CMC CLI STI Meaning : : : : :
03 02 . 08
Result (0351) = 02
Let BX points to the starting address of the look up Let SI points to the address of binary numbers Load the string byte into AL register. Translate a byte in AL from the look up table stored in the memory pointed by BX. Move the equivalent gray code to location SI+1
Operation (AH)Flags (flags) (AH) (CF) 0 (CF) 1 (CF) (CF) (IF) 0 (IF) 1
Load AH from flags Store AH into flags Clear carry flag Set carry flag Complement carry flag Clear interrupt flag Set interrupt flag
Flags affected None SF,ZF,AF,PF,CF CF CF CF IF IF
Fig. : Flag control Instructions The first two instructions LAHF and SAHF can be used either to read the flags or to change them respectively notice that the data transfer that takes place is always between the AH register and flag register. For instance, we may want to start an operation with certain flags set or reset. Assume that we want to preset all flags to logic 1. To do this we can first load AH with FF and then execute the SAHF instruction. Example: Write an instruction sequence to save the contents of the 8086s flags in memory location MEM1 and then reload the flags with the contents of memory location MEM2. Assume that MEM1 and MEM2 are in the same data segment defined by the current contents of DS. LAHF : Load current flags in AH register MOV (MEM1), AH : Save in (MEM1) MOV AH, (MEM2) : Copy the contents of (MEM2) SAHF : Store AH contents into the flags.
Strings and String Handling Instructions: The 8086 microprocessor is equipped with special instructions to handle string operations. By string we mean a series of data words or bytes that reside in consecutive memory locations. The string instructions of the 8086 permit a programmer to implement operations such as to move data from one block of memory to a block elsewhere in memory. A second type of operation that is easily performed is to scan a string and data elements stored in memory looking for a specific value. Other examples are to compare the elements and two strings together in order to determine whether they are the same or different. Move String: MOV SB, MOV SW: An element of the string specified by the source index (SI) register with respect to the current data segment (DS) register is moved to the location specified by the destination index (DI) register with respect to the current extra segment (ES) register. The move can be performed on a byte (MOV SB) or a word (MOV SW) of data. After the move is complete, the contents of both SI & DI are automatically incremented or decremented by 1 for a byte move and by 2 for a word move. Address pointers SI and DI increment or decrement depends on how the direction flag DF is set. Example: Block move program using MOV MOV MOV MOV MOV MOV CDF NEXT: the move string instruction AX, DATA SEG ADDR DS, AX ES, AX SI, BLK 1 ADDR DI, BLK 2 ADDR CK, N ; DF=0
MOV SB LOOP NEXT HLT Load and store strings: (LOD SB/LOD SW and STO SB/STO SW) LOD SB: Loads a byte from a string in memory into AL. The address in SI is used relative to DS to determine the address of the memory location of the string element. (AL) [(DS) + (SI)] (SI) (SI) + 1 LOD SW: The word string element at the physical address derived from DS and SI is to be loaded into AX. SI is automatically incremented by 2. (AX) [(DS) + (SI)] (SI) (SI) + 2 STO SB: Stores a byte from AL into a string location in memory. This time the contents of ES and DI are used to form the address of the storage location in memory [(ES) + (DI)] (AL) (DI) (DI) + 1 STO SW : [(ES) + (DI)] (AX) DEPT. OF ECE, SITS, KHAMMAM Prepared by VENKATESH RACHA
(DI) (DI) + 2 Mnemonic MOV SB Meaning Move String Byte Move String Word Load String Store String Format MOV SB Operation ((ES)+(DI))((DS)+(SI)) (SI)(SI) 1 (DI) 1 ((ES)+(DI))((DS)+(SI)) ((ES)+(DI)+1)(DS)+(SI)+1) (SI) (SI) 2 (DI) (DI) 2 (AL) or (AX) ((DS)+(SI)) (SI)(SI) 1 or 2 ((ES)+(DI))(AL) or (AX) (DI) (DI) 71 or 2 Flags affected None
MOV SW
MOV SW LOD SB/ LOD SW STOSB/ STOSW
None
LOD SB / LOD SW STOSB/ STOSW
None None
Example :
AGAIN : NEXT : Clear A000 to A00F to 0016
Clearing a block of memory with a STOSB operation. MOV AX, 0 MOV DS, AX MOV ES, AX MOV DI, A000 MOV CX, OF CDF STO SB LOOP NE AGAIN
Repeat String : REP The basic string operations must be repeated to process arrays of data. This is done by inserting a repeat prefix before the instruction that is to be repeated. Prefix REP causes the basic string operation to be repeated until the contents of register CX become equal to zero. Each time the instruction is executed, it causes CX to be tested for zero, if CX is found to be nonzero it is decremented by 1 and the basic string operation is repeated. Example : Clearing a block of memory by repeating STOSB MOV AX, 0 MOV ES, AX MOV DI, A000 MOV CX, OF CDF REP STOSB NEXT: The prefixes REPE and REPZ stand for same function. They are meant for use with the CMPS and SCAS instructions. With REPE/REPZ the basic compare or scan operation can be repeated as long as both the contents of CX are not equal to zero and zero flag is 1. DEPT. OF ECE, SITS, KHAMMAM Prepared by VENKATESH RACHA
REPNE and REPNZ works similarly to REPE/REPZ except that now the operation is repeated as long as CX0 and ZF=0. Comparison or scanning is to be performed as long as the string elements are unequal (ZF=0) and the end of the string is not yet found (CX0). Prefix REP REPE/ REPZ REPNE/REPNZ Example : Used with MOVS STOS CMPS SCAS CMPS SCAS Meaning Repeat while not end of string CX0 CX0 & ZF=1 CX0 & ZF=0
CLD ; DF =0 MOV AX, DATA SEGMENT ADDR MOV DS, AX MOV AX, EXTRA SEGMENT ADDR MOV ES, AX MOV CX, 20 MOV SI, OFFSET MASTER MOV DI, OFFSET COPY REP MOVSB
Moves a block of 32 consecutive bytes from the block of memory locations starting at offset address MASTER with respect to the current data segment (DS) to a block of locations starting at offset address copy with respect to the current extra segment (ES). Auto Indexing for String Instructions: SI & DI addresses are either automatically incremented or decremented based on the setting of the direction flag DF. When CLD (Clear Direction Flag) is executed DF=0 permits auto increment by 1. When STD (Set Direction Flag) is executed DF=1 permits auto decrement by 1. Mnemonic CLD STD Meaning Clear DF Set DF Format CLD STD Operation (DF) 0 (DF) 1 Flags affected DF DF
1. LDS Instruction: LDS register, memory (Loads register and DS with words from memory) This instruction copies a word from two memory locations into the register specified in the instruction. It then copies a word from the next two memory locations into the DS register. LDS is useful for pointing SI and DS at the start of the string before using one of the string instructions. LDS affects no flags. Example 1 :LDS BX [1234] Copy contents of memory at displacement 1234 in DS to BL. Contents of 1235H to BH. Copy contents at displacement of 1236H and 1237H is DS to DS register.
Example 2:
LDS, SI String Pointer (SI) [String Pointer] (DS) [String Pointer +2] DS, SI now points at start and desired string 2. LEA Instruction : Load Effective Address (LEA register, source) This instruction determines the offset of the variable or memory location named as the source and puts this offset in the indicated 16 bit register. LEA will not affect the flags. Examples : LEA BX, PRICES Load BX with offset and PRICES in DS LEA BP, SS : STACK TOP Load BP with offset of stack-top in SS LEA CX, [BX] [DI] Loads CX with EA : (BX) + (DI)
3. LES instruction : LES register, memory Example 1: LES BX, [789A H] (BX) [789A] in DS (ES) [789C] in DS Example 2 : LES DI, [BX] (DI) [BX] in DS (ES) [BX+2] in DS
Assembler Directives
ASSUME DB - Defined Byte. DD - Defined Double Word DQ - Defined Quad Word DT - Define Ten Bytes DW - Define Word
ASSUME Directive - The ASSUME directive is used to tell the assembler that the name of the logical segment should be used for a specified segment. The 8086 works directly with only 4 physical segments: a Code segment, a data segment, a stack segment, and an extra segment. Example: ASUME CS: CODE; this tells the assembler that the logical segment named CODE contains the instruction statements for the program and should be treated as a code segment. ASUME DS:DATA ;This tells the assembler that for any instruction which refers to a data in the data segment, data will found in the logical segment DATA. DB - DB directive is used to declare a byte type variable or to store a byte in memory location. Example: 1. PRICE DB 49h, 98h, 29h; Declare an array of 3 bytes, named as PRICE and initialize. 2. NAME DB ABCDEF; Declare an array of 6 bytes and initialize with ASCII code for letters 3. TEMP DB 100 DUP(?) ;Set 100 bytes of storage in memory and give it the name as TEMP, but leave the 100 bytes uninitialized. Program instructions will load values into these locations. DW - The DW directive is used to define a variable of type word or to reserve storage location of type word in memory. Example: MULTIPLIER DW 437Ah; this declares a variable of type word and named it as MULTIPLIER. This variable is initialized with the value 437Ah when it is loaded into memory to run. EXP1 DW 1234h, 3456h, 5678h; this declares an array of 3 words and initialized with specified values. STOR1 DW 100 DUP(0); Reserve an array of 100 words of memory and initialize all words with 0000.Array is named as STOR1. END - END directive is placed after the last statement of a program to tell the assembler that this is the end of the program module. The assembler will ignore any statement after an END directive. Carriage return is required after the END directive.
ENDP - ENDP directive is used along with the name of the procedure to indicate the end of a procedure to the assembler Example: SQUARE_NUM PROCE; It start the procedure; some steps to find the square root of a number SQUARE_NUM ENDP; Hear it is the End for the procedure END - End Program ENDP - End Procedure ENDS - End Segment EQU - Equate EVEN - Align on Even Memory Address EXTRN ENDS - This ENDS directive is used with name of the segment to indicate the end of that logic segment. Example: CODE SEGMENT; Hear it Start the logic ;segment containing code ; Some instructions statements to perform the logical ;operation CODE ENDS ;End of segment named as ;CODE EQU - This EQU directive is used to give a name to some value or to a symbol. Each time the assembler finds the name in the program, it will replace the name with the value or symbol you given to that name. Example: FACTOR EQU 03H; you has to write this statement at the starting of your program and later in the program you can use this as follows ADD AL, FACTOR; When it codes this instruction the assembler will code it as ADDAL, 03H ;The advantage of using EQU in this manner is, if FACTOR is used many no of times in a program and you want to change the value, all you had to do is change the EQU statement at beginning, it will changes the rest of all. EVEN - This EVEN directive instructs the assembler to increment the location of the counter to the next even address if it is not already in the even address. If the word is at even address 8086 can read a memory in 1 bus cycle. If the word starts at an odd address, the 8086 will take 2 bus cycles to get the data. A series of words can be read much more quickly if they are at even address. When EVEN is used the location counter will simply incremented to next address and NOP instruction is inserted in that incremented location. Example: DATA1 SEGMENT ; Location counter will point to 0009 after assembler reads ; next statement SALES DB 9 DUP (?); declare an array of 9 bytes EVEN ; increment location counter to 000AH RECORD DW 100 DUP( 0 ) ;Array of 100 words will start ;from an even address for quicker read DEPT. OF ECE, SITS, KHAMMAM Prepared by VENKATESH RACHA
DATA1 ENDS GROUP - Group Related Segments LABLE NAME OFFSET ORG Originate GROUP - The GROUP directive is used to group the logical segments named after the directive into one logical group segment. INCLUDE - This INCLUDE directive is used to insert a block of source code from the named file into the current source module. PROC - Procedure PTR - Pointer PUBLC SEGMENT SHORT TYPE PROC - The PROC directive is used to identify the start of a procedure. The term near or far is used to specify the type of the procedure. Example: SMART PROC FAR ; This identifies that the start of a procedure named as SMART and instructs the assembler that the procedure is far . SMART ENDP This PROC is used with ENDP to indicate the break of the procedure. PTR - This PTR operator is used to assign a specific type of a variable or to a label. Example: INC [BX] ; This instruction will not know whether to increment the byte pointed to by BX or a word pointed to by BX. INC BYTE PTR [BX] ;increment the byte ;pointed to by BX This PTR operator can also be used to override the declared type of variable . If we want to access the a byte in an array WORDS DW 437Ah, 0B97h, MOV AL, BYTE PTR WORDS PUBLIC - The PUBLIC directive is used to instruct the assembler that a specified name or label will be accessed from other modules. Example: PUBLIC DIVISOR, DIVIDEND ;these two variables are public so these are available to all modules. If an instruction in a module refers to a variable in another assembly module, we can access that module by declaring as EXTRN directive. TYPE - TYPE operator instructs the assembler to determine the type of a variable and determines the number of bytes specified to that variable.
Example: Byte type variable assembler will give a value 1 Word type variable assembler will give a value 2 Double word type variable assembler will give a value 4 ADD BX, TYPE WORD_ ARRAY ; hear we want to increment BX to point to next word in an array of words. AH 00H : Terminate a Program AH 01H : Read the Keyboard AH 02H : Write to a Standard Output Device AH 08H : Read a Standard Input without Echo AH 09H : Display a Character String AH 0AH : Buffered keyboard Input INT 21H : Call DOS Function
REVIEW QUESTIONS
1. 2. 3. 4. 5. Compare 8 bit processor and 16 bit processor from architectural view. Write short notes on evolution of microprocessors. Write the features of 8086 microprocessor? Explain the architecture of 8086. What is the length of the instruction queue in 8086? Discuss the use of queue? Explain the reason for limiting the length of queue? 6. Explain why 8086 internal architecture is divided into BIU and EU? Discuss A-bus, B-bus and C-bus and use. 7. What is pipelining. How is it implemented in 8086? 8. What is memory segmentation? How is it achieved in 8086? List the advantages of memory segmentation? 9. How do you find out 20-bit address? Explain with one example. 10. Explain the register organization of 8086 11. Draw and describe the flag register 12. The register contents of 8086 are given below. 13. CS=5000H, DS=8000H, SS=9000H, ES=7000H, SI=1000H, DI=2000H, BP=0008H, SP=0002H, AX=0000H, BX=5200H, CX=8000H, DX=2800H. Calculate the effective address and physical address for different addressing modes of 8086 14. Discuss the addressing modes provided by 8086 and explain with example? 15. Explain the use of addressing mode? It is necessary to move a byte from location 4000H: 2000H to 4000H: 2005H. Give all possible methods using 8086 addressing modes? Microprocessor by assuming suitable instructions. 16. Explain the string instructions supported by 8086. 17. Explain the logical instructions supported by 8086. 18. Explain the Addition instructions supported by 8086. 19. Explain the subtraction instructions supported by 8086. 20. Explain the shift and rotate instructions supported by 8086. 21. Explain the CALL and RET instructions. 22. List out assembler directives of 8086? And explain them with examples. 23. What are the various types of procedures? 24. Write short notes on macros? 25. Differentiate between MACRO and PROCEDURE.
OBJECTIVE TYPE QUESTION

1. Which interrupt has the highest priority? a) INTR b) TRAP c) RST6.5 2. In 8085 name the 16 bit registers? a) Stack pointer b) Program counter
c) a & b
3. Which of the following is hardware interrupts? a) RST5.5, RST6.5, RST7.5 b) INTR, TRAP 4. What is the RST for the TRAP? a) RST5.5 b) RST4.5 c) RST4 5. What are level Triggering interrupts? a) INTR&TRAP b)RST6.5&RST5.5
c) a & b
c)RST7.5&RST6.5
6. Which interrupt is not level sensitive in 8085? a) RST6.5 is a raising edge-trigging interrupt. b) RST7.5 is a raising edge-trigging interrupt. c) a & b. 7. What are software interrupts? a) RST 0 - 7 b) RST 5.5 - 7.5
c) INTR, TRAP
8. Which stack is used in 8085? a) FIFO b) LIFO c) FILO 9. Why 8085 processor is called an 8 bit processor? a) Because 8085 processor has 8 bit ALU. b) Because 8085 processor has 8 bit data bus. c) a & b. 10. What is SIM? a) Select Interrupt Mask
b) Sorting Interrupt Mask
c) Set Interrupt Mask.
11. RIM is used to check whether, ______ a) The write operation is done or not b) The interrupt is Masked or not c) a & b 12. What is meant by Maskable interrupts? a) An interrupt which can never be turned off. b) An interrupt that can be turned off by the programmer.
c) none 13. In 8086, Example for Non maskable interrupts are a) Trap b) RST6.5 c) INTR 14. What does microprocessor speed depends on? a) Clock b) Data bus width c) Address bus width 15. Can ROM be used as stack? a) Yes b) No c) sometimes yes, sometimes no 16. Which processor structure is pipelined? a) all x80 processors b) all x85 processors 17. Address line for RST3 is? a) 0020H b) 0028H c) 0018H 18. In 8086 the overflow flag is set when a) The sum is more than 16 bits b) Signed numbers go out of their range after an arithmetic operation c) Carry and sign flags are set d) During subtraction 19. The advantage of memory mapped I/O over I/O mapped I/O is, a) Faster b) Many instructions supporting memory mapped I/O c) Require a bigger address decoder d) All the above 20. BHE of 8086 microprocessor signal is used to interface the a) Even bank memory b) Odd bank memory c) I/O d) DMA 21. In 8086 microprocessor the following has the highest priority among all type interrupts. a) NMI b) DIV 0 c) TYPE 255 d) OVER FLOW 22. In 8086 microprocessor one of the following statements is not true. a) Coprocessor is interfaced in MAX mode b) Coprocessor is interfaced in MIN mode c) I/O can be interfaced in MAX / MIN mode d) Supports pipelining
c) all x86 processors
23. 8088 microprocessor differs with 8086 microprocessor in a) Data width on the output b) Address capability c) Support of coprocessor d) Support of MAX / MIN mode 24. Address line for TRAP is? DEPT. OF ECE, SITS, KHAMMAM Prepared by VENKATESH RACHA
a) 0023H
b) 0024H
c) 0033H
25. In 8085 name the 16 bit registers? a) Stack pointer b) Program counter
c) a & b
26. Why 8085 processor is called an 8 bit processor? a) Because 8085 processor has 8 bit ALU. b) Because 8085 processor has 8 bit data bus. c) a & b. 27. What is meant by Maskable interrupts? a) An interrupt which can never be turned off. b) An interrupt that can be turned off by the programmer. c) None 29. What does microprocessor speed depends on? a) Clock b) Data bus width c) Address bus width 30. Which processor structure is pipelined? a) All x80 processors b) all x85 processors
c) all x86 processors
31. In 8086 the overflow flag is set when a) The sum is more than 16 bits b) Signed numbers go out of their range after an arithmetic operation c) Carry and sign flags are set d) During subtraction 32. The contents of different registers are given below. Form Effective addresses for different addressing modes are as follow : Offset = 5000H [AX]- 1000H, [BX]- 2000H, [SI]- 3000H, [DI]- 4000H, [BP]- 5000H, [SP]- 6000H, [CS]- 0000H, [DS]- 1000H, [SS]- 2000H, [IP]- 7000H. I. MOV AX, [5000H] a) 5000H b) 15000H c) 10500H II. MOV AX, [BX] [SI] a) 13000H b) 15000H III. MOV AX, 5000H [BX] [SI] a) 20000H b) 1A000H
c) 12000H
c) 1A00H
Key: 1 C 2 C 3 C 4 B 5 B 6 B 7 A 8 B 9 A 10 C 11 B 12 B 13 A 14 C 15 B 16 C 17 C 18 B 19 D 20 B 21 A 22 B 23 A 24 B

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