EC 2354 - VLSI DESIGN/ Unit1-simple/AAMEC/ECE/JA MOS (Metal Oxide Semiconductor) Transistor Theory 1 Introduction The MOS transistor is a majority-carrier

er device in which the currentis controlled by a voltage applied to the gate. In an nMOS transistor, the majority carriers are electrons; in a pMOS transistor, the majoritycarriers are holes. 1.1 Simple MOS structure: The behaviour of MOS transistor can be understood by examining the isolated MOS structure with a gate and body as shown in Fig.1. The top layer of the structure is a good conductor(metal or poly-silicon) called the gate. The middle layer is a very thin insulating film of SiO2 called the gate oxide. The bottom layer is the doped silicon (semiconductor) body. 1.1.1 Mode of operation (MOS structure) Accumulation Mode: In Fig.1(a), a negative voltage is applied to the gate. The holes in the body are attracted to the region beneath the gate. This is called the accumulation mode. Depletion Mode:

In Fig.1(b), a small positive voltage is applied to the gate. The holes in the body are repelled from the region directly beneath the gate. The region, with depleted of carriers, is called depletion region.
Inversion Mode

In Fig.1(c), a higher positive potential (>Vt) is applied to the gate. The holes are repelled further and some free electrons in the body are attracted below the gate. This layer is called the inversion layer.

Fig.1.(a)

Fig.1.(b)

Fig.1.(c)

1.2 Three mode (Region) of Operation for nMOS Transistor: There are three mode of operations (cut-off, linear, Saturation). Cut-off Mode (Region) : Condition : Vgs < Vt Almost zero current flows. We say the transistor is OFF, and this mode of operation is called cutoff (Fig.2.(a)). Linear Mode (Region) : Conditions: (i) Vgs> Vt (ii) 0 < Vds < (Vgs-Vt). The MOS transistor acts as a linear resistor in which the current (Ids) is proportional to Vds. This mode of operation is termed linear, resistive, triode, non-saturated, or unsaturated (Fig.2.(b). Saturation Mode (Region) : Condition: (i) Vgs>Vt (ii) Vds > (Vgs-Vt). The MOS transistor acts as a current source in which the current (Ids) becomes independent of Vds. This mode of operation is saturation mode (Fig.2.(c). Pinch-off: When Vds > Vgs-Vt , the region near drain is depleted (no channel).

Fig.2.(a)

Fig.2.(b)

Fig.2.(c)

2 Ideal (Long-Channel) Model I-V Characteristics MOS transistors have three regions of operation: 1. Cutoff or sub-threshold region 2. Linear region 3. Saturation region This model is variously known as the long-channel, ideal, first-order, or Shockley model. The model assumes that the channel length is long and the current through an OFF transistor is 0 (Cut-off). 2.1 Current in the Linear Region: Drain to Source current, Ids = Where, Qchannel time Qchannel: (1) carrier Charge at the channel. Distance / Velocity.

EC 2354 - VLSI DESIGN/ Unit1-simple/AAMEC/ECE/JA Q = CgVc ; where, Cg- Capacitance of the gate to channel. Vc Voltage. Vc , Minimum voltage required to form channel = (Vgs Vt Vds /2). Cg =
ox

(2)

= CoxWL

... (3)

From Eqns. (2) and (3): Q = CoxWL(Vgs Vt Vds /2) (4) Velocity (v) : v = Eds = Vds/L ...(5) where, - mobility of the majority carrier; Eds Electric field b/w drain and source. From Eqns. (1), (4) and (5) Ids = = Where, = ; = .(6)

Eqn.(6) describes the linear region of operation. It is called linear or resistive because when Vds << (Vgs Vt), Ids increases almost linearly with Vds, just like an ideal resistor. 2.2 Current in the Saturation Region: If Vds > Vdsat ( , we say it is pinched off. Beyond this point, increasing the drain voltage(Vds) has no further effect on current(Ids). Substituting Vds = : Eqn.(6) : Ids =

= =

= .(7)

This expression is valid for Vgs > Vt and Vds >Vdsat. Thus, long-channel MOS transistors are said to exhibit squarelaw behavior in saturation. EQ (2.10) summarizes the current in the three regions:

Ids =

..(8)

3 DC Transfer Characteristics of CMOS inverter: Fig.1. CMOS inverter 3.1 CMOS Inverter When the input A is 0, the nMOS transistor is OFF and the pMOS transistor is ON; and the output Y is pulled up to 1. Conversely, when A is 1, the nMOS is ON, the pMOS is OFF; and Y is pulled down to 0. 3.2 DC Transfer Characteristics The DC transfer characteristics (sometimes called the voltage-transfer characteristic) of a CMOS inverter relate the output voltage to the input voltage. By assuming the input changes slowly enough, Specific ranges of input and output voltages are defined as valid 0 and 1 logic levels. The operation of the CMOS inverter can be divided into five regions indicated on Fig.2. The state of each transistor in each region is shown in Table 2.3. 1. In region A, the nMOS transistor is OFF so the pMOS transistor pulls the output to VDD. 2. In region B, the nMOS transistor starts to turn ON, pulling the output down. 3. In region C, both transistors are in saturation. 4. In region D, the pMOS transistor is partially ON 5. In region E, the pMOS transistor is completely OFF, leaving the nMOS transistor to pull the output down to GND.

Fig.2. DC Characteristics

EC 2354 - VLSI DESIGN/ Unit1-simple/AAMEC/ECE/JA

Output voltage, Vout: Region A: Vout = VDD Region B: Region C: Region D: Vout = (Vin Vtp) +

Vin Vtn < Vout < Vin - Vtp

Vout = (Vin Vtn) -

Region E: Vout = 0. 4.1 CMOS Technology : The n-well process: Typical n-well fabrication steps are: (i) Substrate selection: p-substrate. (ii) n-type impurity diffusion to form n-well.(Figs.1,2) (a) SiO2 - layer formation (Oxidation) (b) Photoresist (c) Photomask (d) UV rays exposure (e) Oxide etching (f) Ion implantation (diffusion) (g) Remaining Photoresist and oxides removal. (iii) Poly-silicon-Gate formation (Fig.3) a. Thin Gate Oxide formation (oxidation) b. Poly-silicon formation (Chemical vapour Deposition) c. Photomask and etching (iv) Source Drain formation: a. Oxidation, Photomask and etching. b. n+ regions diffused to make source and drain for pMOS c. p+ regions diffused to make source and drain for nMOS (v) Contact cut (Sputtering, aluminium is used as a contact) 4.2 CMOS Technology : The p-well process: Typical p-well fabrication steps are similar to an n-well process, except that a p-well is implanted rather than an n-well. (vi) n-substrate (vii) p-type impurity diffusion to form p-well.(Figs.1,2) (h) SiO2 - layer formation (Oxidation) (i) Photoresist (j) Photomask (k) UV rays exposure (l) Oxide etching (m) Ion implantation (diffusion) (n) Remaining Photoresist and oxides removal. (viii) Poly-silicon-Gate formation (Fig.3) a. Thin Gate Oxide formation (oxidation) b. Poly-silicon formation (Chemical vapour Deposition) c. Photomask and etching (ix) Source Drain formation: d. Oxidation, Photomask and etching. e. n+ regions diffused to make source and drain for pMOS f. p+ regions diffused to make source and drain for nMOS (x) Contact cut (Sputtering, aluminium is used as a contact) 4.3 CMOS Technology: Twin-Tub Processes: In Twin-tub CMOS technology: p-type and n-type transistors can be optimized independently. Thus, the threshold voltage, body effect, and the gain associated with n-type and p-type devices can be independently optimized. Generally, the starting material is either an n+ or p+ substrate with a lightly doped epitaxial or epi-layer, which is used for protection against latch-up. The aim of epitaxy is to grow high-purity silicon layers of controlled thickness with accurately determined dopant concentrations distributed homogeneously throughout the layer. The electrical properties of this layer are determined by dopant and its concentration in the silicon. The process sequence, which is similar to the n-well process apart from the tub formation where both p-well and n-well are utilized, leads to the following steps. Since this process provides separately optimized wells, balanced performance n-transistor and ptransistor may be constructed

EC 2354 - VLSI DESIGN/ Unit1-simple/AAMEC/ECE/JA

The process sequence, which is similar to the n-well process apart from the tub formation where both p-well and nwell are utilized, leads to the following steps. (i) Tub formation. (ii) Thin-oxide construction. (iii) Source and drain implantations. (iv) Contact cut definition. (v) Metallization. Threshold adjust steps is included in this process.
n+ n+ p+ p+

p-well

n-well

n (or p)-substrate
Fig.5 twin-tub structure

Epitaxial layer

Silicon On Insulator- (CMOS Process Enhancement): Silicon On Insulator(SOI) CMOS processes have several potential advantages over the traditional CMOS technologies. These include no latch-up problems and lower parasitic capacitances. In the SOI process, a thin layer of single crystal silicon is epitaxially grown on an insulator such as sapphire. The steps used in typical SOI CMOS processes are: A thin film of very lightly-doped n-type Si is grown over an insulator (e.g., sapphire) as shown in Fig.(a). An etching process is used to remove the Si except where a diffusion area (n or p) will be needed (Fig.(b,c)). The p-islands are formed next by masking the n-islands with a photoresist. A p-type dopant (e.g., Boron) is then implanted(Fig.(d)). The p-islands will become n-channel devices. The p-islands are then covered with a photoresist and an n-type dopant (e.g., Phosporous) is then implanted to form n-islands(Fig.(e)). The n-islands will become p-channel devices. A thin gate oxide is normally grown over all the Si structure. This is normally done by thermal oxidation(Fig.(f)). A polysilicon film is deposited over the oxide (Fig.(f)). The polysilicon is then patterned by photomasking and is etched. This defines the polysilicon layer (Gate) in the structure(Fig.(g)). The next step is to form the n-doped source and drain of the n-channel devices in the p-islands. The n-islands are covered with photoresist to block the n-type implantation. After this step, the nchannel devices are completed. (Fig.(h)). The p-channel devices are formed next by masking the p-islands and implanting a p-type dopant such as boron at the n-islands. Thus, the p-channel devices are formed(Fig.(i)). The aluminium will flow through the contact cuts to make the contact with source, drain and polysilicon regions. (Fig.(j)). A final passivation layer of a phosphorous glass is deposited to protect the devices.

Advantages: 1. Higher density (no well formation is present). 2. Low capacitances ( provide the basis of very fast circuits). 3. No field inversion problem (since, the Substrate is insulator). 4. No Latch-up Problem. 5. There are no body effect problems. 4

EC 2354 - VLSI DESIGN/ Unit1-simple/AAMEC/ECE/JA

6. Enhanced radiation tolerance. Disadvantages: 1. Expensive. 2. Process is complex. 3. Device gain is low.

Layout (Design) Rules 1. Layout rules can be considered a prescription for preparing the photo-masks that are used in the IC fabrication. 2. The rules are defined in terms of feature sizes (widths), separations, and overlaps. 3. The main objective of the layout rules is to build reliably functional circuits in as small an area as possible. 4. There are two types of Layout Design Rules: 1. MOSIS Scalable Design rule ( rule) 2. Micron rule ( rule) 5. Most important Rules are: 1. Well- rules 2. Transistor rules 3. Contact rules 4. Metal rules 5. Via rules Well Rules: 1. Width of the well 12 2. Spacing to well at same Potential - 6 3. Spacing to well at different potential 18 Transistor Rules 1. CMOS transistors are generally defined by active, n-select, p-select and poly-silicon. 2. The active mask defines all areas where either n- or p-type diffusion is to be placed. 3. The gates of transistors are defined by the poly-silicon mask . 4. The select layers define what type of diffusion is required. 1. n-select surrounds active regions where n-type diffusion is required. 2. p-select surrounds areas where p-type diffusion is required. 1. Select 1. Spacing to select 2 2. Spacing from substrate contact to select - 3 3. Overlap to active - 2 2. Active (diffusion) 1. Width - 3 2. Spacing to active - 3 3. Spacing to active of opposite type - 6 3. Polysilicon: 1. width 2 2. Gate extension beyond Active - 2 Contact Rules There are several generally available contacts: 1. Metal to p-active (p-diffusion) 2. Metal to n-active (n-diffusion) 3. Metal to poly-silicon 4. Metal to well or substrate 1. Contact width (exact) 2x2 2. Spacing to contact - 3 3. Spacing of poly contact to other poly 5 4. Spacing of active contact to poly contact - 4 Via Rules: Large vias required on power busses are constructed from an array of uniformly sized vias. 1. Width - 2x2 2. Spacing to via on same layer - 3 Metal Rules 1. Metal spacing may vary with the width of the metal line. 2. If wider wires are desired, they are constructed by paralleling a number of smaller wires and adding checkerboard links to tie the wires together. Rules: 1. Width 3 2. Spacing to same layer metal - 3 3. Spacing to metal for lines wider than 10 - 6 Non-ideal(second-order) I-V Effects Ideal I-V Characteristics: When Vds > Vgs Vt ; the current (Ids) will be saturated (constant). Non-ideal I-V characteristics: a. When Vds > Vgs Vt ; the current (Ids) will not be saturated. b. Ids in non-ideal characteristics is less than the ideal. Some Second-order effects are:

EC 2354 - VLSI DESIGN/ Unit1-simple/AAMEC/ECE/JA 1. Velocity saturation, mobility degradation, channel length modulation, sub-threshold conduction, body effect, etc. 1.Velocity saturation Velocity, = E; i.e., E (It is valid only for low electric field) 1. At high lateral field strengths (Vds/L), carrier velocity stops to increase linearly with field strength 2. Result in lower Ids than expected at high Vds 2.Mobility degradation 1. At high vertical field strengths (Vgs/tox), the carriers scatter more often. 2. Also lead to less current than expected at high Vgs. 3.Channel Length Modulation (Channel length reduction) 1. Ideally, Ids is independent of Vds for a transistor in saturation, making the transistor a perfect current source. 2. When Vds > Vgs-Vt : A p-n junction between the drain and body forms a depletion region with a width Ld . (as shown in Fig.). 1. The depletion region effectively shortens the channel length to Leff = L Ld. 2. Channel length modulation is very important to analog designers because it reduces the gain of amplifiers. 4.Threshold Voltage Effects 1. In non-ideal characteristics : Threshold voltage(vt) is not a constant. 2. Vt increases with (i) the increase in source voltage. (ii) the increase in channel length. 3. Vt decreases with (i) the increase in drain voltage. (ii) the increase in body voltage. 4.1 Body Effect: 1. Until now, we have considered a transistor to be a three-terminal device with gate, source, and drain. 2. However, the body is an implicit fourth terminal. 3. When a voltage Vsb is applied between the source and body, it increases the amount of charge required to invert the channel, hence, it increases the threshold voltage. The threshold voltage can be modeled as ..(1) Where, Vt0 - the threshold voltage when the source is at the body potential. Vt - the threshold voltage when the source potential is greater than the body. s - the surface potential at threshold. - the body effect coefficient (depend on the doping level in the channel, NA). Body effect - Summary: 1. When Source potential is greater than the body potential, threshold voltage increases. 2. When body potential is greater than the source potential, threshold voltage decreases. 4.2 Short-Channel Effect: 1. The threshold voltage typically increases with channel length (L) and vice-versa. 2. If the channel length is short, Vt decreases and leakage current(sub-threshold conduction) increases. 4.3 Drain-Induced Barrier Lowering: ( Increase in Drain voltage, reduce the vt) 1. The drain voltage Vds creates an electric field that affects the threshold voltage. 2. This drain-induced barrier lowering (DIBL) effect is especially pronounced in short-channel transistors. It can be modeled as Vt = Vt0 - Vds .(6.3) Where, is the DIBL coefficient, typically on the order of 0.1 (often expressed as 100 mV/V). Drain-induced barrier lowering causes Ids to increase with Vds in saturation, in much the same way as channel length modulation does. More significantly, DIBL increases sub-threshold leakage at high Vds. 4.4 Leakage (sub-threshold conduction) Even when transistors are nominally OFF, they leak small amounts of current. Leakage mechanisms include: sub-threshold conduction between source and drain gate leakage from the gate to body(hot-electrons) junction leakage from source to body and drain to body (as illustrated in Fig.). Overall, leakage has become an important design consideration in nanometer processes. 4.5 Temperature Dependence 1. Transistor characteristics are influenced by temperature. Carrier mobility decreases with temperature. 2. The magnitude of the threshold voltage decreases nearly linearly with temperature. 4.

EC 2354 - VLSI DESIGN/ Unit1-simple/AAMEC/ECE/JA Processing Steps in CMOS Technologies: 1. Wafer Formation (Czochralski method ) The basic raw material used in CMOS fabrication unit is a wafer. Wafers are cut from boules (silicon ingots) that have been pulled from a crucible of pure molten silicon. Sand (SiO2) is placed inside the quartz crystal and the crucible is heated at 1425oC by radio-frequency induction. Controlled amounts of impurities are added to the melt to provide the crystal with the required electrical properties. Seed and crucible are rotated in opposite directions to grow silicon ingots. The silicon ingot takes on the same crystal orientation as the seed. This is known as the Czochralski method and is currently the most common method for producing single-crystal material. 2. Photolithography The regions of dopants, poly-silicon, metal, and contacts are defined using masks. For instance, in places covered by the mask, ion implantation might not occur or the dielectric or metal layer might be left intact. In areas where the mask is absent, the implantation can occur, or dielectric or metal could be etched away. The primary method for defining areas on a wafer is by the use of photo-resists. The wafer is coated with the photo-resist and subjected to selective illumination through the photo-mask. A photo-mask is constructed with chr omium (chrome) covered quartz glass. A UV light source is used to expose the photo-resist. The photo-mask has chrome where light should be blocked. Figure 3.3 illustrates the lithography process. The UV light floods the mask from the backside and passes through the clear sections of the mask to expose the organic photo-resist (PR) that has been coated on the wafer. A developer solvent is then used to dissolve the soluble unexposed photo-resist, leaving islands of insoluble exposed photo-resist. This is termed a negative photo-resist. A positive resist is initially insoluble, and when exposed to UV becomes soluble. 3. Oxidation (Processing method to form SiO2 Layer) Oxidation of silicon is achieved by heating silicon wafers in an oxidizing atmosphere. The following are some common approaches: Wet oxidationwhen the oxidizing atmosphere contains water vapor. o The temperature is usually between 900 C and 1000 C. o This is also called pyrogenic oxidation when a 2:1 mixture of hydrogen and oxygen is used. o Wet oxidation is a rapid process. Dry oxidationwhen the oxidizing atmosphere is pure oxygen. o Temperatures are in the region of 1200 C to achieve an acceptable growth rate. o Dry oxidation forms a better quality oxide than wet oxidation. o It is used to form thin, highly controlled gate oxides, while wet oxidation may be used to form thick field oxides. Atomic layer deposition (ALD) It is a chemical process. when a thin chemical layer (material A) is attached to a surface and then a chemical (material B) is introduced to produce a thin layer of the required layer (i.e., SiO2this can also be used for other various dielectrics and metals). 4. Isolation Individual devices in a CMOS process need to be isolated from one another so that they do not have unexpected interactions. The source and drain of the transistors form reverse-biased pn junctions with the substrate or well, isolating them from their neighbors. The thick oxide used to be formed by a process called Local Oxidation of Silicon(LOCOS). shallow trench isolation (STI) was introduced to avoid the problems with LOCOS. o The trenches isolate the wires from the substrate, preventing unwanted channel formation. o They also reduce the sidewall capacitance and junction leakage current of the source and drain. Summary - Three types: 1. Reverse biased PN junction 2. LOCOS (Field oxide) 3. Shallow Trench Isolation (STI) 5. Contacts and Metallization

EC 2354 - VLSI DESIGN/ Unit1-simple/AAMEC/ECE/JA Contact cuts are made to source, drain, and gate according to the contact mask. These are holes etched in the dielectric. after the source/drain step discussed in the previous section. Older processes commonly use aluminum (Al) for wires, although newer ones offer copper (Cu) for lower resistance. Metallization is the process of building wires to connect the devices. Aluminum can be deposited either by evaporation or sputtering. Evaporation is performed by passing a high electrical current through a thick aluminum wire in a vacuum chamber. Wet or dry etching can be used to remove unwanted metal. Piranha solution is a 3:1 to 5:1 mix of sulfuric acid and hydrogen peroxide that is used to clean wafers of organic and metal contaminants or photoresist after metal patterning. Plasma etching is a dry etch process with fluorine or chlorine gas used for metallization steps. Very sharp etch profiles can be achieved using plasma etching. 6. Passivation The final processing step is to add a protective glass layer called passivation or overglass that prevents contaminants. Openings in the passivation layer, called overglass cuts, allow connection to I/O pads and test probe points if needed. After passivation, the chip to be directly connected to a circuit board using plated solder bumps in the pad openings. 7. Metrology Metrology is the science of measuring. Everything that is built in a semiconductor process has to be measured to give feedback to the manufacturing process. This ranges from simple optical measurements of line widths to advanced techniques to measure thin films and defects such as voids in copper interconnect. 8. Formation of Gate, Source and Drain: The polysilicon gate and source/drain diffusion have high resistance due to the resistivity of silicon and their extremely small dimensions. Modern processes form a surface layer of a refractory metal on the silicon to reduce the resistance. A refractory metal is one with a high melting point that will not be damaged during subsequent processing. Tantalum, nickel, molybdenum, titanium, or cobalt are commonly used. The metal is deposited on the silicon. A layer of silicide is formed when the two substances react at elevated temperatures. The silicide process lowers the resistance of the polysilicon interconnect and the source and drain diffusion.

Latch-up: Earlier, CMOS devices were unintentionally slowed by low-resistance paths between VDD and GND. The phenomenon, called latch-up, occurs when parasitic bipolar transistors formed by the substrate, well, and diffusion turn ON(Fig.). This latch up effect can be avoided by reducing the resistances of the substrate (Rsub) and well(Rwell). SOI processes avoid latch-up entirely because they have no parasitic bipolar structures.