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VALPARAISO UNIVERSITY ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT ECE 222 DESIGN PROJECT #1 - BINARY MULTIPLIER SPRING 2014

Introduction: The objective of this project is to design a circuit, which accepts two 4-bit unsigned binary numbers as input, and produces the corresponding 8-bit product as the output. There are many ways of accomplishing this task, and several of them are discussed in your textbook. In this project we will investigate implementing a sequential muliplier using a shift-and-add procedure. SECTION I. A Sequential Circuit Multiplier Realization

You will implement a 4x4 shift-and-add multiplier as described below. The two numbers in the multiplication are referred to as the multiplicand (MD) and the multiplier (MR). The basic operation of the implementation involves checking each bit in the MR starting with the least significant bit (LSB). If the bit is 1, then the MD is added to the upper-most bits of the overall product. After each bit of the MR is checked, the product is shifted one location to the right. This check-add-shift continues until all four bits of the MR have been examined. The product that remains is the final solution. To demonstrate how this multiplication would work, lets look at an example involving the multiplication of the following two numbers: x 1101 1011 (multiplicand MD) (multiplier MR)

We will work through the operations, examining the 8-bit product after each step. Included is a carry out bit, Cout, which will be needed when we perform the addition. To begin with, Product & Cout are initialized to 0.

Cout 0 0 0 0

Product 0 0 0 0 0

The first step is to examine the LSB of MR. Since it is a 1, the MD is added to the upper portion of the Product producing:

Cout 0
and then that result is shifted to the right.

Product 1 1 0 1 0 0 0 0

Cout 0 0 1 1

Product 0 1 0 0 0

The next bit MR(1) is checked and is again found to be a 1. Therefore the MD is again added to the upper-most 4 bits to produce:
Cout 1 0 0 1 Product 1 1 0 0 0

Note that Cout now has a value of 1 and that the lower four bits will remain the same. Again a shift right occurs which shifts the contents of the Cout into the MSB of the product:

Cout 0 1 0 0

Product 1 1 1 0 0

The next bit to check is MR(2). This bit is a zero and therefore no addition is done. The shift right, however, will always occur so the updated Product is:

Cout 0 0 1 0

Product 0 1 1 1 0

Finally, the MSB of MR is checked and found to be a 1. Therefore the addition is performed to produce:

Cout 1 0 0 0

Product 1 1 1 1 0

and the last right shift gives us the final product:

Cout 0 1 0 0

Product 0 1 1 1 1

The logical configuration of the multiplier is given below. Instead of having a separate register for the MR, the lower 4 bits of the product register are used. This saves hardware because MR will be shifted out to make room for the product.

The multiplier implementation contains a 4-bit full adder, two shift registers that contain MR and the Product, a counter, and a controller, which provides control signals to the various components. Each of the various components is detailed below:

74194

4-Bit Universal Shift Register


74194
SLSI SRSI A B C D S0 S1 CLRN CLK
inst

QA QB QC QD

SHIFT REG.

Two instances of this IC can be used to implement the two shift registers R1 and R2. Based on the values of the mode bits S1 and S0, the register exhibits the following modes at the output pins QA, QB, QC, and QD:

S1 S0 0 0 0 1 1 0 1 1

Mode
Hold old value Shift Right Shift Left Load new value from ABCD

SLSI is the shift left serial input and SRSI is the shift right serial input.

7483
7483
C0 A1 B1 A2 B2 A3 B3 A4 B4
inst

4-Bit Full Adder

S1 S2 S3 S4 C4

FULL ADDER

This is a combinational 4-bit full adder. The inputs are 4 bits for A and 4 bits for B and the carry in (C0). The outputs are 4 bits for the sum S and a carry out C4.

7493

Mod-2 and Mod-8 Counter


7493
RO1 RO2 CLKA CLKB inst1 COUNTER QA QB QC QD

The 7493 consists of a modulo-2 counter with input CLKA and output QA, and a modulo-8 counter with input CLKB and outputs QB, QC and QD. The modulo-2 counter will not be used, so its CLKA input should be connected to ground. The active-high asynchronous reset inputs R01 and R02 should be connected together and are used to clear the counter.

74175

4-Bit D Flip Flop with Asynchronous Clear


74175
1D 2D 3D 4D 1Q 1QN 2Q 2QN 3Q 3QN 4Q 4QN

CLRN CLK
inst2

REGISTER

This IC includes 4 D-Flip Flops with their inputs being 1D - 4D and their outputs being 1Q 4Q and complemented outputs 1QN 4QN. These D-Flip Flops will be used for the implementation of the FSM of the controller as well as other storage needs. The 7483 adder forms the binary sum of A and B and C0 (carry-in), to produce the sum S and carry-out (C4). The LSBs are A1, B1, S1. For the shift registers R1 and R2 (74194s), we will use the loading and the shift right modes. The MSB is A. Thus the input MD(0) is connected to adder A1, adder S1 goes to R1 input D, and R1 output QD goes to adder input B1. Similarly, input MR(0) is connected to R2 input D. The output P(7:0) is comprised of the eight outputs of the combined registers R1 and R2, with P(7) connected to R1 output QA and P(0) to R2 output QD. The QD output of R1 should go to the SRSI input of R2, and the SLSI inputs of both registers should go to ground. You must provide logic for the SRSI input of R1 to shift in the stored carry bit C4 only when an add was performed (P(0)=1). The algorithmic state machine (ASM) chart for the controller is shown below. It includes three states: an initial state (S0), a check and add state (S1), and a shift and test for complete state (S2).

The table below outlines the specific variable (net) names you will use to implement this circuit.

Port Function Description input CLR Master asynchronous clear for all counters and registers input CLK Master clock for all synchronous counters and registers input BGN Start signal for multiplier: high for one clock period input MD(3:0) Multiplicand, input to the adder, constant during multiply input MR(3:0) Multiplier, parallel input (ABCD) to Shift Register 2 (R2) output P(7:0) Product, output from R1 & R2 output RDY Multiply complete signal, from controller The CLR input should be held high for about 50 ns at the beginning of the simulation to establish initial zero conditions on all flip-flops. Then CLR should go low and remain low for the duration of the simulation. The BGN input going high for a clock period (200 ns) will command a multiply operation, and the final product should remain in P until BGN goes high again to request another product. Values on the MD and MR inputs should remain constant during a multiply operation. You must provide logic to clear the counter and R1 when the second and subsequent multiply operations are requested by BGN. This internal clear signal will be called RST. This signal should be logically combined with the asynchronous input CLR to reset the counter and register R1. The other shift register R2 and the D flip flops should be cleared using the asynchronous reset.
An increment signal INC will be generated by the controller and connected to CLKB of the counter. The MSB QD generates the CNT4 signal, which serves as an input to the controller.

Controller FSM Design


The controller is a sequential machine whose ASM chart was shown earlier. 1. Refer to the description above to understand the operating modes of the 74194 universal shift register. For each operation in the ASM chart, write the corresponding control levels (0 or 1) for the mode bits (S1 and S0) of the shift registers (R1 and R2). We refer to these 4 signals by R1_S1, R1_S0, R2_S1, and R2_S0. 2. Since the ASM chart includes 3 states, 2 D-Flip Flops A and B are used to represent the states as follows:

State QA QB 0 0 S0 0 1 S1 1 0 S2 Using the given state assignments and the register mode controls from the previous step, and using the ASM chart, complete the corresponding state table shown below. The last row in the table denotes the unused or don't care state. INPUTS QA 0 0 0 0 1 1 1 QB 0 0 1 1 0 0 1 BGN 0 1 P0 CNT4 QA* 0 0 QB* 0 1 RDY 1 0 RST 0 1 OUTPUTS R1_S1 0 0 R1_S0 0 0 R2_S1 0 1 R2_S0 0 1 INC 0 0

S0 S1 S2

3. Note that your completed table denotes each of the nine outputs as a sum of product terms in the five input variables. Simplify the logic using Minilog or any other CAD tool of your choice. Make sure you check both the single output and multiple output minimizations to see which will give you the best minimization. 4. Create a schematic of your multiplier circuit in Altera. Make sure you add a title block to your design and use the TTL parts described earlier in the lab. When implementing the design in Altera, there could be a potential problem due to the fact that the registers and counters have asynchronous clears. If there is a glitch in the RST logic, all of these devices will reset. Therefore to ensure there are no problems with timing, AND together the RST logic with NOT clk. This will ensure that there are no unsuspecting resets in your circuit. 5. Create an appropriate vwf file to verify your device. Study the simulated output waveforms to make sure your multiplier is working correctly and cycling through all of the states. You may wish to expand areas of the waveform display to see the details of the state transitions. Keep the radix in hexadecimal not ASCII or signed/unsigned decimal. If it is not working correctly, try tracing other signals such as the state and counter signals to determine where the error might occur. You may also wish to test for other values of the multiplier and multiplicand to see if the correct product is obtained. 6. Once your design is correct, print out a copy of your schematic and waveforms.

SECTION II.

WHAT TO TURN IN?

1. Design project header page containing your name and the signed honor code. 2. The completed state transition table along with your Minilog input and output files associated with the conceptual design of the 4-Bit Multiplier. 3. A copy of your design schematic and the output waveforms (from mult.vec) verifying that your 4-bit multiplier is working properly.

ECE 222 Advanced Logic Design Design Project #1: Binary Multiplier
January 27, 2014

Name: ____________________________________________________

Honor Code Pledge:

_____________________________________________________________________________ ______________________________________________________________________________ ____________________________________________________________________________

Signature:__________________________________________________

Please staple this sheet to the front of your assignment

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