CD54/74HC73, CD74HCT73

Data sheet acquired from Harris Semiconductor SCHS134A

February 1998 - Revised May 2000

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Description
The HC73 and CD74HCT73 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. These ip-ops have independent J, K, Reset and Clock inputs and Q and Q outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input. This device is functionally identical to the HC/HCT107 but differs in terminal assignment and in some parametric limits. The HCT logic family is functionally as well as pin compatible with the standard LS logic family.

Features
Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times Asynchronous Reset Complementary Outputs Buffered Inputs Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Signicant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH

[ /Title (CD74 HC73, CD74 HCT73 ) /Subject (Dual J-K FlipFlop

Ordering Information
PART NUMBER CD54HC73F CD54HC73F3A CD74HC73E CD74HC73M CD74HCT73E NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld CERDIP 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC 14 Ld PDIP

Pinout
CD54HC73 (CERDIP) CD74HC73, CD74HCT73 (PDIP, SOIC) TOP VIEW
1CP 1 1R 2 1K 3 VCC 4 2CP 5 2R 6 2J 7 14 1J 13 1Q 12 1Q 11 GND 10 2K 9 2Q 8 2Q

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

2000, Texas Instruments Incorporated

CD54/74HC73, CD74HCT73 Functional Diagram

14 1J 3 1K 1 1CP 2 1R 7 2J 10 2K 5 2CP 2R 6 GND = 11 VCC = 4 FF 2 9 2Q 8 2Q FF 1 12 1Q 13 1Q

TRUTH TABLE INPUTS R L H H H H H NOTE: H =High Level (Steady State) L =Low Level (Steady State) X = Irrelevant = High-to-Low Transition CP X J X L H L H X K X L L H H X H L Toggle No Change Q L No Change L H OUTPUTS Q H

Logic Diagram
14 (7) J 3(10) K 1 (5) CP nA J K CL CL R 13 (8) Q 12 (9) Q

2 (6) R

CD54/74HC73, CD74HCT73
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . . . . . .25mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .50mA

Thermal Information
Thermal Resistance (Typical, Note 3) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)

Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specication is not implied.

NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 1 V V V V V V V V V V V V V V V V V V A SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS

CD54/74HC73, CD74HCT73
DC Electrical Specications
(Continued) TEST CONDITIONS PARAMETER Quiescent Device Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II VCC and GND VCC or GND VCC - 2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL ICC VI (V) VCC or GND IO (mA) VCC (V) 0 6 MIN 25oC TYP MAX 4 -40oC TO 85oC MIN MAX 40 -55oC TO 125oC MIN MAX 80 UNITS A

-0.02

4.5

3.98

3.84

3.7

-4 0.02

4.5 4.5

0.1 0.26

0.1 0.33

0.1 0.4

V V

5.5

0.1

ICC ICC

0 -

5.5 4.5 to 5.5

100

4 360

40 450

80 490

A A

HCT Input Loading Table

INPUT All UNIT LOADS 0.3 Input Level VS HC TYPES VCC 50% VCC HCT TYPES 3V 1.3V

NOTE: Unit Load is ICC limit specied in DC Electrical Specications table, e.g., 360A max at 25oC.

NOTE: Transition times and propagation delay times

Prerequisite For Switching Specications

PARAMETER HC TYPES CP Pulse Width tw -CL = 50pF 2 4.5 6 R Pulse Width tw -CL = 50pF 2 4.5 6 80 16 14 80 16 14 100 20 17 100 20 17 120 24 20 120 24 20 ns ns ns ns ns ns SYMBOL TEST CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS

CD54/74HC73, CD74HCT73
Prerequisite For Switching Specications
PARAMETER Setup Time, J, K to CP SYMBOL tSU (Continued) VCC (V) 2 4.5 6 Hold Time, J, K to CP tH CL = 50pF 2 4.5 6 Removal Time tREM -CL = 50pF 2 4.5 6 CP Frequency fMAX CL = 50pF 2 4.5 CL = 15pF CL = 50pF HCT TYPES CP Pulse Width R Pulse Width Setup Time, J, K to CP Hold Time, J, K to CP Removal Time CP Frequency tw tw tSU tH tREM fMAX CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 15pF 4.5 4.5 4.5 4.5 4.5 4.5 5 16 18 16 3 12 30 60 20 23 20 3 15 25 24 27 24 3 18 20 ns ns ns ns ns MHz MHz 5 6 25oC MIN 80 16 14 3 3 3 80 16 14 6 30 35 TYP 60 MAX -40oC TO 85oC -55oC TO 125oC MIN 100 20 17 3 3 3 100 20 17 5 25 29 MAX MIN 120 24 20 3 3 3 120 24 20 4 20 23 MAX UNITS ns ns ns ns ns ns ns ns ns MHz MHz MHz MHz

TEST CONDITIONS CL = 50pF

Switching Specications Input tr, tf = 6ns

PARAMETER HC TYPES Propagation Delay, CP to Q tPLH, tPHL CL = 50pF 2 4.5 CL = 15pF CL = 50pF Propagation Delay, CP to Q tPLH, tPHL CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF Propagation Delay, R to Q, Q tPLH, tPHL CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF Output Transition Time tTLH, tTHL CL = 50pF 5 6 2 4.5 6 13 13 12 160 32 28 160 32 28 145 29 25 75 15 13 200 40 34 200 40 34 180 36 31 95 19 16 18 240 48 41 240 48 41 220 44 38 110 22 19 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL TEST CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS

CD54/74HC73, CD74HCT73
Switching Specications Input tr, tf = 6ns
PARAMETER Input Capacitance Power Dissipation Capacitance (Notes 5, 6) HCT TYPES Propagation Delay, CP to Q Propagation Delay, CP to Q Propagation Delay, R to Q, Q Output Transition Time Input Capacitance Power Dissipation Capacitance (Notes 5, 6) NOTES: 6. PD = CPD VCC2 fi + CL VCC2 fo where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage. 5. CPD is used to determine the dynamic power consumption, per flip-flop. tPLH, tPHL tPLH, tPHL tPLH, tPHL tTLH, tTHL CI CPD CL = 50pF CL = 50pF CL = 50pF CL = 50pF 4.5 4.5 4.5 4.5 5 28 38 36 34 15 10 48 45 43 19 10 57 54 51 22 10 ns ns ns ns pF pF SYMBOL CI CPD (Continued) VCC (V) 5 25oC MIN TYP 28 MAX 10 -40oC TO 85oC -55oC TO 125oC MIN MAX 10 MIN MAX 10 UNITS pF pF

TEST CONDITIONS -

Test Circuits and Waveforms

trCL CLOCK 90% 10% tfCL tWL + tWH = I fCL VCC 50% 10% tWL 50% 50% GND tWH CLOCK 2.7V 0.3V trCL = 6ns tWL + tWH = tfCL = 6ns I fCL 3V 1.3V 0.3V tWL 1.3V 1.3V GND tWH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH

tr = 6ns INPUT 90% 50% 10%

tf = 6ns VCC

tr = 6ns INPUT GND 2.7V 1.3V 0.3V

tf = 6ns 3V

GND tTLH 90%

tTHL

tTLH 90% 50% 10% tPHL tPLH

tTHL

INVERTING OUTPUT

INVERTING OUTPUT tPHL tPLH

1.3V 10%

FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC

FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC

CD54/74HC73, CD74HCT73 Test Circuits and Waveforms

trCL CLOCK INPUT 90% 10% tH(H) 50% GND tH(L) VCC DATA INPUT tSU(H) tTLH 90% OUTPUT tPLH tREM VCC SET, RESET OR PRESET tSU(L) tTHL 90% 50% 10% tPHL tREM 3V SET, RESET OR PRESET 50% GND tSU(H) tTLH OUTPUT 90% 1.3V tPLH 90% 1.3V 10% tPHL tSU(L) tTHL DATA INPUT tfCL VCC CLOCK INPUT

(Continued)
trCL 2.7V 0.3V tH(H) 1.3V GND tH(L) 3V 1.3V 1.3V 1.3V GND tfCL 3V

50% GND

1.3V GND

IC

CL 50pF

IC

CL 50pF

FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS

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Copyright 2000, Texas Instruments Incorporated