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UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Lingkai Kong Homework 1 Due Thursday, Feb. 7th 2013 EECS 240

Use the EECS 45nm GPDK design kit in all homework and projects unless otherwise noted. The setup of Cadence as well as the PDK can be found on the course website. 1. This problem reviews some of the basic analysis you have learned in EE140 or its equivalent. Please analyze the simple amplier design shown below with the assumption that the small signal output impedance (ro ) is innity.

RF Vout RS Vin R1 C1

Figure 1: Schematic of problem 1 (a) Draw the small signal model of the above circuit. For simplicity, you can include only Cgs and set both Cd and Cds to be zero. (b) As a function of the transistors transconductance gm and resistors RS , RF and R1 , what is the DC small signal gain of this amplier (Vout /Vin )? (c) Calculate the AC response of the amplier and sketch the Bode plot of Vout /Vin . You need to lable the positions of poles and zeros and the corresponding magitude of the transfer function. 2. In this problem we will look at the design of MOM capacitors in our 9-layer metal process. Unless otherwise noted, you should assume that all metal layers have a thickness T = 200nm, minimum width W = 100nm, minimum horizontal spacing S = 100nm, vertical spacing H = 200nm, and that the insulator is SiO2 ( r = 3.9). You can assume that the separation of the lowest layer of metal from the substrate is also H = 200nm, and that the inter-layer vias have the same width as the wires they are connected to. For simplicity, you can ignore fringing elds in all of these calculations. (a) What is the maximum capacitance density (in f F/m2 ) you can achieve with horizontal parallel plate? What is the ratio of capacitance to bottom plate parasitic? (b) What is the maximum capacitance density (in f F/m2 ) you can achieve with vertical parallel plate? You can assume you are able to build a via wall without any spacing between vias. Now what is the ratio of capacitance to bottom plate parasitic? (c) In both cases, removing bottom layers can reduce the bottom plate parasitic at the cost of lower capacitance density. Plot the ratio of the bottom plate parasitic to the capacitance versus the capcitance density.

3. In this problem you will need to run BAG or Spectre/HSPICE (or whatever your favorite simulator is). For some of the problems you should access internal device parameters such as gm or Vth . If you do not know how to do that, please come to the discussion session. If you are using BAG, please refer to the BAG tutorial for the syntax. For this problem, you should plot the results for all of the process corners provided in the library (i.e. SS, TT, FF). Unless otherwise specied, use minimum length transistors with W = 1m and a maximum |Vgs | and |Vds | of 1.0V. (a) Plot the magnitude of the threshold voltage of an NMOS and PMOS transistor as a function of the channel length L. You should sweep L from 50nm to 500nm be sure to use a step size small enough to measure a smooth curve. (b) Plot the gm versus Vgs of an NMOS on a linear AND log scale, biasing the transistor with Vgs = Vds . (c) Plot gm /Ids as a function of |Vgs | (still with Vgs = Vds ) for an NMOS AND PMOS with L=50nm, 100nm, 150nm, and 200nm. (d) Use the data from part (c) to plot V = 2Ids /gm as a function of |Vgs |. (e) Using the data from part (c), plot Ids as a function of V . (f) Plot the output resistance ro and DC gain gm ro versus Vds for an NMOS and PMOS. You should bias the transistors with V = 200mV . What is the allowed output swing to maintain a DC gain of 80% of the peak value? If you are not sure how to set up this simulation, please come to the disscussion session as well. (g) Plot fT and fT (gm /Ids ) as a function of |Vgs Vth | for L=50nm, 100nm, 150nm, and 200nm. You should set Vgs = Vds and vary |Vgs Vth | from 0 to 500mV. What is the V that achieves the maximum fT (gm /Ids ) for each channel length?