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Spring 2014
Please bring your code to lab and demonstrate your design on the board and also turn in a printed write-up containing your code and a small description of your design. For this assignment you will design the following timer module that counts up every 0.1s and displays the 4-digit count on the 4-digit seven segment display. timer_100ms enable G18 timing_gen
hundred_ms one_ms d0 d1 d2 d3 display_ digit
display_controller
an0
clk
timer_100ms is the top module of this design and consists of timing_gen, bcd_counter_4d, bin_to_sseg and display_controller modules. For this assignment you will do the following: Write timer_100ms Use timing_gen module provided at the end Write bcd_counter_4d re-use bin_to_sseg from assignment 1 1
EC1610 Advanced Digital Design. Spring 2014 write testbench to verify your design
Input enable is connected using FPGA pin G18 to Switch 0 on the board. Input reset is connected using FPGA pin H13 to BTN3 on the board. Input clk is connected using FPGA pin B8 to the 50MHz clock on the board. Outputs ca, cb, cc, cd, ce, cf and cg connect to the seven segment display on the board the same way as in assignment 1. Outputs an0, an1, an2 and an3 are connected using FPGA pins F17, H17, C18 and F15 respectively. The timing_gen module divides down in the input 50MHz clk to generate the one_ms pulse every 1 ms. It also generates the hundred_ms pulse every 100ms. The bcd_counter_4d is a four digit BCD counter. BCD stands for Binary Coded Decimal. It uses 4bits to represent a single decimal digit. Each digit counts in the sequence 0b0000, 0b0001, 0b0010 till 0b1001 and the n back to 0b0000 (i.e. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 and then restart from 0). bcd_counter_4d has the following I/O: module bcd_counter_4d( input reset, input clk, input enable, // 0=suspend counting 1=allowing counting input incr, // count up when high output output output output ); d3, d2, d1, d0 form a four digit decimal number. The decimal count goes up by one if enable is high and incr is high. If enable is low then counting is suspended. The counting should be 0000, 0001, 0002 to 0009 then 0010, 0011 and so on. Connect the hundred_ms signal from timing_gen to the incr input of bcd_counter_4d so that the count goes up by one every hundred_ms. The enable input of bcd_counter_4d is controlled by Switch 0 on the board. The digits from the bcd_counter_4d are sent to a multiplexer. The output of the multiplexer is sent to the bin_to_sseg module. 2 [3:0]d0, [3:0]d1, [3:0]d2, [3:0]d3, // // // // BCD BCD BCD BCD digit digit digit digit 0 1 2 3
display_counter module contains a state machine that controls the multiplexer and the seven segment display anodes an0, an1, an2, an3. The state machine should display each digit for 1ms sequentially as follows: set an0 = 0, other ans to set an1 = 0, other ans to set an2 = 0, other ans to set an3 = 0, other ans to repeat above sequence. 1 1 1 1 and and and and set set set set display_digit display_digit display_digit display_digit to to to to d0 d1 d2 d3 for for for for 1ms 1ms 1ms 1ms
Draw a State Transition Diagram for this state machine. Use the following code for the timing_gen (put in timing_gen.v file): module timing_gen ( input reset, input clk, // global reset // clock signal // one ms pulse // 100 ms pulse
// clock divider to generate 1ms pulse from 50MHz clock reg [15:0]clk_counter; wire ons_ms_count = (clk_counter == 49999); always @(posedge reset or posedge clk) begin if (reset) begin clk_counter <= 0; one_ms <= 0; end else begin if (ons_ms_count) begin clk_counter <= 0; one_ms <= 1; end else begin clk_counter <= clk_counter + 1; one_ms <= 0; end end end
// generate 100ms pulse using the one_ms pulse reg [6:0] one_ms_counter; wire hundred_ms_count = (one_ms_counter == 99); always @(posedge reset or posedge clk) begin if (reset) begin one_ms_counter <= 0; hundred_ms <= 0; end else begin if (one_ms & hundred_ms_count) begin one_ms_counter <= 0; hundred_ms <= 1; end else if (one_ms) begin one_ms_counter <= one_ms_counter + 1; hundred_ms <= 0; end else hundred_ms <= 0; end end endmodule