CHAPTER 10 OPERATIONAL-AMPLIFIER CIRCUITS

Chapter Outline
10.1 The Two-Stage CMOS Op Amp
10.2 The Folded-CascodeCMOS Op Amp
10.3 The 741 Op-Amp Circuit
10.4 DC Analysis of the 741
10.5 Small-Signal Analysis of the 741
10.6 Gain, Frequency Response, and Slew Rate of the 741
10.7 Modern Techniques for the Design of BJ T Op Amp
NTUEE Electronics L.H. Lu 10-1
10.1 The Two-Stage CMOS Op Amp
Multi-stage amplifiers
Practical transistor amplifiers usually consist of a number of stages connected in cascade
Input stage:
High input resistance to avoid signal loss due to high-resistance source
Voltage gain
Large CMRR for differential amplifiers
Middle stages:
Voltage gain
Shifting of the dc level for required voltage swing
Differential tosingle-endedconversionif necessary
NTUEE Electronics L.H. Lu 10-2
Differential to singleended conversion if necessary
Output stage:
Low output resistance to avoid loss of gain due to low-resistance load
Current supply required by the load
Sufficient voltage swing required by the load
Small-signal approximation may not apply
Circuit Configuration
Most widely used op amp in VLSI circuits
Bias circuit: I
REF
and Q
8
Input stage: Q
1
-Q
5
Active-loaded MOS differential pair
Differential input and single-ended output
Provides voltage gain and high input resistance
Output stage: Q
6
-Q
7
Active-loaded common-source amplifier
Providesvoltagegain Provides voltage gain
High output resistance (not suitable for low-impedance loads)
DC arrangement:
The bias current of the input differential pair is provided by Q
5
The bias current of the second stage is provided by Q
7
To avoid systematic (predictable) offset:
NTUEE Electronics L.H. Lu 10-3
5
7
4
6
) / (
) / (
2
) / (
) / (
L W
L W
L W
L W
=
Input common-mode range and output swing
The transistors are supposed to be in saturation for proper circuit operation
ICMR:
Output swing:
Voltage gain
Low-frequency small-signal gain:
5 1 3 OV OV tp DD ICM tp tn OV SS
V V V V V V V V V s s + +
7 6 OV DD O OV SS
V V v V V s s +
) || (
||
6 2
4 2 1 1 1 1
4 2 1
2 1 1
m m
o o m m
o o
m m m
g G
r r g R G A
r r R
g g G
=
= =
=
= =
Amplifier prototype:
Input resistance:
Output resistance:
Transconductance:
Common-mode rejection ratio:
NTUEE Electronics L.H. Lu 10-4
) || ( ) || (
) || (
||
7 6 6 4 2 1 2 1
7 6 6 2 2 2
7 6 2
6 2
o o m o o m v
o o m m
o o
m m
r r g r r g A A A
r r g R G A
r r R
g
= =
= =
=
6 4 2 1
) || (
m o o m m
g r r g G =
=
i
R
7 6
||
o o o
r r R =
SS m o o m
R g r r g CMRR
3 4 2 1
2 ) || ( =
Frequency response
Poles and zeros
C
m
Z
m
P
C m
P
L gd db db
gs db gd db gd
C
G
f
C
G
f
C R G R
f
C C C C C
C C C C C C
2
1
2
2
2
2 2 1
1
7 7 6 2
6 4 4 2 2 1
2
1
2
1
1
2
1
t
t
t
~
~
~
+ + + =
+ + + + =
f
P2
decreases for a capacitive load
May result in stability issue
Unity-gain frequency for a dominant pole case
and
Phase margin
NTUEE Electronics L.H. Lu 10-5
C
m
P v t
C
G
f A f
1
1
2
1
t
= ~
2 1 m m
G G <
2
2 1
C
G
C
G
m
C
m
<
) / ( tan ) / ( tan 90 180
) / ( tan ) / ( tan 90
) / ( tan
) / ( tan
1
2
1
1
2
1
1
2
1
2
Z t P t total
Z t P t total
Z t Z
P t P
f f f f PM
f f f f
f f
f f

= =
+ + =
=
=

|
|
|
|
Phase margin improvement technique
Adding a series resistance in the feedback path
The zero is defined by
The zero can be moved toward higher frequencies for better phase margin
Slew rate
Slew rate is defined as the maximum voltage change rate at output
Associatedwithcharging/dischargingtimeof C
2 2
2
1
i m
i
V G
sC
R
V
=
+
|
|
.
|

\
|

=
R
G
C
s
m
C
2
1
1
Associated with charging/discharging time of C
C
Extreme cases:
Limited by bias current of Q
5
(typical case): SR =I/C
C
Limited by bias current of Q
7
: SR =I
7
/C
C
Relationship between SR and f
t
SR =2tf
t
V
OV
=e
t
V
OV
Slew rate is determined by the overdrive voltage
for a given unity-gain frequency
PMOS devices are preferred for the differential pair
with a fixed current I at the cost of lower gain
NTUEE Electronics L.H. Lu 10-6
Power-supply rejection ratio (PSRR)
PSRR is defined as the ratio of the amplifier differential gain to the gain from the supply voltage
Design trade-offs
CMOS two-stage op amp performance is determined by
The channel length of the MOSFETs
Theoverdrivevoltageof theMOSFETs
ss o
id o d
dd o
id o d
v v
v v
A
A
PSRR
v v
v v
A
A
PSRR
/
/
/
/
=
=

+
+
The overdrive voltage of the MOSFETs
Performance benefit for a larger channel length: gain, CMRR, PSRR
Performance benefit for a smaller overdrive voltage: gain, CMRR, PSRR, ICMR, output swing and offset
Performance benefit for a larger overdrive voltage: high-frequency characteristics (gain)
For modern submicron CMOS technologies:
Typical V
OV
between 0.1 to 0.3 V
Channel length is at least 1.5 to 2 times minimum length (L
min
)
NTUEE Electronics L.H. Lu 10-7
2
5 . 1
2
1
2
1
L
V
C C
g
f
OV n
gd gs
m
T

t t
~
+
=
10.2 The Folded-Cascode CMOS Op Amp
Circuit Configuration
Cascodetopology to increase the gain of the input differential pair
Folded topology to improve the ICMR and to reduce the required supply voltage
Is generally considered a single-stage amplifier
Also called operational transconductanceamplifier (OTA)
DC bias:
Bias current for Q
1
-Q
2
is I/2
Bias current for Q
3
-Q
8
is I/2 I
B
I
B
can be realized by MOS current mirrors
NTUEE Electronics L.H. Lu 10-8
Input common-mode range and output swing
ICMR:
Output swing:
Voltage gain
High voltage gain due to increased output resistance
Not desirable for applications where low output resistance is needed for the op amp
F
tn OV DD ICM tn OV OV SS
V V V V V V V V + s s + + +
9 1 11
4 10 7 5 OV OV DD O tn OV OV SS
V V V v V V V V s s + + +
)} ( || )] || ( {[
) ( || )] || ( [ ||
8 6 6 10 2 4 4 2
8 6 6 10 2 4 4 6 4
2 1
o o m o o o m m o m v
o o m o o o m o o o
m m m
r r g r r r g g R G A
r r g r r r g R R R
g g G
~ =
~ =
= =
Frequency response
Dominant pole at the output node
Excellent high-frequency response
Slew rate
The slew rate is limited by the bias current I and the load CL
Slew rate SR =I/C
L
=2tf
t
V
OV1
for I
B
>I
Typically I
B
is set 10% ~20% larger than I
NTUEE Electronics L.H. Lu 10-9
o L
o m
id
o
R sC
R G
V
V
+
=
1
L
m
t
C
G
f
t 2
1
=
Increasing the ICMR: rail-to-rail input operation
NMOS and PMOS differential pairs in parallel
ICMR exceeds the power supply voltage
Differential output voltage provided
ICM in the middle:
Both pairs operate simultaneously
A
v
=2G
m
R
o
ICM near supply voltage:
Only one of the pairs is operational
Gaindropstohalf Gain drops to half
Increasing the output voltage range: wide-swing current mirror
Modified cascodecurrent mirror
Output swing increased by V
t
Output resistance remains the same
A proper dc bias voltage V
BIAS
is needed
NTUEE Electronics L.H. Lu 10-10
The BJT Device
High-frequency hybrid-t model:
The base-charging or diffusion capacitance C
de
:
The base-emitter junction capacitance C
je
:
The collector-base junction capacitance C

:
T
C
F m F de
V
I
g C t t = =
0
2
j je
C C ~
m
c
CB
V
V
C
C
|
|
.
|

\
|
+
=
0
0
1

The cutoff (unity-gain) frequency:

NTUEE Electronics L.H. Lu 8-11
c
V
. \ 0
T
C m
T
m
fe
m
b
c
fe
b
b
m c
V C C
I
C C
g
f
r C C s r C C s
r g
h
C C s r
sC g
I
I
h
sC sC r
I
C C r I V
V sC g I
) ( 2
1
2
1
) ( 1 ) ( 1
) ( / 1
/ 1
) || || (
) (
0
t t
t t t t
t
t t

t t
t t t
t
t t
|
+
=
+
=
+ +
=
+ +
~
+ +

=
+ +
= =
=
8.3 The 741 Op-Amp Circuit
741 Op-Amp
Device parameters:
npn: I
S
=10
-14
A, | =200, V
A
=125 V
pnp: I
S
=10
-14
A, | =50, V
A
=50 V
NTUEE Electronics L.H. Lu 10-12
Bias circuit:
Reference current generated by Q
11
, Q
12
and R
5
Bias for input stage: Widlar current source (Q
10
, Q
11
and R
4
) and current mirror Q
8
, Q
9
Bias for second stage: current mirror Q
12
, Q
13B
(Q
13
is a two-output current source)
Bias for output stage: current mirror Q
12
, Q
13A
/Q
18
-Q
19
provides 2V
BE
drop between V
B14
and V
B20
Input stage: (Q
1
-Q
7
, R
1
-R
3
)
Input emitter follower (Q
1
-Q
2
): high input resistance
Current-mirror load (Q
5
-Q
7
, R
1
-R
3
):high output resistance and differential to single-ended conversion
Level shifting (Q
3
and Q
4
): for required voltage swing and dc level at the input of the second stage
Secondstage: (Q
16
-Q
17
, Q
13B
, R
8
-R
9
) Second stage: (Q
16
Q
17
, Q
13B
, R
8
R
9
)
Emitter follower Q
16
for high input resistance
Common-emitter Q
17
for voltage gain
Miller compensation technique by C
C
Output stage: (Q
14
, Q
20
)
Complementary pair Q
14
and Q
20
Low output resistance
Relatively large load current without dissipating a large amount of power
Emitter follower Q
23
to increase input resistance of the output stage
Short-circuit protection circuitry Q
15
, Q
21
, Q
24
, Q
22
, R
6
, R
7
, R
11
NTUEE Electronics L.H. Lu 10-13
10.4 DC Analysis of the 741
Reference bias current
Provided by Q
11
, Q
12
and R
5
I
REF
=0.73 mA (for V
CC
=V
EE
=15 V)
Input-stage bias
Widlar current source Q
11
, Q
10
and R
4
:
I =19A
5
11 12
) (
R
V V V V
I
EE BE EB CC
REF

=
4 10
10
ln R I
I
I
V
C
C
REF
T
=
|
|
.
|

\
|
I
C10
=19 A
Current mirror Q
8
and Q
9
:
I
C1
=I
C2
~ I
C3
=I
C4
=9.5 A
Q
1
-Q
4
and Q
8
-Q
9
form a negative feedback loop
Bias current can be stabilized by the negative feedback
NTUEE Electronics L.H. Lu 10-14
10
2
/ 2 1
2
C
P P
I
I I
= +
+ | |
Current-source load Q
5
-Q
7
and R
1
-R
3
I
C7
=10.5 A
Input bias current and offset currents
Input bias current:
I
B
=47.5 nA
I ff
3
2
3
2 6
7 7
6 5
) / ln( 2 2
R
IR I I V I
R
IR V I
I I
I I I
S T
N
BE
N
E C
C C
+
+ =
+
+ = ~
~ =
| |
N
B B
B
I I I
I
|
=
+
=
2
2 1
Input offset current:
Non-zero input offset due to mismatches in the | value
Input common-mode range:
Input common-mode voltage over which the input stage remains in the linear active mode
The upper end limited by saturation of Q
1
and Q
2
The lower end limited by saturation of Q
3
and Q
4
NTUEE Electronics L.H. Lu 10-15
2 1 B B OS
I I I =
Second-stage bias
I
C17
~ I
C13B
=550 A
V
EB17
=618 mV and I
C16
=16.2 A
Output-stage bias
DC for Q
23
:
|
|
.
|

\
|
=
~ ~
S
C
T BE
REF B C C
I
I
V V
I I I
17
17
13 17
ln
75 . 0
9
17 8 17
17 16 16
R
V R I
I I I
BE E
B E C
+
+ = ~
I
C23
~ 180 A (I
B23
~ 3.6 A negligible for I
C17
)
DC for Q
18
-Q
19
:
I
C18
~ 165 A and I
C19
~ V
BE18
/R
10
+I
B18
=15.8 A
DC for Q
14
and Q
20
:
V
BB
=V
BE18
+V
BE19
=588 mV +530 mV =1.118 V
I
C14
=I
C20
=154 A (for I
S14
=I
S20
=310
-14
A)
NTUEE Electronics L.H. Lu 10-16
REF E C
I I I 25 . 0
23 23
~ ~
|
|
.
|

\
|
=
~
S
C
T BE
BE REF C
I
I
V V
R V I I
18
18
10 18 18
ln
/ 25 . 0
10.5 Small-Signal Analysis of the 741
The input stage
Differential input resistance:
r
e
=2.63 kO and R
id
=2.1 MO
Transconductance:
G
m1
=0.19 mA/V
Outputresistance:
e N id
e i e
r R
r v i
) 1 ( 4
) 4 /(
+ =
=
|
1 1
2
1
2
2
m
e i
e
i
o
m
g
r v
i
v
i
G = = ~
o o
Output resistance:
R
o4
=r
o4
[1 +g
m4
(r
e4
||r
t2
)] =10.5 MO
R
o6
=r
o6
[1 +g
m6
(R
2
||r
t6
)] =18.2 MO
R
o1
=R
o4
||R
o6
=6.7 MO
Equivalent circuit for the input stage:
NTUEE Electronics L.H. Lu 10-17
)] || ( 1 [
t
r R g r R
e m o o
+ =
The second stage
Input resistance
R
i2
~ 4 MO
Transconductance
)]} )( 1 ( || [ ){ 1 (
8 17 17 9 16 16 2
R r R r R
e e i
+ + + + = | |
17 9 17
2
17 9 6
17 9
2 17
8 17
17
17
||
||
||
||
i c
m
i e
i
i b
e
b
c
R R r
R R
R r v
i
G
R R r
R R
v v
R r
v
i
+ +
=
+
=
+
=
o
o
G
m2
=6.5 mA/V
Output resistance
R
o2
=81 kO
Equivalent circuit for the second stage:
NTUEE Electronics L.H. Lu 10-18
17 9 6 8 17 2
||
i e e i
R R r R r v + +
)]} || ( 1 [ { || ||
8 17 17 17 13 17 13 2
R r g r r R R R
m o B o o B o o t
+ ~ =
The output stage
Output voltage limits
approximately 1 V below V
CC
and 1.5 V above V
EE
Input resistance (for R
L
=2 kO, I
C20
=5 mA and I
C14
=0)
R
in3
~ 3.7 MO
Open-circuitvoltagegain
20 23 min
14 max
EB EB CEsat EE O
BE CEsat CC O
V V V V v
V V V v
+ + + =
=
) || ( ) || )( 1 (
) 1 (
13 20 23 13 20 23 23 3
20 20 20 20
A o i A o i in
L L i
r R r R r R
R R r R
| |
| |
t
t
~ + + ~
~ + + =
Open circuit voltage gain
Transconductance
NTUEE Electronics L.H. Lu 10-19
1
2
3
~ =
=
L
R
o
o
vo
v
v
G
20
20
0
3
3
20 23 23 3
1
m
e
R
i
o
m
b e b i
g
r v
i
G
v v v v
L
~ ~
= ~ =
=
Output resistance
R
out
~ 34 O
Equivalent circuit for the output stage
1 1
||
1
20
23
20
20
13 23
20
23
2
23 23
+
+ ~
+
+ =
+
+ =
| |
|
o
e
A o o
e out
o
e o
R
r
r R
r R
R
r R
Output short-circuit protection
One of the two output transistors could conduct
a large amount of current if output is short-circuited
Short-circuit protection is adopted in the 741 op amp
For current source case (I
C14
>20 mA)
V
BE15
>540 mA
Q
15
turns on and takes away the base current of Q
14
I
C14
is limited as the base current is reduced
Similar case for current sink case (I
C20
>20 mA)
NTUEE Electronics L.H. Lu 10-20
10.6 Gain, Frequency Response and Slew Rate of the 741
Small-signal gain
A
v
=243147 V/V =107.7 dB
Frequency response
out L
L
vo o m i o m
o
o
i
o
i
i
i
o
v
R R
R
G R G R R G
v
v
v
v
v
v
v
v
A
+
= =
3 2 2 2 1 1
2 2
2 2
) )( || (
P t
t in
P
i o t
C in
f A f
R C
f
R R R
A C C
0
2 1
2
1
2
1
||
|) | 1 (
=
=
=
+ =
t
f
P
=4.1 Hz
f
t
=1 MHz
Slew rate
SR =0.63 V/s
Relationship between f
t
and slew rate
Slew rate of MOS opampwith same f
t
is 2~3 times higher than the 741
G
m
-reduction method: total bias current is kept constant with reduced G
m1
NTUEE Electronics L.H. Lu 10-21
C
C
I
SR
2
=
t T
V SR e 4 =