BOUNDARY SCAN TEST

Presented By: Devendra Singh Sagar Balecha

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Interconnect Faults
Short faults Open faults Delay faults Noise/ crosstalk Ground bounce

Short Faults

Possible shorts: : bond wire, leg, solder, interconnect wired-wired-AND, wired Shorts are usually modeled as wired OR faults
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 Miniaturization of electronic components. Multilayer and surface mount techniques.

Test of boards become more complicate!!

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 On this problem small group from European electronics companies meets first time in 1985. Later North American companies joined the group called Joint Test Action Group (JTAG)

Boundary Scan
Boundary scan is a method for testing interconnects (wire lines) on printed circuit boards or sub-blocks inside an integrated circuit. Boundary scan is also widely used as a debugging method to watch integrated circuit pin states, measure voltage, or analyze subblocks inside an integrated circuit.
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Joint Test Action Group (JTAG)

The Joint Test Action Group(JTAG) developed a specification for boundary scan testing that was standardized in 1990 as the IEEE Standard
Test Access Port and Boundary-Scan Architecture.

The boundary scan architecture provides a means to test interconnects (including clusters of logic, memories, etc.) without using physical test probes.
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PCB Level or Core Level Testing

After the fabrication of the circuit. There are two types of PCB level testing. 1. Bad of Nails testing(IN early 90s). 2. Boundary scan test.

Bad of Nails Testing

Disadvantages
It takes long time. No specific input or output patterns are decided. Usually works with small circuits More problems arises when IC design shifts to system on chip.

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System on Chip

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An Introduction (Boundary Scan Test)

Basically it is a protocol (IEEE standard 1149.1) of testing. It is also known as JTAG. Protocol is the set of rules decided by IEEE to i.e. have to followed every vendors or company to made the testing specification.

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Basic Concept (Binary Scan Cells)

It defines a test for digital and mixed signals processing ICs. Its named due to use of boundary scan cells. Inputs and outputs of ICs are accessible by Binary scan cell (BSC). The serial chain of this BSC performs.
Scan Capture Update
Note: These operations enables testing in the chip.
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Basic Concept (Binary Scan Cells)

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For More than one cells

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Test Architecture

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Test Architecture
Test Access Ports.
TDI (Test Data Inputs). TDO (Test Data Outputs). TMS (Test Mode Selects). TCK (Test clock).

* TRST (Test reset).

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Test Architecture
Instructions registers
Mandatory Mandatory Mandatory

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Test Architecture
Registers
Test Data Registers Bypass Registers Misc. Registers
Device ID register Design Specified Registers

Boundary Scan Registers (Collection of Boundary scan Cells)

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Test Architecture
Boundary Scan Cells

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Working of BSC
IN : Input Signal line OUT: Output Signal tied to input of internal logic. S0: Previous cells output. SI: Next cells input.

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Working of BSC
When Mode = 0 Then OUT=IN When Mode = 1 Then three main test operation occurs a. Capture b. Shift c. Update
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Working of BSC
a. Capture If shiftDR = 0 after one clock S0=IN b. Shift If shiftDR = 1 after one clock S0=SI c. Update If shiftDR = 0 after clocks and updateDR = 1 Then OUT = IN
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Tap Controller
It generates following Control Signals
1. 2. 3. 4. 5. 6. 7. 8. 9. Clock DR Shift DR Update DR Clock IR Shift IR Clock IR Select T Clock Enable (Reset)

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How it Works?
1. A boundary-scan test instruction is shifted into the IR through the TDI. 2. The instruction is decoded by the decoder associated with the IR to generate the required control signals so as to properly configure the test logic. 3. A test pattern is shifted into the selected data register through the TDI and then applied to the logic to be tested. 4. The test response is captured into some data register.
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How it Works?...
5. The captured response is shifted out through the TDO for observation and, at the same time, a new test pattern can be scanned in through the TDI. 6. Steps 3 to 5 are repeated until all test patterns are shifted in and applied, and all test responses are shifted out.

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