i

DESIGN OF CMOS 1K BIT SRAM

B.Tech. Project Report






G.Achyuth Varma (09241A0401)
E.Harish (09241A0408)
D.Santosh (09241A0425)
G.Sankaraiah (09241A0432)











DEPARTMENT OF ELECTRONICS AND
COMMUNICATION ENGINEERING

GOKARAJU RANGARAJU INSTITUTE OF
ENGINEERINGAND TECHNOLOGY
(Affiliated to Jawaharlal Nehru Technological University)

HYDERABAD 500 090
2013
ii


DESIGN OF CMOS 1K BIT SRAM



Project Report Submitted in Partial Fulfilment of
the Requirements for the Degree of

Bachelor of Technology
In
Electronics and Communication Engineering
by

G.Achyuth Varma
E.Harish
D.Santosh
G.Sankaraiah









DEPARTMENT OF ELECTRONICS AND
COMMUNICATION ENGINEERING

GOKARAJU RANGARAJU INSTITUTE OF
ENGINEERINGAND TECHNOLOGY
(Affiliated to Jawaharlal Nehru Technological University)

HYDERABAD 500 090

2013

iii


Department of Electronics and Communication Engineering

Gokaraju Rangaraju Institute of Engineering and Technology
(Affiliated to Jawaharlal Nehru Technological University)


Hyderabad 500 090

2013









Certificate

This is to certify that this project report entitled Design of CMOS 1K bit SRAM by
G.Achyuth Varma, E.Harish, D.Santosh and G.Sankaraiah, submitted in partial fulfilment
of the requirements for the degree of Bachelor of Technology in Electronics and
Communication Engineering of the Jawaharlal Nehru Technological University,
Hyderabad, during the academic year 2012-13, is a bonafide record of work carried
out under our guidance and supervision.
The results embodied in this report have not been submitted to any other University or
Institution for the award of any degree or diploma.








(Guide) (External Examiner) (Head of Department)

G. Surekha Professor Dr. Ravi Billa



iv

ACKNOWLEDGMENT


We have taken efforts in this project. However, it would not have been possible without
the kind support and help of many individuals and organizations. We would like to extend my
sincere thanks to all of them.

We are highly indebted to Mrs G.Surekha, Asst.Professor and dept. of E.C.E, GRIET,
Hyderabad, for their guidance and constant supervision as well as for providing necessary
information regarding the project & also for their support in completing the project.

We would like to express our special gratitude and thanks to Dr. Ravi billa HOD-ECE, Mr
K. N. Balaji kumar, Mr Radhanand and Mr V. H. Raju for giving us such attention and time.



G. Achyuth Varma ________________________

E.Harish ________________________

D.Santosh _______________________

G.Sankaraiah ________________________

PLACE: HYDERABAD
DATE: 23-04-2013


v

ABSTRACT
In todays technological environment, there is a huge demand for devices with low
power and low cost storage space. Memories with low power are driving the entire VLSI
industry mainly because most of the devices work on remote power supply. Demand of low
power becomes the key of VLSI designs rather than high speed, particularly in embedded
SRAMs and caches. Leakage current of memory increases with the capacity such that more
power will be consumed even in the standby cycle. Many schemes exist mentioned to
improve power consumption of the SRAM. However, there are many challenges in the design
of both embedded and standalone SRAMs such as, the estimation and optimization of stand-
by power and design of high-speed peripheral circuits.
The objective of this project is to design and implement 1Kbit SRAM in 180nm
Technology with the supply voltage of 1.8V. The total number of address lines needed for
accessing 1024 locations is ten. 6T (6 transistors) cell is used to store one bit data. The design
blocks required are Precharge circuit, Sense amplifier, 2x4 Decoder and 4 by1 multiplexer
1Kbit CMOS SRAM cell. Each and every block is verified functionally. Pre-layout and post
layout simulations are performed and the outputs are analysed for functionality. This project
was implemented using CADENCE Tools. Full Custom Layout of the 1Kbit SRAM was
realized using Virtuoso Layout editor. DRC and LVS were verified using ASSURA and the
parasitic extraction and post layout simulation were performed using SPECTRE.








vi

List of Figures
2.1 Typical microprocessor memory configuration...................................................................5
2.2 SRAM cell............................................................................................................................7
2.3 Simplified model of CMOS SRAM cell during read (Q=1, Vprecharge=VDD).................8
2.4 Voltage rise inside the cell upon read versus Cell ratio (Ratio of M1/M5) ......................10
2.5 Simplified model of CMOS SRAM cell during write (Q=1).............................................11
2.6 Voltage written into the cell versus pull up ratio (size ratio between the PMOS pull up
and access transistor)................................................................................................................12
2.7 4-Transistor SRAM cell.....................................................................................................13
2.8 6-Transistor SRAM cell.....................................................................................................14
2.9 Thin film transistor SRAM cell..........................................................................................14
3.1 Architecture of SRAM 1bit................................................................................................17
3.2 Precharge circuit.................................................................................................................18
3.3 Data enable circuit..............................................................................................................19
3.4 Sense amplifier circuit........................................................................................................20
3.5 SRAM 1bit.........................................................................................................................21
3.6 Architecture of SRAM 4bit................................................................................................24
3.7 2 to 4 Decoder....................................................................................................................25
3.8 4 by 1 Multiplexer..............................................................................................................26
3.9 SRAM 1024bit Architecture..............................................................................................30








vii

Contents
Chapter1 ..................................................................................................................................... 1
INTRODUCTION ..................................................................................................................... 1
1.1 Aim of the project: ........................................................................................................... 1
1.2 Methodology: ................................................................................................................... 2
1.3 Significance of this Work:................................................................................................ 4
1.4 Designing Environment: .................................................................................................. 4
Chapter 2 .................................................................................................................................... 5
CLASSIFICATION OF SRAM ................................................................................................. 5
2.1 INTRODUCTION ............................................................................................................ 5
2.2 SRAM CELL.................................................................................................................... 6
2.2.1 CMOS SRAM-Read Operation ..................................................................................... 7
2.2.2 CMOS SRAM Write Operation ................................................................................ 10
2.3 OTHER TYPES OF SRAM CELLS .............................................................................. 12
2.3.1 4T (Four Transistor) Cell ......................................................................................... 12
2.3.2 6T (Six Transistor) Cell ........................................................................................... 13
2.3.3 TFT (Thin Film Transistor) Cell ............................................................................. 14
2.4 CLASSIFICATION OF SRAM ..................................................................................... 15
Chapter3 ................................................................................................................................... 17
Design of CMOS-1024 bit SRAM ........................................................................................... 17
Fig 3.1 Architecture of SRAM 1bit ...................................................................................... 17
3.1.1Precharge: ................................................................................................................. 18
3.1.2Data Enable circuit ................................................................................................... 18
3.1.3 Sense amplifier ........................................................................................................ 19
3.1.4SRAM 1bit design diagram ...................................................................................... 20
3.3 SRAM 4bit ..................................................................................................................... 23
3.4 2 to 4 Decoder: ............................................................................................................... 24
3.5 4 by 1 Multiplexer: ......................................................................................................... 25
3.6 SRAM16bit: ................................................................................................................... 27
3.7 SRAM64bit .................................................................................................................... 27
3.8 SRAM 256bit ................................................................................................................. 28
Chapter4 ................................................................................................................................... 32
Schematics, Layouts and Test Results ..................................................................................... 32

viii

4.1 Precharge Circuit: ........................................................................................................... 32
4.1.1 Precharge Circuit Schematic: .................................................................................. 32
4.1.2Precharge Circuit Layout: ......................................................................................... 33
4.2 Sense Amplifier .............................................................................................................. 34
4.2.1 Sense Amplifier Schematic: .................................................................................... 34
4.2.2 Sense Amplifier Layout: .......................................................................................... 34
4.3 Data Enable .................................................................................................................... 35
4.3.1 Data Enable Schematic: ........................................................................................... 35
4.3.2 Data Enable Layout: ................................................................................................ 35
4.4 6T SRAM cell ................................................................................................................ 36
4.4.1 Schematic................................................................................................................. 36
4.4.2 Layout ...................................................................................................................... 36
4.5SRAM 1bit ...................................................................................................................... 37
4.5.1 SRAM 1bit Schematic: ............................................................................................ 37
4.5.2 SRAM 1bit Layout .................................................................................................. 37
4.5.3 SRAM 1bit Waveforms ........................................................................................... 38
4.6 2 to 4 Decoder ............................................................................................................... 38
4.6.1 2 to 4 Decoder Schematic ....................................................................................... 38
4.6.2 2 to 4 Decoder layout............................................................................................. 39
4.6.3 2 to 4 Decoder Wave forms .................................................................................... 39
4.7 Multiplexer 4 by 1(4x1) ................................................................................................ 40
4.7.1 4x1 Multiplexer Schematic ...................................................................................... 40
4.7.2 4x1 Multiplexer Layout .......................................................................................... 40
4.7.3 4x1 Multiplexer Waveform ..................................................................................... 41
4.8 SRAM 4bit .................................................................................................................... 41
4.8.1 SRAM 4bit Schematic ............................................................................................. 41
4.8.2SRAM 4bit Waveforms ............................................................................................ 42
4.9 SRAM 16bit: .................................................................................................................. 43
4.9.1 SRAM 16bit Schematic: .......................................................................................... 43
4.9.2 SRAM 16bit waveform: .......................................................................................... 44
4.10SRAM 64bit .................................................................................................................. 45
4.10.1 SRAM 64bitSchematic: ......................................................................................... 45
4.10.2 SRAM 64bit Waveform: ....................................................................................... 45

ix

4.11SRAM 256bit ................................................................................................................ 46
4.11.1 SRAM 256bitSchematic: ....................................................................................... 46
4.11.2 SRAM 256bitWave form: ..................................................................................... 47
4.12SRAM 1024bit .............................................................................................................. 48
4.12.1 SRAM 1024bitSchematic: ..................................................................................... 48
4.12.2 SRAM 1024bitWave form: ................................................................................... 48
Chapter 5 .................................................................................................................................. 50
Conclusion ............................................................................................................................... 50
REFERENCES ........................................................................................................................ 51












1

Chapter1
INTRODUCTION
1.1 Aim of the project:
Starting from the design specification to the generation of mask layout, layout design
of an integrated circuit has several processing steps which have to be carefully exercised.
These steps include design of transistor level schematic, simulation of the circuit according to
the designed W/L ratios of the individual transistors, drawing of the layout using a layout
editor, design rule check by ASSURA, parasitic extraction and final simulation and
verification. These all processing methods are inevitable for the error free operation of chip
and similar methodology is followed for the design of 1 Kbit SRAM IC. Basic building block
of the SRAM is SRAM cell which stores one bit data. Using common bit lines data can be
read and written to the SRAM cell. CADENCE, being an industry standard tool for circuit
simulation and analysis, is used for the simulation and analysis of SRAM cell and
subsequently for the whole design. Precharge circuit; sense amplifier and read-write circuits
complete one SRAM memory. The memory is arranged in row- column matrix which
facilitates easy addressing of memory bits and also provides design flexibility. Once the
functionality of one memory cell array is proved it can be duplicated several times with
minor design changes in the I/O control circuitry.

10 Address lines
A0
A9 Read out

Data in
Write enable Read out
Sense (read)




SRAM -1024bit

2

1024 memory locations are there for above SRAM, these memory locations are accessed by
using 10 address lines. Each memory cell can be accessed at a time, at that particular time
only one operation can be done (either read or write operation).
1.2 Methodology:
The size of a SRAM with address lines and data lines

words or

.
Here each word size is , but we designed as single bit sized word so we for 1024-bit size
written as fallows.

10 address lines with word size of single bit.
It is too difficult to construct 1024-bit memory directly, by keeping all 1024 cells and their
decoder, other circuitry with their connections. It becomes complex and lengthy, in accurate
and also time consuming.
So in order to eliminate above discomforts, we constructed small modules
constructed, and these modules are used in next higher module, these module is used further
module.
Firstly precharge, sense amplifier, 6T SRAM cell, data enable, 2 to 4 decoder, 4 by 1
multiplexer are designed.
After constructing above basic modules, SRAM 1bit is constructed and after that
Four single SRAM -1bits used for constructing SRAM 4bit.
Four single SRAM-4bits used for constructing SRAM-16bit.
Four single SRAM-16bits used for constructing SRAM-64bit.
Four single SRAM-64bits used for constructing SRAM-256bit.
Four single SRAM-256bits used for constructing SRAM-1024bit.

The design flow of the project will be understood by the following chart



3






Nv No
Yes


No No

Yes


No


Yes



Design Specifications
Schematic Design of 1K bit
SRAM
Layout Design of 1K bit SRAM
Simulation
&
verification
Simulation
&
verification
Layout vs Schematic
GDS (Graphical Data Stream)
file
Matched?

4

1.3 Significance of this Work:

Now a days power consumption and size of the device are the main constraints. To
get rid of these constraints VLSI is the right platform, because the compactness of the
electronic design systems is due to large scale integration. Full-custom design involves back-
end and front-end processes. Our project deals with back-end process. These design systems
can be done in the cadence environment which gives a set of tools for designing, debugging
and for simulation. So this will be useful in future for designing more compact and low
power consumed electronic goods.
1.4 Designing Environment:

Red hat enterprise Linux version 5.1.19.6(Operating system)
Virtuoso version 6.1.4(Cadence tool)
Generic pdk180nm version 3.2 (Technology)











5

Chapter 2
CLASSIFICATION OF SRAM
2.1 INTRODUCTION
Static random access memory (SRAM) is a type of volatile semiconductor memory
to store binary logic '1' and '0' bits. SRAM uses bistable latching circuitry made of
Transistors/MOSFETS to store each bit. Compared to Dynamic RAM (DRAM), SRAM
doesnt have a capacitor to store the data, hence SRAM works without refreshing. In SRAM
the data is lost when the memory is not electrically powered. SRAM is faster and more
reliable than the more common DRAM. While DRAM supports access times (access time is
the time required to read or write data to/from memory) of about 60 nanoseconds, SRAM
can give access times as low as 10 nanoseconds. In addition, its cycle time is much shorter
than that of DRAM because it does not need to pause between accesses. Unfortunately, it is
also much more expensive to produce than DRAM. Due to its high cost, SRAM is often
used only as a memory cache. The Microprocessor memory configuration is shown in
Fig.2.1

Figure 2.1 Typical Microprocessor Memory Configuration
SRAM is generally used for high-speed registers, caches and relatively small memory
banks such as a frame buffer on a display adapter. In contrast, the main memory in a
computer is typically dynamic RAM (DRAM, D-RAM). An SRAM is designed to fill two
needs: to provide a direct interface with the CPU at speeds not attainable by DRAMs and to
replace DRAMs in systems that require very low power consumption. In the first role, the
SRAM serves as cache memory, interfacing between DRAMs and the CPU. The second

6

driving force for SRAM technology is low power applications. In this case, Rams are used
in most portable equipment because the DRAM refresh current is several orders of
magnitude more than the low-power SRAM standby current.
Many categories of industrial and scientific subsystems, automotive electronics, and
similar, contains static RAM. Several megabytes of SRAM may be used in complex
products such as digital cameras, cell phones, synthesizers etc. SRAM is also used in
personal computers, workstations, routers and peripheral equipment: internal CPU caches
and external burst mode SRAM caches, hard disk buffers, router buffers, etc. LCD screens
and printers also normally employ SRAM to hold the image displayed or to be printed.
Small SRAM buffers are also found in CDROM and CDRW drives to buffer track data,
which is transferred in blocks instead of as single values. The same applies to cable
modems and similar equipment connected to computers.
2.2 SRAM CELL
The SRAM cell consists of a bi-stable flip-flop connected to the internal circuitry by
two access transistors. When the cell is not addressed, the two access transistors are closed
and the data is kept to a stable state, latched within the flip-flop. The flip-flop needs the
power supply to keep the information. The data in an SRAM cell is volatile (i.e., the data is
lost when the power is removed). However, the data does not "leak away" like in a DRAM,
so the SRAM does not require a refresh cycle. Static RAM is fast because the six-transistor
configuration (shown in Fig 2.2) of its flip-flop circuits keeps current flowing in one
direction or the other (0 or 1). The 0 or 1 state can be written and read instantly without
waiting for a capacitor to fill up or drain (like in DRAM). However, the six transistors take
more space than DRAM cells made of one transistor and one capacitor. When opposite
voltages are applied to the column wires, the flip-flop is oriented in one of two directions
for a 0 or 1. At that point, the flip-flop becomes a self-perpetuating storage cell as long as a
constant voltage is applied. Random access means that locations in the memory can be
written to or read from read and write operations sequentially. Newer synchronous static
RAM chips overlap reads and writes. Contrast with dynamic RAM.

7


Figure 2.2 SRAM Cell
2.2.1 CMOS SRAM-Read Operation
Assume that 1 is stored at Q. We further assume that both bit lines are precharged to
2.5 V before the read operation is initiated. The read cycle is started by asserting the word
line, enabling both pass transistors M5 and M6 after the initial word-lone delay. During a
correct read operation, the values stored in Q and Q bar are transferred to the bit lines by
leaving BL at its precharged value and by discharging BL through M1-M5. A careful
sizing of the transistors is necessary to avoid accidentally writing a 1 into the cell. This type
of function is frequently called a read upset. This is illustrated in Figure 2.2. Consider the
BL side of the cell. The bit line capacitance for larger memories is in the pF range.
Consequently, the value of BL stays at the precharged value Vdd upon enabling of the read
operation (WL1).This series Combination of two NMOS transistors pulls down the BL
towards ground. For a small-sized cell, we would like to have these transistor sized as close
to minimum as possible, which would result in a very slow discharge of the large bit line
capacitance. As the difference between BL and BL builds up, the sense amplifier is
activated to accelerate the reading process.

8



Figure 2.3 Simplified model of CMOS SRAM cell during read (Q=1, V precharge=Vdd).
Initially, upon the rise of the WL, the intermediate node between these two NMOS
transistors, Q is pulled up toward the precharged value of BL. This voltage rise of Q must
stay low enough not to cause a substantial current through the M3-M4 inverter, which in the
worst case could flip the cell. It is necessary to keep the resistance of transistor M5 larger
than that of M1 to prevent this from happening.
The boundary constraints on the device sizes can be derived by solving the current
equation at the maximum allowed value of the voltage ripple V. We ignore the body effect
on transistor M5 for simplicity and write
k
n,M5
(( V
DD
V V
Tn
)V
DSATn
V
2
DSATn
/2)=k
n,M5
(( V
DD
V
Tn
) V V
2
/2)
----- (1)
This simplifies to

BL
M6
M4
Q=1
M5
M1 VDD
VDD
Q=0
WL
VDD

BL

Cb Cbit

9


------- (2)
Where CR is called the cell ratio and is defined as

------ (3)
The value of voltage rise V as a function of CR is plotted in Fig 3.4. To keep the
node voltage from rising above the transistor threshold (of about 0.4V), the cell ratio must be
greater than 1.2.For large memory arrays; it is desirable to keep the cell size minimal while
maintaining read stability. If the transistor M1 is minimum sized, the access pass transistor
M5 has to be made weaker by increasing its length. This is undesirable, because it adds to the
load of the bit line. A preferred solution is to minimize the size of the pass transistor, and
increase the width of the NMOS pull-down M5 to meet the stability constraint. Beyond
adjusting the size of the cell transistors, the erroneous toggling can be prevented by pre
charging the bit lines to another value, such as Vdd/2. This effectively makes it impossible
for Q to reach switching threshold of the connecting inverter. Pre charging to the midpoint of
the voltage range has some performance benefits as well, since it limits the voltage swing on
the bit lines.

10



Figure 2.4 Voltage rise inside the cell upon read versus cell ratio (ratio of M1/M5)
2.2.2 CMOS SRAM Write Operation
In this example, we derive the device constraints necessary to ensure a correct write
operation. Assume that a 1 is stored in the cell (or Q = 1). A 0 is written in the cell by setting
BL to 1 and BL to 0, which is identical to applying a reset pulse to an SR latch. This causes
the flip-flip to change state if the devices are sized properly. During the initiation of a write,
the schematic of the SRAM cell can be simplified to the model of Figure 3.4. It is reasonable
to assume that the gates of transistors M1 and M4 stay at Vdd and GND, respectively, as long
as the switching has not commenced. While this Condition is violated once the flip-flop starts
toggling.
Note that Q side of the cell cannot be pulled high enough to ensure the writing of 1.
The sizing constraint, imposed by the read stability, ensures that this voltage is kept below
0.4 Therefore; the new value of the cell has to be written through transistor M6. A reliable
writing of the cell is ensured if we can pull node Q low enough this is, below the threshold
value of the transistor M1. The conditions for this to occur can be derived by writing out the
dc current equations at the desired threshold point, as follows:

0

0.2
0.4
0.6
0.8
1
1.2
0.5 1 1.2 1.5 2
Cell ratio (CR)
2.5 3





Rise
Voltag
e

11

k
n,M6
(( V
DD
V
Tn
)V
Q
V
2
Q
/2)=k
n,M4
(( V
DD
|V
Tp
| ) V
DSATp
V
2
DSATn
/2)
------ (4)

Figure
2.5 Simplified model of CMOS SRAM cell during write (Q=1)

Solving for Vq leads to
( )
|
|
.
|

\
|
=
2
2 ) (
2
2 DSATp
DD
p
Tn DD
V
V V V PR
n
V V V V V DSATp Tn Tn DD Q

------- (5)
Where the pull up ratio of the cell, PR is defined as the size ratio between the PMOS pull up
and the NMOS pass transistor:
6
6
4
4
L
W
L
W
PR = ----- (6)
The dependence of Vq on PR for is plotted in Figure. The lower PR, the lower the value of
M6
M4
Q=1
M1
VDD
Q=0
VDD
M5
BL=0
BL=1

WL

12

Vq. If we wish to pull the node below Vth, the pull up ratio has to be below 1.8.
This constraint is met, by a large margin, when using minimum-sized devices for both
the PMOS pull-up M4 and NMOS access transistor M6. Our initial assumption was that the
transistors M1 and M2 do not participate in the writing process. This is not completely true in
practice. As soon as one side of the cell starts switching, the other side eventually follows,
engaging the positive feedback.

Figure 2.6 Voltage written into the cell versus pull-up ratio (size ratio between the PMOS
pull-up and access transistor)
2.3 OTHER TYPES OF SRAM CELLS
The SRAM cells are categorized based on the type of load used in the elementary
inverter of the flip-flop cell. There are commonly three types of SRAM memory cells:
1. 4Tcell(four NMOS transistors plus two poly load resistors)
2. 6Tcell (six transistors-four NMOS transistors plus two PMOS transistors)
3. TFT cell (four NMOS transistors plus two loads called TFTs)
2.3.1 4T (Four Transistor) Cell
This design consists of four NMOS transistors plus two poly-load resistors. Two
NMOS transistors are pass-transistors. These transistors have their gates tied to the word
line and connect the cell to the columns. The two other NMOS transistors are the pull-
downs of the flip-flop inverters. The loads of the inverters consist of a very high poly-
silicon resistor. The cell needs room only for the four NMOS transistors. The poly loads are

13

stacked above these transistors. Although the 4T SRAM cell may be smaller than the 6T
cell, it is still about four times as large as the cell of a DRAM cell.

Figure 2.7 4Transistor SRAM cell
The complexity of the 4T cell is to make a resistor load high enough (in the range of
giga-ohms) to minimize the current. However, this resistor must not be too high to
guarantee good functionality. Despite its size advantage, the 4T cells have several
limitations.
1. Each cell has current flowing in one resistor. (i.e., the SRAM has a high standby current)
2. The cell is sensitive to noise and soft error because the resistance is so high.
3. The cell is not as fast as the 6T cell.
2.3.2 6T (Six Transistor) Cell
A different cell design that eliminates the above limitations is the use of a CMOS
flip-flop. In this case, the load is replaced by a PMOS transistor. This SRAM cell is
composed of six transistors, one NMOS transistor and one PMOS transistor for each
inverter, plus two NMOS transistors connected to the row line (as shown in fig 2.8) This
configuration is called a 6T Cell. This cell offers better electrical performances (speed,
noise immunity, standby current) than a 4T structure.

14


Figure 2.8 6Transistor SRAM cell
2.3.3 TFT (Thin Film Transistor) Cell
This new structure reduces the current flow through the resistor load of the old 4T
cell. This change in electrical characteristics of the resistor load is done by controlling the
channel of a transistor. This resistor is configured as a PMOS transistor and is called a thin
film transistor (TFT). It is formed by depositing several layers of poly silicon above the
silicon surface. The source/channel/ drain is formed in the poly silicon load. The gate of this
TFT is poly silicon and is tied to the gate of the opposite inverter as in the 6T cell
architecture. The oxide between this control gate and the TFT poly silicon channel must be
thin enough to ensure the effectiveness of the transistor. The performance of the TFT
PMOS transistor is not as good as a standard PMOS silicon transistor used in a 6T cell.

Figure 2.9 Thin Film Transistor SRAM cell

15

This type of cell possesses complex technology compared to the 4T cell technology and
poor TFT electrical characteristics compared to a PMOS transistor. In addition to such
SRAM types, other kinds of SRAM chips use 8T, 10T, or more transistors per bit. This is
sometimes used to implement more than one (read and/or write) port, which may be useful
in certain types of video memory and register files implemented with multi ported SRAM
circuitry. Memory cells that use fewer than 6 transistors such as 3T or 1T cells are
DRAM, not SRAM.
2.4 CLASSIFICATION OF SRAM
By Transistor
1. Bipolar junction transistor (used in TTL and ECL): very fast but consumes a lot of
power
2. MOSFET (used in CMOS): low power and very common today
By Function
1. Asynchronous: independent of clock frequency; data in and data out are controlled by
address transition.
2. Synchronous: As computer system clocks increased, the demand for very fast SRAMs
necessitated variations on the standard asynchronous fast SRAM. The result was the
Synchronous SRAM (SSRAM). Synchronous SRAMs have their read or write cycles
synchronized with the microprocessor clock and therefore can be used in very high-speed
applications. An important application for synchronous SRAMs is cache SRAM used in
PCs. SSRAMs typically have a 32 bit output configuration while standard ASRAMs have
typically a 8 bit output configuration. All timings are initiated by the clock edge(s).
Address, data in and other control signals are associated with the clock signals.
By Feature
1. ZBT (zero bus turnaround): the turnaround is the number of clock cycles it takes to change
access to the SRAM from write to read and vice versa. The turnaround for ZBT SRAMs or
the latency between read and writes cycle is zero. In short the ZBT is designed to eliminate
dead cycles when turning the bus around between read and writes and reads.

16

2. Sync-Burst (synchronous-burst SRAM): features synchronous burst write access to the
SRAM to increase write operation to the SRAM.
3. DDR SRAM: Synchronous, single read/write port, double data rate IO. It increases the
performance of the device by transferring data on both edges of the clock.
4. Quad Data Rate SRAM: Synchronous, separate read & write ports, double data rate IO
5. Pipelined SRAM: They (also called register to register mode SRAM) add a register
between the memory array and the output. Pipelined SRAMs are less expensive than standard
ASRAMs for equivalent electrical performance. The pipelined design does not require the
aggressive manufacturing process of a standard ASRAM.
6. Late-Write SRAM: Late-write SRAM requires the input data only at the end of the cycle















17

Chapter3
Design of CMOS-1024 bit SRAM

In this chapter CMOS SRAM-1024 bit design is explained clearly, starting from basic
building modules like 6T-SRAM cell, precharge circuit, sense amplifier, data enable circuit
and other modules for constructing SRAM-1024 bit are SRAM-1bit, SRAM-4bit, SRAM-
16bit, SRAM-64bit, SRAM-256bit also designed respectively.



3.1Architecture of SRAM 1bit:




Data in
Word enable
Write enable


Sense
Read out read out bar
Fig 3.1 Architecture of SRAM 1bit

Precharge circuit

6TSRAM cell
Sense Amplifier

Enable Circuit

Enable Circuit


18

The architecture of SRAM 1bit is shown in figure 3.1
Write enable=1, for write operation
At a time only one operation can be done (either read or write operation)
Word enable should always high for Read or Write operations, if it is low indicates stand by
(store).
3.1.1Precharge:
The function of precharge circuit is to charge the bit line and bit-bar line to 5V. Precharge
enables the bit line to be charged high at all times except during read and write operation. The
following figure 3.2 shows the schematic for precharge circuit. The PMOS transistors are
used to build precharge circuit.


Bit line .Bit bar line
Fig 3.2 precharge circuit
PM0, PM1 are PMOS transistors, hence when their gates are grounded they are in ON state.
So the bit and bit_bar line goes to Vdd level.
3.1.2Data Enable circuit:
Write operation into the memory cell can be done only when the write enable ON. This
enable operation can be easily understood by the following circuit.

19

to bit or bit bar line
Fig 3.3 data enable circuit
When write enable goes to high, and thenPM6&NM3 gets ON, which makes a way into bit
or bit bar line for data.
Hence when write enable = 1; write operation.
3.1.3 Sense amplifier:
A Sense amplifier circuit is used to read the data from the cell. in addition, it helps reduce the
delay times and minimizes the power consumption in overall SRAM chip by sensing small
difference in voltage on the bit lines. The schematic of sense amplifier is shown in below
figure 3.4. A low-voltage sense amplifier was used in SRAM design to support high
performance.

20


Fig 3.4 sense amplifier circuit
Sense=0, for read operation, hence sense is read bar (READ) signal.
Sense=0 makes PM2 and PM3 as in ON position and also PM4, PM5, NM6, NM7, NM8
(acts like differential amplifier) transistors to calculate the difference of bit and bit bar lines.
As this voltage difference is low, it amplifies that small voltage.
3.1.4SRAM 1bit design diagram:
SRAM 1bit can be implemented by using simple 6T-SRAM cell, precharge circuit, sense
amplifier, data enable circuit.

21



Fig 3.5 SRAM 1bit
Design flow of SRAM 1024 bit:
The design of 1024 bit, with module wise will be explained the following flow chart




22
























By using above modules (pecharge, sense amplifier, data enable, 6T-SRAM
cell) SRAM 1-bit construction.
Design of2 to 4 decoder and multiplexer 4 by 1(Data selector).
SRAM-4bit design (
2
; two address lines, one data line). Four
single bit memory cells accessed by 2 to 4 decoder and output of each
memory cell output is multiplexed by mux4 by 1.
SRAM-16bit design (6
4

2

2
; four address lines, one
data line). Four 4 bit memory modules accessed by 2 to 4 decoder and output
of each memory module output is multiplexed by mux4 by 1.
SRAM-64bit design (6
6

2

2

2
; six address lines,
one data line). Four 16 bit memory modules accessed by 2 to 4 decoder and
output of each memory module output is multiplexed by mux4 by 1.
SRAM-256bit design (56
8

2

2

2

2
; eight
address lines, one data line). Four 64 bit memory modules accessed by 2 to 4
decoder and output of each memory module output is multiplexed by mux4
by 1.
SRAM-1024bit design (

2

2

2

2

2
; ten
address lines, one data line). Four 256 bit memory modules accessed by 2 to
4 decoder and output of each memory module output is multiplexed by mux4
by 1.
Designs of 6T-SRAM cell, precharge circuit, sense amplifier, Data enable
circuit.

23

3.3 SRAM 4bit:

2 Address lines
A0
A1 Read out

Data in
Write enable Read out
Sense (read)


4 bits can be addressed by using 2 address lines (A0, A1) by using 2 to 4 decoder, so we have
to design 2 to 4 decoder first.

2
(Here 2 address lines and 1 data line)
According to A1, A0 values decoder selects one memory cell out of four each time.

A1 A0 Memory cell accessed
0 0 1
st

0 1 2
nd

1 0 3
rd

1 1 4
th








SRAM 4bit

24



Data in
Write enable
Sense (read)













Fig 3.6 Architecture of SRAM 4bit
3.4 2 to 4 Decoder:

SRAM 1bit

SRAM 1bit


SRAM 1bit


SRAM 1bit

MUX 4 by 1


MUX 4 by 1

2 to 4
DECODER

25


Fig 3.7.2 to 4 Decoder

Decoder is a combinational circuit that converts binary information from n input lines to a
maximum of

unique output lines. In digital electronics, a decoder can take the form of a
multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs,
where the input and output codes are different.

Decoder consists of

outputs and inputs also AND, not gates.

2 to 4 decoder consists of
2
outputs, 2 inputs & 4 AND, 2 not gates.

3.5 4 by 1 Multiplexer:
A multiplexer (MUX) is device that selects one of several inputs by using selection lines. A
multiplexer of

inputs has selection lines, which are used to select which input line to
send to the output.
A multiplexer is also called as DATA SELECTOR, as it selects one data line out of several
inputs.

26


Fig 3.8. 4 by 1 multiplexer
We can access (either read or write) one memory cell at a particular time (because we
designed serial data memory), so we have to use data selector (multiplexer) .the data
multiplexer selection lines are connected to selection lines of decoder.
So we can write the data into selected memory location by using decoder and selected
location can be read by using multiplexer.
4x1 multiplexer operation takes place as follows:
Selection lines (for Decoder as well as
Multiplexer )
Output selected from
A1 A0
0 0
From 1
st
Memory Module
0 1
From 2
nd
Memory Module
1 0
From 3
rd
Memory Module
1 1
From 4
th
Memory Module





27


3.6 SRAM16bit:

4 Address lines
A0
A3 Read out

Data in
Write enable Read out
Sense (read)


16bits can be addressed by using 4 address lines (A0, A1, A2, A3) by using 2to 4 decoder.
For designing 16bit SRAM we use 4 previously designed 4bit SRAMs. At the output section
we use two 4x1 Multiplexers for read and read_bar operation. The selection lines were taken
from the inputs of the Decoder.
16=2
4
1 (Here 4 address lines and 1 data line).
For example to access 9
Th
Memory cell the Decoder will select the address as follows
A3A2A1A0=1001
A1A0 from the address lines of each 4bit (consists 2 address lines) module.
A3A2- from the two decoder inputs.
3.7 SRAM64bit:
6
6
Hence 6 address lines (A0, A1, A2, A3, A4 and A5) one data line.



SRAM 16bit


28

Four SRAM-16 bits are used for designing SRAM-64bit.
A0, A1 (decoder inputs) are used for selecting one out of four SRAM-16bit modules.
A2-A5 (SRAM-16bit 4 address lines) used for selecting 16 bits in SRAM-16bit module.

6 Address lines
A0
A5 Read out

Data in
Write enable Read out
Sense (read)


3.8 SRAM 256bit:
256
8
Hence 8 address lines (A0, A1, A2, A3, A4, A5, A6 and A7) one data line.
Four SRAM-64 bits are used for designing SRAM-256bit.
A0, A1 (decoder inputs) are used for selecting one out of four SRAM-64bit modules.
A2-A7 (SRAM-64bit 6 address lines) used for selecting 64 bits in SRAM-64bit module.







SRAM 64bit



29



8 Address lines
A0
A7 Read out

Data in
Write enable Read out
Sense (read)


3.9 SRAM 1024bit:
1024

Hence 8 address lines (A0, A1, A2, A3, A4, A5, A6, A7, A8 and A9) one
data line.
Four SRAM-256 bits are used for designing SRAM-1024bit.
A0, A1 (decoder inputs) are used for selecting one out of four SRAM-256bit modules.
A2-A9 (SRAM-256bit 8 address lines) used for selecting 256 bits in SRAM-256bit module










SRAM -256bit

30


8 address lines (A2-A9)
Data in
Write enable
Sense (read)


(A0, A1)










Fig 3.9 SRAM 1024bit Architecture




SRAM 256bit

SRAM 256bit


SRAM 256bit


SRAM 256bit

MUX 4 by 1


MUX 4 by 1

2 to 4
DECODER

31







10 Address lines
A0
A9 Read out

Data in
Write enable Read out
Sense (read)









SRAM -1024bit

32

Chapter4
Schematics, Layouts and Test Results

4.1 Precharge Circuit:
4.1.1 Precharge Circuit Schematic:







33

4.1.2Precharge Circuit Layout:




34

4.2 Sense Amplifier
4.2.1 Sense Amplifier Schematic:

4.2.2 Sense Amplifier Layout:


35

4.3 Data Enable
4.3.1 Data Enable Schematic:

4.3.2 Data Enable Layout:


36

4.4 6T SRAM cell
4.4.1 Schematic

4.4.2 Layout



37


4.5SRAM 1bit
4.5.1 SRAM 1bit Schematic:


4.5.2 SRAM 1bit Layout:


38

4.5.3 SRAM 1bit Waveforms:

4.6 2 to 4 Decoder
4.6.1 2 to 4 Decoder Schematic:




39

4.6.2 2 to 4 Decoder layout:



4.6.3 2 to 4 Decoder Wave forms:



40

4.7 Multiplexer 4 by 1(4x1)
4.7.1 4x1 Multiplexer Schematic:

4.7.2 4x1 Multiplexer Layout:


41

4.7.3 4x1 Multiplexer Waveform:

4.8 SRAM 4bit
4.8.1 SRAM 4bit Schematic:


42

4.8.2SRAM 4bit Waveforms:



43

4.9 SRAM 16bit:
4.9.1 SRAM 16bit Schematic:


44

4.9.2 SRAM 16bit waveform:



45

4.10SRAM 64bit
4.10.1 SRAM 64bitSchematic:

4.10.2 SRAM 64bit Waveform:


46


4.11SRAM 256bit
4.11.1 SRAM 256bitSchematic:


47

4.11.2 SRAM 256bitWave form:




48

4.12SRAM 1024bit
4.12.1 SRAM 1024bitSchematic:

4.12.2 SRAM 1024bitWave form:




49






50

Chapter 5
Conclusion


The design of 1024 bit SRAM bit has been done in this project, and corresponding results
(read, write operations) were noted.
In this design process different small modules were done, and these modules were used in
next higher modules for reducing the complexity of the designing process.
For all of these modules schematic design, symbol creation, test schematics with proper
results were done.
Basic building blocks of SRAM 1bit (precharge, sense amplifier, data enable circuit, 6T-
SRAM cell) were designed and for SRAM 1bit, SRAM 4bit, 16bit, 64bit, 256bit read, write
operations were observed.


51

REFERENCES

[1] Jan M Rabaey & Anantha Chandrakasan & Borivoje Nikolic, Digital integrated circuits-a
design perspective, Pearson education, third edition, 2005.
[2] Sedra & smith, Microelectronic circuits, oxford university press, fifth edition, 2004.
[3] Sung Mo Kang and Yusuf Leblebici, CMOS digital integrated circuits-analysis and
design, Tata McGraw hill, third edition, 2003.
[4] Behzad Razavi, Design of Analog CMOS Integrated Circuits, TATAMCGRAW-Hill
Edition.
[5] Tadayoshi Enomoto and Yuki Higuchi, A Low-leakage Current Power 180-nm CMOS
SRAM IEEE 2008,101-102.