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1.

1ADS1251/52ADC

INTERFACINGTHEADS1251/52TOTHEMSP430F449


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4th-Order
DS
Modulator
Digital
Filter
Serial
Interface
Control
V
REF
CLK
SCLK
DOUT/DRDY
+V
DD
GND
+V
IN
V
IN
1.2SIGMA-DELTAMODULATOR
+

A
B C
D
E
Latched
Comparator
Integrator
1-BIT
DAC


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1 1 1 0 0 0
1 1 1 0 0 0 1 0
Integrator Output
Comparator Output
Integrator Output
Comparator Output
V
D
= 0 V
V
D
= V
REF
2
1.3DIGITALFILTER


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400
300
200
100
0
0 0.05 0.1
G
a
i
n


d
B
f
i
Input Frequency kHz
1.4HPA449DEVELOPMENTSYSTEM


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Oscillator ACLK
SMCLK
CPU
Incl. 16 Reg.
Bus
Conv
MCB
XIN XOUT P3 P4 P2
XT2IN
XT2OUT
TMS
TCK
MDB, 16 Bit
MAB, 16 Bit
MCLK
4
TDI/TCLK
TDO/TDI
P5 P6
MAB,
4 Bit
DV
CC1/2 DV
SS1/2
AV
CC
AV
SS
RST/NMI P1
Hardware
Multiplier
MPY, MPYS
MAC,MACS
60KB
Flash
48KB
Flash
32KB
Flash
2KB RAM
2KB RAM
1KB RAM
ADC12
12-Bit
8 Channels
<10s
Conv.
Watchdog
Timer
15/16-Bit
Timer_B7
7 CC Reg
Shadow
Reg
Timer_A3
3 CC Reg
Test
JTAG
E
m
u
l
a
t
i
o
n
M
o
d
u
l
e
I/O Port
1/2
16 I/Os,
with
Interrupt
Capability
I/O Port 3/4
16 I/Os
POR
SVS
Brownout
Comparator
A
Basic
Timer 1
1 Interrupt
Vector
USART0
USART1
UART
Mode
SPI Mode
I/O Port 5/6
16 I/Os
MDB, 16-Bit
MAB, 16-Bit
LCD
160
Segments
1,2,3,4 MUX
f
LCD
FLL+
8 8 8 8 8 8
MDB, 8 Bit


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Receive Buffer UxRXBUF Transmit Buffer UxTXBUF


Receive Shift Register Transmit Shift Register
MSB MSB LSB LSB
SOMI
MASTER
SPI Receive Buffer
Data Shift Register (DSR)
MSB LSB
SOMI
UCLK SCLK
MSP430 USART COMMON SPI
SLAVE
MSP430F449 ADS1251/52
3.1ADS1251/52OPERATINGPROCEDURE
DATA
DRDY Mode DOUT Mode DOUT Mode
DATA DATA
t
4
t
2
t
3
t
1
DRDY Mode
DOUT/DRDY


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Divider
/1/2/4/B
FLL_DIVx
ACLK
ACLK
f
crystal
LF XT
LFOff
XT1Off
0 V
0 V
XIN
XOUT
OSCOFF XTS_FLL
ENABLE Reset
10-Bit
Frequency
Integrator
+

XOSCxPF
LFXT1 Oscillator
/(N+1)
SCG0 PUC
10
DCO
+
Modulator
DC
Generator
M
4
FNx SCG1
Off
Divider
/1/2/4/B
FLL_Dx
f
DCO
1
0
00
01
10
11
0
1
DCCPLUS
SELS
0
1
0
1
MCLK
SMCLKOFF
SMCLK
XT20FF
XT2IN
XT2OUT
XT2Oscllator

3.1.1.1INITIALIZINGTHECLOCKSOURCE


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3.1.1.2INITIALIZINGTHEMSP430PORTS

3.1.1.3INITIALIZINGTHEMSPINTERRUPTS

3.1.1.4USINGTIMERA


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00
01
10
11
0
1
Set TACCR2
CCIFG
Divider
/1/2/4/B
TACLK
ACLK
AMCLK
INCLK
TASSELx
IDx
Timer Clock
Clear
15 0
RC
16-Bit Timer
TAR
Count
Mode
MCx
EQU0
Set TAIFG
TACLR
Timer Block
CCR0
CCR1
CCR2
00
01
10
11
Divider
/1/2/4/B
CC12A
CC12B
GND
VCC
CCISx
CMx
Logic
0
1 Sync
CCR2
Comparator 2
15 0
CAP
SCS
COV
Time Clock
A
EN
Y SCCI
Output
Unit2
EQU0
OUT
D Q
Reset
Time Clock
POR
OUT2 Signal
OUTMODx

3.1.1.5RESETTINGTHEADCMODULATOR


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SCLK
DOUT/DRDY
For This Amount of Time The Host
System Must Maintain SCLK HIGH.
Note: D is 47.4 ms


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RXERR
USPIEx* TXEPT STC SWRST
*Refer to the device-specific data sheet for locations
Receive Control
Receiver Buffer UxRXBUF
Receiver Shift Register
Baud-Rate Generator
Prescaler/Divider UxBRx
Modulator UxMCTL
Transmit Shift Register
Transmit Buffer UxTXBUF
Transmit Control
Receiver Status
SWRST USPIEx* URXEIE URXWIE
URXIFGx*
UCLKS
CHAR PEV PENA SP
FE PE OE BRK
00
01
10
11
UCLKI
ACLK
SMCLK
SMCLK
SSEL1 SSEL0
SWRST USPIEx* URXEIE URXWIE
WUT
TXWAKE
UTXIFG*
Clock Phase and Polarity
UCLKI
SYNC CKPH CKPL
SOMI
URXD
STE
UTXD
SIMO
UCLK
0
1
0
1
0
1
0
1
0
1
0
1
LSTEN MM SYNC
SYNC = 1
RXWAKE

3.1.1.6INITIALIZINGTHEUSART


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3.2RETRIEVINGDATA


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The interrupt to
the MSP430
occurs here.
This is DRDY time 36 MCLKs
The completion of the
DRDY phase is here,
36 MCLKs later
Begin clocking
data into the
MSP430 here.
MCLK
SCLK
DOUT/
DRDY
SCLK
DOUT/DRDY


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Digital output code(Hex)
7FFFFF
800000
FFFFFF
000000
Analog Input
V
D
= ( +V
IN
) ( V
IN
)
Analog Input
V
D
= ( +V
IN
) ( V
IN
)
Analog Input
V
D
= ( +V
IN
) ( V
IN
)


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