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Load Compensating DSTATCOM in Weak AC Systems

Arindam Ghosh and Gerard Ledwich
AbstractThe paper discusses load compensation using a distribution static compensator (DSTATCOM). It is assumed that the DSTATCOM is associated with a load that is remote from the supply. It is shown that the operation of a DSTATCOM assuming that it is connected to a stiff source in such situations will result in distortions in source current and voltage at the point of common coupling. To avoid this, the DSTATCOM is connected in parallel with a filter capacitor that allows the high frequency component of the current to pass. This however generates control issues in tracking, as standard controls such as a hysteresis control are not suitable in these circumstances. This paper proposes a new switching control scheme and demonstrates its suitability for this problem. It also proposes a scheme in which the fundamental sequence components of a three-phase signal can be computed from its samples. The overall performance of the proposed scheme is verified using digital computer simulation studies. Index TermsDSTATCOM, load compensation, switching control, weak ac system.

I. INTRODUCTION OWER quality issues are rising in importance particularly for highly integrated plants that are sensitive to distortions or voltage dips. Almost all power quality problems originate in distribution networks. In most countries, there exist regulations which place limits on the distortion and unbalance that a customer can inject to a distribution system [1]. These regulations may require the installation of compensators (filters) on customer premises. This paper specifically examines the use of a power electronic shunt compensator to correct the current drawn from a utility to closely approximate balanced sinusoidal waveforms, without adversely affecting the voltage at the point of common coupling. A distribution static compensator (DSTATCOM) is a voltage source converter (VSC)-based power electronic device. Usually, this device is supported by short-term energy stored in a dc capacitor. The DSTATCOM filters load current such that it meets the specifications for utility connection. If properly utilized, this device can cancel the effect of poor load power factor such that the current drawn from the source has a near unity power factor; the effect of harmonic contents in loads such that current drawn from the source is sinusoidal;
Manuscript received March 24, 2000; revised August 31, 2001. A. Ghosh is with the School of Electrical and Electronic Systems Engineering, Queensland University of Technology, Brisbane 4001, Australia, on leave from the Indian Institute of Technology, Kanpur 208016, India. G. Ledwich is with the School of Electrical and Electronic Systems Engineering, Queensland University of Technology, Brisbane 4001, Australia (e-mail: g.ledwich@ qut.edu.au). Digital Object Identifier 10.1109/TPWRD.2003.817743

the effect of unbalanced loads such that the current drawn from the source is balanced; the dc offset in loads such that the current drawn from the source has no offset. In this paper, the discussion concerns the structure and control of a DSTATCOM that is capable of the first three cancellations even when the ac supply system is weak. In this, a weak (or nonstiff) supply implies that the load is connected at the end of a long radial feeder. One of the major considerations in applying a DSTATCOM is the generation of the reference compensator currents. The compensator, when it tracks these reference currents, injects three-phase currents in the ac system to cancel out disturbances caused by the load. Therefore, the generation of reference currents from the measurements of local variables has attracted wide attention [2][5]. These methods carry an implicit assumption that the source is stiff (i.e., the voltage at the point of common coupling is tightly regulated and cannot be influenced by the currents injected by the shunt device). This however is not a valid assumption and the performance of the compensator will degrade considerably with high impedance ac supplies. This paper assumes that a balanced source supplies an unbalanced load through a long feeder. The load power factor may be poor and it can also contain harmonics. The compensator is designed such that it not only cleans the distortion created by the load, but also improves the voltage quality at the point of common coupling (PCC). Specifically, a compensator-passive filter structure is proposed for this. The other aspect of the proposal is for a linear quadratic regulator (LQR)-based switching controller scheme that tracks reference using the proposed compensator-filter structure.

II. DSTATCOM PERFORMANCE EVALUATION The system under study is a three-phase, four-wire distribution system, the single line diagram of which is shown in Fig. 1. In this system, a nonlinear load is supplied by a balanced voltage through a feeder. The feeder has a resistance and source an inductance . The load is compensated by a DSTATCOM , a resistance , that contains a VSC, a dc capacitor . Three phase quantities are denoted by and an inductance subscripts a, b, and c. For example, the source voltages are de, , and , and the load currents by , , and noted by , and so on. Further, the voltage at the point of common coupling is defined as the terminal voltage . It can be seen that this voltage is equal to the load voltage.

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Fig. 1. Single-line diagram of shunt compensation of a load supplied through a feeder.

A. DSTATCOM Structure The DSTATCOM structure considered in this paper is shown in Fig. 2. It contains three H-bridge VSCs that are connected to a common dc storage capacitor [5]. In this figure, each switch represents a power semiconductor device combined with an antiparallel diode. Each VSC is connected to the network through a transformer. Six output terminals of the transformer are connected in star. The purpose of including the transformers is to provide isolation between the inverters. This prevents the dc storage capacitor from being shorted through switches in difin this figure represents the ferent inverters. The inductance leakage inductance of each transformer and additional external inductance, if any. The switching losses of an inverter and the copper loss of the connecting transformer are represented by a . The iron losses of the transformer are neglected. resistance For star connected load, the neutral point of the three transformers is connected to the load neutral. The problem of using an ordinary three-phase bridge inverter is that the sum of three currents must be equal to zero. The requirement of DSTATCOM is a topology that will be able to force three independent currents through its limbs. This prevents the use of the three leg bridge as a DSTATCOM power circuit. The topology shown in Fig. 2 allows three independent current injections as this contains three separate H-bridge inverters. It is to be noted that due to the presence of transformers, this topology is not suitable for canceling any dc component in the load current. One alternate topology for loads containing dc current is given in [6]. A four leg converter can also be used and the control techniques described here would be readily translated. B. DSTATCOM Performance In this paper, the reference current generation method proposed in [4], [5] is utilized. This method ensures that 1) The sum of the three source currents is zero (i.e., ). 2) The combined load and compensator system draws unity power factor current (i.e., the phase angle difference between the terminal voltage and source current is zero). 3) The source supplies only the real power required by the where is the load (i.e., average load power). Under this condition, the compensator supplies the zero-mean oscillating power required by the unbalanced nonlinear load. It is to be noted however that the source power factor may not be unity due to the presence of feeder impedance.
Fig. 2. Compensator structure used in which three separate VSCs are supplied from a common dc storage capacitor.

Let us denote the reference compensator currents by . These are then given by and

(1)

( when the terminal voltwhere . In the above ages are balanced) and is obtained by a moving average filter algorithm, the term that gives a continuous measurement of the average power by averaging it over the immediate previous half cycle. However, a direct application of this method will suffer from the problem of harmonic contamination of the point of common coupling due the inverter switching of DSTATCOM. Let us illustrate this with the following example. Example 1: Consider the system shown in Fig. 1 where the source voltage is balanced with a peak of 1.0 p.u. It supplies an unbalanced RL load given in per unit by

The feeder impedance in per unit is given by

For simplicity, it is assumed that the VSCs are lossless and connected to a fixed dc supply. The DSTATCOM parameters in per unit are given by

The compensator is connected at the end of first half cycle when the average power measurement becomes available. The control is based on hysteretic control of compensator current. When the current is below the reference by more than the hysteresis band, the voltage is switched high, when the current is correspondingly high, the converter voltage is switched low. The results of the Matlab simulation are shown in Fig. 3. The load currents are shown in Fig. 3(a), while Fig. 3(b) depicts the source currents. It can be seen that the source currents become distorted as soon as the compensator is pressed into action.

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Fig. 3. Single-line diagram of shunt compensation in the presence of a filter capacitor.

Fig. 4. Tolerable compensation but undesirable terminal voltage of a system with a nonstiff source.

Fig. 3(c) depicts the phase-a voltage of the point of common coupling. This voltage increases in magnitude and also gets distorted as soon as the compensator is connected. As a result, the magnitude of the load currents increases with it. This is evident from Fig. 3(a). The phase-a of the injected shunt current is shown in Fig. 3(d). The reason for the distortion in the source current is simple. The injected current contains high frequency harmonics. These harmonic currents, when injected into the feeder, corrupt the terminal voltage. Now since the terminal voltage is not sinusoidal, the reference current generation scheme based on this voltage will not function properly. As a result of this, the injected compensator currents will be erroneous thereby injecting more harmonics in the feeder. Furthermore, a hysteresis band of 0.01 p.u. has been chosen and this has resulted in a switching frequency of around 15.4 kHz, which is excessively high. The above example clearly demonstrates that the algorithm given in (1) cannot be utilized in a direct manner due to the presence of the VSC distortion of the terminal voltage. Therefore, the fundamental component of this voltage must be extracted online. An algorithm for extracting the fundamental frequency sequence components from the measurements of voltage signal is given in Appendix A. This algorithm assumes that voltage signals are sampled at discrete intervals of time. These samples are then transformed into instantaneous symmetrical component vectors, the discrete Fourier transform of which produces the symmetrical components. It is to be noted that for online application, an average over half a cycle replaces the integral associated with the determination of Fourier coefficients. This Fourier average is taken to be the moving average such that any change in the voltage can be fully reflected on the extracted voltage, exactly half a cycle after the change. Example 2: Let us consider the same system as given in example 1. The algorithm given in Appendix A is used to extract the fundamental positive sequence voltage. Since the source voltages are assumed to be balanced, the other two sequences theoretically remain zero. Once the magnitude and phase of the positive sequence voltage are obtained, the instantaneous terminal voltages are synthesized with respect to the phase of the voltage waveform as measured over the previous half cycle. The results with this added computation are shown in Fig. 4. The load currents are unbalanced as seen in Fig. 4(a). The source currents are shown in Fig. 4(b). It can be seen that they are balanced

and relatively free of low-frequency harmonics. The phase a voltage at the terminals is seen in Fig. 4(c) and the current injected by the compensator is shown in Fig. 4(d). It is evident that even though the source currents are almost free of harmonics, the terminal voltage still contains a very large amount of harmonics. This, of course, will cause distortion in any other load that may be connected in the terminal bus. The hysteresis band in this case is also chosen as 0.01 p.u. However, since the computation now is based on fundamental extraction, the switching frequency is below 4.5 kHz. III. DSTATCOM FOR NONSTIFF SOURCES A. DSTATCOM Structure to Eliminate Terminal Voltage Harmonics The above example demonstrates that through the extraction of the fundamental component of the terminal voltage, any distortion in the source current can be eliminated. However, the switch-frequency component in the terminal voltage still remains. Thus, a path for the switching harmonic current must provided to flow thorough a filter. To facilitate this, the circuit of Fig. 1 is modified by placing a filter capacitor in parallel with the DSTATCOM at the point of common coupling. This is shown in Fig. 5. With respect to this figure, the injected shunt current is defined as (2) This choice enables us to use the relations given in (1) since the ) remains undisturbed. Further KCL at the PCC (i.e., note that the terminal voltage in this case is the voltage across the (i.e., ). Let us now demonstrate the efcapacitor ficacy of this algorithm with the help of the following example. Example 3: Let us consider the same system used in examples 1 and 2. In addition to the feeder and load parameters mentioned, the following filter-DSTATCOM parameters in per unit are chosen as

The VSC is still assumed to be lossless and it is still supplied by a fixed dc voltage source rather than a storage capacitor. The magnitude of the dc voltage is the same as chosen in the previous two examples. Once the reference currents are generated

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Fig. 5. Single-line diagram of shunt compensation in the presence of a filter capacitor.

Fig. 6. Effect of hysteresis control on the DSTATCOM of Fig. 5.

using (1), they are tracked using a hysteresis band current control scheme with a band of 0.01. The compensator is turned on at 0.01 s. Fig. 6 shows the phase-a source current for this case. It can be seen that the source current diverges as soon as the compensator is pressed into action. A hysteresis controller can be viewed as a high gain proportional controller. Also, the hysteresis band adds a certain phase lag in the operation. For a first order system, like the DSTATCOM of Fig. 1, this never makes the closed-loop system unstable. However, this can have a detrimental effort on an oscillatory system as shown in Fig. 5. It is thus imperative that an alternative stabilizing controller be designed for this system. B. DSTATCOM Control In this subsection, the control design is presented for the structure shown in Fig. 5. The equivalent circuit of the compensated system is shown in Fig. 7. Let the state vector be defined as

Fig. 7. Equivalent circuit of the DSTATCOM.

the above observation, the following state transformation can be made:

(4)

The state (3) then can be transformed into (5) 1) Proportional Control: Assuming full control over , an infinite time linear quadratic regulator (LQR) can be designed for this problem. The control is of the form (6) is the desired state vector. In an LQR problem, a where performance index of the form (7) is chosen. It is then minimized to obtain the optimal control law through the solution of steady state Riccati equation [7]. For the system described in Example 3, the LQR performance index is minimized with

where is the transpose operator. The state-space equation of the circuit then can be written as

(3) is the switch state. The currents In the above equation, of Fig. 5 are defined in terms of the currents of Fig. 7 as follows:

The state (3) contains the feeder and load impedances. While the former is measurable, the latter may change at any time. Moreover, any feedback controller must rely only on the locally measured variables. From Fig. 5, it can be seen that the local variables for the DSTATCOM are terminal voltage, source current, filter current, and the filter capacitor current. Based on

where is a diagonal matrix. The two variables that are most and the terminal important to be controlled are the current voltage. The weighting matrix reflects the importance of these . states. The gain matrix is given by Using this feedback, the oscillatory closed-loop eigenvalues are . To avoid the complexity to the left of the line of forming a reference for the load current, the gain matrix is . This reduced state feedback restricted to results in a minimal shift in the closed-loop eigenvalues to the . left of

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2) Switching Control: The control signal as defined by the LQR design is a continuous signal. In practice, the control signal is the switching decision of the VSC of the DSTATCOM and is thus constrained to be either 1 or 1. One important property of the linear quadratic regulator is that it is tolerant of input nonlinearities, as shown in Fig. 8. LQR design is stable provided that the effective gain of the input nonlinearity is constrained in the sector between and 2 [7]. When the errors are large and the control is bounded between 1 and 1, the gains of must be small. The switching control is 1 when the LQR value is positive, and has the value 1 when it is negative. For a set of decreasing values of , there is a corresponding set of increasing values of . Thus, there will always exist a value of such that is bounded appropriately. Finite time convergence of the regulator problem can be shown, provided is chosen , . This gives a better performance such that as than the exponential convergence of proportional control as discussed in [7] for regulator problems. For the tracking problems, the system aims to remain in close proximity to the reference. After the initial transient is over, the control based only on the sign of LQR value will chatter at a rate limited by the switches. To avoid this, the switching is based on (8) where the function is defined by

Fig. 8. State feedback control with a nonlinear element in the forward path.

Fig. 9. Compensation of a load containing harmonics when the source is nonstiff and the compensator includes a filter capacitor.

(9) The selection of lim determines the switching frequency while tracking the reference. This use of projection of the LQR design gives good convergence to the tracking band as well as good stability of tracking. In this control law, the switching decision is based on a linear combination of multiple states. Hence, this control is called a switching band tracking control. For a well-known environment, such as tracking sine waves, the range of errors is known beforehand; therefore, a gain matrix can be found that will keep the control value in the desired range (1/2 to 2). 3) Computation of References: To implement the switching control of (8) using the reduced state feedback, the references for compensator current are computed using (1). The references for the terminal voltage and the current through the filter capacitor must be formed consistent with the compensator reference. In the process of forming (1), as mentioned in Example 2, the fundamental positive sequence component of the terminal voltage is also obtained. Once this voltage is obtained, both the references for terminal voltage as well as the current through the filter capacitor can be formed. Thus, the reference signals are computed based on the actual measurements and fundamental extraction. It is to be noted here that the measurements and the fundamental extraction are continuous. However, it has a settling time of half a cyclewhich implies that the compensator requires half a cycle to settle to zero power flow following any transient. The consistency of the state references is an integral part of the proof of control convergence given in Appendix B. Starting from an arbitrary initial state, the stability properties imply that the system will converge; if the reference is suffi-

ciently small, the system will converge to the switching surface. If the above conditions are always satisfied, perfect tracking of system states to within tracking band will result. It is to be noted however that unmodeled disturbances such as lightning strikes, faults, or large load changes may saturate the control leading to imperfect tracking. Example 4: Let us consider the same system given in Example 3. In addition to the load given in Example 1, a rectifier load that is drawing a peak current of 0.35 p.u. is also added. The and LQR controller is used with a gain of . The response is shown in Fig. 9. From this, it can be seen that both load currents and the terminal voltages become balanced and free of harmonics once the compensator action settles. Fig. 9(d) shows the three instantaneous powers. It can be seen that the power drawn by the load changes dramatically with the introduction of the compensator as it balances the terminal voltage as well. As expected, the source power becomes constant and the compensator power becomes zero-mean. It is to be noted that the gain matrix is designed with the parameters of phase-a of the system and is subsequently used for the other two phases. Since the load parameters are different for the different phases, the algorithm can be claimed to be robust to the variations in the load parameters. It is also important to investigate the robustness of the system with respect to the variations in the feeder parameters since the feeder configuration may change with time. The system is started with the parameters and gain matrix given above where the DSTATCOM is switched at the end of first half cycle. The feeder resistance is forced to zero and its reactance is changed to 0.1 p.u. at the end of the second cycle (0.04 s). Keeping the feeder resistance to zero, the feeder reactance is changed to 0.05 p.u. at the end of the fourth cycle (0.08 s). Subsequently, at the end of sixth cycle (0.12 s), the feeder impedance is changed again to have a resistance of 2.0 p.u. and a reactance of 0.9 p.u. The results are seen in Fig. 10 which shows that the desired current compensation is maintained. It can be seen that both source current and terminal voltage remain balanced and distortion free despite the changes in the feeder parameters.

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Fig. 11. Control signal and dc capacitor voltage when the control system is started from zero initial condition. Fig. 10. System response to changes in the feeder parameters.

IV. DC CAPACITOR CONTROL So far in the discussion, it has been assumed that the VSCs of the DSTATCOM are supplied by a dc source. In practice, dc capacitor is used as shown in Fig. 2. It has been assumed fur. This is again an ther that the compensator is lossless invalid assumption as there will always be switching losses and losses in the connecting transformer. These losses will tend to force the dc capacitor to discharge resulting in loss of tracking. in the It is therefore imperative that the dc voltage stored is maintained around a prespecified set storage capacitor value. This is only possible by drawing additional power to overcome the losses due the switching, modeled here as . In order to accommodate this, the real power supplied by the source is not only the average load power but also the total of average load power and power lost in the DSTATCOM circuit. Equation (1) can be modified to accommodate this loss as

Fig. 12. change.

Changes in instantaneous powers and capacitor voltage with load

Example 5: Consider the same system as given in Example 4. The DSTATCOM is not assumed to be lossless in this case. The following per unit quantities have been chosen, where the capacitor value is quoted at the system frequency of 50 Hz to maintain the per unit system

(10) The PI controller parameters chosen are is the power lost due to . The correction where must be generated through a suitable feedback control such across the storage capacitor is that the dc voltage maintained. The feedback aims to correct the deviation of the average from a reference value . The average value can value of be obtained at the end of each cycle or even running average can be can be used as a feedback signal. Let us define the following error signal (11) is the average value of the dc capacitor voltage, where measured at the end of a cycle. In the simplest form of feedback, a proportional-plus-integral (PI) controller is used to correct for any discharge in the capacitor voltage. The controller is then given by (12) is then substituted in (10) and as a result of The value of which an additional amount of real power will be drawn from the source to maintain the dc capacitor voltage.

The system is started from rest (i.e., the compensator is connected at the end of first half cycle after the average load power is obtained). The capacitor is assumed to be precharged to 1.5 p.u. and this value is also chosen as the set point for this voltage. The controller is started from a zero initial condition. The results are shown in Fig. 11 in which the capacitor voltage and the control signal are plotted. It can be seen that after the initial transient, the capacitor voltage returns to its desired value. The capacitor voltage settles in about 0.3 s. To investigate the effect of load change on the compensator system, the RL component of the load is sudden changed to

when the system is operating in the steady state. The harmonic currents drawn by the load however remains unchanged. The system response is shown in Fig. 12. In Fig. 12(a), the instantaneous powers are shown. Even if the load power settles within a couple of cycles, the source power and the compensator power take longer to settle. The capacitor voltage settles within 0.15 s.

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However, during this transient, the tracking is perfect, apart from the half cycle delay in formulation of correct references. V. CONCLUSIONS This paper discusses the issues for correction of load unbalance and distortion at a weak ac bus using DSTATCOM. It has been shown that for weak ac buses, the DSTATCOM may introduce distortion in the line current or the voltage at the point of common coupling. The distortion in the line current may be eliminated using the fundamental voltage of the PCC in the governing equations, but the voltage distortion cannot be eliminated without adding a filter capacitor in parallel with the DSTATCOM. However, the addition of the filter capacitor complicates the tracking problem. To solve the tracking problem, we have proposed a control scheme that depends on the extraction of the reference signals. The reference current generation scheme along with fundamental extraction of PCC voltage constitutes the reference of this controller. The control scheme proposed in the paper is based on half cycle sliding (moving) averaging. We recommend the use moving average filter for this half cycle averaging such that the reference signals are continuously extracted as we move along in time. This has faster settling time for reference extraction compared with cycle by cycle averaging. Consequently, the system quantities also settle faster. APPENDIX A VI. EXTRACTING SEQUENCE COMPONENTS FROM SAMPLES In this appendix, we propose a method for the extraction of phasor symmetrical components of currents (or voltages) from their samples. For this, we utilize the method of instantaneous symmetrical component that is defined in [8]

Their phasor symmetrical components are then

(A.3) The instantaneous components of these currents are then

From (A.2), the zero-sequence is given by

(A.4) Then from (A.2)

Now, for a system in steady state, if is chosen equal to half a cycle (or any integer multiple of half a cycle), the above equation can be evaluated as (A.5) In a similar way it can show that (A.6) Thus, the Fourier coefficients of the instantaneous symmetrical components are able to yield the sequence components. APPENDIX B

(A.1)

where , , and are the instantaneous three-phase currents, is the zero-sequence, and and are two vectors that are complex conjugate of each other. The symmetrical compo. Let us now define the nent operator is defined as following coefficients:

VII. PROOF OF TRACKING CONTROLLER CONVERGENCE The system state space description is given in (5) as (B.1) Let us form a reference that is defined by

(A.2) Defining an error vector as the above two equations that

(B.2) , it can be shown from (B.3) From the control law given in (5), if the trajectory remains on the switching surface [7]

The above are the complex Fourier coefficients for the fundamental components.[9]. Let us define a set of three unbalanced currents phasor terms as

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This yields

From the above equation, the control error can be found as (B.4) Substituting (B.4) in (B.3), the error equation becomes (B.5) Hence, the tracking error will converge to zero for any initial condition provided that have 1) all the eigenvalues of the matrix negative real parts; 2) the reference signal can be generated by an equation in the form of (B.2); 3) Since u is bounded between 1 and 1, (B.4) requires . that It is a property of switching law based on LQR design that condition (1) above is satisfied. Most tracking problems are . posed as the output of the plant following some reference . The task is to define a state reference satisfying In frequency domain, the output equation can be given as (B.6) Assuming that the system is tracking a single output and since the plant in (B.1) is single input, then from (B.6)

Condition (3) cannot be true satisfied for arbitrary references. Since the source is always bounded, from (B.7) it can seen implies a bounded . The system states that a bounded and the system states are not necessarily bounded. But if are sufficiently small, then the condition (3) can be satisfied and perfect tracking can occur. REFERENCES
[1] R. C. Dugan, M. F. McGranaghan, and H. W. Beaty, Electrical Power Systems Quality. New York: McGraw-Hill, 1996. [2] H. Akagi, Y. Kanazawa, and A. Nabae, Instantaneous reactive power compensators comprising switching devices without energy storage components, IEEE Trans. Ind. Applicat., vol. IA-20, pp. 625630, May/June 1984. [3] H. Akagi, A. Nabae, and S. Atoh, Control strategy of active power filters using multiple voltage-source PWM converters, IEEE Trans. Ind. Applicat., vol. IA-22, no. 3, pp. 460465, May/June 1986. [4] A. Ghosh and A. Joshi, A new method for load balancing and power factor correction using instantaneous symmetrical components, IEEE Power Eng. Rev. (Power Eng. Lett.), vol. 18, no. 9, pp. 6062, 1998. , A new approach to load balancing and power factor correction [5] in power distribution system, IEEE Trans. Power Delivery, vol. 15, pp. 417422, Jan. 2000. [6] M. K. Mishra, A. Ghosh, and A. Joshi, A new STATCOM topology to compensate loads containing ac and dc components, in IEEE Winter Power Meeting, Singapore, 2000. [7] B. D. O. Anderson and J. B. Moore, Linear Optimal Control. Englewood Cliffs, NJ: Prentice-Hall, 1971. [8] W. V. Lyon, Transient Analysis of Alternating-Current Machinery. New York: Wiley, 1954, ch. 2. [9] J. D. Irwin, Basic Engineering Circuit Analysis, 4th ed. New York: Macmillan, 1993.

Arindam Ghosh (S80M83SM93) received the Ph.D. degree in electrical engineering from the University of Calgary, AB, Canada, in 1983. Currently, he is a Visiting Professor at the Queensland University of Technology, Brisbane, Australia. He is also a Professor of Electrical Engineering at the Indian Institute of Technology Kanpur since 1991. He has held visiting positions in Nanyang Technological University, Singapore, and the University of Queensland. His research interests include power systems, power electronics, and controls.

(B.7) Thus, the corresponding reference state can be formed from (B.8) Thus, any single output-tracking problem can be translated into a state tracking problem and expressed in the form of (B.2). In practice, circuit analysis would be the easiest method to form from , particularly for sinusoidal tracking. This will satisfy condition (2).
Gerard Ledwich (M73SM92) received the Ph.D. in electrical engineering from the University of Newcastle, Newcastle, Australia, in 1976. Currently, he is a Chair Professor in Electrical Asset Management at the Queensland University of Technology, Australia, where he has been since 1998. He was also Head of Electrical Engineering at the University of Newcastle from 1997 to 1998. He was associated with the University of Queensland from 1976 to 1994. He has also held visiting appointments with the University of Calgary, Auckland University in New Zealand, University of Wisconsin at Madison, and Queensland Electricity Commission. His interests are in the areas of power systems, power electronics, and controls.