VLSI

Porting of Micro blaze processor with its peripherals on to an FPGAA Test Pattern Generation Method Based on Fault Injection for Logic Ele ents of FPGA Efficient i ple entation of !on"olution encoder and #iterbi decoder for pipelined MB$%F&M 'ltra (ide Band FPGA$Based Ad"anced )eal Traffic Light !ontroller *+ste &esign

BI*T$based test and diagnosis of fault circuit with FPGA logic bloc,s !iphering algorith in Micro Blaze$based e bedded s+ste s on -ilin. FPGA ulti$channel 'A)T controller for co ple. control

FPGA I ple entation of FIF% based s+ste s

Efficient i ple entation of Arith etic Logic 'nit for -ilin- FPGA using #/&L Efficient architecture for )eed *olo on bloc,$ &esign and i ple entation of scra ble and descra bler for pipelined MB$%F&M 'ltra (ide Band A high perfor ance FPGA i ple entation of &E* #L*I &esign 0 I ple entation of Basic )*A Encr+ption Engine

#L*I &esign 0 I ple entation of Basic &es !r+pto !ore FPGA i ple entation of interlea"er and deinterlea"er for pipelined MB$%F&M 'ltra (ide Band$1232 Efficient FPGA Architectures for FI) Filtering using #/&L &eter inistic built$in self$test using linear feedbac, shift registers Efficient i ple entation of dice ga e si ulator on *partan 4E FPGA Efficient i ple entation of !ode !on"erters for -ilin- FPGA using #/&L

FPGA i ple entation of )*A public$,e+ cr+ptographic coprocessor !hip$pac,age !o$i ple entation of a triple &E* Processor #L*I &esign 0 I ple entation of Associate Me or+ using #/&L *tatechart Based Ele"ator !ontroller and Its #erification$1225 Low Power /ardware I ple entation of /igh *peed FFT !ore$1232 #/&L odel of &ual$port )AM with *+nchronous )ead using -ilin- *partan4E FPGA

)econfigurable co puting for )!6 cr+ptograph+$1227 &esign and I ple entation of II) filter on -ilin- FPGA using #/&L #/&L i ple entation of FPGA s+nthesizable scaled A)M 89 "$: soft processor core for e bedded *+ste $on$!hip applications$122; #L*I i ple entations of the triple$&E* bloc, cipher on -ilin. *partan 4E FPGA$1227 Triple$&E* A*I! Module for a *+ste $on$!hip Architecture$1225 FPGA design of )!6 encr+ption and decr+ption algorith <o"el stepper using #/&L$1232

otor controller based on FPGA hardware i ple entation$122:

&esigning FI) filter using MATLAB and s+nthesizing on to -ilin- FPGA #L*I &esign 0 I ple entation of Basic )*A Encr+ption Engine$1232 #L*I &esign 0 I ple entation of Bus Arbiter using #/&L #L*I &esign 0 I ple entation of I1c !ontroller !ore An Area$Efficient 'ni"ersal !r+ptograph+ Processor for * art !ards = 1232 A #/&L I ple entation of 'A)T &esign with Bist !apabilit+ = 122; A )obust 'art Architecture based on )ecursi"e )unning *u Perfor ance = 122; Filter for Better <oise

FPGA I ple entation of '*B Transcei"er Macrocell Interface with 'sb1>2 *pecifications I ple entation of a Multi$!hannel 'A)T !ontroller based on FIF% Techni?ue and FPGA$ 1225 #L*I &esign 0 I ple entation of Encr+ption 0 &ecr+ption using #/&L

#L*I &esign 0 I ple entation of Arith etic Logic 'nit using #/&L #L*I &esign 0 I ple entation of !ode !on"erters using #/&L &esigning II) filter using MATLAB and s+nthesizing on to -ilin- FPGA #L*I &esign 0 I ple entation of *tepper Motor !ontroller I ple entation of *cra blers and &escra blers in Fiber %ptic!o and %tn$1224 #/&L odel of I1! controller for interfacing unication *+ste s = *onet

icrocontrollers based on -ilin. FPGA

I ple entation of */A hash function for a digital signature *+ste $on$!hip in FPGA$1232 /igh &efinition @/dA T" &ata Encoding and &ecoding using )eed *olo on #L*I &esign 0 I ple entation of Fir &esigning I ple entation of a )I*!$architecture on FPGA using #/&L for *+ste $on$!hip application$ 122; FPGA I ple entations of the &E* and Triple$&E* on -ilin. FPGA$1225 Efficient i ple entation of I1c Master !ontroller using -ilin- FPGA FPGA i ple entation of Pc Printer Port B *erial Port on -ilin- *partan 4E &esigning of Progra &esigning of Progra able Peripheral Interface @PpiA using #erilog /dl able Ti er Interface @PtiA using #erilog/dl

&esigning of 'ni"ersal *+nc B As+nc )ecei"er and Trans itter@'sartA <o"el !ontent Addressable Me or+ Architecture using -ilin- FPGA &esign and I ple entation of Ele"ator !ontroller$1225 Traffic light s+ste design on FPGA$1232

#L*I &esign and I ple entation of Encoder 0 &ecoder using#/&L Bz$FadC A Low$Power Low$Area Multiplier Based %n *hift$and$ Add Architecture $ 1232 <o"el Area$Efficient FPGA Architectures for Fir Filtering with*+ 1232 A !o pact AE* Encr+ption !ore on -ilin. FPGA $ 1232 etric *ignal E.tension $

A <ew Low Power Test Pattern Generator using A #ariable$ Length )ing !ounter $ 1232 Power opti ization of linear feedbac, shift )egister @LF*)A for low power BI*T $ 1232 Efficienc+ Anal+sis and *ecurit+ e"aluation of )!6 Bloc, !ipher$1225 &e"iation$Based LF*) )eseeding for Test$&ata !o pression $1232 *uperscalar Power Efficient Fast Fourier Transfor FFT Architecture $ 1232

A <ew /igh$*peed Architecture for )eed$*olo on &ecoder $1232 !ost$Efficient */A /ardware Accelerators $ 1232 The &esign of )adi.$: FFT b+ FPGA$122; Low Power &esign of Preco putation$Based !ontent$ Addressable Me or+ $ 122; &esign and I ple entation of '*B 1>2 core interface using #/&L &esign %f Ad"anced Encr+ption *tandard 'sing #/&L $ 122; A )obust architecture for bus arbiter i ple ented on -ilin- FPGA using #/&L The E"aluation )eport of */A !r+pt Anal+sis /ash Function$1232 Acceleration of )*A !r+ptographic %perations 'sing FPGA Technolog+$122; #l*I &esign of &es@&ata Encr+ption *tandardA Algorith I ple entation Fi"e *tage Pipelined )I*! Processor for Parallel Processing$1226 I ple entation of !ontent Addressable Me or+ for At Applications