8259A/82C59A-2 Programmable Interrupt Controller Technical Questions and Answers - Rev 2, Sep '95

Q1. What is it? A1. The 8259A/82C59A-2 is a programmable interrupt controller (PIC). It is designed to allow prioritizing and handling of Fahardware interrupt requests from peripheral devices, mainly in a PC environment. Q2. Why is a device like this needed? A2. I/O devices require servicing in an efficient manner. The PIC allows I/O devices to be serviced using the "interrupt" technique rather than with a CPU "polling" technique. The "interrupt" technique allows the microprocessor to continue to execute its programs and only stop to service peripheral devices when it is told to do so. The microprocessor is saved the overhead of determining the source and priority of the interrupting device. Q3. How does the PIC work? A3. The PIC receives an interrupt request from an I/O device and tells the microprocessor. The CPU completes whatever instruction it is currently executing and then fetches a new routine that will service the requesting device. Once this peripheral service is completed, the CPU resumes doing exactly what it was doing when the interrupt request occurred. The PIC functions as an overall manager of hardware interrupt requests in an interrupt driven system environment. Q4. How do the 8259A/82C59A-2 accomplish the interrupt activity? A4. a. The device requiring service signals the PIC via one of the seven PIC interrupt request (IR) input lines. The corresponding bit in the PIC Interrupt Request register (IIR) is set. b. The PIC activates the INT line which is connected to the CPU INTR line. c. If the interrupts are not masked at the CPU, it finishes the currently executing instruction and sends one interrupt acknowledge (INTA) pulse to the PIC. d. In an X86 environment, the PIC responds by setting the highest priority In Service Register (ISR) bit and the corresponding IIR bit is reset. There is no PIC activity on the data bus in this cycle. e. The CPU will initiate a second INTA pulse. During this pulse, the PIC releases an 8-bit pointer on to the data bus where it is read by the CPU. f. The CPU reads the interrupt-type number, determines the associated address of the interrupt service routine (ISR), then fetches and executes the ISR. g. In the Automatic End Of Interrupt (AEOI) Mode the ISR bit is reset at the end of the second INTA pulse. Otherwise the ISR bit remains set until an appropriate EOI command is issued at the end of the ISR. Q5. Is it really this simple? A5. Basically, yes. The scenario can be complicated by the requirement to program the PIC to fit the environment. For example, there are various Modes to which the PIC can be programmed. Another complication is interconnecting or cascading one master and up to eight slave PIC's in an application. Q6. How is the PIC programmed? A6. Programming the PIC can be broken into two parts. These are initialization and operation. The PIC therefore accepts two types of command words generated by the CPU:

1. Initialization Command Words (ICWs) determine the basic operating mode of the PIC. Two to four ICW bytes must be used. The ICW inputs are timed by WR# pulses. ICW1 and ICW2 must always be used. ICW3 and ICW4 are used only if they are required by specifying so in ICW1. ICWs must be completed before continuing on to the second type of command word. 2. Operation Command Words (OCWs) can be written into the PIC anytime after the ICWs are written. There are three OCWs. The OCWs customize the priority features and give the user the ability to write/read various registers. The OCWs also tell the PIC to operate in various interrupt modes. There are 4 modes. A description of the first mode follows. A similar description of the remaining 3 modes can be found in the data book: Fully nested mode: Default mode after initialization. The IRs are ordered in priority 0 - 7, with 0 as the highest. When an interrupt is acknowledged the highest priority request is determined and its vector is placed on the bus. Additionally, bit IS0 - IS7 is set and remains set until the microprocessor issues an EOI or until the trailing edge of the last INTA if AEOI is set. While the ISx bit is set, all further interrupts of the same or lower priority are inhibited, while higher level priority interrupts will be acknowledged only if the microprocessor internal interrupt flipflop has been re-enabled through software. - Rotating priority mode. - Special mask mode. - Polled mode. Q7. How are the interrupt controllers cascaded? A7. One master and eight slave PIC's can handle 64 interrupt priority levels. The master controls the slaves through the 3 line cascade bus. (The cascade bus is a separate bus. It is not associated with the PC address, data, or control busses.) The cascade feature cannot be implemented on the IBM PC because the required cascade lines (CAS0-2) and the INT-INTA lines do not exist on the I/O channel. Each 82C59A-2 in the application must follow a separate initialization sequence and can be programmed to work in a different mode. An EOI command must be issued twice: once for the master and once for the corresponding slave. Here is the cascade configuration: 1. The slave interrupt outputs (INT) are connected to the master interrupt request inputs (IR0-7). When a slave request line is activated and afterwards acknowledged, the master will enable the corresponding slave to release the device routine address during bytes 2 and 3 of INTA. (Byte 2 only for 80C86 and 80C88). 2. Only the master INT is connected to the CPU INTR via the control bus. 3. The CAS0-2 lines are respectively connected PIC-to-PIC. The cascade bus acts like chip selects to the slaves during the INTA# sequence. 4. The INTA of each PIC is connected to the control bus. Q8. What is the clock speed and what does the 82C59"-2" mean? A8. The device is not clocked, but it usually connects to an 8MHz bus. Marketing shows it as an 8MHz device. The "-2" means an improved timing. In this case it is improved AC characteristics when compared to the older (no longer available) 82C59A. Q9. The 1993 Peripheral Handbook, Pg. 3-200, last paragraph: "...When the 82C59A-2 PIC receives.....After an unspecified amount of time..." What is the minimum of this unspecified amount of time? A9. This is the "INT Priority Problem Window" errata which is found separately in Lotus Notes for Intel FAE/FSE/DFAE and in Intel's on-line services for everyone else. Q10. The data sheet and Ap-59 are unclear on one specific point regarding the 8259A PIC. When an initialization routine (writing ICWS1) is started, are the IRR and ISR registers automatically cleared? If the IRR is not cleared, is there any way to clear the IRR through software?

A10. AP-59 says after the first ICW is issued: 1. The ISR register is cleared. 2. The IRR is selected for the read register command. Item 2 means the Status Read is set to the IRR. A low on RD# allows the 8259A to send the status of the IRR to the data bus. A normal operation to read the IRR without use of the first ICW would be, prior to the RD# pulse, issue a Read Register Command with OCW3 (RR=1, RIS=0). Disable interrupts during this operation. The question becomes whether or not an IRR read operation clears the IRR register. Since the IRR stores all the interrupts which are requesting service, and the highest priority in the IRR is strobed into the corresponding bit of the ISR, the priority of the interrupt request complicates the picture. However, there is no indication that the IRR is cleared by a read operation. The customer might try reading the IRR twice to see if the second read operation shows no interrupts exist in the IRR. Don't forget that had there been an interrupt in existence, it would be strobed into ISR on the INTR# pulse. The next question is whether or not the user can write to the IRR register. There is no known way to do this. Loading IR0-IR7 with additional circuits may be one solution. These additional circuits would allow the user to "program" the interrupt request lines to the edge or level triggered equivalents of "no interrupts exist". Q11. Does the slave or master send out the interrupt service routine vector in a cascade environment? A11. In a cascaded environment, the master enables the slave to release the device routine address during bytes 2 and 3 (or byte 2 only depending on the CPU in use). Q12. Does INT have to be active before issuing a poll command? Using the Poll Mode, the sequence of events is: (1) IRQ occurs, (2) INT issued, (3) IRQ's are masked, (4) the chip is polled. Is this right? A12. The INT must be active before issuing a poll command. The reason for this is the PIC must have an interrupt request into IR0-7 to set the internal logic and store the interrupt request in the interrupt request register. The PIC then makes INT high as a normal course of activity for all modes. However, in the polled mode the microprocessor should ignore the interrupt. This is done by not connecting the INT output to the microprocessor or by masking the interrupts within the microprocessor. This disables the microprocessor interrupt input and allows the polling mode service routine to handle the interrupts. Rather than having the microprocessor poll each peripheral to determine if a device needs service, it polls the PIC. The sequence of events is (1) an interrupt occurs (the appropriate IR into the PIC goes high), (2) the PIC issues an INT (this is ignored by the microprocessor because the INT is not seen by the microprocessor), (3) the poll command is issued, (4) the PIC treats the next RD# pulse as an interrupt acknowledge and sets the appropriate IS bit if there really is an interrupt request, (5) the PIC places a word onto the data bus during the RD#, (6) the word shows whether an interrupt request has occurred and the highest priority requesting service, (7) the microprocessor reads the word and branches to the appropriate service routine, if necessary. Q13. An application has glitches in the IR lines which cause the 8259A to issue an interrupt level 7. (This is normal operation for the device. See pages 3-177 and 3-188 of the 1993 Peripheral Components data book.) The customer is trying to ignore this situation by having the interrupt service routine do masking. Is this correct? A13. The correct solution is to eliminate the glitches on the IR lines. However, the customer is trying to fix this with software. One technique is to read the Interrupt Request Register after the INTA# pulse and also determine if the IR line is still high. If it is, there is a real interrupt. If no IR lines are still high, it was a glitch. Care must be taken because a real IR may come into existence during this process. Q14. What is the state of the CAS lines 01 and 02 upon reset? Is there a possibility for contention? Which are driven during power-up? A14. The three I/O pins (CAS0-2) are outputs when the 8259A is used as a master and inputs when the 8259A is used as a slave. The customer should insure the software issues the correct ICW's and OCW's to the 8259A(s) to correctly configure it (them) as master or slaves. The CAS lines in an 8259A are specifically

designed to source or sink current at power-up depending on how the device is configured as a master or slave. Also, the CAS lines are a private 8259A bus. These lines do not connect to any other bus in a PC application and do not connect to the processor. It should not matter if the CAS lines are driving or not upon power-up if there is no interface of the CAS lines to any other part of the PC system. Q15. What are the conditions for latching interrupt requests during mask? Are all interrupt requests ignored during mask? Are all interrupts recognized? Are certain interrupts ignored in certain conditions? If so, under what conditions are interrupts ignored? A15. There is no reason to mask an interrupt line, however, if the software does this and another interrupt comes in on the same line, the second interrupt is latched and will be asserted at the end of the first interrupt service routine. The Priority Cell - Simplified Logic Diagram in the data book shows how this is done at logic level. There are different methods of handling the problem of multiple interrupts on the same interrupt line. Some applications have the EOI early in the interrupt service routine, some have it in the middle, and some have it at the end. Some applications do not mask the interrupt line. The best method for handling interrupts with a stand-alone 8259A/82C59A-2 interrupt service routine is shown below: 1. 2. 3. 4. 5. 6. 7. 8. Save all registers. Execute uninterruptable code. Enable interrupts. Execute interruptible code. Disable interrupts. Issue nonspecific EOI to Bank A (master) IRQ. Restore registers. Interrupt return.

The best method for handling interrupts with a cascaded 8259A/82C59A-2 ISR is shown below where B=Slave and A=Master: 1. 2. 3. 4. 5. 6. 7. 8. Save all registers. Execute uninterruptable code. Enable interrupts. Execute interruptible code. Disable interrupts. Issue nonspecific EOI to Bank B PIC. Read Bank B ISR. Is there a lower priority interrupt in service on Bank B PIC? NO: Issue nonspecific EOI to Bank A PIC. Restore registers. Interrupt return. YES: Restore registers. Interrupt return.

Q16. The 8259A is used in the Cascade mode. An interrupt occurs on IR0. The IR0 interrupt line is then masked. A second interrupt signal is asserted to the IR0 input. In this sequence, is the second interrupt request to IR0 recognized when the mask is removed? What are the conditions for latching interrupt requests during mask? Are interrupt requests ignored during mask? A16. There is no reason to mask the IR0 interrupt line, however, if the software or hardware does this and another interrupt comes in on IR0, the second interrupt is latched and will be asserted at the end of the first interrupt service routine. The Priority Cell - Simplified Logic Diagram in the data book shows how this is done at logic level. Q17. How are multiple interrupts in succession on the same IR line handled? Are they all recognized? Are there any conditions where they are ignored? A17. There are different methods of handling the problem of multiple interrupts on the same interrupt line.

Obviously, these interrupts should all come from the same source and therefore require the same interrupt service routine. The flow chart seen in A15 above is an excellent technique for the interrupt service routine. Beyond this, the application should be designed such that when an interrupt occurs and the associated IR line goes high, it should remain high until the interrupt request is acknowledged. Q18. An application is operating in the cascade mode. Does the FREEZE signal latch all of the interrupt requests? A18. The FREEZE# signal is an internal signal demonstrated in Figure 9 of the 8259A data book. FREEZE# is active during INTA and poll sequences only. It latches all interrupt requests. Q19. Does INTA acknowledge all of the interrupt requests? A19. An INTA is generated by the CPU as a result of the INT from the 8259A. As long as any interrupt request line to the 8259A is active, the 8259A determines the priority of the interrupt request and places the appropriate 8-bit pointer to the correct interrupt service routine onto the data bus at the second INTA pulse from the CPU. All interrupt requests are acknowledged. Q20. If a higher interrupt request occurs to the slave between two INTA cycles (of lower priority interrupt), which vector will be placed on the bus? A20. If a higher interrupt request occurs between the CPU INTA pulses (which are being generated from an earlier but lower priority) interrupt, that interrupt service routine will be completed depending upon the mode of the 8259A (masked modes) and how the interrupt service routine is written. It takes time for the new higher interrupt to be recognized by the 8259A, prioritized, and change the IRR and ISR bits to reflect the presence of the higher interrupt. Meanwhile, the interrupt service routine for the earlier, lower priority interrupt is being operated on. The interrupt service routine for each interrupt must be aware that higher priority interrupts can occur. The flow chart for correct interrupt service routine activity (Q14 above) should be followed. Q21. Will the master be able to acknowledge that a higher priority interrupt is pending? A21. The master may not even be aware that a higher priority interrupt occurred. It simply executes the interrupt service routines pointed to by the 8259A. The interrupt service routines are the key. They must be written correctly. Again, the flow chart in Q15 above should be followed. Q22. Reference figure 10, page 3-188, 1993 Data Book. For any interrupt request (IR) input, master or slave, the IR input should remain high until an interrupt acknowledge is received. This is described in the reference above. If the following events occur: 1. 2. 3. 4. A slave interrupt occurs. The INTR output of the slave is set high (goes to IR of the master). Before an acknowledge occurs, a higher priority slave interrupt occurs. The INTR output of the slave is pulsed low to indicate that a higher priority slave INT occurred.

The question is: Does this pulse at the IR input of the master create a short interrupt situation on the master? A22. The higher priority interrupt should not cause INTR to deassert and reassert. I think the INTR circuit is an ORing of latched IRQs, call it LIRQ. If IRQ4 is asserted, it causes LIRQ4 to go active and stay active. INTR goes active because LIRQ4 is active. If IRQ3 is asserted, LIRQ3 will be active. Since INTR is already active, no pulse is seen. Could the question be confusing the scenario where a higher priority interrupt occurs during a lower priority interrupt acknowledge? In this instance, the IRQ3 is asserted between the two INTA cycles. IRQ4 caused INTR to go active. When the second INTA from IRQ4 is completed, INTR pulses inactive then active. INTR went inactive because IRQ4 was acknowledged. Then, INTR goes active because IRQ3 is asserted. However, INTR many not meet the 100ns minimum low time. See the errata concerning the 100ns requirement found in Lotus Notes (for Intel FSE/FAE/DFAE) or Intel's on-line services. Essentially, if the 8259A/82C59A are cascaded and no additional circuitry is added to ensure the minimum low time of INT is at least 100ns, the master must be programmed for level triggered interrupts. The 8259A/82C59A fails to maintain INT low for at

least 100ns. It therefore does not successfully arm the edge detector of the master. This entire scenario was resolved by programming the master in the polled mode first, then later programming it in the mode the customer wanted. Now everything works fine. Bottom line: there was probably a timing violation which was corrected by the extra programming step. Q23. An application uses "a bunch of slaves". The application is in the Fully Nested Mode. If there is a second Interrupt Request before there is any INTA for the first IR, will any INTS be lost? A23. No. As soon as an INTA appears, the device resets the In Service register to reflect the presence of the highest status interrupt. While the In Service register bit is set, all further interrupts of the same or lower priority are inhibited. However, the older and lower status interrupt which previously existed is not overwritten or lost. Q24. From the "Priority Cell" diagram in the data sheet, a pull-up resistor is shown on the IR signal line. What is the value of this pull-up? How was this calculated? A24. The unused IR lines can be left disconnected, so there are very weak internal *pull-down* resistors shown on the IR lines in the Priority cell. This protects against noise activating the interrupt request sequence on unused IR lines in an application. The weak internal pull down resistors are overcome by the high applied to the IR inputs when they are used in an application and there is a real interrupt. The presence of a 5V high on the IR pin meets no resistance into the device and any long-term real IR signal is latched. If it is a noise spike on the IR lines, the weak pull down resistor inside the priority cell is sufficient to prevent the short-term false high from being interpreted as a real high. The exact value of the weak pull-down resistors on the interrupt controller IR lines is not documented. Q25. Can the 82C59A-2 device operate in both Poll command and AEOI mode? It doesn't appear that there would be any problem but please verify. A25. When using the Poll command, the processor does not poll each peripheral in order to find the actual device requesting service, the processor polls the 82C59A. When using the AEOI mode, the processor does not need to issue a command to notify the 82C59A it has completed an Interrupt Service Routine. The two functions can be used together. Q26. Are there any Schmitt Triggers on the input pins of the 82C59A? A26. No. The old 8259 had a hybrid edge/level triggered IR input but it was not a Schmitt Trigger. All the inputs of the 82C59A are digital logic, so there are no requirements to smooth any analog signals. Q27. Are there any issues using the 82C59A-2 in an 82386EX application? A27. Interfacing an external 82C59A is not straight forward! The interrupt controllers in the 386EX are called '82C59 compatible' but they are NOT 82C59s. The 82C59 requires a minimum 360ns INTA signal and needs two INTA signals per interrupt acknowledge. The 386EX has only 220ns interrupt acknowledge cycles, leaving the 82C59 140ns short of its required minimum. Therefore, the 82C59 will not 'bolt up' directly. It requires PLDs to interface to take control of the 386EX to stretch the interrupt acknowledge cycles. PLEASE NOTE: This product is no longer being manufactured by Intel. THESE DOCUMENTS ARE PROVIDED FOR HISTORICAL REFERENCE PURPOSES ONLY AND ARE SUBJECT TO THE TERMS SET FORTH IN THE "LEGAL INFORMATION" LINK BELOW. For information on currently available Intel products, please seehttp://www.intel.com/ and/or developer.intel.com

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