Lecture 6

SAR ADC
George Yuan Hong Kong University of Science and Technology Fall 2010

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Outline
SAR ADC
Resistive SAR Capacitive SAR

SAR calibration, compensation, redundancy Low voltage SAR Accurate SAR

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SAR ADC

Vx Vsig

Ci Vref C i

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Comparison Example

Vx waveform

What if COMP makes a mistake?

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Comparator

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Capacitor Layout

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SAR Logic
Top DL generates bitcycling clock Bottom DL generates bits RST:
TDL1: 1 Others: 0\

TDLi = 1
DTLi = 1 DTLi-1=COMP
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Power Consumption

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Flash & SAR Comparison

Flash: N bits, 2N comparators SAR: N bits, 1 comparator, N comparisons

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Resistive SAR

DAC, Comparator
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Current Cell
Identical current split ?

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Binary Current Division

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Current Summation

Offset reduction Clamping

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Input V-I Converter

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Capacitive SAR

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Comparator Input

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Comparator Self-Timing

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Outline
SAR ADC
Resistive SAR Capacitive SAR

SAR calibration, compensation, redundancy Low voltage SAR Accurate SAR

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Mismatch Error

Vx Vsig

Ci Vref C i
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Calibration Fundamentals

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Calibration Questions
How to measure the capacitor mismatch error? How to compensate the measured mismatch error?

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SAR Calibration, 15b, 12kS/s

N bit capacitive DAC M bit resistive DAC More accurate calibration DAC

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Highly Accurate Comparator

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Bridge Capacitor
Cb

Vx

Ci Cb Vref CbC LSB CbCMSB C LSB CMSB

Vx

Ci C LSB Cb Vref CbC LSB CbC MSB C LSB CMSB

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SAR ADC Calibration

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Example

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Non-binary SAR

Binary: 128, 64, 32, 16, 8, 4, 2, 1, 1 Non-binary: 128, 67, 35, 19, 10, 5, 3, 1, 1

Radix = 1.9

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Non-binary SAR Example

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Comparison Sequence

Assume 12.7% settling error

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Thermometer Coding
ROM

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Capacitor Layout

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Compensation Capacitor

Every capacitor has three states: 0, +1, -1 Signal range reduction by half
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Compensation Fundamentals

Extra comparison Only few times Vx ~ zero

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Compensation Hardware

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Outline
SAR ADC
Resistive SAR Capacitive SAR

SAR calibration, compensation, redundancy Low voltage SAR Accurate SAR

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Low Supply Voltage

No reference voltage, only Vdd

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CMOS Switch Voltage Range

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Comparator, S/H

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Low Voltage Rail-to-Rail Comparator

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Anti-Leakage Switch

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Outline
SAR ADC
Resistive SAR Capacitive SAR

SAR calibration, compensation, redundancy Low voltage SAR Accurate SAR

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12-bit SAR

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Operation Cycles
Purging

Sampling

Auto-zeroing

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Comparator

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Latch Offset Compensation

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Latch Auto-zeroing Phase

Sample M1,2, M9,10 offset on M11,12

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Sample M3,4 offset on themselves

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Latch Resolving Phase

Samples M1,2, M5,6 offset on M7,8

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Higher amplifier gain

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References
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. H. Lee, D. Hodges, and P. Gray, A self-calibrating 15bit CMOS A/D converter, IEEE J. Solid-State Circuits, Vol. SC-19, pp. 813-819, Dec. 1984 C. Hammerschmied, and Q. Huang, Design and implementation of an untrimmed MOSFET-only 10-bit A/D converter with -79dB THD, IEEE J. Solid-State Circuits, Vol. 33, pp. 1148-1157, Aug. 1998 G. Promitzer, 12-bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1MS/s, IEEE J. Solid-State Circuits, Vol. 36, pp. 1138-1143, Jul. 2001 J. Sauerbrey, D. Schmitt-Landsiedel, and R. Tewes, A 0.5V 1uW successive approximation ADC, IEEE J. Solid-State Circuits, Vol. 38, pp. 1261, Jul. 2001 C. Liu, S. Chang, G. Huang, Y. Lin, C. Huang, C. Huang, L. Bu, and C. Tsai, A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation, ISSCC Dig. Tech. Papers, pp. 386-387, Feb. 2010 M. Scott, B. Boser, and K. Pister, An ultralow-energy ADC for smart dust, IEEE J. Solid-State Circuits, Vol. 38, pp. 1123-1129, Jul. 2003 S. Gambini, and J. Rabaey, Low-power successive approximation converter with 0.5V supply in 90nm CMOS, IEEE J. Solid-State Circuits, Vol. 42, pp. 2348-2356, Nov. 2007 B. Ginsburg, A. Chandrakasan, Dual time-interleaved successive approximation register ADCs for an ultra-wideband receiver, IEEE J. Solid-State Circuits, Vol. 42, pp. 247-257, Feb. 2007 H. Hong, and G. Lee, A 65fJ/Conversion-step 0.9v 200kS/s rail-to-rail 8-bit successive approximation ADC, IEEE J. Solid-State Circuits, Vol. 42, pp. 2161-2168, Oct. 2007 N. Verma, and A. Chandrakasan, An ultra low energy 12-bit rate resolution scalable SAR ADC for wireless sensor nodes, IEEE J. Solid-State Circuits, Vol. 42, pp. 1196-1205, Jun. 2007 F. Kuttner, A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13um CMOS, ISSCC Dig. Tech. Papers, 10.6, Feb. 2002

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