141302 Advantages

DIGITAL PRINCIPLES AND SYSTEM DESIGN

The usual advantages of digital circuits when compared to analog circuits are:

Digital systems interface well with computers and are easy to control with software. New features can often be added to a digital system without ch hardware. Often this can be done outside of the factory by updating the product's software. So the product's design errors can be corrected after the p is in a customer's hands. !nformation storage can be easier in digital systems than in analog ones. The noise"immunity of digital systems permits dat stored and retrieved without degradation. !n an analog system noise from aging and wear degrade the information stored. !n a digital system as long as the total noise is below a certain level the information can be recovered perfectly. Robustness One of the primary advantages of digital electronics is its robustness. Digital electronics are robust because if the noise is less than the noise margin then the system performs as if there were no noise at all. Therefore digital signals can be regenerated to achieve lossless data transmission within certain limits. Analog signal transmission and processing by contrast always introduces noise. Disadvantages !n some cases digital circuits use more energy than analog circuits to accomplish the same tas#s thus producing more heat as well. !n portable or battery"powered systems this can limit use of digital systems.

$or e%ample battery"powered cellular telephones often use a low"power analog front"end to amplify and tune in the radio signals from the base station. &owever a base station has grid power and can use power"hungry but very fle%ible software radios. Such base stations can be easily reprogrammed to process the signals used in new cellular standards. Digital circuits are sometimes more e%pensive especially in small 'uantities.

The sensed world is analog and signals from this world are analog 'uantities. $or e%ample light temperature sound electrical conductivity electric and magnetic fields are analog. (ost useful digital systems must translate from continuous analog signals to discrete digital signals. This causes 'uanti)ation errors.

*uanti)ation error can be reduced if the system stores enough digital data to represent the signal to the desired degree of fidelity. The Ny'uist"Shannon sampling theorem provides an important guideline as to how much digital data is needed to accurately portray a given analog signal.

UNIT I -NUMBER SYSTEMS

Numbering S stem

Many number systems are in use in digital technology. The most common are the decimal, binary, octal, and hexadecimal systems. The decimal system is clearly the most familiar to us because it is a tool that we use every day. Examining some of its characteristics will help us to better understand the other systems. In the next few pages we shall introduce four numerical representation systems that are used in the digital system. There are other systems, which we will look at briefly.
Decimal +inary Octal &e%adecimal

De!im"# S stem The decimal system is composed of ,- numerals or symbols. These ,- symbols are - , . / 0 1 2 3 4 5. 6sing these symbols as digits of a number we can e%press any 'uantity. The decimal system is also called the base",- system because it has ,- digits. 103 7,--(ost Significant Digit 102 7,-101 7,100 7, 10$1 7-., 10$2 7-.-, 10$3 7-.--, 8east Significant Digit

. Decimal point

9ven though the decimal system has only ,- symbols any number of any magnitude can be e%pressed by using our system of positional weighting.

De!im"# E%"m&#es

/.,0,1.,,-.0,20---,-

'in"r S stem !n the binary system there are only two symbols or possible digit values - and ,. This base". system can be used to represent any 'uantity that can be represented in decimal or other base system. 23 74 (ost Significant Digit 22 70 21 7. 20 7, 2$1 7-.1 2$2 7-..1 2$3 7-.,.1 8east Significant Digit

. +inary point

'in"r Counting The +inary counting se'uence is shown in the table:

23 -

22 ,

21 , , -

20 , , -

De!im"# , . / 0

(NIT )*MEM+RY Semiconductor memories are classified in different ways. A distinction is made between read"only :;O(< and read"write :;=(< memories. The contents ;=(s can be changed in a short time for a virtually unlimited number of times and contents of ;O(s are mostly useful for fre'uent reading and occasional writing. Since ;=( memories use active circuitry :transistors< to store the information they belong to the class of called volatile memories. This is because the data would be lost when the supply voltage is turned off. ;ead"only memories on the other hand encode information by the presence or absence of devices. Their data cannot be modified and they belong to the class of nonvolatile memories. That means the stored data is lost by the disconnection of supply voltage. Table 1 : Classification Semiconductor Memories R,M R"n-om A!!ess Non R"n-om A!!ess S;A( D;A( $!$O Shift ;egister

N)R,M R+M 9>;O( 9.>;O( $8AS& (as#"programmed ;O( >rogrammable ;O(

St"ti! R"n-om A!!ess Memor .SRAM/ A single S;A( memory cell is shown in $ig. 1. Two N(OS and two >(OS transistors :(, to (0< forms the simple latch to store the data and two pass N(OS transistors :(1 and (2< are controlled by =ord 8ine to pass +it 8ine and into the cell.

A ,rite operation is performed by first charging the +it 8ine and with values that are desired to be stored in the memory cell. Setting the =ord 8ine high performs the actual write operation and the new data is latched into the circuit. A Re"- operation is initiated by pre"charging both +it 8ine and to logic ,.

=ord 8ine is set high to close N(OS pass transistors to put the contents stored in the cell on the +it 8ine and

Transistors (, to (0 constitute the latch and are constantly toggling bac# and forth. During these switching the power consumption in ?(OS circuits ta#es place and therefore the si)es of these transistors are #ept as small as possible. N(OS transistors are basically switches opening and closing access to the S;A( cell. To minimi)e the propagation delay caused by these transistors their si)es are #ept relatively larger.

D n"mi! R"n-om A!!ess Memor .DRAM/

D;A( stores each bit in a storage cell consisting of a capacitor and a transistor. ?apacitors tend to lose their charge rather 'uic#ly@ thus the need for recharging. The presence or absence of charge in the capacitor determines whether the cell contains a ',' or a '-'. The Re"- operation begins by precharging the bit line to an intermediate value . The word line is raised to a high potential and the charge stored on capacitor is shared with

that on the bit line. The change in the bit line voltage is given by the change on the bit line capacitor when the charge stored on capacitor ? is shared with the bit line. +ased on the access pattern ;=(s are classified as random access class and serial memories. $!$O :first"in"first"out< is an e%ample for serial memories. (ost memories belong to the random access class which means memory locations can be read or written in random order. One would e%pect memories of this class to be called ;A( :random access memory<@ nevertheless for historic reasons ;A( has been reserved for random access ;=( memories. That means though most ;O( units also provide random access but the acronym ;A( should not be used for them. )+LATILE MEM+RIES

Static ;andom Access (emory :S;A(< and Dynamic ;andom Access (emory :D;A(< are volatile memories. S;A( is used as a cache memory in computers since it offers the fastest writeAread :B4ns< speed among all memories. &ardware design of a single S;A( cell consists of 2 transistors. A D;A( cell consists of one transistor and one capacitor and it is based on the charge stored in a capacitor. !t is superior to S;A( because of its low cost per bit storage@ nevertheless it is slower :C1-ns<. !n D;A( the stored charge in the capacitor can be maintained only for few milli"seconds and therefore an e%tra hardware circuit is needed to periodically refresh the data periodically.

N+N$)+LATILE MEM+RIES +ased on the programmability of the devices non"volatile memories are categori)ed as follows. =riting data into ;O(s is possible only at the time of manufacturing the devices and used only for reading the data stored. 9ven though these devices are less in cost the constraint that they are to be programmed at the time of manufacturing is an inconvenience. >;O( devices are one time programmable ;O(. At the time of device manufacturing every cell is stored with D,D and can be programmed by customer once. +ut single write phase ma#es them unattractive. $or instance a single error in the programming process or application ma#es the device unusable. 9>;O( is 9rasable >;O(. (ultiple times programming feature is added in 9>;O(. !n this case first whole memory is to be erased by shining ultraviolet light. The erase process is slow and can ta#e from seconds to several minutes depending on the intensity of the 6E source. >rogramming ta#es several :1",-< Aword. 9>;O( cell is e%tremely simple and dense ma#ing it possible to fabricate large memories at a low cost. 9>;O(s were therefore attractive in applications that not re'uire fre'uent programming. 9lectrically"9rasable >;O( :99>;O(< can be erased without removing from board unli#e in 6E erasable where memory must be removed from the board. The voltage appro%imately applied for programming is ,4E. !n addition it is a reverse process@ means by applying high negative voltage at gate can erase the cell. Another advantage over 9>;O( is that 99>;O( can be programmed for ,-1 cycles.

Asynchronous se uential circuits! Do not use clock pulses. The change of internal state occurs when there is a change in the input variable. Their memory elements are either unclocked flip-flops or time-delay elements. They often resemble combinational circuits with feedback. Their synthesis is much more difficult than the synthesis of clocked synchronous sequential circuits. They are used when speed of operation is important. The communication of two units, with each unit having its own independent clock, must be done with asynchronous circuits.

(NIT I)*ASYNC0R+N+(S SE1(ENTIAL CIRC(IT

The next step is to plot the "1 and " functions in a map!

Asynchronous Sequential
"ombining the binary values in corresponding squares the following transition table is obtained!

Circuits

The analysis of asynchronous sequential circuits proceeds in much the same way as that of clocked synchronous sequential circuits. #rom a logic diagram, $oolean expressions are written and then transferred into tabular form. #.# Transition Table /

#. Analysis $rocedure

The analysis of the circuit starts by considering the excitation variables &'1 and " ( as outputs and the secondary variables &y1 and y ( as inputs. 0 The $oolean expressions are! "1 = xy1 + x y " = xy1 + x y

The transition table shows the value of " % "1" inside each square. Those entries where " % y are circled to indicate a stable condition.

The circuit has four stable total states ) y1y x % ***, *11, 11*, and 1*1 ) and four unstable total states ) **1, *1*, 111, and 1**. The state table of the circuit is shown below! +n order to obtain the circuit described by a flow table, it is necessary to assign to each state a distinct value. This assignment converts the flow table into a transition table. This is shown below! This table provides the same information as the transition table. #.% &low Table +n a flow table the states are named by letter symbols. ,xamples of flow tables are as follows! The resulting logic diagram is shown below! primitive flow table 1 2 #.' (ace )onditions - race condition exists in an asynchronous circuit when two or more binary state variables change value in response to a change in an input variable. .hen unequal delays are encountered, a race condition may cause the state variable to change in an unpredictable manner. +f the final stable state that the circuit reaches does not depend on the order in which the state variables change, the race is called a noncritical race. ,xamples of noncritical races are illustrated in the transition tables below! The transition tables below illustrate critical races! /aces can be avoided by directing the circuit through a uni ue sequence of intermediate unstable states. .hen a circuit does that, it is said to have a cycle. ,xamples of cycles are! 3 4

#.* +tability )onsiderations -n asynchronous sequential circuit may become unstable and oscillate between unstable states because of the presence of feedback. The instability condition can be detected from the transition table. "onsider the following circuit! %. )ircuits with +( ,atches The +( latch is used as a time-delay element in asynchronous sequential circuits. The 01/ gate +( latch and its truth table are! The excitation function is! " = & x1y ( x = & x1 + y (x = x1x + x y The feedback is more visible when the circuit is redrawn as! and the transition table for the circuit is! The $oolean function of the output is! " = 2&+ + y ( + ( 3 = &+ + y (( = +( + ( y Those values of " that are equal to y are circled and represent stable states. .hen the input x1x is 11, the state variable alternates between * and 1 indefinitely. 5 and the transition table for the circuit is! ,The 0-0D gate +( latch and its truth table are! The behaviour of the +( latch can be investigated from the transition table. The condition to be avoided is that both 4 and / inputs must not be 1 simultaneously. This condition is avoided when +( % * &i.e., -0Ding of + and ( must always result in *(. .hen +( % * holds at all times, the excitation function derived previously! " = +( + ( y The transition table for the circuit is! can be expressed as! "=++( y The condition to be avoided here is that both + and ( not be * simultaneously which is satisfied when +-(- % *. The excitation function for the circuit is! ,, " = 2+&(y ( 3 = + + (y ,.

%.# Analysis Example "onsider the following circuit! The next step is to derive the transition table of the circuit. The excitation functions are derived from the relation " % + 5 (-y as! "1 = +1 + (1y1 = x1y + & x1 + x (y1 = x1y + x1y1 + x y1 " =+ +( y = x1x + & x + y1 (y = x1x + x y 0ext a composite map for " % "1" is developed! The first step is to obtain the $oolean functions for the + and ( inputs in each latch! +1 = x1y (1 = x1x + = x1x ( =x y1 The next step is to check if +( % * is satisfied! +1(1 = x1y x1x = * + ( = x1x x y1 = * +nvestigation of the transition table reveals that the circuit is stable. There is a critical race condition when the circuit is initially in total state y1y x1x % 11*1 and x changes from 1 to *. +f "1 changes to * before " , the circuit goes to total state *1** instead of ****. ,/ ,0 The result is * because x1x-1 % x x- % * %.% +( ,atch Excitation Table 6ists the required inputs + and ( for each of the possible transitions from the secondary variable y to the excitation variable ". . represents a don/t care condition. The maps are then used to derive the simplified $oolean functions! 7seful for obtaining the $oolean functions for + and ( and the circuit8s logic diagram from a given transition table. %.' Implementation Example "onsider the following transition table! + = x1x ( = x1 The logic diagram consists of an +( latch and gates required to implement the + and ( $oolean functions. The circuit when a 01/ +( latch is used is as shown below! " = x1x + x1y #rom the information given in the transition table and the +( latch excitation table, we can obtain maps for the + and ( inputs of the latch! ,1 .ith a 0-0D +( latch the complemented values for + and ( must be used. ,2

+ y1y

'. 0esign $rocedure There are a number of steps that must be carried out in order to minimi9e the circuit complexity and to produce a stable circuit without critical races. $riefly, the design steps are as follows! 1. . :. 1btain a primitive flow table from the given specification. /educe the flow table by merging rows in the primitive flow table. -ssign binary states variables to each row of the reduced flow table to obtain the transition table. -ssign output values to the dashes associated with the unstable states to obtain the output maps. 4implify the $oolean functions of the excitation and output variables and draw the logic diagram. '.# 0esign Example 1 +pecification Design a gated latch circuit with two inputs, 2 &gate( and 0 &data(, and one output 3. The gated latch is a memory element that accepts the value of 0 when 2 % 1 and retains this value after 2 goes to *. 1nce 2 % *, a change in 0 does not change the value of the output 3. +tep #! $rimitive &low Table - primitive flow table is a flow table with only one stable total state in each row. The total state consists of the internal state combined with the input. To derive the primitive flow table, first a table with all possible total states in the system is needed! ;. <. The design process will be demonstrated by going through a specific example! ,ach row in the above table specifies a total state. ,3 ,4 The resulting primitive table for the gated latch is shown below! +tep %! (eduction of the $rimitive &low Table The primitive flow table can be reduced to a smaller number of rows if two or more stable states are placed in the same row of the flow table. The simplified merging rules are as follows! 1. Two or more rows in the primitive flow table can be merged into one if there are nonconflicting states and outputs in each of the columns. .henever, one state symbol and don/t care entries are encountered in the same column, the state is listed in the merged row. +f the state is circled in one of the rows, it is also circled in the merged row. The output state is included with each stable state in the merged row. . #irst, we fill in one square in each row belonging to the stable state in that row. 0ext recalling that both inputs are not allowed to change at the same time, we enter dash marks in each row that differs in two or more variables from the input variables associated with the stable state. 0ext we find values for two more squares in each row. The comments listed in the previous table may help in deriving the necessary information. - dash indicates don8t care conditions. ,5 :. ;.

0ow apply these rules to the primitive flow table shown previously. To see how this is done the primitive flow table is separated into two parts of three rows each! .-

The circuit has four stable total states ) y1y x % ***, *11, 11*, and 1*1 ) and four unstable total states ) **1, *1*, 111, and 1**.

primitive flow table +n order to obtain the circuit described by a flow table, it is necessary to assign to each state a distinct value. This assignment converts the flow table into a transition table. This is shown below!

The state table of the circuit is shown below!

This table provides the same information as the transition table. The resulting logic diagram is shown below! #.% &low Table +n a flow table the states are named by letter symbols. ,xamples of flow tables are as follows!