DDR3 204-Pin Unbuffered SO-DIMM Design Spec

JEDEC Standard No. 21C Page 4.20.
18-1
4.20.18 - 204-Pin DDR3 SDRAM Unbuffered SO-DIMM Design Specification
PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 Unbuffered SO-DIMM Reference Design Specification Revision 1.0 February 2009
Release 18A
Revision 1.0
JEDEC Standard No. 21C Page 4.20.18-2
Contents
Product Description ................................................................................................................................... 4 Product Family Attributes ....................................................................................................................... 4 Raw Cards Summary ............................................................................................................................. 4 Environmental Requirements.................................................................................................................... 6 Absolute Maximum Ratings ................................................................................................................... 6 Architecture................................................................................................................................................. 6 Pin Description ....................................................................................................................................... 6 Input/Output Functional Description....................................................................................................... 8 DDR3 SDRAM SO-DIMM Pinout. .......................................................................................................... 9 Block Diagram: Raw Card Version A(Populated as 2ranks of x16 SDRAMs) ..................................... 10 Block Diagram: Raw Card Version B(Populated as 1rank of x8 SDRAMs) ......................................... 11 Block Diagram: Raw Card Version C(Populated as 1rank of x16 SDRAMs) ....................................... 12 Block Diagram: Raw Card Version D(Populated as 2ranks of x8 stacked SDRAMs) .......................... 13 Block Diagram: Raw Card Version F(Populated as 2ranks of x8 SDRAMs)........................................ 15 Component Details ................................................................................................................................... 16 SO-DIMM landing pattern for x8 .......................................................................................................... 16 SO-DIMM landing pattern for x16 ........................................................................................................ 17 x8 Ball-pattern for 512Mb, 1Gb, 2Gb and 4Gb DDR3 SDRAMs (Top View) ....................................... 18 x16 Ball-pattern for 512Mb, 1Gb, 2Gb and 4Gb DDR3 SDRAMs (Top View) ..................................... 19 DDR3 SDRAM FBGA Component Specifications ................................................................................ 19 Reference SPD and Temp Sensor Component Specifications ............................................................ 19 Unbuffered SO-DIMM Details................................................................................................................... 20 DDR3 SDRAM Module Configurations (Reference Designs) .............................................................. 20 Input Loading Matrix............................................................................................................................. 20 DDR3 SO-DIMM Gerber File Releases ............................................................................................... 22 Example Raw Card Component Placement Raw Cards A, B, C, D ..................................................... 23 Example Raw Card Component Placement Raw Cards E(design on hold) , F ................................... 24 SO-DIMM Wiring Details........................................................................................................................... 25 Signal Groups ...................................................................................................................................... 25 General Net Structure Routing Guidelines........................................................................................... 25 Explanation of Net Structure Diagrams ................................................................................................ 25 Clock Control and Address/Command Groups .................................................................................... 25 Module Length Matching Rules............................................................................................................ 25 Lead-in vs Loaded Sections................................................................................................................. 26 Length/Delay Matching to SDRAM Devices......................................................................................... 26 Velocity Compensation ........................................................................................................................ 27 Data and Strobe Group ........................................................................................................................ 27 DQ/DQS Matching ............................................................................................................................... 27 Via Compensation................................................................................................................................ 27
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Decoupling Capacitor Guideline........................................................................................................... 28 Differential Clock Net Structures .......................................................................................................... 29 Clock Net Wiring CK[1:0], CK[1:0] (Raw Cards A , C) ......................................................................... 29 Clock Net Wiring CK[0], CK[0] (Raw Card B)....................................................................................... 30 Clock Net Wiring CK[1:0], CK[1:0] (Raw Card D) ................................................................................ 31 Clock Net Wiring CK[1:0], CK[1:0] (Raw Card F)................................................................................. 33 Control Net Structures S [1:0], CKE[1:0], ODT[1:0] (Raw cards A , C)................................................ 35 Control Net Structures S [0], CKE[0], ODT[0] (Raw card B) ................................................................ 35 Control Net Structures S [0], CKE[0], ODT[0] (Raw card D). ............................................................... 36 Control Net Structures S [1:0], CKE[1:0], ODT[1:0] (Raw card F) ....................................................... 38 Address/Command Net Structures Ax, BAx, RAS, CAS, WE (Raw cards A , B)................................. 40 Address/Command Net Structures Ax, BAx, RAS, CAS, WE (Raw card C)........................................ 41 Address/Command Net Structures Ax, BAx, RAS, CAS, WE (Raw card D)........................................ 42 Address/Command Net Structures Ax, BAx, RAS, CAS, WE (Raw card F) ........................................ 45 Data Net Structures.............................................................................................................................. 47 Net Structure Routing for DQ[63:0], DM[7:0], DQS[7:0], DQS[7:0] (Raw card A, F)............................ 47 Data Net Structures DQ[63:0], DM[7:0], DQS[7:0], DQS[7:0] (Raw cards B, C).................................. 49 Data Net Structures DQ[63:0], DM[7:0], DQS[7:0], DQS[7:0] (Raw cards D) ...................................... 51 Cross Section Recommendations........................................................................................................ 52 Example 6 layers stack-up for Raw Card A, C..................................................................................... 52 Example 8 layers stackup for Raw Card B, D, F.................................................................................. 53 Test Points ................................................................................................................................................ 55 Raw Card A Test Points....................................................................................................................... 55 Raw Card B Test Points....................................................................................................................... 56 Raw Card C Test Points....................................................................................................................... 57 Raw Card D Test Points....................................................................................................................... 58 Raw Card F Test Points ....................................................................................................................... 59 Serial Presence Detect Definition ........................................................................................................... 60 Serial Presence Detect Data Example................................................................................................. 61 Product Label............................................................................................................................................ 63 SO-DIMM Mechanical Specifications...................................................................................................... 65 Application Note ....................................................................................................................................... 66 Max Cin for the stacked DRAM on R/C D x8 2ranks module............................................................... 66
Release 18A
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1. Product Description
This reference specification defines the electrical and mechanical requirements for the PC3-12800 memory module, a 204-pin, 800MHz clock (1600 MT/s data rate), 64-bit wide, Unbuffered Synchronous Double Data Rate 3(DDR3) DRAM Small outline Dual In-Line Memory Module (DDR3 SDRAM SO-DIMMs). It also defines a slower version, the PC3-10600, using 667MHz clock (1333 MT/s data rate) DDR3 SDRAMs, the PC3-8500, using 533MHz clock (1066 MT/s data rate) DDR3 SDRAMs, the PC3-6400, using 400MHz clock (800 MT/s data rate) DDR3 SDRAMs. These DDR3 SDRAM SO-DIMMs are intended for use as main memory when installed in systems such as mobile personal computers. Note: R/C D(2ranks x8 stacked DRAM) is defined only for PC3-6400 & PC3-8500. Reference design examples are included which provide an initial basis for Unbuffered SO-DIMM designs. Any modifications to these reference designs must meet all system timing, signal integrity and thermal requirements for 800MHz clock rate support. Other designs are acceptable, and all Unbuffered DDR3 SO-DIMM implementations must use simulations and lab verification to ensure proper timing requirements and signal integrity in the system.
Product Family Attributes

Attribute: SO-DIMM Organization Dimensions (nominal) SO-DIMM Types Supported Pin Count DDR3 SDRAMs Supported Capacity Serial Presence Detect Values: x 64 30.0 mm high, 67.6 mm wide / MO-268 variation CA Unbuffered 204 512Mb, 1Gb, 2Gb, 4Gb 256MB, 512MB, 1GB, 2GB, 4GB, 8GB Consistent with JEDEC latest revision 1.5 V VDD 1.5 V VDDQ 3.0V - 3.6V VDDSPD SSTL_15 Notes:
Voltage Options, Nominal
Interface
Note 1: VDDSPD can not be tied to VDD or VDDQ on the DDR3 SO-DIMM.
Raw Cards Summary

Raw Card A B C D Number of DDR3 SDRAMs 8 8 4 16 SDRAM Organization x16 x8 x16 x8 Stacked Number of Ranks 2 1 1 2 Comments Max DRAM W x L = 12.3 x 20.0 Max DRAM W x L = 12.3 x 20.0 Max DRAM W x L = 12.3 x 20.0 Max DRAM W x L = 12.3 x 20.0 PC3-6400, 8500 Only
Revision 1.0
Release 18A
16
x8
Reserved for planar with square DRAM(Design on Hold) Planar with rectangle DRAM, Max DRAM W x L = 10.5 x 14.4
16
x8
Release 18A
Revision 1.0
2. Environmental Requirements
DDR3 SDRAM Unbuffered SO-DIMMs are intended for use in mobile computing environments that have limited capacity for heat dissipation.
Absolute Maximum Ratings

Symbol TOPR TSTG Parameter Operating Temperature (ambient) Storage Temperature Rating 0 to 65 -50 to 100 Units C C Notes 1 1
1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3. Architecture
Pin Description
CK[1:0] CK[1:0] CKE[1:0] RAS CAS WE S[1:0] Clock Inputs, positive line Clock inputs, negative line Clock Enables Row Address Strobe Column Address Strobe Write Enable Chip Selects 2 2 2 1 1 1 2 14 1 1 3 2 1 1 2 VREFDQ, VREFCA VDDSPD Vtt NC Input/Output Reference SPD and Temp sensor Power Termination voltage Reserved for future use 2 1 2 2 Total: 204 DQ[63:0] DM[7:0] DQS[7:0] DQS[7:0] RESET TEST EVENT VDD VSS Data Input/Output Data Masks Data strobes Data strobes complement Reset Pin 64 8 8 8 1
Logic Analyzer specific test pin (No connect on SO1 DIMM) Temperature event pin Core and I/O Power Ground 1 18 52
A[9:0],A11,A[15:13] Address Inputs A10/AP A12/BC BA[2:0] ODT[1:0] SCL SDA SA[1:0] Address Input/Autoprecharge Address Input/Burst chop SDRAM Bank Address On-die termination control Serial Presence Detect (SPD) and Thermal sensor(TS) Clock Input SPD and TS Data Input/Output SPD and TS address
Revision 1.0
Release 18A
Input/Output Functional Description

Symbol CK0/CK0, CK1/CK1 CKE[1:0] Type Input Polarity Cross point Function The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock.
Input
Active High Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR3 SDRAM command decoder when low and disables the comActive Low mand decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1. Active Low When sampled at the cross point of the rising edge of CK and falling edge of CK, signals CAS, RAS, and WE define the operation to be executed by the SDRAM. Active High Selects which DDR3 SDRAM internal bank of eight is activated. Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3 SDRAM mode register. During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. A12(BC) is sampled during READ and WRITE commands to determine if burst chop (on-thefly) will be performed (HIGH, no burst chop; LOW, burst chopped) Data Input/Output pins.
S[1:0] RAS, CAS, WE BA[2:0] ODT[1:0]
Input
Input Input Input
A[9:0], A10/AP, A11 A12/BC, A[15:13]
Input
DQ[63:0] DM[7:0]
In/Out Input
The data write masks, associated with one data byte. In Write mode, DM operates as a byte Active High mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR3 SDRAMs and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module. Reference voltage for SSTL15 inputs. This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and Temp sensor. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up. This pin is used to clock data into and out of the SPD EEPROM and Temp sensor. A resistor must be connected from the SCL bus line to VDDSPD on the system planar to act as a pull up Address pins used to select the Serial Presence Detect and Temp sensor base address. The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules (SO-DIMMs).
DQS[7:0], DQS[7:0]
In/Out
Cross point
VDD, VDDSPD, VSS VREFDQ, VREFCA SDA
Supply
Supply
In/Out
SCL SA[1:0] TEST
Input Input In/Out
Release 18A
Revision 1.0
Input/Output Functional Description

Symbol EVENT RESET Type WireOR Out In Polarity Active Low Function This pin is an output of the Thermal Sensor to indicate critical module temperature. A resistor must be connected from EVENT bus line to VDDSPD on the system planar to act as a pullup.
Active Low This signal resets the DDR3 SDRAM
Revision 1.0
Release 18A
DDR3 SDRAM SO-DIMM Pinout.

Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 Front Side VREFDQ Vss DQ0 DQ1 Vss DM0 Vss DQ2 DQ3 Vss DQ8 DQ9 Vss DQS1 DQS1 Vss DQ10 DQ11 Vss DQ16 DQ17 Vss DQS2 DQS2 Vss DQ18 Pin # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 Back Side Vss DQ4 DQ5 Vss DQS0 DQS0 Vss DQ6 DQ7 Vss DQ12 DQ13 Vss DM1 RESET Vss DQ14 DQ15 Vss DQ20 DQ21 Vss DM2 Vss DQ22 DQ23 Pin # 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 Front Side DQ19 Vss DQ24 DQ25 Vss DM3 Vss DQ26 DQ27 Vss CKE0 VDD NC BA2 VDD A12/BC A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0 Pin # 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 Back Side Vss DQ28 DQ29 Vss DQS3 DQS3 Vss DQ30 DQ31 Vss CKE1 VDD
A15
3
Pin # 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155
Front Side VDD A10/AP BA0 VDD WE CAS VDD A133 S1 VDD TEST Vss DQ32 DQ33 Vss DQS4 DQS4 Vss DQ34 DQ35 Vss DQ40 DQ41 Vss DM5 Vss
Pin # 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156
Back Side VDD BA1 RAS VDD S0 ODT0 VDD ODT1 NC VDD VREFCA Vss DQ36 DQ37 Vss DM4 Vss DQ38 DQ39 Vss DQ44 DQ45 Vss DQS5 DQS5 Vss
Pin # 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203
Front Side DQ42 DQ43 Vss DQ48 DQ49 Vss DQS6 DQS6 Vss DQ50 DQ51 Vss DQ56 DQ57 Vss DM7 Vss DQ58 DQ59 Vss SA0 VDDSPD SA1 Vtt
Pin # 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
Back Side DQ46 DQ47 Vss DQ52 DQ53 Vss DM6 Vss DQ54 DQ55 Vss DQ60 DQ61 Vss DQS7 DQS7 Vss DQ62 DQ63 Vss EVENT SDA SCL Vtt
A143 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1
1. NC = No Connect, NU = Not Useable, RFU = Reserved Future Use 2. TEST(pin 125) is reserved for bus analysis probes and is NC on normal memory modules. 3. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor.
Release 18A
Revision 1.0
Block Diagram: Raw Card Version A(Populated as 2ranks of x16 SDRAMs)

S0 RAS CAS WE CK0 CK0 CKE0 ODT0 A[0: N]/BA[0:N]
CK1 CK1 CKE1 ODT1
SCL SA0 SA1
SCL A0 Temp Sensor A1 (with SPD) A2 EVENT EVENT
S1
SDA The SPD may be integrated with the Temp Sensor or may be a separate component. SDA
CS RAS CAS WE CK CK CKE ODT A[0: N]/BA[0:N]
DQS0 DQS0 DM0 DQ [0:7] DQS1 DQS1 DM1 DQ [8: :15]
LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15 ]
240ohm +/-1% ZQ
D0
240ohm +/-1% ZQ
D4
SCL SA0 SA1
SCL A0 A1 A2
(SPD) WP
Vtt VDDSPD VREFCA VREFDQ
Vtt SPD / TS D0-D7 D0-D7 D0-D7 D0-D7, SPD, Temp sensor D0-D3 D4-D7 D0-D3 D4-D7 Temp Sensor D0-D7
DQS2 DQS2 DM2 DQ [16:23] DQS3 DQS3 DM3 DQ [24:31]
240ohm +/-1% ZQ
D1
240ohm +/-1% ZQ
VDD VSS CK0 CK1 CK0 CK1 EVENT RESET
D5
240ohm +/-1% ZQ
D2
LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15]
D6
240ohm +/-1% ZQ
D3
240ohm +/-1% ZQ
D7
Add ress and Control lines NOT ES 1. DQ wiring may differ from t hat shown however ,DQ,DM, D ,QS and DQS relations hips are maint aine d as shown
Rank 0 Rank 1
Vtt Vtt VDD VDD Vtt
Revision 1.0
Vtt
V1
D0
V2
D1
V3
D2
V4
D3
Vtt
240ohm +/-1% ZQ
V1
D4
V2
D5
V3
D6
V4
D7
Release 18A
Block Diagram: Raw Card Version B(Populated as 1rank of x8 SDRAMs)

S0 RAS CAS WE CK0 CK0 CKE0 ODT0 A[0: N]\BA [0:N]
DQS0 DQS0 DM0 DQ [0:7]
DQS DQS DM DQ [0:7]
240ohm +/-1% ZQ
CS RAS CAS WE CK CK CKE ODT A[0: N]\BA [0:N]
D0
DQS1 DQS1 DM1 DQ [8: 15]
DQS DQS DM DQ [0:7]
240ohm +/-1% ZQ
SCL SA0 SA1
SCL A0 Temp Sensor A1 (with SPD) A2 EVENT EVENT
SDA
D4
SCL SA0 SA1 SCL A0 A1 A2
The SPD may be integrated with the Temp Sensor or may be a separate component.
SDA
(SPD) WP
DQS DQS DM DQ [0:7]
240ohm +/-1% ZQ
D1
DQS DQS DM DQ [0:7]
240ohm +/-1% ZQ
Vtt VDDSPD VREFCA VREFDQ VDD VSS CK0 CK0 CK1 CK1 S1 ODT1 CKE1 EVENT RESET
Vtt SPD / TS D0-D7 D0-D7 D0-D7 D0-D7, SPD, Temp sensor D0-D7 D0-D7 Terminated near card edge NC NC NC Temp Sensor D0-D7
D5
DQS4 DQS4 DM4 DQ [32::39]
DQS DQS DM DQ [0:7]
240ohm +/-1% ZQ
D2
DQS DQS DM DQ [0:7]
240ohm +/-1% ZQ
D6
DQS DQS DM DQ [0:7]
240ohm +/-1% ZQ
D3
DQS DQS DM DQ [0:7]
240ohm +/-1% ZQ
D7
Address and Control lines NOT ES 1. DQ wiring may differ from that shown however ,DQ, DM, DQS, and DQS relationships are maintained as shown
Rank 0
Vtt Vtt
VDD
Release 18A
Revision 1.0
Vtt
V1
D0
V2
D1
V3
D2
V4
D3
Vtt
V1
D4
V2
D5
V3
D6
V4
D7
Block Diagram: Raw Card Version C(Populated as 1rank of x16 SDRAMs)

S0 RAS CAS WE CK0 CK0 CKE0 ODT0 A[0: N]/BA[0:N]
DQS0 DQS0 DM0 DQ [0:7] DQS1 DQS1 DM1 :15] DQ [8:
240ohm +/-1% ZQ
SCL SA0 SA1
SCL Temp Sensor A0 (with SPD) A1 A2 EVENT EVENT
SDA
D0
SCL SA0 SA1
SCL A0 A1 A2
(SPD) WP
SDA
Vtt DQS2 DQS2 DM2 DQ [16::23] DQS3 DQS3 DM3 DQ [24::31] LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15 ]
240ohm +/-1% ZQ
Vtt SPD / TS D0-D3 D0-D3 D0-D3 D0-D3, SPD, Temp sensor D0-D3 D0-D3
Terminated at near card edge
VDDSPD VREFCA VREFDQ VDD VSS CK0 CK0 CK1 CK1 ODT 1 S1 CKE1 EVENT RESET
D1
NC NC NC Temp Sensor D0-D3
DQS4 DQS4 DM4 DQ [32::39] DQS5 DQS5 DM5 DQ [40::47]
240ohm +/-1% ZQ
D2
DQS6 DQS6 DM6 DQ [48::55] DQS7 DQS7 DM7 DQ [56::63]
240ohm +/-1% ZQ
Address an d Control lines
D3
NOT ES 1. DQ wiring may differ from that shown however ,DQ, DM, DQS, and DQS relationships are maintained as shown
Rank 0
Vtt Vtt
VDD
Revision 1.0
Vtt
D0
D1
D2
D3
Release 18A
Block Diagram: Raw Card Version D(Populated as 2ranks of x8 stacked SDRAMs)

S0/S1 RAS CAS WE CK0 CK0 CKE0/CKE1 ODT0/ODT1 A[0: N]/BA[0:N]
CK1 CK1 SCL SA0 SA1 SCL A0 Temp Sensor A1 (with SPD) A2 EVENT EVENT SCL SA0 SA1 SCL A0 A1 A2 (SPD) WP
SDA
DQS DQS DM DQ [0:7]
240ohm +/-1% x2 ZQ
CS0/CS1 RAS CAS WE CK CK CKE0/CKE1 ODT0/ODT1 A[0: N]/BA[0:N]
D0,D8 (Stacked)
DQS DQS DM DQ [0:7]
240ohm +/-1% x2 ZQ
D4,D12 (Stacked)
SDA
Vtt VDDSPD VREFCA VREFDQ VDD VSS CK0 CK1 CK0 CK1 CKE0 CKE1 S0 S1 ODT0 ODT1 EVENT
Vtt SPD / TS D0-D15 D0-D15 D0-D15 D0-D15, SPD, TS D0-D3, D8-D11 D4-D7, D12-D15 D0-D3. D8-D11 D4-D7. D0-D7 D8-D15 D0-D7 D8-D15 D0-D7 D8-D15 Temp Sensor D0-D15 D12-D15
DQS DQS DM DQ [0:7]
240ohm +/-1% x2 ZQ
DQS DQS DM DQ [0:7]
240ohm +/-1% x2 ZQ
D1,D9 (Stacked)
DQS DQS DM DQ [0:7]
240ohm +/-1% x2 ZQ
D5,D13 (Stacked)
DQS6 DQS6 DM6 DQ[48:55]
DQS DQS DM DQ [0:7]
240ohm +/-1% x2 ZQ
D3,D11 (Stacked)
DQS DQS DM DQ [0:7]
240ohm +/-1% x2 ZQ
D7,D15 (Stacked)
Address and Control lines NOT ES 1. DQ wiring may differ from that shown however ,DQ, DM, DQS, and DQS relationships are maintained as shown
Rank 0
Vtt Vtt VDD VDD
Rank 1
Release 18A
Revision 1.0
Vtt
V1 D0,D8
V2 D1,D9
V3 D2,D10 V4 D3,D11
Vtt
D2,D10 (Stacked)
DQS5 DQS5 DM5 DQ[40:47]
DQS DQS DM DQ [0:7]
240ohm +/-1% x2 ZQ
RESET
D6,D14 (Stacked)
V1 D4,D12 V2 D5,D13 V3 D6,D14 V4 D7,D15
Block Diagram: Raw Card Version E(on Hold)
Raw Card E( x8 2R planar with square DRAM) design is on hold
Revision 1.0
Release 18A
Block Diagram: Raw Card Version F(Populated as 2ranks of x8 SDRAMs)

VDD Cterm S1 RAS CAS WE CK1 CK1 CKE1 ODT1 A[0: N]/BA[0:N] Cterm VDD Vtt CK0 CK0 CKE0 ODT0 S0 Vtt Vtt
DQS DQS DM DQ [0:7]
240ohm +/-1% ZQ
DQS1 DQS1 DM1 DQ [8: 15]
DQS DQS DM DQ [0:7]
240ohm +/-1% ZQ
DQS0 DQS0 DM0 DQ [0 : 7]
DQS DQS DM DQ [0:7]
240ohm +/-1% ZQ
DQS DQS DM DQ [0:7]
240ohm +/-1% ZQ
SCL SA0 SA1
Vtt SCL A0 A1 A2 VDDSPD VREFCA D6

V7 V4
(SPD ) WP
SDA
D9
V3
V2
D3
V1 V9
D12
V8
VREFDQ VDD VSS CK0 CK1 CK0 CK1
SCL SA0 SA1
SCL Temp Sensor A0 A1 (with SPD) A2 EVENT EVENT
D8 SDA D0
V3
D10
V5
D5
V6
D7
V4
D2
V5
D13
V6
D15
V7
CKE0 CKE1 S0 S1 ODT0 ODT 1 EVENT RESET
NOT ES 1. DQ wiring may differ from that shown however ,DQ, DM, DQS, and DQS relationships are maintained as shown
Vtt
V2
D1
D11
V1
V9
D4
V8
D14
Rank 0 Rank 1
Release 18A
D2
DQS DQS DM DQ [0:7]
240ohm +/-1% ZQ
D10
DQS DQS DM DQ [0:7]
240ohm +/-1% ZQ
D13
DQS DQS DM DQ [0:7]
D0
DQS DQS DM DQ [0:7]
240ohm +/-1% ZQ
D8
DQS DQS DM DQ [0:7]
240ohm +/-1% ZQ
D15
DQS DQS DM DQ [0:7]
D1
DQS DQS DM DQ [0:7]
240ohm +/-1% ZQ
D9
DQS DQS DM DQ [0:7]
240ohm +/-1% ZQ
D11
DQS DQS DM DQ [0:7]
240ohm +/-1% ZQ
D3
DQS DQS DM DQ [0:7]
240ohm +/-1% ZQ
D4
DQS DQS DM DQ [0:7]
240ohm +/-1% ZQ
D12
D14
DQS DQS DM DQ [0:7]
240ohm +/-1% ZQ
D6
240ohm +/-1% ZQ
D7
240ohm +/-1% ZQ
D5
Vtt SPD / TS D0-D15 D0-D15 D0-D15 D0-D15, SPD, Temp sensor D0-D7 D8-D15 D0-D7 D8-D15 D0-D7 D8-D15 D0-D7 D8-D15 D0-D7 D8-D15 Temp sensor D0-D15
Revision 1.0
4. Component Details
SO-DIMM landing pattern for x8
-
x8 MAX Dimensions and Support Ball Location
17.6 mm 9.6 mm
6.4 mm 8.0 mm 12.3 mm Active Signal Pitch 0.8mm x 0.8mm

Reference: MO-207 DW-Z
Support Ball (NCto the die)

pads are not necessary where package does not extend to.
Unpopulated Note : The max package size for Raw card F is smaller. For smaller package, support ball
Revision 1.0
20.0 mm
Release 18A
SO-DIMM landing pattern for x16
x16 MAX Dimensions and Support Ball Location
16.8 mm 12.0 mm
6.4 mm 8.0 mm 12.3 mm Active Signal Pitch 0.8mm x 0.8mm

Reference: MO-207 DY-Z
Support Ball (NCto the die) Unpopulated
Release 18A
20.0 mm
Revision 1.0
x8 Ball-pattern for 512Mb, 1Gb, 2Gb and 4Gb DDR3 SDRAMs (Top View)
1 VSS VSS VDDQ VSSQ VREFDQ ODT1
2
2 VDD VSSQ DQ2 DQ6 VDDQ VSS VDD CS0# BA0 A3 A5 A7 RESET#
3 NC DQ0 DQS DQS# DQ4 RAS# CAS# WE# BA2 A0 A2 A9 A13
7 NU/TDQS# DM/TDQS DQ1 VDD DQ7 CK CK# A10/AP A15 A12/BC# A1 A11 A14
8 VSS VSSQ DQ3 VSS DQ5 VSS VDD ZQ0 VREFCA BA1 A4 A6 A8
9 VDD VDDQ VSSQ VSSQ VDDQ CKE12 CKE0 ZQ12 VSS VDD VSS VDD VSS
A B C D E F G H J K L M N
ODT0 CS1# VSS VDD VSS VDD VSS

2
1. This Ball-pattern uses MO-207 DT-Z ball number. 2. The above pattern also applies for stacked components. CS1#, ODT1, CKE1 and ZQ1 are only used in a stacked package. For planar components, CS0#, ODT0, CKE0 and ZQ0 should be read as CS#, ODT, CKE and ZQ.
Revision 1.0
Release 18A
x16 Ball-pattern for 512Mb, 1Gb, 2Gb and 4Gb DDR3 SDRAMs (Top View)
1 VDDQ VSSQ VDDQ VSSQ VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 2 DQU5 VDD DQU3 VDDQ VSSQ DQL2 DQL6 VDDQ VSS VDD CS# BA0 A3 A5 A7 RESET# 3 DQU7 VSS DQU1 DMU DQL0 DQSL DQSL# DQL4 RAS# CAS# WE# BA2 A0 A2 A9 A13
.
7 DQU4 DQSU# DQSU DQU0 DML DQL1 VDD DQL7 CK CK# A10/AP A15 A12 A1 A11 A14
8 VDDQ DQU6 DQU2 VSSQ VSSQ DQL3 VSS DQL5 VSS VDD ZQ VREFCA BA1 A4 A6 A8
9 VSS VSSQ VDDQ VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS
A B C D E F G H J K L M N P R T
1. This ball-pattern uses MO-207 DU-Z ball number
DDR3 SDRAM FBGA Component Specifications

The DDR3 SDRAM components used with this DIMM design specification are intended to be consistent with JEDEC MO-207 DT-Z(x8, no support ball)and DW-Z(x8, with support ball), DU-Z(x16, no support ball)and DY-Z(x16, with support ball). The DDR3 SO-DIMM is designed for a variety of maximum component widths and maximum lengths, refer to the applicable raw card for exact componet size allowed. Components used on DDR3 SO-DIMMs are also limited to a maximum height (as shown in dimension "A" of MO-207) of 1.35 mm.
Reference SPD and Temp Sensor Component Specifications

The Serial Presence Detect EEPROMs and Temp sensor have their own power pin, VDDSPD, so that they can be programmed or read without powering up the rest of the module. The voltage range permits use with 3.3V serial buses.The Temp Sensor has the common SMBus signals and power/Vss pins with SPD. It must support the overvoltage(Max 10V) tolerance on the A0 pin.
DC Electrical Characteristics
Symbol VDDSPD Core Supply Voltage Parameter Min 3.0 Typ 3.3 Max 3.6 Units V
Release 18A
Revision 1.0
5. Unbuffered SO-DIMM Details DDR3 SDRAM Module Configurations (Reference Designs)

Raw Card A A A A SO-DIMM SO-DIMM Capacity Organization 512 MB 1 GB 2 GB 4 GB 64 M x 64 128 M x 64 256 M x 64 512 M x 64 SDRAM Density 512 Mbit 1 Gbit 2 Gbit 4 Gbit SDRAM # of Organization SDRAMs 32 M x 16 64 M x 16 128 M x 16 256 M x 16 8 8 8 8 # of Ranks 2 2 2 2 SDRAM Package Type FBGA FBGA FBGA FBGA # of banks in SDRAM 8 8 8 8 # Address bits row/col 12/10 13/10 14/10 15/10
Raw Card B B B B
SO-DIMM SO-DIMM Capacity Organization 512 MB 1 GB 2 GB 4 GB 64 M x 64 128 M x 64 256 M x 64 512 M x 64
SDRAM Density 512 Mbit 1 Gbit 2 Gbit 4 Gbit
SDRAM # of # of Organization SDRAMs Ranks 64 M x 8 128 M x 8 256 M x 8 512 M x 8 8 8 8 8 1 1 1 1
SDRAM Package Type FBGA FBGA FBGA FBGA
# of banks in SDRAM 8 8 8 8
# Address bits row/col 13/10 14/10 15/10 16/10
Raw Card C C C C
SO-DIMM SO-DIMM Capacity Organization 256 MB 512 MB 1 GB 2 GB 32 M x 64 64 M x 64 128 M x 64 256 M x 64
Raw Card D D D D
SO-DIMM SO-DIMM Capacity Organization 1 GB 2 GB 4 GB 8 GB 128 M x 64 256 M x 64 512 M x 64 1024 M x 64
1. Raw Card D uses stacked SDRAMs.
Raw Card F F
SO-DIMM SO-DIMM Capacity Organization 1 GB 2 GB 128 M x 64 256 M x 64
SDRAM Density 512 Mbit 1 Gbit
SDRAM # of # of Organization SDRAMs Ranks 64 M x 8 128 M x 8 16 16 2 2
SDRAM Package Type FBGA FBGA
# of banks in SDRAM 8 8
# Address bits row/col 13/10 14/10
Revision 1.0
Release 18A
Raw Card F
SO-DIMM SO-DIMM Capacity Organization 4GB 512M x 64
SDRAM Density 2 Gbit
SDRAM # of # of Organization SDRAMs Ranks 256 M x 8 16 2
SDRAM Package Type FBGA
# of banks in SDRAM 8
# Address bits row/col 15/10
1. Raw Card F is a planar solution.
Input Loading Matrix

Signal Names Clock (CK0, CK0 - CK1, CK1) CKE0/CKE1/S0/S1/ODT0/ODT1 Addr/RAS/CAS/BA/WE DQ/DQS/DQS/DM RESET SCL/SDA/SA Input Device SDRAM SDRAM SDRAM SDRAM SDRAM EEPROM/TS R/C A 4 4 8 2 8 1/2 R/C B 8 8 8 1 8 1/2 R/C C 4 4 4 1 4 1/2 R/C D 8 8 16 2 16 1/2 R/C E NA NA NA NA NA NA R/C F 8 8 16 2 16 1/2
1. Raw card D is a stacked solution, raw card F is a planar solution. 2. The EEPROM can be a single load or dual load depending on the tempsensor. The integrated temp sensor would be a single load. The stand alone tempsensor would be shown as the dual load
Release 18A
Revision 1.0
DDR3 SO-DIMM Gerber File Releases

Reference design file updates will be released as needed. This specification will reflect the most recent design files, but may be updated to reflect clarifications to the specification only; in these cases, the design files will not be updated. The following table outlines the most recent design file releases Note: Future design file releases will include both a date and a revision label. All changes to the design file are also documented within the read-me file.
Raw Card A B C D E F Revision 1.0 Specification Revision Gerber ReviApplicable Design File sion A1 B1 C1 PC3-12800_SODIMM_V055_RC_A1_20071121.zip PC3-12800_SODIMM_V055_RC_B1_20071102.zip PC3-12800_SODIMM_V055_RC_C1_20070918.zip
NA F2
On Hold PC3-12800_SODIMM_V100_RC-F2_20080603.zip
Revision 1.0
Release 18A
Example Raw Card Component Placement Raw Cards A, B, C , D

The component layout for Raw Cards A, B, C, and D are similar. In the case of Raw Card C , DDR3 SDRAMs will be included only on the front side of the card; however, passive components are on both sides of the board. The thermal sensor should be placed on the same side as SDRAMs for Raw Card C.
Front View
SPD DDR3 SDRAMs
max min max min
Component Keepout Area
DDR3 SDRAMs
max min max min
DDR3 SDRAM FBGA PACKAGE DIMENSIONS Raw Cards A, B, and C 12.3mm max min X 20mm
71 73
203 X=
Rear View
2 72 74 204
9.0mm for x8 DDR3 SDRAMs 12.2mm for x16 DDR3 SDRAMs
7.4mm
max min
max min
max min
max min
DDR3 SDRAMs
DDR3 SDRAMs
Release 18A
Revision 1.0
Example Raw Card Component Placement Raw Cards E(design on hold) , F

The component layout for raw cards E and F are similar. In the case of raw card E the DRAMs are placed vertical and for raw card F the DRAMs are placed horizontal to the edge connector. .
DDR3 SDRAMs Temp Sensor(with SPD) DDR3 SDRAMs
Keepout Component Area
max
max
max
max
min
min
min
min
Front View
max max max max min min min min
71 73
203
72 74
204
max
max
max
max
min
min
min
min
Rear View
max max max max min min min min
DDR3 SDRAMs
SPD
DDR3 SDRAMs
W max min X H PACKAGE DIMENSIONS DDR3 SDRAM FBGA Raw Cards E: W = TBD mm, H = TBD mm Raw Cards F: W = 10.5mm, H = 14.4mm
7.4mm X = 9.0mm for x8 DDR3 SDRAMs
Revision 1.0
Release 18A
6. SO-DIMM Wiring Details

Signal Groups
This specification categorizes SDRAM timing-critical signals into four groups whose members have identical loadings and routings. The following table summarizes the signals contained in each group.
.
Signal Group Clocks for Unbuffered SO-DIMM Select, Clock Enable, ODT Address/Command Data, Data Mask, Data Strobe
Signals In Group CK [1:0], CK [1:0] S [1:0], CKE [1:0], ODT[1:0] Ax, BAx, RAS, CAS, WE, ODT[1:0] DQ [63:0], DM[7:0], DQS[7:0], DQS[7:0]
Page 29-33 34-39 40-46 47-50
General Net Structure Routing Guidelines

Net structures diagrams for each signal group are shown in the following sections. Each diagram is accompanied by a trace segment length table that summarizes the minimum and maximum length for each trace segment in each signal group. The remainder of this section provides a general overview of DDR3 net structure concepts and documents the routing rules to be followed in the design of the DDR3 modules
Explanation of Net Structure Diagrams

The net structure routing diagrams provide a reference design example for each raw card version. These designs provide an initial basis for unbuffered SO-DIMM designs. The diagrams should be used to determine individual signal wiring on a SO-DIMM for any supported configuration. Only transmission lines (represented as cylinders and labeled with trace length designators TL) represent physical trace segments. All other lines are zero in length. To verify SO-DIMM functionality, a full simulation of all signal integrity and timing is required. The given net structure diagrams and associated trace lengths define the current set of approved raw card designs, but are not neccessary inclusive of all raw card solutions. However, any raw card design which is intended to be compatible with one of the current raw card designations, must adhere to the net structure and trace lengths defined for that raw card type, or adopt a new raw card designation. Once the net structure has been determined, the permitted trace lengths for the net structure can be read from the table below each net structure routing diagram. Some configurations require the use of multiple net structure routing diagrams to account for varying load quantities on the same signal. All diagrams define one load as one DDR3 SDRAM input unless specified as two loads (stacked DRAM has two loads). It is highly recommended that the net structure routing data in this document be simulated by the user.
Clock Control and Address/Command Groups

The DDR3 modules implement a fly-by topology for routing CLK, CTRL, and ADD/CMD signal groups, rather than the traditional Tree structure utilized on legacy DDR modules. On DDR3 modules, the CTRL and ADD/CMD groups are length/delay matched to CLK, between the connector and each SDRAM, resulting in significantly reduced timing skew across these groups, vs legacy modules. This fundamental topology change is instrumental in enabling the higher operating speeds of DDR3. A summary table of the length/delay matching rules associated with these signal groups is provided below.
Module Length Matching Rules

Signal Group CLK to CLK# Matching CLK Pair to CLK Pair Matching (Pair to Pair - Avg. Length) CTRL Group Matching Matching Rules Match TLx segment by TLx to segment to within 0.1mm Match total compensated length from connector to each DRAM to within 0.25mm Match total compensated length from connector to each DRAM to within 1.0mm
Release 18A
Revision 1.0
Module Length Matching Rules

Signal Group CTRL to CLK Matching ADR/CMD Matching ADR/CMD to CLK Matching TL2 Stub Length Matching Matching Rules Match total compensated length of all CTRL signals from connector to each DRAM to within CLK +/- 0.5mm Match total compensated length from connector to each DRAM to within 1.0mm Match total compensated length of all ADR/CMD signals from connector to each DRAM to within CLK +/- 0.5mm Match TL2 stub length at each DRAM (top and bottom), on a given signal, to within 0.5mm CLK : TL2 </= 3.0mm CTR: TL2 </= 4.0mm ADR/CMD: TL2 </= 5.6mm The maximum length from the first DRAM and the last DRAM = 166mm 5.0mm </= length </= 10.0mm Match to within +/- 1.0mm
TL2 MAX Stub Length Limits
CLK First to Last Length Neckdown Length 1. 2. 3. 4. 5. 6.
All length matching is done using velocity compensated stripline equivalent lengths. The velocity compensation ratio of 1.1 will be used (MS length / 1.1 = SL equivalent length The neckdown length is the trailing portion of the lead-in section, which is routed at 0.1mm width Maximum first to last length can be calculated by subtracting lenght to the fist DRAM from the length to the last DRAM Via compensation is not required All clocks are length matched, segment by segment and have matched via count
Lead-in vs Loaded Sections

The CLK, CTRL, and ADD/CMD topologies are conceptually divided into two topology sections. The segments between the connector and the first SDRAM node via (TL0 + TL1) are collectively termed the leadin section, while the segments that run between SDRAM node vias (TL3, TL4, TL5), as well as the SDRAM load stubs (TL2), are collectively termed the loaded section. The loaded section also includes the segments between the last SDRAM and the termination. In order to reduce the impedance discontinuity seen at the first load, the lead-in section is routed at a lower nominal impedance than the loaded section, typically with the lead-in section routed at 45 ohms nominal and the loaded section routed at 60 ohms nominal, although some modules may vary. The transition from the wider lead-in trace width to the standard width of the loaded section must occur within a length window preceding the first SDRAM node via, which is termed the neckdown length.
Length/Delay Matching to SDRAM Devices

As mentioned previously, length/delay matching is required between the connector and each SDRAM individually. The length/delay matching process is iterative in nature, and there is no single best method defined. It is generally recommended that the path from the connector to the first SDRAM (TL0 + TL1 + TL2) be matched across the CLK group, and then across CTRL and ADD/CMD groups, as per the length matching guidelines, adjusting CLK length as needed to reach the length window of the CTRL and ADD/CMD groups. It is important to note that the matching is done from connector to the SDRAM ball, and includes the TL2 segment. It is during this process that the breakout pattern dependent length variance in the TL2 stub on each signal will be tuned out. Once length/delay matching to the first device is completed, the length matching to the remaining devices is straightforward, and can be accomplished by simply length matching the intra-node segments (TL3, TL4, TL5..), assuming the TL2 stub length for a given signal does not vary from SDRAM to SDRAM. Note that it is recommended that the TL2 stub length on any given signal be closely matched on top and
Revision 1.0
Release 18A
bottom side pattern, and at each SDRAM. This will facilitate the most accurate overall length/delay matching. The total compensated length from the connector to each SDRAM is documented in the segment length tables for each module type, in the net structure definitions sections. It is required that the length matching rules be met at all SDRAM devices.
Velocity Compensation
Since the lead-in section can have a wide variation in the proportion of its length routed as microstrip vs stripline, the length/delay matching process includes a mechanism for compensating for the velocity delta between these two types of PCB interconnect. A compensation factor of 1.1 has been specified for this purpose. All microstrip segment lengths are to be divided by 1.1 before summation into the length matching equation. The resulting compensated length is termed the stripline equivalent length. While some amount of residual velocity mismatch skew remains in the design, the process is a substantial improvement over simple length matching.
Data and Strobe Group

The DDR3 modules treat each byte lane as a separate signal sub-group, with each byte lane group length/delay matched, with velocity compensation as previously described. The length of the individual byte lanes may vary substantially across the module, with the controller providing timing realignment circuitry. A summary table of the length/delay matching rules associated with the data signal group is provided below.
DQ/DQS Matching
Signal Group DQS to DQS# Matching DQ/DM to DQS within Byte Lane Matching Rules Match TLx segmant by TLx to segment to within 0.1mm Match total compensated length from connector to DRAM of all DQ and DM signals within a byte lane to DQS within +/- 0.2mm
1. All length matching is done using velocity compensated stripline equivalent lengths. 2. The velocity compensation ratio of 1.1 will be used (MS length / 1.1 = SL equivalent length 3. Via compensation is only required if the via count varies within the byte lane. Via equivalent length = 2.0mm
Via Compensation
All current SO-DIMM module designs have matched via counts within all byte lanes, and therefore, via compensation is not required. Should future modules be developed where the via count is mismatched within a byte lane, then via compensation must be implemented, and the via equivalent length is defined to be 2.0 mm.
Release 18A
Revision 1.0
Decoupling Capacitor Guideline

Value, Counts Minimum 3 of 0.1uF decoupling capacitors per DRAM Minimum 2 of 2.2uF bulk decoupling capacitors per module Minimum 1 of 0.1uF decoupling capacitors per 3 termination resistors (per 2 termination resistors is preferable.) Minimum 1 of 0.1uF decoupling capacitor at near the card edge Vtt pin Minimum 1 of 0.1uF decoupling capacitor per DRAM VREFCA Minimum 1 of 0.1uF decoupling capacitor at near the card edge VREFCA pin Minimum 1 of 0.1uF decoupling capacitor per DRAM VREFDQ Minimum 1 of 0.1uF decoupling capacitor at near the card edge VREFDQ pin Should be placed as close as possible to the DARM VREFDQ ball Should be placed as close as possible to the DRAM VREFCA ball Should be placed as close as possible to the Vtt termination resistor Note Should be placed as close as possible to the DRAM VDD ball
VDD
Vtt
1. This guideline should be kept as long as the space permits. 2. 0.1uF can be replaced with 0.22uF
Revision 1.0
Release 18A
Differential Clock Net Structures CK[1:0], CK[1:0]

DDR3 SDRAM clock signals must be carefully routed to meet the following requirements: Signal quality Rise/Fall time Cross point of the differential pair in the SDRAM
Clock Net Wiring CK[1:0], CK[1:0] (Raw Cards A, C)

SDRAM SDRAM SDRAM SDRAM
TL2-1
TL2-2
Cterm
Edge Finger
Differential Pair Routing
TL2-3
TL2-4
30ohm
Rtt VDD TL6 TL7 Rtt
CK
TL0A TL0B TL1 TL3 TL4 TL5
CK
Lead-in Neckdown
0.1uF
30ohm
Clock Routing Trace Lengths Raw Card A

TL0B TL2 TL0A TL1 TL3 Micro Micro Strip Strip Micro -Strip -Strip -Strip MIN MAX 3.0 3.2 25.6 28.3 51.5 54.1 2.0 2.1 14.8 14.8 CompenCompen- CompenCompensated TL7 Necksated sated TL0+TL1 TL6 sated Micro down TL0+TL1 TL0+TL1 Cterm Notes +TL3+TL Strip TL0+TL1 -Strip length +TL3+TL +TL3+TL 4+TL5+T +TL2-1 2-2 4+TL2-3 L2-4 6.3 7.4 0.9 1.2 8.9 9.1 81.9 82.1 96.7 96.9 118.1 118.3 132.9 133.1 2.2pF 1, 2,3
TL4 Strip
TL5 Strip
21.4 21.4
14.8 14.8
1. All distances are given in millimeters. 2. Recommended Trace-Trace spacing : CK, CK and other spacing: minimum 0.3 3. In the column of compensated length, Micro-strip line length is compensated as Equivalent Stripline Length (= Microstrip Length / 1.1), e.g: (compensated TL0+TL1+TL2-1) = TL0A/1.1 + TL0B/1.1 + TL1 + TL2-1/1.1
Clock Routing Trace Lengths Raw Card C

TL0B TL0A TL1 Micro Strip Micro -Strip -Strip MIN MAX 3.3 3.3 21.3 21.3 51.8 51.8 CompenCompen- CompenCompensated TL7 Necksated sated TL0+TL1 TL6 sated Micro down TL0+TL1 TL0+TL1 Cterm Notes +TL3+TL Strip TL0+TL1 -Strip length +TL3+TL +TL3+TL 4+TL5+T +TL2-1 2-2 4+TL2-3 L2-4 8.3 8.4 1.3 1.5 6.9 7.1 74.6 74.6 88.5 88.5 110.8 110.8 124.7 124.7 3.3pF 1, 2, 3, 4
TL2 Strip
TL3 Strip
TL4 Strip
TL5 Strip
0.6 0.6
13.9 13.9
22.3 22.3
13.9 13.9
1. All distances are given in millimeters. 2. Recommended Trace-Trace spacing : CK, CK and other spacing: minimum 0.3 3. In the column of compensated length, Micro-strip line length is compensated as Equivalent Stripline Length (= Microstrip Length / 1.1), e.g: (compensated TL0+TL1+TL2-1) = TL0A/1.1 + TL0B/1.1 + TL1 + TL2-1/1.1 4. Ck1, CK1 are terminated with 75 ohm resistor near card edge on R/C C.
Release 18A
Revision 1.0
Clock Net Wiring CK[0], CK[0] (Raw Card B)

TL2-1
Edge Finger
Cterm
TL2-3
TL2-4
3.3pF
CK
TL0A
TL2-2
30ohm
Rtt VDD TL6 TL7 0.1uf Rtt
TL0B
TL1
TL3
TL4
TL5
CK
TL2-1 TL2-2 TL2-3 TL2-4 Lead-in Neckdown
30ohm
SDRAM
SDRAM
SDRAM
SDRAM
Clock Routing Trace Lengths Raw Card B

CompenCompen- Compensated CompenTL0+TL1 sated sated sated TL0+TL1 TL0+TL1 +TL3+TL Notes TL0+TL1 +TL3+TL +TL3+TL 4+TL5+T +TL2-1 L2-4 2-2 4+TL2-3 76.9 76.9 92.1 92.1 112.2 112.2 127.4 127.4
TL0A TL0B TL2 TL1 TL3 Micro Micro Micro Strip Strip -Strip -Strip -Strip
TL4 Strip
TL5 Strip
TL7 TL6 MicroStrip Strip
Neckdown length
MIN MAX
3.3 3.4
1.3 1.4
70.3 70.4
2.5 2.6
15.2 15.2
20.0 20.1
15.2 15.2
14.8 14.9
1.2 1.4
7.4 7.6
1, 2, 3
1. All distances are given in millimeters. 2. Recommended Trace-Trace spacing : CK, CK and other spacing: minimum 0.3 3. In the column of compensated length, Micro-strip line length is compensated as Equivalent Stripline Length (= Microstrip Length / 1.1), e.g: (compensated TL0+TL1+TL2-1) = TL0A/1.1 + TL0B/1.1 + TL1 + TL2-1/1.1 4. Ck1, CK1 are terminated with 75ohm resistor near card edge on R/C B
Revision 1.0
Release 18A
Clock Net Wiring CK[1:0], CK[1:0] (Raw Card D, PC3-6400, 8500 ONLY)
SDRA M SDRA M SDRA M SDRA M SDRA M SDRA M SDRA M SDRA M
TL2-1
TL2-3
Edge Finger
Cterm
TL2-4
3.3pF
TL2-2
30ohm
Rtt VDD
CK
TL0A TL0B TL1 TL3 TL4 TL5 TL6 TL7
CK
Lead-in Neckdown
0.1uf Rtt
30ohm
Clock Routing Trace LengthsRaw Card D

TL0A TL0B Micro Micro-Strip Strip TL2 TL3 MicroStrip Strip TL7 MicroStrip CompenCompen- CompenCompensated sated sated TL0+TL1 sated TL0+TL1 TL0+TL1 Notes +TL3+TL TL0+TL1 +TL3+TL +TL3+TL 4+TL5+T +TL2-1 2-2 4+TL2-3 L2-4 60.8 61.0 76.6 76.7 94.7 94.9 110.5 110.6 1, 2, 3
TL1 Strip
TL4 Strip
TL5 Strip
TL6 Strip
Neckdown
MIN MAX
3.1 3.6
0.9 1.1
56.0 56.6
0.7 0.8
15.6 15.8
18.1 18.3
15.6 15.8
12.6 16.0
0.9 1.6
7.2 7.5
1. All distances are given in millimeters. 2. Recommended Trace-Trace spacing : CK, CK and other spacing: minimum 0.3 3. In the column of compensated length, Micro-strip line length is compensated as Equivalent Stripline Length( = Microstrip Length / 1.1), e.g: (compensated TL0+TL1+TL2-1) = TL0A/1.1 + TL0B/1.1 + TL1 + TL2-1/1.1
Release 18A
Revision 1.0
Clock Net Wiring CK[1:0], CK[1:0] (Raw Card E)
Revision 1.0
Release 18A
Clock Net Wiring CK[1:0], CK[1:0] (Raw Card F)

TL2-4
TL2-3
TL2-5
Differential Pair Routing TL5 TL6 TL7
30ohm
TL4 VDD
Rtt 0.1uF TL8
30ohm
Rtt
TL3
TL1
TL11
TL10
TL9
TL2-1
TL2-8
TL2-2
3.3 pF
Cterm
R/C F has no lead-in section

TL0A SDRAM SDRAM
SDRAM
SDRAM
Edge Finger
CK
CK
Clock Routing Trace Lengths Raw Card F

TL0A TL0B Micro- MicroStrip Strip MIN MAX 3.1 3.2 1.6 1.8 TL1 Strip 21.7 21.9 TL2 MicroStrip 2.0 2.1 TL3 Strip 30.0 30.1 TL4 Strip 14.6 14.7 TL5 Strip 24.2 24.3 TL6 Strip 27.4 27.6 TL7 Strip 24.2 24.3 TL8 Strip 14.6 14.7 TL9 Strip 30.0 30.1 TL10 Strip 16.2 16.4 TL11 Micro- Notes Strip 0.9 1.1 1, 2, 3
Compensated TL0+TL1+T L2-1 MIN MAX 28.0 28.1
CompenCompenCompenCompenCompensated sated sated sated TL0+TL1+T sated TL0+TL1+T TL0+TL1+T TL0+TL1+T L3+TL4+TL5 TL0+TL1+T L3+TL4+TL2 L3+TL4+TL5 L3+TL4+TL5 +TL6+TL7+ L3+TL2-2 -3 +TL2-4 +TL6+TL2-5 TL2-6 58.0 58.2 72.7 72.9 96.9 97.1 124.4 124.6 148.6 148.8
CompenCompensated sated TL0+TL1+TL3+ TL0+TL1+T TL4+TL5+TL6+ Notes L3+TL4+TL5 TL7+TL8+TL9+ +TL6+TL7+ TL2-8 TL8+TL2-7 163.3 163.5 193.3 193.5 1, 2, 3
1. All distances are given in millimeters. 2. Recommended Trace-Trace spacing : CK, CK and other spacing: minimum 0.2 3. In the column of compensated length, Micro-strip line length is compensated as Equivalent Stripline Length (= Microstrip Length / 1.1), e.g: (compensated TL0+TL1+TL2-1) = TL0A/1.1 + TL0B/1.1 + TL1 + TL2-1/1.1
Release 18A
TL2-7
TL0B
TL2-6
Revision 1.0
Control Net Structures S [1:0], CKE[1:0], ODT[1:0] (Raw cards A , C) Net Structure Routing for Control nets (Raw Cards A, C)
TL2-1
TL2-2
Lead-in
Neckdown
TL2-3
TL2-4
36ohm
Vtt
CTRL
Edge Finger TL0 TL1 TL3 TL4 TL5 TL6 TL7 Rtt
Control Routing Trace Lengths Raw Card A

TL0 TL2 TL1 TL3 MicroMicroStrip Strip Strip Strip TL7 Micro -Strip Neckdown length CompenCompen- CompenCompensated sated sated TL0+TL1 sated TL0+TL1 TL0+TL1 Notes +TL3+TL TL0+TL1 +TL3+TL +TL3+TL 4+TL5+T +TL2-1 2-2 4+TL2-3 L2-4 81.9 82.1 96.7 96.9 118.1 118.3 132.9 133.1 1,2,3
TL4 Strip
TL5 Strip
TL6 Strip
MIN MAX
27.1 48.4
36.8 56.7
0.7 1.7
14.7 14.8
21.4 21.4
14.8 14.8
8.7 19.6
0.9 1.8
8.9 9.1
1. All distances are given in millimeters. 2. Recommended Trace-Trace spacing : min0.2(Lead-in section), min0.25(Loaded section, between vias is min 0.1) 3. In the column of compensated length, Micro-strip line length is compensated as Equivalent Stripline Length (= Microstrip Length / 1.1), e.g: (compensated TL0+TL1+TL2-1) = TL0/1.1 + TL1 + TL2-1/1.1
Control Routing Trace Lengths Raw Card C

TL0 TL1 MicroStrip Strip TL7 Micro -Strip Neckdown length CompenCompen- CompenCompensated sated sated TL0+TL1 sated TL0+TL1 TL0+TL1 Notes +TL3+TL TL0+TL1 +TL3+TL +TL3+TL 4+TL5+T +TL2-1 2-2 4+TL2-3 L2-4 74.6 74.6 88.5 88.5 110.8 110.8 124.7 124.7 1,2, 3
TL2 Strip
TL3 Strip
TL4 Strip
TL5 Strip
TL6 Strip
MIN MAX
31.3 42.2
35.7 45.6
0.6 0.7
13.8 13.9
22.2 22.3
13.9 14.0
5.2 11.0
0.9 1.1
6.9 7.1
Revision 1.0
Release 18A
Control Net Structures S [0], CKE[0], ODT[0] (Raw card B)

.
Net Structure Routing for Control Nets

TL2-1
TL2-2
Edge Finger
TL2-3
TL2-4
36ohm
TL0 TL1 TL3 TL2-2 TL4 TL2-3 TL5 TL2-4 TL6 TL7 Rtt
Vtt
CTRL
Lead-in
Neckdown
SDRAM
TL2-1
SDRAM
SDRAM
SDRAM
Control Routing Trace Lengths Raw Card B

CompenCompen- Compensated CompenTL0+TL1 sated sated sated TL0+TL1 TL0+TL1 +TL3+TL Notes TL0+TL1 +TL3+TL +TL3+TL 4+TL5+T +TL2-1 L2-4 2-2 4+TL2-3 76.9 77.0 92.1 92.2 112.1 112.2 127.3 127.4
TL0 TL2 TL1 TL3 Micro Micro Strip Strip -Strip -Strip
TL4 Strip
TL5 Strip
TL7 TL6 MicroStrip Strip
Neckdown length
MIN MAX
2.2 2.6
70.8 71.7
3.5 4.1
15.2 15.2
20.0 20.1
15.2 15.2
10.3 15.7
0.9 1.2
7.3 7.7
1, 2, 3
Release 18A
Revision 1.0
Control Net Structures S [0], CKE[0], ODT[0] (Raw card D, PC3-6400, 8500 ONLY). Net Structure Routing for Control Nets Raw Card D
SDRAM
SDRAM
SDRAM
SDRAM
TL2-1
Lead-in
Neckdown
Control
TL2-2
TL2-3
TL2-4
30ohm
Vtt TL0a TL0b TL1 TL2-1 TL3 TL2-2 TL4 TL2-3 TL5 TL2-4 TL6 TL7 Rtt
Edge Finger
2.2pF Vss
SDRAM
SDRAM
SDRAM
SDRAM
Control Routing Trace Lengths Raw Card D

CompenCompen- Compensated CompenTL0+TL1 TL7 Necksated sated TL6 sated Micro- down TL0+TL1 TL0+TL1 +TL3+TL Notes Strip TL0+TL1 Strip length +TL3+TL +TL3+TL 4+TL5+T +TL2-1 L2-4 2-2 4+TL2-3 9.6 15.9 1.7 4.6 6.0 6.4 60.5 61.0 76.1 76.7 94.5 95.1 110.1 110.9
TL0a TL0b TL2 TL1 TL3 MicroMicro- MicroStrip Strip Strip Strip Strip
TL4 Strip
TL5 Strip
MIN MAX
3.1 5.8
0.7 7.4
44.8 53.4
3.3 4.6
15.6 16.1
18.2 18.6
15.5 15.9
1, 2, 3
1. All distances are given in millimeters. 2. Recommended Trace-Trace spacing : min0.2(Lead-in section), min0.25(Loaded section, between vias is min 0.1) 3. In the column of compensated length, Micro-strip line length is compensated as Equivalent Stripline Length (= Microstrip Length / 1.1), e.g: (compensated TL0+TL1+TL2-1) = TL0/1.1 + TL1 + TL2-1/1.1 4. Target impedance for leadin section is 40ohm(0.254mm width trace)
Revision 1.0
Release 18A
Control Net Structures S [1:0], CKE[1:0], ODT[1:0] (Raw card E)

.
Net Structure Routing for Control Nets Raw Card E
Release 18A
Revision 1.0
Control Net Structures S [1:0], CKE[1:0], ODT[1:0] (Raw card F) Net Structure Routing for Control Nets Raw Card F
TL2-5
TL2-3
TL2-4
TL7 TL6
TL5
36ohm
Vtt TL4 Rtt TL8
TL11
TL10
TL9
TL3 TL2-1 TL2-2
TL1 TL2-8 TL0 TL2-7 SDRAM
SDRAM
SDRAM
Edge Finger
SDRAM
Control Routing Trace Lengths Raw Card F

TL0 MicroStrip MIN MAX 2.4 4.3 TL1 Strip 23.8 25.7 TL2 MicroStrip 0.5 0.6 TL3 Strip 30.0 30.1 TL4 Strip 14.6 14.8 TL5 Strip 24.1 24.3 TL6 Strip 27.4 27.6 TL7 Strip 24.1 24.3 TL8 Strip 14.6 14.8 TL9 Strip 30.0 30.1 TL10 Strip 15.8 16.6 TL11 MicroStrip 0.7 1.5 Notes
CTRL
Revision 1.0
TL2-6
1,2, 3
Release 18A
CompenCompenCompenCompenCompenCompenCompenCompensated sated sated sated sated TL0+TL1+TL TL0+TL1+TL TL0+TL1+TL sated sated sated TL0+TL1+TL TL0+TL1+TL Notes 3+TL4+TL5+ 3+TL4+TL5+ 3+TL4+TL5+ TL0+TL1+TL TL0+TL1+TL TL0+TL1+TL 3+TL4+TL5+ 3+TL4+TL5+ TL6+TL7+TL TL6+TL7+TL TL6+TL7+TL 2-1 3+TL2-2 3+TL4+TL2-3 TL2-4 TL6+TL2-5 2-6 8+TL2-7 8+TL9+TL2-8 MIN MAX 28.2 28.5 58.2 58.5 72.9 73.2 97.1 97.4 124.6 124.9 148.8 149.1 163.5 163.8 193.5 193.8 1, 2, 3
1. All distances are given in millimeters. 2. Recommended Trace-Trace spacing : 0.3mm(minimum 0.15mm) 3. In the column of compensated length, Micro-strip line length is compensated as Equivalent Stripline Length (= Microstrip Length / 1.1), e.g: (compensated TL0+TL1+TL2-1) = TL0/1.1 + TL1 + TL2-1/1.1
Release 18A
Revision 1.0
Address/Command Net Structures Ax, BAx, RAS, CAS, WE (Raw cards A , B) Net Structure Routing for Address and Command Raw Card A, B
SDRAM
SDRAM
SDRAM
SDRAM
TL2-1
Lead-in
Neckdown
TL2-2
TL2-3
TL2-4
36ohm
Address/ Command
Vtt TL0 TL1 TL2-1 TL3 TL2-2 TL4 TL2-3 TL5 TL2-4 TL6 TL7 Rtt
Edge Finger
SDRAM
SDRAM
SDRAM
SDRAM
Trace Lengths for Address and Command Net Structures Raw Card A
TL0 MicroStrip TL2 MicroStrip CompenCompen- CompenCompensated TL7 Necksated sated TL0+TL1 sated Micro- down TL0+TL1 TL0+TL1 Notes +TL3+TL TL0+TL1 Strip length +TL3+TL +TL3+TL 4+TL5+T +TL2-1 2-2 4+TL2-3 L2-4 0.8 2.2 8.9 9.1 81.9 82.1 96.8 96.9 118.2 118.3 133.0 133.1 1, 2, 3
TL1 Strip
TL3 Strip
TL4 Strip
TL5 Strip
TL6 Strip
MIN MAX
2.2 83.8
4.1 56.6
1.6 5.0
14.8 14.9
21.4 21.4
14.8 14.9
2.7 16.0
1. All distances are given in millimeters. 2. Recommended Trace-Trace spacing : min0.2(Lead-in section), min0.2(Loaded section, between vias is min 0.1) 3. In the column of compensated length, Micro-strip line length is compensated as Equivalent Stripline Length( = Microstrip Length / 1.1), e.g: (compensated TL0+TL1+TL2-1) = TL0/1.1 + TL1 + TL2-1/1.1
Trace Lengths for Address and Command Net Structures Raw Card B
TL0 MicroStrip TL2 MicroStrip CompenCompen- CompenCompensated TL7 Necksated sated sated TL0+TL1 Micro- down TL0+TL1 TL0+TL1 Notes TL0+TL1 +TL3+TL Strip length +TL3+TL +TL3+TL +TL2-1 4+TL5+T 2-2 4+TL2-3 L2-4 0.9 2.8 7.0 7.9 76.8 77.0 92.0 92.2 112.1 112.2 127.3 127.4 1,2, 3
TL1 Strip
TL3 Strip
TL4 Strip
TL5 Strip
TL6 Strip
MIN MAX
2.0 70.5
9.8 72.3
2.3 5.0
15.2 15.2
20.0 20.1
15.2 15.2
3.1 17.9
Revision 1.0
Release 18A

.
Address/Command Net Structures Ax, BAx, RAS, CAS, WE (Raw card C) Net Structure Routing for Address and Command Raw Card C
TL2-1
TL2-2
TL2-3
Lead-in
Neckdown
TL2-4
36ohm
Vtt
Address/ Command
Edge Finger
TL0
TL1
TL3
TL4
TL5
TL6
TL7
Rtt
Trace Lengths for Address and Command Net Structures Raw Card C
TL0 MicroStrip TL2 MicroStrip CompenCompen- CompenCompensated TL7 Necksated sated TL0+TL1 sated Micro- Down TL0+TL1 TL0+TL1 Notes +TL3+TL TL0+TL1 Strip Length +TL3+TL +TL3+TL 4+TL5+T +TL2-1 2-2 4+TL2-3 L2-4 0.9 1.2 6.9 7.1 74.6 74.6 88.5 88.5 110.8 110.8 124.7 124.7 1, 2, 3
TL1 Strip
TL3 Strip
TL4 Strip
TL5 Strip
TL6 Strip
MIN MAX
25.0 55.8
23.3 51.3
0.5 2.0
13.7 14.0
22.2 22.3
13.8 14.0
2.7 15.2
Release 18A
Revision 1.0
Address/Command Net Structures Ax, BAx, RAS, CAS, WE (Raw card D, PC3-6400, 8500 ONLY)
Raw Card D Address/Commands have two topologies.
Net Structure Routing for Address and Command Raw Card D #1
SDRAM SDRAM
SDRAM SDRAM
SDRAM SDRAM
SDRAM SDRAM
TL2-1
TL2-3
Address / Command
Edge Finger
TL2-2
TL2-4
36ohm
Vtt
TL0
TL1
TL3 TL2-2
TL4
TL5 TL2-3 TL2-4
TL6
TL7
Rtt
Lead-in
Neckdown
TL2-1 SDRAM SDRAM
SDRAM SDRAM
SDRAM SDRAM
SDRAM SDRAM
Trace Lengths for Address and Command Net Structures Raw Card D #1
TL0 MicroStrip TL2 MicroStrip CompenCompen- CompenCompensated TL7 Necksated sated TL0+TL1 sated Micro- Down TL0+TL1 TL0+TL1 Notes +TL3+TL TL0+TL1 Strip length +TL3+TL +TL3+TL 4+TL5+T +TL2-1 2-2 4+TL2-3 L2-4 0.8 3.6 6.1 7.6 60.4 61.2 76.1 77.1 94.4 95.5 110.4 111.1 1, 2, 3
TL1 Strip
TL3 Strip
TL4 Strip
TL5 Strip
TL6 Strip
MIN MAX
2.6 31.2
29.9 56.6
1.7 5.0
15.2 16.5
17.9 18.7
15.6 16.1
4.6 8.7
Revision 1.0
Release 18A
Net Structure Routing for Address and Command Raw Card D #2
SDRAM SDRAM
SDRAM SDRAM
SDRAM SDRAM
SDRAM SDRAM
TL2-3
TL2-5
TL2-1
TL2-7
Address/ Command
Edge Finger
36ohm
Vtt
TL0
TL1
TL3 TL2-2
TL4
TL5
TL6
TL7
TL8
TL9
TL10
TL11
Rtt
TL2-4
TL2-6
Lead-in
Neckdown
SDRAM SDRAM
SDRAM SDRAM
SDRAM SDRAM
TL2-8
SDRAM SDRAM
#2 topology is used for A3, A4, A5, A7, A11, A13, BA0 and BA1. For these signals, topology #1 causes very long TL2 length.
Trace Lengths for Address and Command Net Structures Raw Card D #2
TL0 MicroStrip MIN MAX 2.2 28.3 TL1 Strip 31.7 56.5 TL2 MicroStrip 0.5 0.6 TL3 Strip 4.1 6.7 TL4 Strip 9.1 11.5 TL5 Strip 4.1 6.7 TL6 Strip 11.4 13.6 TL7 Strip 4.1 6.7 TL8 Strip 9.0 11.6 TL9 Strip 4.1 6.7 TL10 Strip 3.6 8.8 TL11 MicroStrip 0.7 2.0 NeckDown length 6.4 7.6 Notes
1, 2, 3
Compensated Compensated ((TL0+TL1+TL3+TL4+TL5+ Compensated Compensated ((TL0+TL1+TL3+TL4+TL5+ +TL6+TL7+TL8+TL2((TL0+TL1+TL2((TL0+TL1+TL3+TL4+TL2+TL6+TL2Notes 7)+(TL0+TL1+TL3+TL4+TL5 1)+(TL0+TL1+TL3+TL2-2)) / 3)+(TL0+TL1+TL3+TL4+TL5 5)+(TL0+TL1+TL3+TL4+TL5 +TL6+TL7+TL8+TL9+TL22 +TL2-4)) / 2 +TL6+TL7+TL2-6)) / 2 8)) / 2 MIN MAX 60.6 61.3 76.4 76.8 94.4 95.2 110.4 111.2 1, 2, 3
Release 18A
Revision 1.0
Address/Command Net Structures Ax, BAx, RAS, CAS, WE (Raw card E) Net Structure Routing for Address and Command Raw Card E
Revision 1.0
Release 18A
Address/Command Net Structures Ax, BAx, RAS, CAS, WE (Raw card F) Net Structure Routing for Address and Command Raw Card F
Top
SDRAM
SDRAM
Top
SDRAM
SDRAM
Top
SDRAM
SDRAM
Top
SDRAM
SDRAM
Bottom
Bottom
Bottom
Bottom
TL2-3
TL2-4
TL2-5
TL5 Vtt
36ohm
Rtt
TL6
TL7
TL4
TL2-6
TL9 SDRAM
TL11

TL3 TL1
TL10
TL2-1
TL0
TL2-8
TL2-2
Edge Finger
Top
SDRAM
SDRAM
Top
SDRAM
SDRAM
Address/ Command
Top
SDRAM
Top
SDRAM
TL2-7
TL8
SDRAM
Bottom
Bottom
Bottom
Bottom
Address/Command Routing Trace Lengths Raw Card F

TL0 MicroStrip MIN MAX 1.6 5.4 TL1 Strip 19.9 25.2 TL2 MicroStrip 1.9 4.4 TL3 Strip 29.9 30.1 TL4 Strip 14.7 14.8 TL5 Strip 24.1 24.3 TL6 Strip 27.5 27.6 TL7 Strip 24.1 24.3 TL8 Strip 14.7 14.8 TL9 Strip 29.9 30.1 TL10 Strip 11.1 12.9 TL11 MicroStrip 0.7 2.5 Notes
1, 2, 3
Release 18A
Revision 1.0
CompenCompenCompenCompenCompenCompenCompenCompensated sated sated sated sated TL0+TL1+TL TL0+TL1+TL TL0+TL1+TL sated sated sated TL0+TL1+TL TL0+TL1+TL Notes 3+TL4+TL5+ 3+TL4+TL5+ 3+TL4+TL5+ TL0+TL1+TL TL0+TL1+TL TL0+TL1+TL 3+TL4+TL5+ 3+TL4+TL5+ TL6+TL7+TL TL6+TL7+TL TL6+TL7+TL 2-1 3+TL2-2 3+TL4+TL2-3 TL2-4 TL6+TL2-5 2-6 8+TL2-7 8+TL9+TL2-8 MIN MAX 27.9 28.4 57.9 58.4 72.6 73.1 96.8 97.3 124.3 124.8 148.5 149.0 163.2 163.7 193.2 193.7 1, 2, 3
1. All distances are given in millimeters. 2. Recommended Trace-Trace spacing : 0.25mm(minimum 0.1mm) 3. In the column of compensated length, Micro-strip line length is compensated as Equivalent Stripline Length (= Microstrip Length / 1.1), e.g: (compensated TL0+TL1+TL2-1) = TL0/1.1 + TL1 + TL2-1/1.1
Revision 1.0
Release 18A
Data Net Structures

DQ[63:0], DM[7:0], DQS[7:0], DQS[7:0] Special attention has been paid to balancing the data nets within a DDR3 SDRAM, within a particular SODIMM, and across the SO-DIMM family. Data nets have been placed in order to bound the data strobe nets. Because data travels with the data strobe, the placement of the strobe in the middle of the narrow window aids in data timing. Although it is not necessary to ensure consistent delays between SDRAMs and/or card types, doing so facilitates system design, system simulation, and DIMM specifications. It is recommend to maintain consistent delays for all nets as described in the following tables.
Net Structure Routing for DQ[63:0], DM[7:0], DQS[7:0], DQS[7:0] (Raw card A, F)
TL2
SDRAM
Edge Finger TL0A Rs TL0B TL1
Data
15ohm
SDRAM
Trace Lengths for Data Net Structure Raw Card A

TL0A MicroStrip DQ0-DQ7, DM0, DQS0, DQS0 DQ8-DQ15, DM1, DQS1, DQS1 DQ16-DQ23, DM2, DQS2, DQS2 DQ24-DQ31, DM3, DQS3, DQS3 DQ32-DQ39, DM4, DQS4, DQS4 DQ40-DQ47, DM5, DQS5, DQS5 DQ48-DQ55, DM6, DQS6, DQS6 DQ56-DQ63, DM7, DQS7, DQS7 MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX 3.0 3.8 2.9 3.7 2.9 3.3 2.9 3.3 2.9 3.4 3.0 3.6 2.9 3.7 3.3 4.0 TL0B Microstrip 1.0 2.3 1.0 2.2 0.9 2.9 1.0 2.5 0.9 2.4 0.9 2.2 0.9 2.4 0.9 2.3 TL1 Strip 8.5 10.0 8.1 10.6 12.0 14.2 12.5 14.2 9.2 11.7 9.4 11.5 9.0 11.3 8.8 10.8 TL2 Microstrip 0.5 2.1 0.5 2.1 0.5 2.1 0.5 2.1 0.5 2.0 0.5 2.1 0.5 2.1 0.5 2.0 Compensated TL0+TL1+TL2 14.6 14.7 14.6 14.8 18.2 18.3 18.2 18.3 15.7 15.8 15.7 15.8 15.3 15.4 15.3 15.4 1, 2, 3, 4 Notes
1. All distances are given in millimeters. 2. Recommended Trace-Trace spacing : DQ, DM, DQS, DQS and other is minimum 0.3 3. Compensated Total is TL0A + TL0B + TL1 + TL2 in equivalent stripline length. In this column Micro-strip line length is compensated as Equivalent Stripline Length (= Microstrip Length / 1.1) 4. (Compensated TL0+TL1+TL2) = TL0A/1.1 + TL0B/1.1 + TL1 + TL2/1.1
Release 18A
Revision 1.0
Trace Lengths for Data Net Structure Raw Card F

TL0A MicroStrip DQ0-DQ7, DM0, DQS0, DQS0 DQ8-DQ15, DM1, DQS1, DQS1 DQ16-DQ23, DM2, DQS2, DQS2 DQ24-DQ31, DM3, DQS3, DQS3 DQ32-DQ39, DM4, DQS4, DQS4 DQ40-DQ47, DM5, DQS5, DQS5 DQ48-DQ55, DM6, DQS6, DQS6 DQ56-DQ63, DM7, DQS7, DQS7 MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX 3.0 3.4 2.9 3.7 3.0 3.4 2.9 3.5 2.9 3.5 2.9 3.3 3.1 3.4 2.9 4.1 TL0B Microstrip 0.8 2.1 0.7 2.2 0.7 2.1 0.7 2.6 0.7 3.5 0.7 2.1 0.7 2.2 0.7 2.2 TL1 Strip 22.9 25.6 17.7 20.5 22.9 25.5 18.2 20.7 17.8 20.7 23.2 25.7 18.4 20.5 23.3 25.6 TL2 Microstrip 0.5 1.8 0.5 1.8 0.5 1.8 0.5 1.8 0.5 1.8 0.5 1.8 0.5 1.8 0.5 1.8 Compensated TL0+TL1+TL2 29.3 29.5 24.3 24.5 29.3 29.5 24.3 24.6 24.3 24.6 29.3 29.6 24.3 24.5 29.3 29.6 1, 2, 3,4 Notes
1. All distances are given in millimeters. 2. Recommended Trace-Trace spacing : DQ, DM, DQS, DQS and other is 0.2mm(minimum 0.1mm) 3. Compensated Total is TL0A + TL0B + TL1 + TL2 in equivalent stripline length. In this column Micro-strip line length is compensated as Equivalent Stripline Length (= Microstrip Length / 1.1) 4. (Compensated TL0+TL1+TL2) = TL0A/1.1 + TL0B/1.1 + TL1 + TL2/1.1
Revision 1.0
Release 18A
Data Net Structures DQ[63:0], DM[7:0], DQS[7:0], DQS[7:0] (Raw cards B, C) Net Structure Routing for Data, Data Mask, Data Strobe
Edge Finger
TL0A
15ohm
TL0B
TL1
TL2
Data
SDRAM
Trace Lengths for Data Net Structure Raw Card B

Release 18A
Revision 1.0
Trace Lengths for Data Net Structure Raw Card C

Revision 1.0
Release 18A
Data Net Structures DQ[63:0], DM[7:0], DQS[7:0], DQS[7:0] (Raw cards D, PC3-6400, 8500 ONLY) Net Structure Routing for Data, Data Mask, Data Strobe Raw Card D
Edge Finger
SDRAM
TL0A TL0B TL1 TL2
Data
SDRAM
Trace Lengths for Data Net Structure Raw Card D

Release 18A
Revision 1.0
Cross Section Recommendations

The DDR3 SO-DIMM printed circuit board design uses multi-layers of glass epoxy material. It shall have the reference planes to form the signal traces(except low speed signals such as SMBus) the transmission lines. The reference planes can be divided so adjacent signal layers maintain a constant Vss or Vdd reference. All data is referenced to Vss and all address/command and clocks are referenced to Vdd.
PCB Electrical Specifications(Common for all Raw Cards)

Parameter Trace velocity: S0 (outer layers) Trace velocity: S0 (inner layers) Min 5.5 6.5 Max 6.7 7.6 Units ps/mm ps/mm
Example Layer Stackup Example 6 layers stack-up for Raw Card A, C

Mask L1 Copper Prepreg L2 Copper Prepreg L3 Copper Prepreg L4 Copper Prepreg L5 Copper Prepreg L6 Copper Mask 0.015 mm 0.045 mm 0.10 mm 0.03 mm 0.127 mm 0.03 mm 0.34 mm 0.03 mm 0.127 mm 0.03 mm 0.10 mm 0.045 mm 0.015 mm
Overall Thickness(without Mask) = 1.0mm +/- 0.1mm
Signal 0.5 oz + Plating Vdd/Vss 1 oz Signal 1 oz Signal 1 oz Vdd/Vss 1 oz Signal 0.5 oz + Plating
6 layers Geometory/Impedance Table

Single Ended Layer L1 Width 0.1 mm 0.2 mm 0.1 mm 0.2 mm 0.1 mm 0.2 mm Target Z0 60 ohms +/- 10% 45 ohms +/- 10% 60 ohms +/- 10% 45 ohms +/- 10% 60 ohms +/- 10% 45 ohms +/- 10% Width/Space 0.1 / 0.1 mm 0.2 / 0.1 mm 0.1 / 0.1 mm 0.2 / 0.1 mm 0.1 / 0.1 mm 0.2 / 0.1 mm Differential Target Zdiff 88 ohms +/- 15% 68 ohms +/- 15% 88 ohms +/- 15% 68 ohms +/- 15% 88 ohms +/- 15% 68 ohms +/- 15%
L3
L4
1. All trace widths are subject to adjustment by PCB vendor, as required to align impedance targets. 2. Only the 60ohm single ended impedances is firm specification. 3. All other impedance targets are provided for reference only.
Revision 1.0
Release 18A

Single Ended L6 0.1 mm 0.2 mm 60 ohms +/- 10% 45 ohms +/- 10% 0.1 / 0.1 mm 0.2 / 0.1 mm Differential 88 ohms +/- 15% 68 ohms +/- 15%
1. All trace widths are subject to adjustment by PCB vendor, as required to align impedance targets. 2. Only the 60ohm single ended impedances is firm specification. 3. All other impedance targets are provided for reference only.
Example 8 layers stackup for Raw Card B, D, F

Mask L1 Copper Prepreg L2 Copper Prepreg L3 Copper Prepreg L4 Copper Prepreg L5 Copper Prepreg L6 Copper Prepreg L7 Copper Prepreg L8 Copper Mask 0.015 mm 0.045 mm 0.10 mm 0.015 m m 0.10 mm 0.015 m m 0.15 m m 0.015 m m 0.1 mm 0.015 m m 0.15 m m (*) 0.015 mm 0.10 mm 0.015 m m 0.10 mm 0.045 mm 0.015 mm
Overall Thickness(without Mask) = 1.0mm +/- 0.1mm (*)Note : Even if you need to adjust the stackup, the distance between L5 and L6 should be kept >0.1mm to reduce the crosstalk between L5 and L6 traces.
Signal 0.5 oz + Plating Vdd/Vss 0.5oz Signal 0.5 oz Vdd/Vss 0.5oz Signal 0.5 oz Signal 0.5 oz Vdd/Vss 0.5 oz Signal 0.5 oz + Plating

Single Ended Layer L1 Width 0.1 mm 0.2 mm 0.08 mm 0.16 mm 0.1 mm 0.2 mm Target Z0 60 ohms +/- 10% 45 ohms +/- 10% 55 ohms +/- 10% 40 ohms +/- 10% 55 ohms +/- 10% 40 ohms +/- 10% Width/Space 0.1 / 0.1 mm 0.2 / 0.1 mm 0.09 / 0.1 mm 0.18 / 0.1 mm 0.1 / 0.1 mm 0.2 / 0.1 mm Differential Target Zdiff 88 ohms +/- 15% 68 ohms +/- 15% 88 ohms +/- 15% 68 ohms +/- 15% 88 ohms +/- 15% 68 ohms +/- 15%
L3
L5 & L6
1. All trace widths are subject to adjustment by PCB vendor, as required to align impedance targets. 2. Only the 55ohm and 60ohm single ended impedances are firm specification. 3. All other impedance targets are provided for reference only.
Release 18A
Revision 1.0

Single Ended L8 0.1 mm 0.2 mm 60 ohms +/- 10% 45 ohms +/- 10% 0.1 / 0.1 mm 0.2 / 0.1 mm Differential 88 ohms +/- 15% 68 ohms +/- 15%
1. All trace widths are subject to adjustment by PCB vendor, as required to align impedance targets. 2. Only the 55ohm and 60ohm single ended impedances are firm specification. 3. All other impedance targets are provided for reference only.
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7. Test Points
All DDR3 components are in BGA packages which makes the package pads inaccessible for probing during system development. The DDR3 SO-DIMMs have test points identified to make initial evaluation easier. In some cases test pads have been added and in other cases existing vias are used as test points. An effort has been made to provide testability on some signals in all signal groups but 100% coverage is not possible.
Raw Card A Test Points

Raw Card A Front View
CKE0 CKE1 CK0 CK0B CASB CK1 CK1B ODT0 WEB BA2 A12 A15 A9 A8 A3 BA1 BA0 CS1B CS0B A13 ODT1 BA1 A5 A7 A12 RAS CS0 A11 A14 A8 A3 A10 CS1 CKE0 BA0 CKE1
A5 A1 A10 A4 A14 A7 A6
DQ1
DQ3
DQS1B
DQ16
DQ18
DQS4B DQ33 DQ34
DQ49 DQ50
DM7
DQ0
DQ2
DQS1 DQ17
DQ19
DM3
DQ32
DQS4 DQ35
DM5
DQ48
DQ51
Raw Card A Back View

CKE0 CKE1 CK0 CK0B CASB CK1 CK1B ODT0 WEB BA2 A12 A15 A9 A8 A3 BA1 BA0 CS1B CS0B A13 ODT1 BA1 A5 A7 A12 RAS CS0 A11 A14 A8 A3 A10 CS1 CKE0 BA0 CKE1
A5 A1 A10 A4 A14 A7 A6
DQ1
DQ3
DQS1B
DQ16
DQ18
DQS4B DQ33 DQ34
DQ49 DQ50
DM7
DQ0
DQ2
DQS1 DQ17
DQ19
DM3
DQ32 DQS4 DQ35
DM5
DQ48
DQ51
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Raw Card B Test Points

Raw Card B Front View
Raw Card B Back View
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Raw Card C Test Points

The test points for RC C is on the back sides of the card. Most signals can be probed at the vias.
Raw Card C Back Side View
A7
A8
A7
A8
A7
A8 A7
A8
RAS#
RAS#
RAS#
S0# ODT0
DQ54 DQS6# DQS6
CKE0 CK0# CK0
S0# ODT0
DQ34 DQS4# DQS4
CKE0 CK0# CK0
S0# ODT0
DQ30 DQS3# DQS3
CKE0 CK0# CK0
S0# CKE0 CK0# ODT0 CK0 DQ14 DQS1# DQS1 DQS0 DQS0# DQ01
DQS7 DQS7# DQ61
DQS5 DQS5# DQ45
DQS2 DQS2# DQ21
204
RAS#
Viewed from the back side.
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Raw Card D Test Points

Raw Card D Front View
Raw Card D Back View
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Raw Card F Test Points
Raw Card F Front View
Raw Card F Back View
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8. Serial Presence Detect Definition

The Serial Presence Detect (SPD) function MUST be implemented on the DDR3 SDRAM Unbuffered SODIMM. The component used and the data contents must adhere to the most recent version of the JEDEC DDR3 SDRAM SPD Specifications. Please refer to this document for all technical specifications and requirements of the serial presence detect devices. The following table is intended to be an example of a typical DDR3 SO-DIMM. SPD values indicating different SO-DIMM performance characteristics will be utilized based on specific characteristics of the SDRAMs or SO-DIMMs. This example assumes: Module Organization: 512MB Device Composition: 64Mbx8 Device Package: FBGA Module Physical Ranks: 1 CAS latency: 6, 7, 8(DDR3-1066)
Serial Presence Detect Data Example

Byte # (dec) Byte # (hex) Description
(Part 1 of 3)
SPD Entry Value DDR3-1066 Serial PD Data Entry (Hexadecimal) DDR3-1066 92 00 0B 03 01 09 01 03 3 3 3 1, 2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1. 2. 3. 4.
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13
Number of Serial PD Bytes Written / SPD Device Size CRC covers 0-116, total / CRC Coverage 256, 176 used, 00010010 SPD Revision DRAM Device Type Module Type SDRAM Density and Banks SDRAM Addressing Reserved Module Organization Module Memory Bus Width Fine Timebase Dividend and Divisor Medium Timebase Dividend Medium Timebase Divisor SDRAM Minimum Cycle Time (tCKmin) Reserved CAS Latencies Supported, Least Significant Byte CAS Latencies Supported, Most Significant Byte Minimum CAS Latency Time (tAAmin) Minimum Write Recovery Time (tWRmin) Minimum RAS# to CAS# Delay Time (tRCDmin) Minimum Row Active to Row Active Delay Time (tRRDmin) 6, 7, 8 1R, 8bits 64 0.0 DDR3 SDRAM SO-DIMM 8 banks, 512Mb Row 13: CLM: 10
3 1C 3 3 3 3 3 3
This will typically be programmed as 128 bytes or 176 bytes. Size of the SPD device will typically be programmed as 256 bytes. From DDR3 SDRAM data sheet These are optional, in accordance with the JEDEC specification.
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Byte # (dec) 20 21 22 23 24 25 26 27 28 29 30 31 32-59 60 61 62 63 64-116 117 118 119 120 121 122-125 126-127 128-145 146 147 148 149 150-175 1. 2. 3. 4. Byte # (hex) 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 3C 3D 3E 3F 40 75 76 77 78 79 7A 7E 80 92 93 94 95 96 Description
(Part 2 of 3)
SPD Entry Value DDR3-1066 Serial PD Data Entry (Hexadecimal) DDR3-1066 3 3 3 3 3 3 3 3 3 3 3 3 30.0 Back 1.4: Front : 1.4 Raw Card B Standard 0F 11 01 00
Minimum Row Precharge Time (tRPmin) Upper Nibbles for tRAS and tRC Minimum Active to Precharge Time (tRASmin), Least Significant Byte Minimum Active to Active/Refresh Time (tRCmin), Least Significant Byte Minimum Refresh Recovery Time (tRFCmin), Least Significant Byte Minimum Refresh Recovery Time (tRFCmin), Most Significant Byte Minimum Internal Write to Read Command Delay Time (tWTRmin) Minimum Internal Read to Precharge Command Delay Time (tWTRmin) Upper Nibble for tFAW Minimum Four Activate Window Delay Time (tFAWmin) SDRAM Optional Features SDRAM Thermal and Refresh Options Reserved Module Hieght (Nominal) Module Thickness (MAX) Raw Card ID Address Mapping Edge Conector To DRAM Reserved Module MFR ID (LSB) Module MFR ID (MSB) Module MFR Location ID Module MFR Year Module MFR Week Module Serial Number Cyclical Redundancy Code Module Part number Device Die Rev PCB Rev DRAM MaFR ID (LSB DRAM Device MFR (MSB) Manufacturers Specific Data CRC CRC
4 4 4
4 4 4 4
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Byte # (dec) 176-255 1. 2. 3. 4. Byte # (hex) B0 Description
(Part 3 of 3)
SPD Entry Value DDR3-1066 Serial PD Data Entry (Hexadecimal) DDR3-1066
Customer Reserved Bytes
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9. Product Label
DDR3 "End-User" DIMM Label Format:
The following label shall be applied to all DDR3 memory modules targeted at end-user type products to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format. A readable point size should be used, and the number can be printed in one or more rows on the label. Hyphens may be dropped when lines are split, or when font changes sufficiently separate fields. Unused letters in each field, such as ggggg, are to be omitted when not needed.
ggggg eRxff PC3-wwwwwm-aa-bb-ccd

Where:
ggggg = Module total capacity, in bytes 256MB, 512MB, 1GB, 2GB, 4GB, etc. eR = Number of ranks of memory installed 1R = 1 rank of DDR3 SDRAM installed 2R = 2 ranks 4R = 4 ranks xff = Device organization (bit width) of DDR3 SDRAMs used on this assembly x4 = x4 organization (4 DQ lines per SDRAM) x8 = x8 organization x16 = x16 organization wwwww = Module bandwidth in MB/s 6400 = 6.40 GB/s (PC3-800 SDRAMs, 8 byte primary data bus) 8500 = 8.53 GB/s (PC3-1066 SDRAMs, 8 byte primary data bus) 10600 = 10.66 GB/s (PC3-1333 SDRAMs, 8 byte primary data bus) 12800 = 12.80 GB/s (PC3-1600 SDRAMs, 8 byte primary data bus) m = Module Type E = Unbuffered DIMM ("UDIMM"), with ECC (x72 bit module data bus) F = Fully Buffered DIMM ("FB-DIMM") M = Micro-DIMM R = Registered DIMM ("RDIMM") S = Small Outline DIMM ("SO-DIMM") U = Unbuffered DIMM ("UDIMM"), no ECC (x64 bit module data bus) aa = DDR3 SDRAM CAS Latency in clocks at maximum operating frequency bb = JEDEC SPD Revision Encoding and Additions level used on this DIMM cc = Reference design file used for this design (if applicable) A = Reference design for raw card A is used for this assembly B = Reference design for raw card B is used for this assembly AV = Reference design for raw card AV is used for this assembly ZZ = None of the reference designs were used for this assembly d = Revision number of the reference design used 0 = Initial release 1 = First revision 2 = Second revision P = Pre-release or Engineering sample Z = To be used when field cc = ZZ
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Examples:
1GB 2Rx16 PC3-10600S-10-10-AP is a 1GB DDR3 SO-DIMM using 2 ranks of x16 SDRAMs operational to DDR3-1333 performance with CAS Latency = 10 using JEDEC DDR3 SPD revision 1.0, raw card reference design file A Pre-release version used for the assembly 2GB 1Rx8 PC3-8500S-7-10-B0 is a 2GB DDR3 SO-DIMM using 1rank of x8 SDRAMs operational to DDR3-1066 performance with CAS Latency = 7 using JEDEC DDR3 SPD revision 1.0, raw card reference design file B initial release used for the assembly
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10. SO-DIMM Mechanical Specifications

JEDEC has standardized detailed mechanical information for the 204 Pin DIMM family. This information can be accessed on the worldwide web as follows: 1. Go to http://www.jedec.org. 2. Click on Free Standards and Docs. 3. Scroll down and double click on Publication 95. 4. Under Outlines/Registrations, click on Microelectronics Outlines. 5. Scroll down and select MO-268 to download the PDF for this product family This example is for reference only; please refer to JEDEC standard MO-268 variation CA for details.
Reference Simplified Mechanical Drawing with Keying Position

Front
67.60 mm nom.
Component Keepout Area
Side
3.8 mm max.
DDR3 SDRAMs
max min 20.00 mm max min
DDR3 SDRAMs SPD

max min max min 30.0 mm nom.
71 73
203
1.1 mm max. 1.35 mm max. component height from PCB
Voltage Key
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11. Application Note

Max Cin for the stacked SDRAM on Raw Card D x8 2ranks module
Raw Card D uses the stacked SDRAM. There are variety of configurations for stacked SDRAM and there is no standard on the parasitic values as of Jan/07. So these devices may have a wide range of the parasitic values. The behavior of Raw Card D is sensitive to these values. Here is a reference value for the control nets. FYI : Max control Cin for the stacked DRAM : 2.25pF at PC3-8500(DDR3-1066) 1N timing Other parasitic values may have an effect on the operation of Raw Card D. One must use simulations and lab verification to ensure proper timing requirements and signal integrity in the system.
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DDR3 204-Pin Unbuffered SO-DIMM Design Spec

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DDR3 204-Pin Unbuffered SO-DIMM Design Spec

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JEDEC Standard No. 21C Page 4.20.

4.20.18 - 204-Pin DDR3 SDRAM Unbuffered SO-DIMM Design Specification

JEDEC Standard No. 21C Page 4.20.18-2

JEDEC Standard No. 21C Page 4.20.18-3

JEDEC Standard No. 21C Page 4.20.18-4

Product Family Attributes

Voltage Options, Nominal

Raw Cards Summary

JEDEC Standard No. 21C Page 4.20.18-5

JEDEC Standard No. 21C Page 4.20.18-6

Absolute Maximum Ratings

JEDEC Standard No. 21C Page 4.20.18-7

Input/Output Functional Description

S[1:0] RAS, CAS, WE BA[2:0] ODT[1:0]

Input Input Input

A[9:0], A10/AP, A11 A12/BC, A[15:13]

VDD, VDDSPD, VSS VREFDQ, VREFCA SDA

SCL SA[1:0] TEST

Input Input In/Out

JEDEC Standard No. 21C Page 4.20.18-8

Input/Output Functional Description

Active Low This signal resets the DDR3 SDRAM

JEDEC Standard No. 21C Page 4.20.18-9

DDR3 SDRAM SO-DIMM Pinout.

A143 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1

JEDEC Standard No. 21C Page 4.20.18-10

Block Diagram: Raw Card Version A(Populated as 2ranks of x16 SDRAMs)

CK1 CK1 CKE1 ODT1

SCL SA0 SA1

SCL A0 Temp Sensor A1 (with SPD) A2 EVENT EVENT

CS RAS CAS WE CK CK CKE ODT A[0: N]/BA[0:N]

CS RAS CAS WE CK CK CKE ODT A[0: N]/BA[0:N]

DQS0 DQS0 DM0 DQ [0:7] DQS1 DQS1 DM1 DQ [8: :15]

LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15 ]

LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15 ]

SCL SA0 SA1

Vtt VDDSPD VREFCA VREFDQ

CS RAS CAS WE CK CK CKE ODT A[0: N]/BA[0:N]

CS RAS CAS WE CK CK CKE ODT A[0: N]/BA[0:N]

DQS2 DQS2 DM2 DQ [16:23] DQS3 DQS3 DM3 DQ [24:31]

LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15 ]

LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15 ]

VDD VSS CK0 CK1 CK0 CK1 EVENT RESET

CS RAS CAS WE CK CK CKE ODT A[0: N]/BA[0:N]

CS RAS CAS WE CK CK CKE ODT A[0: N]/BA[0:N]

DQS4 DQS4 DM4 DQ [32:39] DQS5 DQS5 DM5 DQ [40:47]

LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15 ]

LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15]

CS RAS CAS WE CK CK CKE ODT A[0: N]/BA[0:N]

CS RAS CAS WE CK CK CKE ODT A[0: N]/BA[0:N]

DQS6 DQS6 DM6 DQ [48:55] DQS7 DQS7 DM7 DQ [56:63]

LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15 ]

LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15]

JEDEC Standard No. 21C Page 4.20.18-11

Block Diagram: Raw Card Version B(Populated as 1rank of x8 SDRAMs)

DQS0 DQS0 DM0 DQ [0:7]

DQS DQS DM DQ [0:7]

CS RAS CAS WE CK CK CKE ODT A[0: N]\BA [0:N]

DQS1 DQS1 DM1 DQ [8: 15]

DQS DQS DM DQ [0:7]

SCL SA0 SA1

SCL A0 Temp Sensor A1 (with SPD) A2 EVENT EVENT