Modular FPGA-Based Software Defined Radio for CubeSats by Steven J.

Olivieri

A Thesis Submitted to the Faculty of the WORCESTER POLYTECHNIC INSTITUTE in partial fulllment of the requirements for the Degree of Master of Science in Electrical and Computer Engineering by May 2011

APPROVED: Professor Alexander M. Wyglinski, Research Advisor Professor Fred J. Looft III Dr. R. Scott Erwin

Abstract
Digital communications devices designed with application-specic integrated circuit (ASIC) technology suer from one very signicant limitationthe integrated circuits are not programmable. Therefore, deploying a new algorithm or an updated standard requires new hardware. Field-programmable gate arrays (FPGAs) solve this problem by introducing what is essentially recongurable hardware. Thus, digital communications devices designed on FPGAs are capable of accommodating multiple communications protocols without the need to deploy new hardware, and can support new protocols in a matter of seconds. In addition, FPGAs provide a means to update systems that are physical dicult to access. For these reasons, FPGAs provide us with an ideal platform for implementing adaptive communications algorithms. This thesis focuses on using FPGAs to implement an adaptive digital communications system. Using the Universal Software Radio Peripheral (USRP) as a base, this thesis aims to create a highly-adaptive, plug and play software-dened radio (SDR) that ts CubeSat form-factor satellites. Such a radio platform would enable CubeSat engineers to develop new satellites faster and with lower costs. This thesis presents a new system, the CubeSat SDR, that adapts the USRP platform to better suit the space and power limitations of a CubeSat.

iii

Acknowledgements
First, I must thank my advisors, Drs. Alex Wyglinski and Fred Looft. Your advice and support for the past three years has been invaluable. I also thank Dr. Scott Erwin for being part of my defense committee. COSMIAC and the Air Force Research Lab at Kirtland Air Force Base provided nancial support for parts of this project. Thank you. Thank you, Professors Jim Duckworth and Xinming Huang, for teaching me how to use FPGAs, VHDL, and Verilog. Without your instruction, I almost certainly would not have been able to complete this project. The professors, students, tutors, and fellow teaching assistants who I have had the pleasure to work with have given me seven fantastic years at WPI. I shall especially thank Isaac, Drew, Zach, Ben, and Zebranky for getting me to play DotA whenever there was work to be done. Mike, Tom, Soe San, and the rest, I thank you for similarly distracting me in labs. Good times! Finally, I thank my family and friends for putting up with my erratic schedule and for their support over the years. You all are awesome.

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Contents
List of Figures List of Tables List of Listings 1 Introduction 1.1 Research Motivation . . 1.2 Current State of the Art 1.3 Research Objectives . . 1.4 Thesis Contributions . . 1.5 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi vii x 1 1 3 4 5 5 6 6 9 11 12 14 19 20 22 23 23 27 30 31 31 32 33 34 37

2 Software-Dened Radio and CubeSats 2.1 Software-Dened Radio . . . . . . . . . . . 2.2 Field-Programmable Gate Arrays . . . . . . 2.3 GNU Radio and the USRP . . . . . . . . . 2.3.1 GNU Radio . . . . . . . . . . . . . . 2.3.2 USRP . . . . . . . . . . . . . . . . . 2.4 CubeSats . . . . . . . . . . . . . . . . . . . 2.4.1 Space Plug-and-Play Avionics (SPA) 2.5 Chapter Summary . . . . . . . . . . . . . . 3 COSMIAC CubeSat SDR 3.1 Hardware . . . . . . . . 3.2 Software . . . . . . . . . 3.3 Chapter Summary . . .

System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Proposed USRP Variant 4.1 Proposed USRP Firmware 4.2 A New FPGA . . . . . . . 4.3 A New Language . . . . . 4.3.1 Header Files . . . 4.3.2 Ternary Operators

v 4.3.3 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 40 42 43 43 44 46 160 171 231

4.4 4.5

5 Conclusions 5.1 Summary and Accomplishments . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A USRP Code B FPGA Board Description (XBD) C USRP Test Benches Bibliography

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List of Figures
1.1 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 3.1 3.2 3.3 3.4 3.5 4.1 4.2 A FPGA swapping modulation schemes. . . . . . . . . . . . . . . . . . . . . Block diagram of a typical software-dened radio. Illustration of a FPGA fabric. . . . . . . . . . . . Illustration of a Spartan3A slice. . . . . . . . . . Data ow through the USRP Platform. . . . . . GNU Radio Companion WBFM Receiver. . . . . A USRP and RF daughtercards. . . . . . . . . . Block diagram of the USRP. . . . . . . . . . . . . Data ow through the USRP. . . . . . . . . . . . Tx data ow through the USRP. . . . . . . . . . Rx data ow through the USRP. . . . . . . . . . A photograph of three CubeSats. . . . . . . . . . Organization of an XTEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 10 11 12 13 15 16 17 18 18 20 21 25 26 26 27 28 39 39

Block diagram of the COSMIAC FPGA board. . . . . . A photograph of the COSMIAC FPGA board. . . . . . A photograph of the COSMIAC CubeSat SDR system. . Block diagram of the COSMIAC RF daughtercard. . . . Block diagram of the proposed CubeSat SDR rmware.

Simulation of a read request FIFO. . . . . . . . . . . . . . . . . . . . . . . . Simulation of a read acknowledgement FIFO. . . . . . . . . . . . . . . . . .

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List of Tables
2.1 2.2 3.1 4.1 4.2 4.3 Comparison of microelectronic platforms for SDR. . . . . . . . . . . . . . . Some examples of SDR implementations. . . . . . . . . . . . . . . . . . . . USB endpoint conguration for the CubeSat SDR. . . . . . . . . . . . . . . Comparison of Cyclone EP1C12 and Spartan3A-1400. . . . . . . . . . . . . Hardware utilization for USRP modules. . . . . . . . . . . . . . . . . . . . . Hardware utilization for the USRP rmware. . . . . . . . . . . . . . . . . . 8 9 30 32 41 42

viii

List of Listings
4.1 4.2 4.3 4.4 4.5 4.6 4-to-1 Multiplexer in Verilog. . . . . . . . . . . . 4-to-1 Multiplexer in VHDL. . . . . . . . . . . . Verilog conguration code (common cong.vh). . VHDL conguration code (common cong.vhd). Example of a Verilog ternary operator. . . . . . . VHDL replacement for ternary operators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 35 36 36 37 38 46 47 52 54 56 57 58 61 63 66 68 70 71 72 73 75 76 77 78 81 82 85 86 89 94 95 102

A.1 acc.vhd . . . . . . . . . . . . A.2 adc interface.vhd . . . . . . . A.3 adc mux.vhd . . . . . . . . . A.4 atr delay.vhd . . . . . . . . . A.5 bidir reg.vhd . . . . . . . . . A.6 bustri.vhd . . . . . . . . . . . A.7 cic decim.vhd . . . . . . . . . A.8 cic dec shifter.vhd . . . . . . A.9 cic interp.vhd . . . . . . . . . A.10 cic int shifter.vhd . . . . . . . A.11 clk divider.vhd . . . . . . . . A.12 coe rom.vhd . . . . . . . . . A.13 common cong.vhd . . . . . . A.14 common cong 1rxhb 1tx.vhd A.15 common cong 2rxhb 0tx.vhd A.16 common cong 2rxhb 2tx.vhd A.17 common cong 2rx 0tx.vhd . A.18 common cong 4rx 0tx.vhd . A.19 cordic.vhd . . . . . . . . . . . A.20 cordic stage.vhd . . . . . . . A.21 fo.vhd . . . . . . . . . . . . A.22 fo 4k 18.vhd . . . . . . . . . A.23 fpga regs common.vhd . . . . A.24 fpga regs standard.vhd . . . . A.25 funcs.vhd . . . . . . . . . . . A.26 halfband decim.vhd . . . . . . A.27 io pins.vhd . . . . . . . . . .

ix A.28 master control.vhd A.29 mult.vhd . . . . . . A.30 phase acc.vhd . . . A.31 ram16.vhd . . . . . A.32 ram16 2sum.vhd . A.33 rssi.vhd . . . . . . A.34 rx buer.vhd . . . A.35 rx chain.vhd . . . . A.36 rx dcoset.vhd . . A.37 serial io.vhd . . . . A.38 setting reg.vhd . . A.39 sign extend.vhd . . A.40 strobe gen.vhd . . A.41 tx buer.vhd . . . A.42 tx chain.vhd . . . . A.43 usrp mux.vhd . . . A.44 usrp std.vhd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 112 113 115 116 118 120 126 130 132 135 136 137 138 143 144 146 160 171 173 175 177 179 180 183 184 186 188 189 191 193 195 199 202 204 207 208 211 213 215 219 222 224

B.1 COSMIAC FPGA Board Description (XBD) . . . . . . . . . . . . . . . . . C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 C.11 C.12 C.13 C.14 C.15 C.16 C.17 C.18 C.19 C.20 C.21 C.22 C.23 C.24 C.25 TB TB TB TB TB TB TB TB TB TB TB TB TB TB TB TB TB TB TB TB TB TB TB TB TB TB acc.vhd . . . . adc mux.vhd . . . atr delay.vhd . . . bidir reg.vhd . . . bustri.vhd . . . . . cic decim.vhd . . . cic dec shifter.vhd cic interp.vhd . . . cic int shifter.vhd clk divider.vhd . . coe rom.vhd . . . cordic.vhd . . . . cordic stage.vhd . fo.vhd . . . . . . io pins.vhd . . . . mult.vhd . . . . . phase acc.vhd . . ram16.vhd . . . . ram16 2sum.vhd . rssi.vhd . . . . . . rx dcoset.vhd . . serial io.vhd . . . setting reg.vhd . . sign extend.vhd . strobe gen.vhd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

x C.26 TB tx chain.vhd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.27 TB usrp mux.vhd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 228

Chapter 1

Introduction
1.1 Research Motivation

Traditionally, communication systems required specialized hardware to implement their functionality. In order to keep production costs low, these systems contained only the hardware necessary to perform the tasks that they were designed for. As a result, these systems were often dicult to modify and upgrade. Today, digital signal processor (DSP) technology has evolved to the point where many of the encoders, modulators, lters, and decoders used by these communication systems can be implemented in software[29]. Some systems rely on software to perform small tasks while others implement all of their baseband functionality in software. Those systems that implement all of their baseband functionality in software are called software-dened radios (SDRs) [42]. SDRs provide engineers with increased exibility, allowing them to implement any number of dierent signal processing elements without altering the system hardware. For example, an engineer might design a transceiver with support for 16-symbol quadrature amplitude modulation (16-QAM) and later update the transceivers software to support 32-QAM. With more traditional systems, such a change would require new modulation and demodulation hardware. In a SDR, this change might require changing only a few lines of C programming language code. While some SDRs use general-purpose processors or even digital signal processors, many

2 use a technology called eld-programmable gate arrays (FPGA). FPGAs consist primary of recongurable logic elements and a switch matrix to route signals between them. These devices can be congured to support simple logic operations, such as addition, or more complex systems, such as digital signal lters. In addition, some FPGAs support a technology called dynamic reconguration. Dynamic reconguration allows a system to swap components as needed, without any reprogramming, as Figure 1.1 shows.

Figure 1.1: A FPGA swapping modulation schemes. The dierent modulation schemes are stored in memory or in the FPGA logic elements and connected as needed. While not shown here, the other components in a FPGA-based SDR could also be recongurable.

The combination of SDR and FPGAs provides engineers and developers with a method for updating communication systems that are physically dicult to access, such as satellites. Using FPGA technology, one can design a satellite to support multiple digital signal processing blocks (such as modulation or source coding) and to swap them as needed [19][29]. Additionally, the rmware on an FPGA can be updated remotely to install new blocks and remove unused blocks, enabling a system to support new protocols while in orbit. These

3 features make FPGA-based SDRs an excellent platform for creating radios for satellites.

1.2

Current State of the Art

A wide variety of SDRs are available today, each optimized for dierent applications. Lyrtechs small form factor (SFF) SDR development platform incorporates advanced FPGA technology (Xilinx Virtex-4), a low-power general- purpose processor (TI MSP430), and multiple RF frontends to create an advanced development platform at the high cost of $9,900 [14]. Other platforms, such as the Wireless Open-Access Research Platform (WARP) from Rice University, provide similarly powerful, yet more aordable systems for academic use [20]. Finally, Ettus Research LLC produces the Universal Software Radio Peripheral (USRP) and the USRP2. These platforms contain less powerful hardware at a signicantly lower cost [16]. Additionally, they use open source hardware and software licenses, making them ideal for academic environments. Some SDRs are optimized for use in satellites. Vulcan Wireless Inc. has developed two such systems. The rst, CubeSat Software Dened Radio (CSR-SDR), provides access to a wide variety of communications protocols and a data rate of up to 10 Mbps at S-Band [19]. The second, Micro Blackbox Transponder, oers fewer protocols and a lower data rate [19]. These two systems support numerous S-Band frequencies (2-4 GHz) and work with a variety of communication protocols and encryption schemes [34]. Finally, these systems use the Space Plug-and-Play Avionics (SPA) protocol for plug and play functionality and the CubeSat small satellite form-factor. Unfortunately, neither system uses open source hardware or software. Therefore, researchers and engineers cannot adapt these systems to their needs, nor can they create derivative solutions from them. Another FPGA-based SDR optimized for the CubeSat form factor is the Firehose Adaptive Software Dened Radio, designed by Adaptive Radio Technologies LLC [39]. This system boasts features such as in ight reprogramming, and programmable transmit and receive paths. However, this SDR system does not support the SPA protocol for plug and play operation and, like the Vulcan Wireless systems, does not use open source hardware or software.

1.3

Research Objectives

The primary objective of this project is to develop an agile software-dened radio that can operate in a picosatellite known as a CubeSat [26]. Thus far, there is no standard communication protocol for CubeSats [31]. Each of the dozens of CubeSats successfully launched so far has used dierent baud rates, modulation schemes, and protocols. Many of the satellites use custom transceivers designed specically for one satellite. As a result, researchers have found it dicult to create base stations that can communicate with a variety of CubeSats. Indeed, only 797 MB of data had been received from CubeSats by the end of 2008, ve years after the initial CubeSat launch [31]. Employing SDRs in CubeSats could solve this problem and increase data throughput signicantly. The CubeSat SDR system should have the following characteristics: Recongurability. The system should be easily recongurable so that it can be used to support any number of encoding, modulation, or other signal processing schemes. In addition, it should support reprogramming post launch so that it can support new protocols. Small size. The system should t the dimensions for a 1U CubeSat, which are 10 10 10 cm, and should meet all other CubeSat standard requirements [26]. Plug and play. The system should use the Space Plug-and-Play Avionics (SPA) communication protocol [33] to allow engineers to include it in new projects with ease. Open Source. The system should consist of open source hardware and software so that other researchers and system designers can adapt it to t their projects and so that they can create derivative systems as needed. Space Ready. The system should not rely on any external processing elements that would not t into a CubeSat. Addition, because CubeSats orbit in low Earth orbit, they require radiation hardened components. Finally, the CubeSat SDR should be able to transmit and receive data on frequency bands suitable for an object in orbit, such as S-Band.

1.4

Thesis Contributions

This thesis presents an initial platform for the system described in Section 1.3. Specically, this thesis presents the following novel contributions: A control system for the Congurable Space Microsystem Innovations & Applications Center (COSMIAC) CubeSat FPGA board [6]. This hardware borrows ideas from the USRP and adapts them to operate in a CubeSat environment. The control system provides the glue that allows the FPGA, USB controller, memory devices, and RF frontend to communicate. A rewrite of the USRP rmware targeting Xilinx FPGA devices and using the VHSIC Hardware Description Language (VHDL). This new rmware is better than the original since it utilizes the safer VHDL language instead of Verilog, it contains more extensive source documentation, and it does not use any proprietary logic elements. A Xilinx board denition le that allows users to create new projects for the COSMIAC FPGA board using the Xilinx Embedded Developers Kit (EDK). This denition le species the inputs, outputs, and conguration parameters for each device on the FPGA board.

1.5

Thesis Organization

This thesis is organized as follows: Chapter 2 describes the USRP platform, its companion software GNU Radio, and the CubeSat small form-factor satellite design. Chapter 3 presents diagrams, ow charts, and descriptions of the COSMIAC FPGA board and the new control system. Chapter 4 details the transition from the original USRP rmware to the new, improved rmware. This chapter also contains simulation and synthesis results to verify the functional equivalence of the new platform. Finally, Chapter 5 oers concluding remarks and directions for future research.

Chapter 2

Software-Dened Radio and CubeSats

This chapter provides an introduction to the technologies utilized in this thesis, including software-dened radio (SDR), a SDR suite called GNU Radio, and the CubeSat satellite platform. GNU Radio is ideal for low-cost, recongurable SDR because it is free, opensource software and it works well with relatively inexpensive RF hardware. Moreover, GNU Radio possesses a very large user community that is actively and constantly improving this software. CubeSats are small satellites in which one might use such a SDR system.

2.1

Software-Dened Radio

Traditional radios consist entirely of specialized hardware. While these radios might employ software to handle certain internal operations (e.g. control of the analog-to-digital and digital-to-analog components), almost all of the signal processing remains in the hardware domain. A software-dened radio replaces the majority of the traditional radio hardware with software. Figure 2.1 shows a the typical data ow in a software-dened radio system [41]. In this system, nearly all of the baseband signal processing on both the transmission and receiving ends is performed in the software domain. Advances in microelectronic technology enable engineers to design smaller, more power

Figure 2.1: Block diagram of a typical software-dened radio. Everything in the digital domain is performed in software while everything in the analog domain remains hardware. ecient devices. Consistent with Moores Law [37], the number of transistors packed into a single integrated circuit has doubled approximately every two years [13]. SDR systems, which rely heavily on such integrated circuits, have followed a similar trend. The United States Military developed a software-dened radio system in the early 1990s that required four of the most powerful digital signal processors (DSP) available (the TMS320C40) and some FPGAs to glue them together. This system, known as SpeakEasy, lled the back of a truck [24]. By the time the engineers nished writing the software for SpeakEasy, three years had passed and the hardware in the system was already obsolete [24]. General purpose processors in the early 1990s had approximately 3.1 million transistors [13]. Today, the Intel Core i7 processors found in typical personal computers contain as many as 1,170 million transistors [11]. Similar advances in DSP and FPGA technology have enabled engineers to develop smaller SDR platforms. In addition, increased clock speeds [13] allow for faster than real-time processing of data. As a result, SDRs are capable of more complex coding and modulation schemes than they were in the past. Performing the baseband signal processing in the software domain allows for much greater recongurability than traditional radios provide. In addition, the cost of a softwaredened radio platform are often lower than those of a more traditional platform because

8 the software is reusable and often available at relatively low cost. Indeed, some SDR software is available for free under the GNU General Public License (GPL) [10]. These two characteristics make SDR ideal for reusable, plug and play systems, for systems that might be dicult to physically recongure, and for systems developed in academic environments. Software-dened radios have been employed on numerous platforms, including general purpose microprocessors (GPP), digital signal processors (DSP), and graphics processing units (GPU). General purpose microprocessors, such as the Intel and AMD devices commonly found in personal computers, are not specialized for any particular application. Therefore, they are very exible. However, SDR systems using GPPs are often wasteful since these processors are designed for speed and generality rather than power eciency or mathematical operations. Digital signal processors solve these two problems. DSPs, such as those manufactured by Texas Instruments, are specialized for performing mathematical operations and typically contain less hardware, increasing power eciency. On the other hand, their narrow focus makes them potentially slow for other applications. Finally, graphics processing units employ massively parallel architectures that are optimized for vector manipulations and other graphical operations. Such parallel designs are well-suited for signal processing, but GPUs are still relatively dicult to program and they are extremely power hungry.

Table 2.1: Comparison of microelectronic platforms for SDR.

Feature DSP Operations General Operations Flexibility Size Power Eciency Common Brands Programming Language GPP Moderate Good High Moderate Moderate Intel, AMD C, Java DSP Good Poor Low Small Good Texas Instruments C, Assembly GPU Good Poor Moderate Large Poor nVidia, AMD CUDA, C FPGA Good Poor High Large Moderate Xilinx, Altera Verilog, VHDL

A fourth option is the eld-programmable gate array (FPGA). FPGAs are recongurable logic devices that enable highly parallel implementations of digital signal processing

9 algorithms. They are becoming increasingly power ecient while simultaneously including specialized hardware for some DSP operations. In additional, they can be reprogrammed remotely. Due to these features, FPGAs make an ideal software-dened radio platform. Table 2.1 compares these four platforms and Table 2.2 highlights some SDR implementations that use them.

Table 2.2: Some examples of SDR implementations. System USRP1 [16] Lyrtech SFF SDR [12] Technology Cyclone EP1C12 FPGA GPP (o-board) Virtex-4 FPGA MSP430 Microprocessor TI DM6446 DSP 5 Virtex-II Pro FPGAs Virtex-II Pro FPGA Pentium-M Microprocessor Virtex-II Pro FPGA Spartan3A-DSP3400 FPGA Released 2005 2006

Berkeley BEE2 [27] Kansas U. Agile Radio [36] Rice University WARP [20] USRP N210 [16]

2007 2007 2008 2010

2.2

Field-Programmable Gate Arrays

FPGAs are recongurable digital logic devices. Like application specic integrated circuits (ASIC), they are often programmed with a hardware description language, such as Verilog or VHDL. However, unlike ASICs, FPGAs are designed to be reprogrammed multiple times to allow for rapid prototyping and system deployment. This technology makes them well-suited for SDR systems. While an FPGA-based SDR might not be as power ecient or as compact as a DSP-based system, it can be more exible. DSPs have a set instruction set and run executable code in the same manner than general purpose processors do. This means that only a xed number of operations can run simultaneously (usually one or two) and that computationally intensive functions can be slow to complete. On the other hand, FPGAs allow their users to dene what the system is capable of and provide resources for massive parallelization.

10 An FPGA consists primarily of congurable logic blocks (CLB) and a congurable switch matrix that connects them together. Other features of modern FPGAs include congurable I/O Banks (IOB) that support multiple digital I/O standards, block memories (BRAM) for faster ROMs and RAMs, and specialized hardware for multiplication and other DSP functions. Figure 2.2 shows part of a FPGA fabric. The Spartan3A-1400 used in this project contains 25,344 CLBs, 589,824 bits of BRAM, and 375 user-accessible I/O pins [3]. Not shown in Figure 2.2 is the network of clock signals that synchronizes the various elements in the device. The Spartan3A-1400 does not contain any DSP-specic hardware, though it does contain thirty-two 18 18 multipliers, also not shown in Figure 2.2.

Figure 2.2: Illustration of a FPGA fabric. Each of the intersections can be programmed to connect dierent IOB, BRAM, and CLB elements together. The design of each CLB varies from one FPGA to another. Figure 2.3 show a highlevel illustration of the CLBs found on the Spartan3A-1400 device [2]. The CLBs in Xilinx FPGAs are called slices. Each slice in the Spartan3A contains two 4-input lookup tables (LUT) that are used to implement digital logic designs. For example, one LUT might be used to implement a 2-bit adder circuit. Though not shown in Figure 2.3, slices contain additional signals to support such operations as carry (for addition) and bit shifting. The output of each LUT is only one bit, making a LUT similar to a 16x1 memory.

11

Figure 2.3: Illustration of a Spartan3A slice. Slices contain additional logic gates and signals that enable faster data paths, such as XOR gates and bypass signals. Some digital logic designs are described as sequential because data moves through them in stages. These designs require synchronous components, such as ip ops. Each slice in the Spartan3A FPGA contains two such ip ops, synchronized with the system-wide clock network. A slice also contains two multiplexers, one for each LUT/FF pair. These multiplexers ensure that each slice has only two output bits, one for each LUT operation. One particular software-dened radio system known as the Universal Software Radio Peripheral and its companion software, GNU Radio, combines FPGA technology with general purpose microprocessor technology. In this system, the FPGA performs interpolation and decimation while GNU Radio, running on a personal computer, performs all of the baseband signal processing.

2.3

GNU Radio and the USRP

The Universal Software Radio Peripheral Platform consists of the GNU Radio software, the libusrp software libraries, the USRP radio, and a wide variety of RF cards that attach to the USRP. Figure 2.4 shows the ow of data from the user to the point of transmission. Digital data rst passes through GNU Radio, where it is compressed, encoded, modulated,

12 and otherwise processed into its nal baseband form. Next, it passes through libusrp, which forms the communication link between a personal computer and the USRP. The data then travels via USB2 to the USRP, which upconverts to an intermediate frequency (IF) band and sends the data through the digital to analog converter. Finally, the data arrives at the RF card where it begins its journey through the air. On the receiving end, the data takes the same path in reverse.

Figure 2.4: Data ow through the USRP platform. GNU Radio and libusrp reside on a general-purpose computer, while the USRP and its RF daughtercards are custom radio hardware.

2.3.1

GNU Radio

GNU Radio is a free, open source software project, licensed under the GNU General Public License 3 (GPL3), that provides users with tools to prepare data for wireless transmission and to receive data from wireless channels. While the GNU Radio software could work with any SDR hardware in theory, it is ideally suited for use with the USRP. GNU Radio runs on the Linux and Windows operating systems and utilizes general-purpose processors to perform digital signal processing tasks. Applications for the GNU Radio platform use the Python scripting language to describe the ow of data through the system, creating ow graphs. These ow graphs connect data sources (e.g. les, microphones) to digital signal processing blocks (e.g. source encoders, modulators) and nally to data sinks (e.g. USRPs). Users can congure each of the blocks

13 in a ow graph to change the way the system operates. For example, one might include a modulation block and choose between BPSK, QPSK, 16-QAM, or another modulation scheme. In addition, GNU Radio provides users with tools such as Fast Fourier Transform sinks to analyze data. In an attempt to make GNU Radio easier to use, Josh Blum developed a graphical user interface (GUI) called GNU Radio Companion (GRC). GRC allows users to select premade blocks, adjust their variables with sliders and text elds, and connect them together with onscreen wires. Figure 2.5 shows a ow graph in GRC that receives wideband FM radio signals with a USRP, processes them, and then outputs them with a sound card [23].

Figure 2.5: A GNU Radio Companion ow graph for a wideband FM receiver. The arrows indicate the ow of data from the USRP to the sound card [23]. The ow graph shown in Figure 2.5 is stored as an XML le. When the user runs the ow graph shown in Figure 2.5, GNU Radio parses the XML le and uses it to create Python code that performs the signal processing operations described by the blocks in the ow graph. In this example, GNU Radio would generate a block to process wideband FM

14 data as well as the code needed to link this block to the USRP and the systems sound card. In addition, it would generate code for the blocks on the left side of Figure 2.5, which allow the user to adjust the frequency band to listen on and the volume of the audio output. Finally, it would generate a real time plot of the fast Fourier transform (FFT) of the incoming data. Data received on the USRPs antenna would go through the ADC, which translates it to an intermediate frequency, then pass through the USRP itself, which translates the data into baseband. The USRP then provides this data to the USB2 port, where libusrp picks it up in packets and passes it to GNU Radio. The USRP Source block in the ow graph lets GNU Radio know to expect data of this format. When GNU Radio receives the data, it passes it through the code blocks that it generated and then sends this processed data to the systems sound card, where it passes through a DAC and nally to the speaker output port. While this is a simple example, GNU Radio supports more complex systems, including transceivers.

2.3.2

USRP

Like GNU Radio, the USRP is entirely open source. The FPGA software is licensed under the GPL2 and the hardware schematics are all available online from Ettus Research [18]. Together, GNU Radio and the USRP provide a low-cost, open software-dened radio platform that permits experimentation and modication. For this reason, this thesis uses the USRP platform as the basis for the new CubeSat SDR. The USRP consists of a large motherboard, which contains an Altera Cyclone FPGA, a Cypress EZ-USB FX2 high-speed USB2 controller, two AD9862 mixed signal processors from Analog Devices, and four I/O headers for RF daughtercards. Transmission data enters the USRP via the USB2 controller, proceeds to the FPGA for interpolation, goes through the AD9862s digital-to-analog converter (DAC), and then nally makes its way to the RF daughtercard for wireless transmission. The RF daughtercards contain the antenna and supporting hardware. Figure 2.6 [32] shows a USRP board with three daughtercards attached and Figure 2.7 [41] shows a block diagram of the USRP system. Ettus Research also makes another SDR platform, the USRP2. This platform oers a

15

Figure 2.6: A USRP and RF daughtercards. The RFX2400 card contains one Tx RF frontend and one Rx RF frontend. The USRP supports up to four total RF frontends simultaneously with a maximum of two Tx and four Rx [32]. larger FPGA, 1 Gbps Ethernet connectivity, faster and more accurate ADCs and DACs, and greater RF bandwidth [16]. However, the cost of the USRP2 is approximately twice the cost of the USRP1 and the engineers at COSMIAC were more familiar with the USRP1 platform. For these reasons, this thesis uses the USRP1 as the basis for the initial CubeSat SDR prototype. The USRP exchanges data with the GNU Radio software via USB2. Data prepared for transmission rst passes through a USB2 controller and then enters the Tx FIFO, which holds 4,096 lines of 16-bit data. From there, the data passes through the Tx Chain (see Figure 2.9) and then to the AD9862, which converts it to analog signals suitable for RF transmission and passes it along to the RF card. Data received on the RF card rst enters the AD9862, which converts it to digital signals, then proceeds to the Rx Chain (see Figure 2.10). Next, this data enters the Rx FIFO (4, 096 16) while it waits for the USB2 controller to send it through to the GNU Radio software [30]. Figure 2.8 illustrates this process. As described in Section 2.3, the GNU Radio software handles all of the baseband signal

16

FX2 Micro-controller (USB Interface)

ADC 1A Receive Daughterboard (RXA Port) ADC 1B

ADC 2A Receive Daughterboard (RXB Port) ADC 2B

FPGA

DAC 1A Transmit Daughterboard (TXA Port) DAC 1B

DAC 2A Transmit Daughterboard (TXB Port) DAC 2B

Figure 2.7: Block diagram of the USRP. This particular USRP has two Tx boards and two Rx boards, but the system could support four Rx boards instead [41].

17

Figure 2.8: Data ow through the USRP. GNU Radio passes data to and from the USRP via the USB2 controller and the USRP handles the remaining signal processing. processing for outgoing data. The role of the USRP hardware is to transform these baseband signals into an intermediate frequency (IF) band and then present the result to the Analog Devices AD9862 mixed signal processor, which prepares it for the RF daughtercard. The USRP supports two complex transmitters and so does the new rmware. However, the CubeSat SDR uses only one complex transmitter. Therefore, the gures in this chapter will display only one transmission path. Figure 2.9 shows the transmission data path through the USRP (the Tx Chain in Figure 2.8). Each of the two signal components (I and Q) passes through a 4-stage cascaded integratorcomb (CIC) interpolator, which increases the number of data samples. This is necessary because the USB2 controller runs at a slower speed than the AD9862 requires. The rest of the upconversion process happens in the AD9862 mixed signal processor. Similarly, GNU Radio handles the baseband processing for incoming data. Thus, the role of the USRP is to receive digital data from the AD9862 processor and then downconvert that data to baseband for GNU Radio. The USRP supports two full receivers or four receivers without the halfband lters. Because the CubeSat SDR platform uses only one complex receiver, the gures in this chapter will display only one receive path. Figure 2.10 shows the receive data path through the USRP (the Rx Chain in Figure 2.8). Signals IN A and IN B, from the AD9862 DACs, rst proceed through a complex

18

Figure 2.9: Tx data ow through the USRP. The remainder of the digital upconversion process is handled by the AD9862.

Figure 2.10: Rx data ow through the USRP. The AD9862 does not provide a Cordic NCO on the receive path, so the FPGA does the conversion from IF band to baseband internally.

19 multiplier where the other two inputs are generated with a Cordic Numerically Controlled Oscillator (NCO), which transforms the signal from its IF band to baseband. From there, the signal passes through a 4-stage CIC decimator, which samples the incoming data, and then a halfband lter which eectively multiplies the decimation rate by two. These lters are needed to reduce the data rate to something that the USB2 controller can sustain.

2.4

CubeSats

A CubeSat is a small form-factor satellite conforming to the CubeSat specications published by California Polytechnic State University [26]. CubeSats are, as their name implies, cube shaped (see Figure 2.11 [8]). Each side is 10 cm, giving them a volume of precisely one liter, and the total weight of a CubeSat cannot exceed 1.33 kg. In addition to this 1U conguration, the CubeSat specications allow for 2U (10 10 20 cm) and 3U (10 10 30 cm) congurations. The CubeSat SDR was designed to t into a 1U CubeSat, though it is ideally utilized in a 2U or 3U conguration so that users can the include sensors and other instruments necessary for their satellites functionality. The majority of CubeSats are developed at academic institutions in countries all over the world [28]. These CubeSats contain CMOS cameras [17], gamma ray detectors [4], GPS receivers [5], and other scientic instruments and devices. A number of non-academic institutions have also designed and deployed CubeSats, including NASA [9] and The Boeing Company [25]. Most of the hardware in these systems consists of is commercially available o-the-shelf (COTS) components, making CubeSats an aordable way to perform experiments in space. However, the majority of CubeSats do not contain interchangeable parts. Instead, they are designed like Swiss watches, using dierent sensors, dierent power systems, and dierent radios [35]. To counter similar problems in other satellites, the Air Force Research Laboratorys Space Vehicle Directorate (AFRL/RV) developed a system that introduces the concept of plug and play components to satellites.

20

Figure 2.11: A photograph of three CubeSats at California Polytechnic State University. These satellites are ready for integration into the launcher system, called P-POD [8].

2.4.1

Space Plug-and-Play Avionics (SPA)

Space Play-and-Play Avionics (SPA) is a set of standards that combines common commercial standards, such as USB and Ethernet, with hardware and software extensions to create communications busses appropriate for use in modern, real-time embedded systems [33]. SPA treats each device in a satellite as a black box. What distinguishes SPA from other attempts at such a system is that each black box is self-describing [33]. This system comprises three primary components: XTEDs, ASIMs, and the SDM. XTEDs, or eXtended Transducer Electronic Datasheets, are XML documents that describe the inputs, outputs, and control variables for a component. Figure 2.12 illustrates the conceptual organization of XTEDs. These documents reside on ASIMs, or appliqu e sensor

21 interface modules. ASIMs function similarly to USB interface chips [35]. They encapsulate the XTEDs that describe the devices they are attached to and provide a SPA interface that allows their client device to communicate with the system. Finally, the SDM (satellite data model) acts as the overall system controller. Its main responsibilities including registering SPA devices and managing subscriptions to those devices [33] [35].

Figure 2.12: Organization of an XTEDs. Like any other XML document, an XTEDs combines user-dened properties and values to describe something. XTEDs are composed of atoms drawn from a common data dictionary (CCD). These atoms compose variables, variables compose message, and so on to form an XTEDs document [35].

SPA supports a number of dierent interfaces, including SPA-U (USB-based), SPA-E (Ethernet-based), SPA-1 (I2C-based), and SPA-S (Spacewire-based). The SPA-U interface is based on the USB 1.1 standard, which provides a 12 Mbps data bus, suitable for most satellite devices (e.g. sensors). As with USB, SPA-U uses the host, endpoint, and hub approach to connect devices together. Unlike USB, SPA-U hubs dynamically determine the direction of a connection. This allows for more complex topologies since any host or

22 endpoint can connect to any port [33]. Devices requiring higher data rates can use the SPA-S standard. SPA-S combines a Spacewire interface with a SPA-U connection. Spacewire is a European Space Agency (ESA) standard [15] that uses a peer-to-peer networking approach. Therefore, SPA-S does not have any hosts. Instead, SPA-S devices connect to a Spacewire router so that they can communicate with each other and to a SPA-U hub so that they can communicate with the rest of the system. Spacewire supports data rates as high as 200 Mbps. AFRL/RV adapted the SPA design to work with CubeSats in a system called CubeFlow. The CubeFlow system details the power and mechanical requirements for using SPA devices in a CubeSat. With such a system, plug and play CubeSats become easier to develop. One component well-suited to SPA and CubeFlow is the radio. Specically, a SPA-compatible software-dened radio would provide a common solution for CubeSats that was capable of adapting to the communication needs of those satellites.

2.5

Chapter Summary

Each of the CubeSats described in this chapter used dierent radio hardware. The goal of this thesis is to ease the development costs of future CubeSat designs by providing a exible, plug and play radio solution. Software-dened radio systems, SPA, and CubeFlow provide us with a cost-eective way to create such a system. One particular softwaredened radio, the Universal Software Radio Peripheral Platform (USRP and GNU Radio), is available at a low cost and consists entirely of open source software and hardware. These characteristics make it an ideal base from which to build the CubeSat SDR platform.

23

Chapter 3

COSMIAC CubeSat SDR System

Engineers at COSMIAC adapted the ideas of the USRP hardware to create a new FPGA board for the CubeSat SDR system. This board accepts daughtercards and an external power board, all of which t into a 1U CubeSat. This chapter presents the full CubeSat SDR system, including the FPGA board and additional FPGA rmware designs.

3.1

Hardware

Like the original USRP, the CubeSat SDR system uses two boards. The rst board contains the majority of the system functionality, including the USB2 controller and FPGA. The daughtercard contains the AD9862 and the RF frontend. Using this design, the CubeSat SDR system can support any number of RF frontends. However, the CubeSat SDR hardware contains a number of signicant changes from the original USRP hardware. Figure 3.1 shows a block diagram of the primary FPGA board [38]. The largest change to this hardware is the new Spartan3A-1400 FPGA, which replaces the Cyclone FPGA present on the USRP. For more information about this change, please refer to Chapter 4. The new FPGA provides more logic elements and I/O pins, which enabled the engineers at COSMIAC to add additional peripherals to the FPGA board. These peripherals include: NAND Flash Memory. The ash memory enables the system to store data through power cycles and to retain data without using power to keep volatile memory active

24 in a powered down state. Power can be dicult to come by in space. DDR2 Memory. This volatile memory can act as a cache for any softcore processors on the FPGA, enabling better performance. NOR Conguration Flash Memory. The NOR ash memory stores the FPGA conguration so that the system can reboot itself without attaching to a JTAG cable. AT90 Microcontoller and SPA Connectors. The AT90 microcontroller connects to the FPGA through three PIO ports. Its primary purpose is to enable plug and play functionality via the Space Plug-and-Play Avionics protocol. The AT90 holds conguration information for the FPGA board and provides this information to the primary operating system, which enables communication between dierent devices in a single CubeSat. The SPA-U connector works similar to USB and the SPA-1 connector like I2C. Ethernet Controller. The FPGA board supports a variety of daughtercards, some of which might communicate via Ethernet instead of USB. The CubeSat SDR system does not use this functionality. LEDs and Switches. The FPGA board contains eight LEDs and a pushbutton to aid with debugging. CubeSats are 10 10 cm on a side, limiting the space available for the FPGA board (see Figure 3.2 [38] and Figure 3.3 [7]). As a result, the Cypress FX2 EZ-USB2 controller present on the original USRP is replaced by a USB3300 USB2 controller on the CubeSat SDR board. The USB3300 oers much less functionality than the FX2. Section 3.2 describes the eects of this change in detail. The RF daughtercard mirrors the XCVR 2450 [16] daughtercard used with the original USRP. This card operates in the 2.4 GHz industrial, scientic, and medical (ISM) band, making it ideal for testing on Earth. Due to space limitations, the AD9862 mixed-signal processor and its associated circuitry were moved from the primary FPGA board to the RF daughtercard. This change makes RF daughtercards more expensive, but allows for other

25

Figure 3.1: Block diagram of the COSMIAC FPGA board. Note the lack of AD9862 processors, which reside instead on the RF daughtercards (see Figure 3.4. This design choice enables CubeSat engineers to design non-SDR systems with the same primary FPGA board [38].

26

Figure 3.2: A photograph of the COSMIAC FPGA board. The board sits on one side of the CubeSat enclosure and four others ank it. The RF card attaches to the two white connectors on the top and bottom of the board [38].

Figure 3.3: A photograph of the COSMIAC CubeSat SDR system. The bottom board is the FPGA board while the one on top is the RF daughtercard. The perpendicular board in the back provides power to the system. All three boards t into a 1U CubeSat [7].

27 peripherals on the primary FPGA board and lowers the cost for systems that do not use a RF daughtercard. Figure 3.4 shows a block diagram of the RF daughtercard currently used in the CubeSat SDR system [38].

Figure 3.4: Block diagram of the COSMIAC RF daughtercard. The AD9862 mixed-signal processors were moved to the daughtercard to make room for other devices on the primary FPGA board [38].

3.2

Software

With the new hardware components described in Section 3.1, the software in the CubeSat SDR system requires more functionality. Specically, the loss of the FX2 USB2 controller requires that the FPGA handle all of the data coming into and leaving the system. The FX2 USB2 controller contained a modern 8051 microprocessor, a full USB2 controller with direct memory access (DMA), RS232 controllers, and controllers for the SPI and I2C buses. The USB3300 chip that replaced it on the CubeSat SDR system contains only a partial USB2 controller. Figure 3.5 shows a block diagram of the proposed CubeSat SDR system design. At the

28

Figure 3.5: Block diagram of the proposed CubeSat SDR rmware. The MicroBlaze processor acts as the central control for all of the various communications blocks.

29 center of the system is the MicroBlaze softcore microprocessor. This processor acts as a trac mediator, guiding data between the USB2 port to the various other devices in the system. The SPI and I2C controllers provide users with a means of sending conguration information to the USRP and to the RF daughtercards. One of the RS232 controllers connects to an serial port on the board; the other connects to the AT90, which controls the ASIM for the device. The other components simply control the peripherals that give them their names (e.g. the DDR2 Memory Controller controls the DDR2 memory). Not shown in Figure 3.5 are the general purpose I/O modules for the LEDs. This design has many advantages. First, it uses well-tested components from Xilinx including the DDR2 memory controller, the SPI and I2C controllers, and the MicroBlaze microprocessor. Second, the Embedded Development Kit (EDK) software from Xilinx provides users with a relatively simple way to design MicroBlaze-based systems for custom hardware. With a Xilinx Board Description (XBD) le, one can quickly create new projects that contain controllers and connections for all of the hardware devices on the FPGA board. Appendix B contains the XBD le for the CubeSat SDR system. Finally, using a MicroBlaze processor to control the system allows one to write much of the logic in the C programming language. VHDL, as its name implies, was designed to describe hardware. Complex control systems can be very dicult to design in VHDL, but those same systems might be relatively simple when described as C programs. This proposed system does have two drawbacks. The majority of the components only work with the Xilinx toolset, so the system loses its platform independence. The Altera toolset has similar devices, such as the NIOS II processor, but these are not compatible with the Xilinx toolset. Thus, anyone wish to use the new USRP rmware in a larger system with Alteras tools could not use this proposed system. In addition, the USB2 controller is currently priced at $14,000 [22], a prohibitive cost for smaller organizations. Xilinx does oer free trial licenses, but a full license is necessary to operate the system without the JTAG connection. The proposed CubeSat SDR system should be compatible with GNU Radio with little, if any, modication. With proper conguration, the USB2 controller and the other devices in the system should be functionally equivalent to the original USRP design. To accomplish

30 this, users should consider two things. First, GNU Radio attempts to reprogram the FX2 USB2 controller and the FPGA every time it runs an application. For the CubeSat SDR system, this behavior is not desirable. Since GNU Radio is open source software, it should be easy to bypass this functionality. Second, the USB2 controller should be congured for the same three endpoints that the original USRP used. Table 3.1 describes this conguration [40].

Table 3.1: USB endpoint conguration for the CubeSat SDR. Endpoint 0 2 6 Function Control, SPI, I2C Tx Data to USRP Rx Data from USRP DMA No Yes Yes

3.3

Chapter Summary

This chapter describes the dierences between the USRP hardware and the CubeSat SDR system hardware. In addition, this chapter presents a proposal for a rmware that incorporates the new USRP adaptation into the overall CubeSat SDR system and explains the advantages and disadvantages of such a system. With the proposed rmware, the CubeSat SDR system should be compatible with the GNU Radio software, providing users with an easy way to test functionality.

31

Chapter 4

Proposed USRP Variant

This chapter introduces a new USRP rmware that is better suited to the needs of the CubeSat SDR system. This new rmware is functionally equivalent to the original USRP rmware, but does not rely on any platform-specic logic, benets from VHDLs strong typing, and contains signicantly more documentation. It is compatible with the original USRP system and the COSMIAC CubeSat SDR system.

4.1

Proposed USRP Firmware

While its advantages are numerous, the original USRP rmware has several drawbacks. First, it only works with Altera FPGAs and Altera tools. Second, it is written entirely in Verilog. Finally, it contains very little documentation. This chapter proposes a new USRP rmware that: Works on Xilinx FPGAs. In fact, this new USRP rmware works on any FPGA large enough to support it, including those from Altera. In addition, there are no proprietary components and so the design should work with any toolset. Is written in VHDL. The VHSIC Hardware Description Language (VHDL) is a standard for government, military, and other public sector projects. In addition, VHDL is a strongly typed language. That is, it uses explicit data types and conversion operations. As a result, VHDL oer an additional layer of safety in the design phase.

32 Contains extensive documentation. One of the benets of open source software is that other parties can modify and extend it to t their own needs. However, working with another persons code can be very dicult when that code contains little or no documentation. The original USRP rmware contains extensive high-level documentation on various websites, but the actual Verilog contains almost none. The proposed USRP rmware contains extensive documentation in the VHDL les. This new USRP rmware will provide for easier integration with other government and military applications, will allow future engineers to modify and extend it with ease, and will work on a larger collection of FPGA devices than the original. The USRP rmware contains almost all of the digital signal processing logic in the system as well as glue logic to control AD9862 mixed signal processor and the USB2 controller. These elements require a suciently powerful FPGA.

4.2

A New FPGA

The original USRP hardware uses an Altera Cyclone EP1C12Q240C8 FPGA. However, the rmware on this FPGA used 95% of the available resources [30]. Therefore, the engineers at COSMIAC opted to use a larger FPGA for the CubeSat SDR system. This new FPGA, the Xilinx Spartan3A-1400 (XCS1400A-5FG484), contains more logic cells, more internal random access memory (RAM), and more user I/O pins. Table 4.1 compares the two FPGAs [1] [3].

Table 4.1: Comparison of Cyclone EP1C12 and Spartan3A-1400. Logic Elements RAM Bits I/O Pins Cyclone EP1C12 12,060 239,616 173 Spartan3A-1400 25,3441 589,824 375

A Spartan3A slice consists of two 4-input lookup tables (LUTs) and 2 registers, while a Cyclone logic element contains only one of each. Thus, it is fair to say that one slice is worth approximately two logic elements. With this in mind, the Spartan3A-1400 would have 50,688 LEs.

33 Aside from providing additional resources, the largest aect of the switch in FPGA technology is the mandatory change in toolset. Altera supplies the Quartus II toolset for use with their FPGAs while Xilinx provides ISE. These toolsets provide similar functionality, but each has its own quirks. For example, each toolset provides tools to automatically generate VHDL through graphical user interfaces (GUI). However, these automatically generated les only work within their original environments. Unlike the original USRP, the CubeSat SDR system does not contain any platform-specic logic.

4.3

A New Language

The USRP rmware written by Ettus Research LLC used the Verilog hardware description language (HDL). As is true for many public sector projects, the sponsors of this thesis preferred the VHSIC HDL (VHDL). Therefore, the CubeSat SDR rmware is written in VHDL. Just as one might translate the text of a novel from German to English, once can translate Verilog logic descriptions into VHDL logic descriptions. This section describes the process of doing just that. Much of the original Verilog code was relatively straightforward to translate into VHDL. Since the logic is not changed, oftentimes translation is a matter of replacing one keyword with another and accounting for syntaxual dierences between the two languages. For example, consider the Verilog code in Listing 4.1. This code describes a 4-to-1 multiplexer where the four inputs are d1, d2, d3, and d4, the select signals are s(1:0), and the output is q. Listing 4.2 describes the same logic in VHDL. Note the similarities and dierences between the two. Both begin by declaring their inputs and outputs and both contain a case statement to implement the multiplexer logic. The Verilog module uses input and output to classify ports, while VHDL uses in and out. In VHDL, ports require a type specier, such as as std logic. Verilog does not require this, but it does require that we classify each port as a wire (connects two ports) or a reg (stores a value). In general, the VHDL code is more verbose. In order to facilitate testing, each VHDL module is port-compatible with its Verilog counterpart. This required changing the port names of some Verilog modules (e.g. ports

34

Listing 4.1: 4-to-1 Multiplexer in Verilog.

1

module mux4to1 ( input wire d1 , input wire d2 , input wire d3 , input wire d4 ,

2 3 4 5 6 7 8 9 10 11 12 13

input wire [ 1 : 0 ] s , output reg q ) ;

always @( d1 , d2 , d3 , d4 , s ) begin case ( s ) 0 : q = d1 ; 1 : q = d2 ; 2 : q = d3 ; 3 : q = d4 ; endcase end endmodule

called in or out, since these are reserved keywords in VHDL). Additionally, it required modifying any modules that did not synthesize properly in the Xilinx toolset. Using this method, one can test a single VHDL module in the original Verilog system and incrementally build a complete VHDL system. Some aspects of the translation were not as simple as replacing keywords and xing syntax. The following subsections describe these challenges.

4.3.1

Header Files

Verilog supports header les; VHDL does not. However, VHDL does support package les. Package les may contain constants, functions, and other declarations and can be included in any VHDL source le. Thus, the CubeSat SDR system uses a series of package les to replace the conguration headers of the original USRP rmware. The primary package le, common cong.vhd, includes a list of other package les that enable dierent transmit and receive congurations on the FPGA. The user may uncomment any one of these congurations and the common cong.vhd package handles the details.

35

Listing 4.2: 4-to-1 Multiplexer in VHDL.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

entity mux4to1 i s port ( d1 : in s t d l o g i c ; d2 : in s t d l o g i c ; d3 : in s t d l o g i c ; d4 : in s t d l o g i c ; s : in s t d l o g i c v e c t o r ( 1 downto 0 ) ; q : out s t d l o g i c ) ; end mux4to1 ;

architecture B e h a v i o r a l of mux4to1 i s begin process ( d1 , d2 , d3 , d4 , s ) begin case s i s when 00 => q <= d1 ; when 01 => q <= d2 ; when 10 => q <= d3 ; when others => q <= d4 ; end case ; end process ; end B e h a v i o r a l ;

One limitation of using package les to replace the headers is VHDLs lack of a preprocessor. Verilog has a preprocessor similar to the one used by ANSI C. It supports directives such as ifdef , endif, and include. Consider Listing 4.3, which shows part of the common cong.vh header le. This header checks to see if TX ON is dened (in another header le) and, if so, checks to see if it should congure one Tx channel or two. If TX SINGLE is dened, then TX EN 0 will also be dened and TX CAP NCHAN will have the value 001 (1). If TX DUAL is dened, then both TX EN 0 and TX EN 1 will be dened and TX CAP NCHAN will have the value 010 (2). These denitions will be used later to determine how many transmit paths to build on the FPGA. Unfortunately, VHDL does not have a preprocessor and package les do not handle conditional assignments like this. However, package les do support constants that are

36

Listing 4.3: Verilog conguration code (common cong.vh).

1 2 3 4 5 6 7 8 9 10 11 12 13

i f d e f TX ON

i f d e f TX SINGLE d e f i n e TX EN 0 d e f i n e TX CAP NCHAN 3 d1 endif

i f d e f TX DUAL d e f i n e TX EN 0 d e f i n e TX EN 1 d e f i n e TX CAP NCHAN 3 d2 endif endif

dened by logic statements. Listing 4.4 demonstrates the same conguration in VHDL. Note that the constants TX EN, TX EN 0, and TX EN 1 are always dened and that we use their values (true or false ) to determine which Tx paths to build rather than relying on future ifdef macros. Listing 4.4: VHDL conguration code (common cong.vhd).
1 2 3 4 5

constant TX EN : b o o l e a n := TX ON; constant TX EN 0 : b o o l e a n := (TX EN and (TX SINGLE or TX DUAL) ) ; constant TX EN 1 : b o o l e a n := (TX EN and TX DUAL) ; constant TX CAP NCHAN : s t d l o g i c v e c t o r ( 2 downto 0 ) := 0 & c o n v s t d l o g i c (TX EN and TX DUAL)

& c o n v s t d l o g i c (TX EN and TX SINGLE ) ) ;

37

4.3.2

Ternary Operators

Like C, Verilog supports a ternary operator, ?: . This operator is similar to if/else logic. For example, the statement assign q = a ? b : c; assigns the value of b to q if a is true, else it assigns the value of c to q. VHDL does not have such an operator. The original USRP rmware used the ternary operator nested three deep to create multiplexers. The easiest way to implement this functionality in VHDL is with if/else logic inside of a process statement. Thus, the Verilog code in Listing 4.5 becomes the VHDL in Listing 4.6. Listing 4.5: Example of a Verilog ternary operator.
1 2 3 4 5

q = mux [ 2 ] ? (mux [ 1 ] ? (mux [ 0 ] ? d3 : d2 ) : (mux [ 0 ] ? d1 : d0 ) ) : 1 b0 ;

Rather than replicating this code for each such multiplexer, the CubeSat SDR rmware contains new multiplexer components with equivalent logic. This results in cleaner code with less room for error at the cost of two additional source les (usrp mux.vhd, adc mux.vhd).

4.3.3

FIFO

The FIFO in the original USRP rmware has two problems. First, it does not synthesize in the Xilinx toolset. The FIFO was designed to work only in Alteras tools. Ettus Research included a vendor-independent FIFO with the USRP code, but it is not functionally equivalent to the original. Thus, the CubeSat SDR system has a new FIFO. This new FIFO is functionally equivalent to the Altera-specic FIFO and available in both VHDL and Verilog (see Listing A.21 for the VHDL version). The second problem with the original FIFO is that it used a read acknowledge model, which outputs the rst data line immediately and switches to the next line after the rising edge of the rdclk (read clock) signal. The problem with this model is that it does not provide a clock for reading data and, therefore, cannot be implemented in block RAM

38

Listing 4.6: VHDL replacement for ternary operators.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

process (mux , d0 , d1 , d2 , d3 ) begin i f (mux( 2 ) = 1 ) then i f (mux( 1 ) = 1 ) then i f (mux( 0 ) = 1 ) then q <= d3 ; else q <= d2 ; end i f ; else i f (mux( 0 ) = 1 ) then q <= d1 ; else q <= d0 ; end i f ; end i f ; else q <= 0 ; end i f ; end process ;

(BRAM). Implementing the read ack FIFO in the FPGA fabric with LUTs is possible, but the two 4096 16-bit FIFOs used in the USRP require more LUTs than the Spartan3A1400 provides. Instead, the new FIFO uses a read request model. In this model, the FIFO does not output any data until the rising edge of the rdclk signal. This FIFO can be implemented in BRAM and ts on the Spartan3A-1400. Figure 4.1 shows a simulation of the read request FIFO. At 20 ns, the write request signal (wrreq) goes high, pushing the value 3855 into the FIFO. For the next three clock cycles, the simulation writes -3856, -13108, and 13107 into the FIFO. At 60 ns, the read request signal (rdreq) goes high and asks to read the rst value pushed into the FIFO.

39 This value appears at 70 ns. For the next three clock cycles, the FIFO continues to output its stored values in the order that they were pushed. At 110 ns, the output q is undened because all values have been read from the FIFO.

Figure 4.1: Simulation of a read request FIFO. Note that the data on bus q is not available until one clock after the rdreq signal is pulled high.

Figure 4.2: Simulation of a read acknowledgement FIFO. Note that the data bus q is available one clock after the rst write and that this output remains until one clock after the rdreq signal is pulled high. Figure 4.2 shows a simulation of the read ack FIFO. As in Figure 4.1, the simulation begins pushing four values into the system at 20 ns. However, notice that the rst value is available on the next clock cycle (30 ns). This value remains on the output bus (q) until the rdreq signal goes high, acknowledging that the output was read. Thus, outputs with this model are read one clock earlier than they are with the other model. The original USRP

40 rmware used this second model, but supported the read request model as an option. Due to space and speed constraints, the read request model is used in the new rmware.

4.4

Synthesis Results

If the two USRP rmwares are logically equivalent, then their hardware usage should be very similar. Table 4.2 shows the hardware usage for each module in the USRP rmware as well as the maximum supported clock speed for that module. Emphasized modules have dierences in hardware usage between the two rmware versions. These results were generated with the 64-bit version of Xilinx ISE 12.3 for the Spartan3A-1400FG484-5 FPGA and are the estimated values reported by that software. The Verilog rmware contains some minor modications to make it compatible with the Xilinx synthesis tools. As Table 4.2 shows, most of the modules have identical hardware usage and maximum clock rates. However, a small set of modules do not match. The cic interp, tx chain, tx buer, and cic dec shifter all have dierences of only one slice of LUT. Since the synthesis outputs and simulations for these modules match, the dierences are likely caused by the manner in which Xilinx XST interprets the two HDLs. The same is probably true for rx dcoset, which diers only in maximum clock speed. While the two HDLs are capable of describing the same logic, the synthesis tool is responsible for choosing how to map that logic. Thus, two modules may be functionally identical even though their hardware usage diers. Other modules have more signicant dierences. In all of these cases, the synthesis tool nds the same quantities and types of logic elements and all tests (see Appendix C) show functional equivalence. However, it is possible to describe a logic function in more than one way and these dierent descriptions might be mapped dierently by Xilinx XST. For example, the VHDL version of the halfband decim module uses an accumulator instead of a simple adder. The functionality is the same and the source code very similar, but Xilinx XST infers an accumulator in the VHDL code and an adder in the Verilog code. Often, these dierences propagate to higher level modules. In this case, the dierence in halfband decim propagates upward to the rx chain.

41

Table 4.2: Hardware utilization for USRP modules.

Module bustri setting reg serial io fo fo 4k 18 bidir reg io pins cic int shifter sign extend cic interp tx chain tx buer rx buer coe rom ram16 2sum ram16 mult acc halfband decim cic dec shifter cic decim cordic stage cordic phase acc rx chain rx dcoset rssi adc interface strobe gen clk divider atr delay master control VHDL LUTs BRAMs 1 0 4 0 258 0 44 1 54 5 16 0 134 0 156 0 0 0 437 0 842 0 77 5 287 5 14 0 113 0 32 0 1 0 35 0 325 0 263 0 616 0 49 0 678 0 68 0 2577 0 106 0 104 0 1100 0 23 0 31 0 57 0 542 0 Verilog LUTs BRAMs 1 0 4 0 258 0 44 1 54 5 16 0 134 0 156 0 0 0 437 0 842 0 76 5 301 5 14 0 97 0 32 0 1 0 35 0 291 0 262 0 601 0 49 0 678 0 68 0 2475 0 106 0 104 0 1096 0 23 0 31 0 57 0 542 0

Flip Flops 0 0 52 40 48 0 64 0 0 383 766 144 191 0 48 16 0 34 118 0 580 0 659 64 2087 32 52 533 8 9 14 412

Slices 1 2 137 23 28 0 41 81 0 284 565 88 191 8 76 16 1 18 169 152 379 24 359 53 1464 56 55 573 12 15 30 316

Max Clock (MHz) 167.972 284.953 263.866 603.883 192.569 192.569 198.275 120.049 143.432 510.204 203.544 138.383 177.055 218.759 172.831 138.383 84.72 143.981 83.974 231.463 221.21 192.897 192.897

Flip Flops 0 0 52 40 48 0 64 0 0 383 766 144 191 0 48 16 0 34 118 0 580 0 659 64 2087 32 52 533 8 9 14 412

Slices 1 2 137 23 28 0 41 81 0 285 566 87 171 8 67 16 1 18 150 151 381 24 359 53 1455 56 55 571 12 15 30 316

Max Clock (MHz) 167.972 284.953 263.866 603.883 192.569 192.569 198.275 120.049 144.489 510.204 203.544 139.367 177.055 218.759 172.831 139.367 74.384 143.981 73.492 231.463 221.21 192.897 192.897

42 Each of the modules in Table 4.2 is a submodule of the usrp std module. Table 4.3 presents three dierent implementations of this top-level module. The rst implementation consists of only VHDL code and the second consists of only Verilog code. The nal implementation uses a Verilog top-level module with purely VHDL submodules. This third implementation shows two things. First, the synthesis dierences between the pure VHDL implementation and the hybrid implementation are minimal and likely a result of XST producing a dierent mapping with equivalent logic and timing. Second, it shows that the system is capable of supporting a mix of VHDL and Verilog modules.

Table 4.3: Hardware utilization for the USRP rmware. Logic Type Slices Flip Flops 4-Input LUTs I/O Buers Block RAMs 1818 Multipliers Clock Buers VHDL No. Used % used 3197 28 4,068 18 5,467 24 173 46 10 31 2 6 3 12 Verilog No. Used % used 3,164 18 4068 28 5,360 23 173 46 10 31 2 6 3 12 Hybrid No. Used % used 3,200 28 4,068 18 5,467 24 173 46 10 31 2 6 3 12

4.5

Chapter Summary

This chapter presented a new rmware for the CubeSat SDR systems USRP and discussed the challenges of targeting a dierent platform and using a dierent language, including the need to work around missing language features, to overcome toolset limitations, and to rewrite some modules. Finally, this chapter included some simulations and synthesis results to show the functional equivalence and hardware usage of the two dierent rmwares.

43

Chapter 5

Conclusions
5.1 Summary and Accomplishments

This thesis presented a exible, plug and play software-dened radio system for CubeSat form-factor satellites. Based on the USRP, this new CubeSat SDR provides CubeSat engineers with an easy to use SDR that is compatible with the GNU Radio software and the Space Plug-and-Play Avionics (SPA) protocol. The new adaptation of the USRP rmware is written in VHDL, instead of Verilog, and contains much more documentation than the original. Each module in the system is portcompatible with and functionally equivalent to its Verilog counterpart from the original USRP rmware. Thus, future users will be able to modify small parts of the system and test them with ease. Further, USRP users could choose to use the new VHDL rmware instead of the Verilog version if it better suits their needs. Like the original, this new rmware is free and open source. The proposed CubeSat SDR system incorporates this rmware into a larger system that replaces the original USRP hardware with a design that ts into a 1U CubeSat. This new hardware maintains the interchangeable RF frontend design, allowing future users to adapt the system to various projects. The combination of hardware, software, and rmware described in this thesis results in a USRP-like system that is compatible with the GNU Radio software, a free SDR design and testing platform.

44

5.2

Future Work

The CubeSat SDR system could benet from further research and design. Some possible areas of exploration include: Migrate to the Spartan6 FPGA. The current Spartan3A-1400 FPGA provides more resources than the original Cyclone FPGA, but it does not provide enough RAM bits to support the large FIFOs and the numerous peripheral controllers in the CubeSat SDR system. The Spartan6 FPGA provides more logic elements, RAM, and I/O capabilities. Further, it was designed as a drop-in replacement for the Spartan3. Migrating to the Spartan6 FPGA would be a relatively simple way to improve numerous aspects of the CubeSat SDR system. Replace the USB2 controller. The current USB2 controller, the USB3300, is significantly inferior to the original Cypress FX2 controller present on the USRP. As a result, a signicant portion of the FPGA is used to supply this lost functionality. With the FX2, future users would have far more space on the FPGA for custom designs. In addition, they would not need to license the rather expensive USB2 IP core from Xilinx. Improve the memory. The CubeSat SDR system has three types of memory that the original USRP lacked. However, these memories are not ideal. The DDR2 memory controller is especially complicated and requires very specic timing constraints. Such controllers are often expensive, hard to use, or both. The NOR ash conguration memory is too small to t the CubeSat SDR rmware. This memory should be larger. Adapt the USRP2. Instead of xing the problems with the current USRP1-based system, respin the CubeSat as a USRP2 adaptation. The USRP2 was designed to work with Xilinx FPGAs and already include a MicroBlaze, memories, and many of the other components that the CubeSat SDR system requires. In addition, it uses Gigabit Ethernet instead of USB2, simplifying the controller design while simultaneously providing higher throughput. One downside to this approach is that the USRP2 is described in Verilog.

45 Eliminate GNU Radio. Regardless of which platform the CubeSat SDR system is based on, GNU radio needs to go. GNU Radio runs on general-purpose personal computers. Such computers would not t into a CubeSat. Therefore, the dependency on GNU Radio needs to go. Instead of using Python or an XML-based GUI to describe digital signal processing operations, a similar system that produces VHDL components and connects them together would add signicant value to the CubeSat SDR system.

46

Appendix A

USRP Code
This appendix presents the VHDL source code for the CubeSat SDR systems USRP rmware, as described in Chapter 4. All of the code listed in this appendix is licensed under the GNU General Public License version 2 (GPL2). Listing A.1: Accumulator module, used with the mult module to create a multiply accumulator (MAC). (acc.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 A c c u m u l a t o r L a s t C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA This pr ogr am is distributed in the hope even that the it will be useful , of the b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License without implied warranty See This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c later version . L ic e n s e as the published C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows . M o d i f i e d : 21 J u l y 2010 Steve Olivieri VHDL A u t h o r :

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

47

29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC SIGNED . ALL ; l i b r a r y WOR K; use WOR K. FUNCS . ALL ; entity acc port ( clock reset clear enable in enable out addend sum ); end a c c ; architecture b e h a v i o r a l si g na l addend t s i g n a l su m t begin a d d e n d t <= c o n v s i g n e d ( c o n v i n t e g e r ( addend ) , 3 1 ) ; sum <= c o n v s t d l o g i c v e c t o r ( su m t ) ; W or kin g w i t h SXT i s we n e e d h a p p y . sign lots signed extend , of logic but it vectors only i n VHDL r e a l l y , really sucks . So , tools : : of acc : : in : : : : out in : out in in in std logic ; std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 3 0 downto 0 ) ; s t d l o g i c v e c t o r ( 3 3 downto 0 )

is

is

s i g n e d ( 3 0 downto 0 ) ;

s i g n e d ( 3 3 downto 0 ) ;

w o r k s on

std logic vector . synthesis I

conversion this in

operators

t o make t h e :)

In Verilog , functions

i s much s i m p l e r ! t h e FUNCS p a c k a g e .

For now ,

w r o t e new

c o n v e r s i o n pro c e ss ( c l o c k ) begin

i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( r e s e t = 1 ) then su m t <= ( o the rs = > 0 ) ; e l s i f ( c l e a r = 1 ) then su m t <= c o n v s i g n e d ( s x t ( c o n v s t d l o g i c v e c t o r ( a d d e n d t ) , 3 4 ) ) ; e l s i f ( e n a b l e i n = 1 ) then su m t <= su m t + c o n v s i g n e d ( s x t ( c o n v s t d l o g i c v e c t o r ( a d d e n d t ) , 3 4 ) ) ; end i f ; end i f ; end pro c e ss ; pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then e n a b l e o u t <= e n a b l e i n ; end i f ; end pro c e ss ; end b e h a v i o r a l ;

Listing A.2: ADC interface module to control the AD9862 mixed signal processor. (adc interface.vhd)
1

48

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

ADC I n t e r f a c e L a s t C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t You s h o u l d along with have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free License write Software 02110 1301 USA This pr ogr am is distributed in the hope even that the it will be useful , of This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows . M o d i f i e d : 20 J u l y 2010 Steve Olivieri VHDL A u t h o r :

under

terms

t h e GNU G e n e r a l P u b l i c later version .

L ic e n s e as the

published

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

the

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; l i b r a r y WOR K; use WOR K.FPGA REGS COMMON. ALL ; use WOR K. FPGA REGS STANDARD . ALL ; use WOR K.COMMON CONFIG . ALL ; FIXME S h o u l d we do entity a d c i n t e r f a c e port ( clock reset enable serial addr serial data serial strobe rx a a rx b a rx a b rx b b rssi 0 rssi 1 rssi 2 rssi 3 ddc0 in i ddc0 in q ddc1 in i ddc1 in q : : : : : : : : : : in in in in in in in in in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; this?

is

: out : out : out : out : out : out : out : out

49

59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 );

ddc2 in i ddc2 in q ddc3 in i ddc3 in q rx numchan

: out : out : out : out : out

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 )

end a d c i n t e r f a c e ; architecture b e h a v i o r a l g e ne ri c ( my addr : ); port ( clock reset strobe ad d r d in d out ch an ged ); end component ; : : : : : in in in in in std logic ; std logic ; std logic ; std logic vector ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic i n t e g e r := 0 adc interface is

of

is

component s e t t i n g r e g

: out : out

component r x d c o f f s e t g e ne ri c ( MYADDR : );

is

i n t e g e r := 0

port ( clock enable reset adc in adc out serial addr serial data serial strobe ); end component ; : : : : in in in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic

: out : : : in in in

component r s s i port ( clock reset enable ad c rssi

is

: : : :

in in in in

std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 )

: out : out

over count ); end component ;

component adc mux i s port ( clock rx realsignals : : in in std logic ; std logic ;

50

116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 signal begin );

ddc mux adc3 corr adc2 corr adc1 corr adc0 corr ddc i ddc q end component ; B u f f e r s s i g n a l ad c0 s i g n a l ad c1 s i g n a l ad c2 s i g n a l ad c3 : : : :

: : : : :

in in in in in

s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 )

: out : out

s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; : s t d l o g i c v e c t o r ( 3 downto 0 ) ; : : : : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

signal dco en

signal adc0 corr signal adc1 corr signal adc2 corr signal adc3 corr s i g n a l ddc0mux : s i g n a l ddc1mux : s i g n a l ddc2mux : s i g n a l ddc3mux :

s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; : std logic ;

rx realsignals

B u f f e r

at

the

inputs

to

the

chip .

pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then ad c0 <= r x a a ; ad c1 <= r x b a ; ad c2 <= r x a b ; ad c3 <= r x b b ; end i f ; end pro c e ss ; Then s c a l e sr dco en : and s u b t r a c t DC o f f s e t .

setting reg reset = > reset , strobe = > serial strobe , ad d r = > serial addr , ch an ged

> FR DC OFFSET CL EN ) g e ne ri c map( my addr = port map ( c l o c k = > clock , > serial data , d in = = > O PEN) ; d o u t ( 3 1 downto 4 ) = > OPEN, d o u t ( 3 downto 0 ) = > dco en ,

rx dcoffset0

rx dcoffset enable = > dco en ( 0 ) , reset = > reset , adc in (15) = > ad c0 ( 1 1 ) ,

g e ne ri c map(MYADDR = > FR ADC OFFSET 0 ) port map ( c l o c k = > clock , a d c i n ( 1 4 downto 3 ) = > adc0 , > serial addr , serial addr = serial strobe ) ; a d c i n ( 2 downto 0 ) = > 000 , a d c o u t = > adc0 corr , serial data = > serial data , serial strobe = >

167 168 169 170 rx dcoffset1 : rx dcoffset enable = > dco en ( 1 ) , reset = > reset , adc in (15) = > ad c1 ( 1 1 ) , g e ne ri c map(MYADDR = > FR ADC OFFSET 1 ) port map ( c l o c k = > clock ,

51

171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 L e v e l

> adc1 , a d c i n ( 1 4 downto 3 ) = serial addr = > serial addr , serial strobe ) ; rx dcoffset2 : rx dcoffset

a d c i n ( 2 downto 0 ) = > 000 , a d c o u t = > adc1 corr , serial data = > serial data , serial strobe = >

g e ne ri c map(MYADDR = > FR ADC OFFSET 2 ) port map ( c l o c k = > clock , enable = > dco en ( 2 ) , reset = > reset , adc in (15) = > ad c2 ( 1 1 ) ,

> adc2 , a d c i n ( 1 4 downto 3 ) = serial addr = > serial addr , serial strobe ) ; rx dcoffset3 : rx dcoffset

a d c i n ( 2 downto 0 ) = > 000 , a d c o u t = > adc2 corr , serial data = > serial data , serial strobe = >

g e ne ri c map(MYADDR = > FR ADC OFFSET 3 ) port map ( c l o c k = > clock , enable = > dco en ( 3 ) , reset = > reset , adc in (15) = > ad c3 ( 1 1 ) , > adc3 , a d c i n ( 1 4 downto 3 ) = serial addr = > serial addr , serial strobe ) ; a d c i n ( 2 downto 0 ) = > 000 , a d c o u t = > adc3 corr , serial data = > serial data , serial strobe = >

sensing :

f o r AGC reset = > reset , enable = > enable , ad c = > adc0 , rssi = > r s s i 0 (15

rssi block 0

rssi

port map ( c l o c k = > clock , downto 0 ) ,

> r s s i 0 ( 3 1 downto 1 6 ) ) ; over count =

rssi block 1

rssi reset = > reset , enable = > enable , ad c = > adc1 , rssi = > r s s i 1 (15

port map ( c l o c k = > clock , downto 0 ) ,

over count = > r s s i 1 ( 3 1 downto 1 6 ) ) ;

rssi block 2

rssi reset = > reset , enable = > enable , ad c = > adc2 , rssi = > r s s i 2 (15

port map ( c l o c k = > clock , downto 0 ) ,

over count = > r s s i 2 ( 3 1 downto 1 6 ) ) ; rssi block 3 : rssi reset = > reset , enable = > enable , ad c = > adc3 , rssi = > r s s i 3 (15

port map ( c l o c k = > clock , downto 0 ) ,

over count = > r s s i 3 ( 3 1 downto 1 6 ) ) ; And MUX t o sr rxmux : the appropriate outputs .

setting reg

g e ne ri c map( my addr = > FR RX MUX) port map ( c l o c k = > clock , d in = > serial data , ddc0mux , d out ( 3 ) = > rx realsignals , O PEN) ; d o u t ( 2 downto 0 ) = > rx numchan ( 3 downto 1 ) , ch an ged = > reset = > reset , strobe = > serial strobe , ad d r = > serial addr , d o u t ( 7 downto 4 ) = > d o u t ( 3 1 downto 2 0 ) = > OPEN, d o u t ( 1 9 downto 1 6 ) = > ddc3mux ,

> ddc2mux , d o u t ( 1 5 downto 1 2 ) =

d o u t ( 1 1 downto 8 ) = > ddc1mux ,

210 211 212 213 214 215 216 217 VHDL r e a l l y rx en 0 t : needs to start using ternary operators ! ?: is awesome , this is ugly . rx numchan ( 0 ) <= 0 ;

i f ( RX EN 0 )

generate rx realsignals = > r x r e a l s i g n a l s , ddc mux = > ddc0mux , adc2 corr = > adc2 corr , adc1 corr = > adc1 corr , adc0 corr

adc mux0 : adc mux port map ( c l o c k = > clock , = > adc0 corr , adc3 corr = > adc3 corr ,

52

218 219 220 221 222 223 224 225 226 227 228 229 rx en 1 t : en d rx en 0 f : en d generate

> ddc0 in i , ddc i = rx en 0 t ; i f ( n o t RX EN 0 )

ddc q = > ddc0 in q ) ;

generate

d d c 0 i n i <= ( o t h e r s => 0 ) ; d d c 0 i n q <= ( o t h e r s => 0 ) ; generate rx en 0 f ; i f ( RX EN 1 ) generate rx realsignals = > r x r e a l s i g n a l s , ddc mux = > ddc1mux , adc2 corr = > adc2 corr , adc1 corr = > adc1 corr , adc0 corr

adc mux1 : adc mux port map ( c l o c k = > clock , adc3 corr = > adc3 corr , = > adc0 corr ,

230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 en d rx en 3 f : en d generate rx en 3 t : en d rx en 2 f : en d generate rx en 2 t : en d rx en 1 f : en d generate

ddc i = > ddc1 in i , rx en 1 t ; i f ( n o t RX EN 1 )

ddc q = > ddc1 in q ) ;

generate

d d c 1 i n i <= ( o t h e r s => 0 ) ; d d c 1 i n q <= ( o t h e r s => 0 ) ; generate rx en 1 f ; i f ( RX EN 2 ) generate > r x r e a l s i g n a l s , ddc mux = > ddc2mux , rx realsignals = adc2 corr = > adc2 corr , adc1 corr = > adc1 corr , adc0 corr

adc mux2 : adc mux port map ( c l o c k = > clock ,

adc3 corr = > adc3 corr , = > adc0 corr , ddc i = > ddc2 in i , rx en 2 t ;

ddc q = > ddc2 in q ) ;

i f ( n o t RX EN 2 )

generate

d d c 2 i n i <= ( o t h e r s => 0 ) ; d d c 2 i n q <= ( o t h e r s => 0 ) ; generate rx en 2 f ; i f ( RX EN 3 ) generate

adc mux3 : adc mux port map ( c l o c k = > clock , = > adc0 corr , ddc i = > ddc3 in i , rx en 3 t ; ddc q = > ddc3 in q ) ; rx realsignals = > r x r e a l s i g n a l s , ddc mux = > ddc3mux , adc2 corr = > adc2 corr , adc1 corr = > adc1 corr , adc0 corr > adc3 corr , adc3 corr =

i f ( n o t RX EN 3 )

generate

d d c 3 i n i <= ( o t h e r s => 0 ) ; d d c 3 i n q <= ( o t h e r s => 0 ) ; generate rx en 3 f ;

end b e h a v i o r a l ;

Listing A.3: Multiplexer for the adc interface module that replaces a large ternary expression from the original Verilog source. No Verilog version exists. (adc mux.vhd)
1 2 3 4 5 6 S p e c i a l MUX f o r ADC S i g n a l s L a s t C o p y r i g h t (C) 2010 COSMIAC M o d i f i e d : 20 J u l y 2010 Steve Olivieri VHDL A u t h o r :

53

7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

You s h o u l d along with have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free License This pr ogr am is distributed in the hope even that the it will be useful , of the This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c later version . L ic e n s e as the published

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

write

Software 02110 1301 USA

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

The o r i g i n a l V e r i l o g , this V e r i l o g USRP1 c o n t a i n s no logic is trivial to equivalent with for the this com pon en t . ?: In

implement

ternary

operator .

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; e n t i t y adc mux i s port ( clock rx realsignals ddc mux adc3 corr adc2 corr adc1 corr adc0 corr ddc i ddc q ); end adc mux ; architecture b e h a v i o r a l begin F i r s t , pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( ddc mux ( 1 ) = 1 ) then i f ( ddc mux ( 0 ) = 1 ) then d d c i <= a d c 3 c o r r ; else d d c i <= a d c 2 c o r r ; end i f ; else i f ( ddc mux ( 0 ) = 1 ) then d d c i <= a d c 1 c o r r ; else : take care of ddc i . The e q u i v a l e n t Verilog statement is : o f adc mux i s : : : : : : in in in in in in : in std logic ; std logic ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; : out : out s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 )

d d c i = ddc m u x [ 1 ]

? ( ddc m u x [ 0 ] ? a d c 3 c o r r : : adc2 corr ) adc0 corr ) ;

( ddc m u x [ 0 ] ? a d c 1 c o r r

54

64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 end i f ; end pro c e ss ; end b e h a v i o r a l ; end i f ; else else Now , pro c e ss ( c l o c k ) begin take end i f ; end pro c e ss ; end i f ;

d d c i <= a d c 0 c o r r ; end i f ;

care

of

ddc q . :

The e q u i v a l e n t ? 1 6 b0 ddc m u x [ 3 ]

Verilog

statement

is :

ddc q = r x r e a l s i g n a l s

? ( ddc m u x [ 2 ] ? a d c 3 c o r r : : : adc2 corr ) adc0 corr ) ; ( ddc m u x [ 2 ] ? a d c 1 c o r r

i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( r x r e a l s i g n a l s = 1 ) then > 0 ) ; d d c q <= ( o the rs =

i f ( ddc mux ( 3 ) = 1 ) then i f ( ddc mux ( 2 ) = 1 ) then d d c q <= a d c 3 c o r r ; else d d c q <= a d c 2 c o r r ; end i f ;

i f ( ddc mux ( 2 ) = 1 ) then d d c q <= a d c 1 c o r r ; else d d c q <= a d c 0 c o r r ; end i f ; end i f ;

Listing A.4: Auto transmit/receive switch that adds a congurable delay when switching from transmit to receive or from receive to transmit. (atr delay.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ATR D e l a y L a s t C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c later version . L ic e n s e as the published C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows . M o d i f i e d : 21 J u l y 2010 Steve Olivieri VHDL A u t h o r :

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

55

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

This

pr ogr am

is

distributed

in

the

hope even

that the

it

will

be

useful , of the

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c You s h o u l d along with have this License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more of details .

r e c e i v e d a copy pr ogr am ; if n ot ,

t h e GNU G e n e r a l P u b l i c to the Free

License

write

Software 02110 1301 USA

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; entity a t r d e l a y port ( clk i rst i ena i tx empty i tx delay i rx delay i atr tx o ); end a t r d e l a y ; Auto T r a n s m i t / R e c e i v e o r fr om Rx t o Tx . Switch . Adds a d e l a y when as a is multiple of switching clock fr om Tx t o Rx : : : in in in : : : in in in std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; : out std logic

is

Configurable of

cycles .

architecture b e h a v i o r a l signal s ta te si g na l count : :

atr delay

s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; Verilog prefer forces grey : : : : one h o t for encoding both and I v e kept that here .

The o r i g i n a l XST seem s to

coding

versions ,

though .

constant ST RX DELAY constant ST RX constant ST TX DELAY constant ST TX begin pro c e ss ( c l k i ) begin

s t d l o g i c v e c t o r ( 3 downto 0 ) := 0001 ; s t d l o g i c v e c t o r ( 3 downto 0 ) := 0010 ; s t d l o g i c v e c t o r ( 3 downto 0 ) := 0100 ; s t d l o g i c v e c t o r ( 3 downto 0 ) := 1000 ;

i f ( c l k i EVENT and c l k i = 1 ) then i f ( r s t i = 1 or e n a i = 0 ) then s t a t e <= ST RX ; c o u n t <= ( o the rs = > 0 ) ; else c a se s t a t e is State something in t h e Tx b u f f e r , go t o Tx .

R e c e i v i n g when ST RX = > I f

there s

i f ( t x e m p t y i = 0 ) then s t a t e <= ST TX DELAY ; c o u n t <= t x d e l a y i ; end i f ; Rx >Tx D e l a y State when ST TX DELAY = >

56

76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 end i f ; end i f ; end pro c e ss ;

i f ( c o u n t = 0 ) then s t a t e <= ST TX ; else c o u n t <= c o u n t 1 ; end i f ; T r a n s m i t t i n g when ST TX = > When t h e Tx b u f f e r is empty , go b a c k t o Rx . i f ( t x e m p t y i = 1 ) then s t a t e <= ST RX DELAY ; c o u n t <= r x d e l a y i ; end i f ; Tx >Rx D e l a y State State

when ST RX DELAY = > i f ( c o u n t = 0 ) then s t a t e <= ST RX ; else c o u n t <= c o u n t 1 ; end i f ; when o the rs = > E r r o r s t a t e <= ST RX ; c o u n t <= ( o the rs = > 0 ) ; end c a se ;

a t r t x o <= 1 when ( s t a t e = ST TX or s t a t e = ST RX DELAY) end b e h a v i o r a l ;

else

0 ;

Listing A.5: A 16-bit tri-state bus with separate enable signals for each bit. (bidir reg.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 T r i S t a t e L a s t Register M o d i f i e d : 21 J u l y 2010 Steve Olivieri

VHDL A u t h o r :

C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t You s h o u l d along with have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free License write Software This pr ogr am is distributed in the hope even that the it will be useful , of b u t WITHOUT ANY WARRANTY; without implied warranty See This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can redistribute it and / o r modify by C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows .

under Free your

terms

t h e GNU G e n e r a l P u b l i c either later version .

L ic e n s e as the

published or

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

License ,

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. GNU G e n e r a l P u b l i c License f o r more details .

the

57

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

02110 1301

USA

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; entity b i d i r r e g port ( tristate oe reg val ); end b i d i r r e g ; architecture b e h a v i o r a l begin T h i s i n is just a n o t h e r macro f o r a 16 b i t enable oe ) for each bit , t r i s t a t e the bus . T h i s on e enable bidir reg : in : : inout in s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 )

is

of

is

h a s a s e p a r a t e bustri . pro c e ss ( r e g v a l , begin for i

unlike

bu s w i d e

i n 15 downto 0 loop

i f ( oe ( i ) = 1 ) then t r i s t a t e ( i ) <= r e g v a l ( i ) ; else t r i s t a t e ( i ) <= Z ; end i f ; end loop ; end pro c e ss ; end b e h a v i o r a l ;

Listing A.6: Another 16-bit tri-state bus, but with only one bus-wide enable signal. (bustri.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 T r i s t a t e L a s t Bus M odel M o d i f i e d : 20 J u l y 2010 Steve Olivieri

VHDL A u t h o r :

C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t This pr ogr am is distributed in the hope even that the it will be useful , of the b u t WITHOUT ANY WARRANTY; without implied warranty See This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can redistribute it and / o r modify by under Free your terms t h e GNU G e n e r a l P u b l i c either L ic e n s e as the published or C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows .

S o f t w a r e Foundation ; o p t i o n ) any later

version 2 of

License ,

version .

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE.

58

22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

GNU G e n e r a l P u b l i c You s h o u l d along with Foundation , have this

License

f o r more of

details . t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA

r e c e i v e d a copy pr ogr am ; if n ot ,

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; entity b u s t r i port ( data enabledt tridata ); end b u s t r i ; : : : out in in s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; std logic ; s t d l o g i c v e c t o r ( 1 5 downto 0 )

is

architecture b e h a v i o r a l begin T h i s is just

of

bustri

is

a macro f o r a 16 b i t

t r i s t a t e else

bus .

t r i d a t a <= d a t a when e n a b l e d t = 1 end b e h a v i o r a l ;

( o the rs = > Z ) ;

Listing A.7: CIC decimator module, part of the rx chain. Decimates received data in baseband. (cic decim.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; CIC D e c i m a t i o n L a s t C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t You s h o u l d along with have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free License This pr ogr am is distributed in the hope even that the it will be useful , of the This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c later version . L ic e n s e as the published C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows . M o d i f i e d : 21 J u l y 2010 Steve Olivieri VHDL A u t h o r :

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

write

Software 02110 1301 USA

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

59

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87

use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; A CIC d e c i m a t o r them s o that the is equivalent m ovin g input goes t o a m ovin g filters all average ( FIR filter . first Basically , separate all combs . and t h e n

t a k e N e q u i v a l e n t

average

f i l t e r s ) , then

through

integrators

We can do m ovin g f i l t e r . and r em ove

this the

because filter , oldest like

b o t h combs and imagine sample , this that then at

integrators each by b y N) .

a r e LTI .

To t h i n k newest stages in

of a the

average

s t e p we add t h e t h e number o f

sample

divide

Something

( divided

y [ n ] = y [ n 1] + x [ n ] x [ nR ] is

entity c i c d e c i m g e ne ri c ( bw N

: : : :

i n t e g e r := 1 6 ;

# o f

bits

for

input rate

i n t e g e r := 4 ; # o f

filter

stages

log2 of max rate maxbitgain );

i n t e g e r := 7 ; l o g 2

o f max s a m p l i n g

i n t e g e r := 28 N l o g 2 o f m a x r a t e

port ( clock reset enable rate strobe in strobe out signal in signal out ); end c i c d e c i m ; architecture b e h a v i o r a l g e ne ri c ( bits in bits out ); port ( d in d out ); end component ; component c i c d e c s h i f t e r g e ne ri c ( bw : i n t e g e r := 1 6 ; : i n t e g e r := 28 : in s t d l o g i c v e c t o r ( b i t s i n 1 downto 0 ) ; s t d l o g i c v e c t o r ( b i t s o u t 1 downto 0 ) : out : : i n t e g e r := 0 ; i n t e g e r := 0 of ci c deci m is : : : in in in : in : in : : in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 7 downto 0 ) ; std logic ; std logic ; s t d l o g i c v e c t o r ( bw1 downto 0 ) ; s t d l o g i c v e c t o r ( bw1 downto 0 )

: out

is

component s i g n e x t e n d

is

maxbitgain ); port ( rate signal in signal out ); end component ;

: :

in in

s t d l o g i c v e c t o r ( 7 downto 0 ) ; s t d l o g i c v e c t o r ( bw+m axb i t gai n 1 downto 0 ) ; s t d l o g i c v e c t o r ( bw1 downto 0 )

: out

60

88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144

type mem i s array ( i n t e g e r range <>) o f signal in t e g r a t o r signal signal p i p e l in e : mem( 0 to N 1) ; : mem( 0 to N 1) ; differentiator

s t d l o g i c v e c t o r ( bw+m axb i t gai n 1 downto 0 ) ;

: mem( 0 to N 1) ; : s t d l o g i c v e c t o r ( bw1 downto 0 ) ;

signal

signal out t

signal

signal in ext

s t d l o g i c v e c t o r ( bw+m axb i t gai n 1 downto 0 ) ; : : s t d l o g i c v e c t o r ( bw1 downto 0 ) ; s t d l o g i c v e c t o r ( bw+m axb i t gai n 1 downto 0 ) ;

signal s ig n a l o u t u nr e g signal signal out unnorm

si g na l sampler begin S i g n extend :

s t d l o g i c v e c t o r ( bw+m axb i t gai n 1 downto 0 ) ; input signal to account for bit gain in the filters .

the

ext input

sign extend bits out = > ( bw+m a x b i t g a i n ) ) d out = > signal in ext ) ;

> bw , g e ne ri c map( b i t s i n = port map ( d i n = > signal in ,

I n t e g r a t o r pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( r e s e t = 1 ) then C l e a r for i the integrator .

i n 0 to N1 loop

i n t e g r a t o r ( i ) <= ( o the rs = > 0 ) ; end loop ; e l s i f ( ( e n a b l e = 1 ) and ( s t r o b e i n = 1 ) ) then Grab t h e next sample .

i n t e g r a t o r ( 0 ) <= i n t e g r a t o r ( 0 ) + s i g n a l i n e x t ; I n t e g r a t e ! m ovin g The i n t e g r a t o r adds the newest sample to the

average .

y [ n ] = y [ n 1] + c [ n ] for i i n 1 to N1 loop

i n t e g r a t o r ( i ) <= i n t e g r a t o r ( i ) + i n t e g r a t o r ( i 1) ; end loop ; end i f ; end i f ; end pro c e ss ;

Comb F i l t e r pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( r e s e t = 1 ) then C l e a r i t h e comb filters .

s a m p l e r <= ( o the rs = > 0 ) ; for i n 0 to N1 loop p i p e l i n e ( i ) <= ( o the rs = > 0 ) ; d i f f e r e n t i a t o r ( i ) <= ( o the rs = > 0 ) ; end loop ; e l s i f ( ( e n a b l e = 1 ) and ( s t r o b e o u t = 1 ) ) then Grab t h e output of the integrator into t h e comb filter . s a m p l e r <= i n t e g r a t o r (N 1) ;

61

145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 R e g i s t e r end i f ; end pro c e ss ;

The comb m ovin g

filters

r em ove

the

oldest

samples

fr om

the

average .

c [ n ] = x [ n ] x [ n R ] d i f f e r e n t i a t o r ( 0 ) <= s a m p l e r ; p i p e l i n e ( 0 ) <= s a m p l e r d i f f e r e n t i a t o r ( 0 ) ; for i i n 1 to N1 loop

d i f f e r e n t i a t o r ( i ) <= p i p e l i n e ( i 1) ; p i p e l i n e ( i ) <= p i p e l i n e ( i 1) d i f f e r e n t i a t o r ( i ) ; end loop ; end i f ;

N o r m a l i z e

the

output

to

bw

bits .

s i g n a l o u t u n n o r m <= p i p e l i n e (N 1) ; cic dec shifter0 : cic dec shifter

g e ne ri c map( bw = > bw) port map ( r a t e = > rate , the outputs . signal in = > signal out unnorm , signal out = > signal out unreg ) ;

pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then s i g n a l o u t <= s i g n a l o u t u n r e g ; end i f ; end pro c e ss ; end b e h a v i o r a l ;

Listing A.8: Decimation shifter to account for bitgain in the decimation process. (cic dec shifter.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 CIC D e c i m a t i o n L a s t C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t You s h o u l d along with have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free License write Software This pr ogr am is distributed in the hope even that the it will be useful , of This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows . Shifter M o d i f i e d : 21 J u l y 2010 Steve Olivieri

VHDL A u t h o r :

under

terms

t h e GNU G e n e r a l P u b l i c later version .

L ic e n s e as the

published

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

the

62

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

02110 1301

USA

T h i s only works f o r N=4 , max d e c i m a t i o n i s ONE LESS THAN t h e rate actual of 128.

The s i g n a l l i b r a r y IEEE ;

rate

rate .

use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; cic dec shifter

entity

is

g e ne ri c ( bw maxbitgain ); port ( rate signal in signal out ); end c i c d e c s h i f t e r ; architecture b e h a v i o r a l signal shift : : cic dec shifter : in : in s t d l o g i c v e c t o r ( 7 downto 0 ) ; s t d l o g i c v e c t o r ( bw+m axb i t gai n 1 downto 0 ) ; s t d l o g i c v e c t o r ( bw1 downto 0 ) : : i n t e g e r := 1 6 ;

i n t e g e r := 28

: out

of

is

s t d l o g i c v e c t o r ( 4 downto 0 ) ; s t d l o g i c v e c t o r ( 7 downto 0 ) ; original it here . Verilog But source is uses really r a t e 1 i n the the top

signal rate1 begin

I don t know why t h e m odu le and t h e n r a t e . r a t e 1 <= r a t e + 1 ; The a c t u a l bit gain fixes

this

decimation

is

determined equal

by to

the

rate ,

where

b i t g a i n = N l o g 2 (R) rate

We f i x N a t 4 h e r e and R i s with c o n v i n t e g e r ( r a t e 1 ) select

s h i f t <= c o n v s t d l o g i c v e c t o r ( 8 , 5 ) when 4 , c o n v s t d l o g i c v e c t o r (12 , c o n v s t d l o g i c v e c t o r (16 , c o n v s t d l o g i c v e c t o r (20 , c o n v s t d l o g i c v e c t o r (24 , c o n v s t d l o g i c v e c t o r (28 , c o n v s t d l o g i c v e c t o r (10 , c o n v s t d l o g i c v e c t o r (11 , c o n v s t d l o g i c v e c t o r (12 , c o n v s t d l o g i c v e c t o r (13 , c o n v s t d l o g i c v e c t o r (14 , c o n v s t d l o g i c v e c t o r (15 , c o n v s t d l o g i c v e c t o r (16 , c o n v s t d l o g i c v e c t o r (17 , c o n v s t d l o g i c v e c t o r (18 , c o n v s t d l o g i c v e c t o r (19 , c o n v s t d l o g i c v e c t o r (20 , c o n v s t d l o g i c v e c t o r (21 , c o n v s t d l o g i c v e c t o r (22 , c o n v s t d l o g i c v e c t o r (23 , 5 ) when 8 , 5 ) when 1 6 , 5 ) when 3 2 , 5 ) when 6 4 , 5 ) when 1 2 8 , 5 ) when 5 , 5 ) when 6 , 5 ) when 7 , 5 ) when 9 , 5 ) when 10 | 5 ) when 12 | 5 ) when 14 | 11 , 13 , 15 , | | 19 , 22 , 26 , 30 | 31 , | 38 , 45 , 52 | 53 , | 44 | | 51 |

5 ) when 17 | 18 5 ) when 20 | 21 5 ) when 23 | 24 5 ) when 27 | 28 5 ) when 33 | 34 5 ) when 39 | 40 5 ) when 46 | 47

| 25 | | 29 | | 35 | | 41 | | 48 |

36 | 37 42 | 43 49 | 50

63

82 83 84

c o n v s t d l o g i c v e c t o r (24 , | | | 63 , c o n v s t d l o g i c v e c t o r (25 , 74 | 75 86 | 87 | 76 , c o n v s t d l o g i c v e c t o r (26 , | 88 | 89 |

5 ) when 54 | 55 5 ) when 65 | 66 5 ) when 77 | 78 90 , 5 ) when 91 | 92 104 | 105 5 ) when o the rs ; the following simulation

| 56 | | 67 | | 79 |

57 | 58 68 | 69 80 | 81

| 59 | | 70 | | 82 |

60 | 61 71 | 72 83 | 84

| 62 | 73 | 85

85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 end b e h a v i o r a l ; Wouldn t Index this

c o n v s t d l o g i c v e c t o r (27 , | 100 | 101 | 102 | c o n v s t d l o g i c v e c t o r (28 , be nice ? does Xilinx

| 93 | |

94 | 95 107 ,

| 96 |

97 | 98

| 99

103 |

| 106

ISE t h r o w s

warning : m ism at ch . conv integer ( s h i f t ) ) ;

value ( s )

n o t m at ch a r r a y

range ,

s i g n a l o u t <= s i g n a l i n ( c o n v i n t e g e r ( s h i f t )+bw 1 dow n t o So i n s t e a d , we r e stuck with this .

s i g n a l o u t <= s i g n a l i n (8+bw1 downto 8 ) when s h i f t = 8 e l s e s i g n a l i n (12+bw1 downto 1 2 ) when s h i f t = 12 e l s e s i g n a l i n (16+bw1 downto 1 6 ) when s h i f t = 16 e l s e s i g n a l i n (20+bw1 downto 2 0 ) when s h i f t = 20 e l s e s i g n a l i n (24+bw1 downto 2 4 ) when s h i f t = 24 e l s e s i g n a l i n (28+bw1 downto 2 8 ) when s h i f t = 28 e l s e s i g n a l i n (10+bw1 downto 1 0 ) when s h i f t = 10 e l s e s i g n a l i n (11+bw1 downto 1 1 ) when s h i f t = 11 e l s e s i g n a l i n (13+bw1 downto 1 3 ) when s h i f t = 13 e l s e s i g n a l i n (14+bw1 downto 1 4 ) when s h i f t = 14 e l s e s i g n a l i n (15+bw1 downto 1 5 ) when s h i f t = 15 e l s e s i g n a l i n (17+bw1 downto 1 7 ) when s h i f t = 17 e l s e s i g n a l i n (18+bw1 downto 1 8 ) when s h i f t = 18 e l s e s i g n a l i n (19+bw1 downto 1 9 ) when s h i f t = 19 e l s e s i g n a l i n (21+bw1 downto 2 1 ) when s h i f t = 21 e l s e s i g n a l i n (22+bw1 downto 2 2 ) when s h i f t = 22 e l s e s i g n a l i n (23+bw1 downto 2 3 ) when s h i f t = 23 e l s e s i g n a l i n (25+bw1 downto 2 5 ) when s h i f t = 25 e l s e s i g n a l i n (26+bw1 downto 2 6 ) when s h i f t = 26 e l s e s i g n a l i n (27+bw1 downto 2 7 ) when s h i f t = 27 e l s e s i g n a l i n (28+bw1 downto 2 8 ) ;

Listing A.9: CIC interpolator module, part of the tx chain. Interpolates data in baseband before sending it to the AD9862 for transmission. (cic interp.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CIC I n t e r p o l a t i o n L a s t M o d i f i e d : 20 F e b r u a r y 2011 Steve Olivieri VHDL A u t h o r : C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t This it the pr ogr am the Free is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c L ic e n s e as the published C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows .

S o f t w a r e Foundation ;

version 2 of

64

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

( at This

your

o p t i o n ) any is

later

version . in the hope even that the it will be useful , of the

pr ogr am

distributed

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

You s h o u l d along with Foundation ,

have this

r e c e i v e d a copy pr ogr am ; if n ot ,

of

t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA

License USA

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; A CIC i n t e r p o l a t o r t a k e N e q u i v a l e n t them s o m ovin g f i l t e r . that the We can do and r em ove this the is equivalent average t o a m ovin g filters all at ( FIR combs each by b y N) . average filter . Basically , separate all integrators . of a the sample in To t h i n k newest stages

m ovin g input

f i l t e r s ) , then first and t h e n a r e LTI .

goes

through that then

because filter , oldest like

b o t h combs and imagine sample , this

integrators

average

s t e p we add t h e t h e number o f

divide

Something

( divided

y [ n ] = y [ n 1] + x [ n ] x [ nR ] is g e ne ri c ( bw N log2 of max rate maxbitgain ); port ( clock reset enable rate strobe in strobe out signal in signal out ); : : : in in in : in : in : : in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 7 downto 0 ) ; std logic ; std logic ; s t d l o g i c v e c t o r ( bw1 downto 0 ) ; s t d l o g i c v e c t o r ( bw1 downto 0 ) : : : : i n t e g e r := 1 6 ; # o f bits for input i n t e g e r := 4 ; # o f filter stages rate

entity c i c i n t e r p

i n t e g e r := 7 ; l o g 2

o f max s a m p l i n g

i n t e g e r := 21 (N 1) l o g 2 o f m a x r a t e

: out

end c i c i n t e r p ; architecture b e h a v i o r a l cic interp is

of

is

component s i g n e x t e n d g e ne ri c ( bits in bits out ); :

i n t e g e r := 0 ; : i n t e g e r := 0

port ( d in d out ); end component ; : in s t d l o g i c v e c t o r ( b i t s i n 1 downto 0 ) ; s t d l o g i c v e c t o r ( b i t s o u t 1 downto 0 ) : out

65

74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 end i f ; end i f ; Comb F i l t e r pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( c l e a r m e = 1 ) then C l e a r for i t h e comb filters . FIXME Not e I t still that this but section is has pipe and diff reversed . w or ks , confusing . A s i m p l e OR g a t e to reset the filters . else 0 ; signal clear me : std logic ; : s t d l o g i c v e c t o r ( bw+m axb i t gai n 1 downto 0 ) ; signal signal out unnorm begin S i g n extend : the input signal to account for bit gain in the filters . signal signal in ext : s t d l o g i c v e c t o r ( bw+m axb i t gai n 1 downto 0 ) ; type mem i s array ( i n t e g e r range <>) o f signal in t e g r a t o r signal signal p i p e l in e : mem( 0 to N 1) ; : mem( 0 to N 1) ; differentiator s t d l o g i c v e c t o r ( bw+m axb i t gai n 1 downto 0 ) ; ); end component ; port ( rate signal in signal out : in : : out in s t d l o g i c v e c t o r ( 7 downto 0 ) ; s t d l o g i c v e c t o r ( bw+m axb i t gai n 1 downto 0 ) ; s t d l o g i c v e c t o r ( bw1 downto 0 ) ); component c i c i n t s h i f t e r g e ne ri c ( bw maxbitgain : : i n t e g e r := 1 6 ; i n t e g e r := 21 is

: mem( 0 to N 1) ;

ext input

sign extend bits out = > ( bw+m a x b i t g a i n ) ) d out = > signal in ext ) ;

g e ne ri c map( b i t s i n = > bw , port map ( d i n = > signal in ,

c l e a r m e <= 1 when ( ( r e s e t = 1 ) or ( e n a b l e = 0 ) )

i n 0 to N1 loop

d i f f e r e n t i a t o r ( i ) <= ( o the rs = > 0 ) ; p i p e l i n e ( i ) <= ( o the rs = > 0 ) ; end loop ; e l s i f ( ( e n a b l e = 1 ) and ( s t r o b e i n = 1 ) ) then The comb m ovin g filters r em ove the oldest samples fr om the

average .

c [ n ] = x [ n ] x [ n R ] d i f f e r e n t i a t o r ( 0 ) <= s i g n a l i n e x t ; p i p e l i n e ( 0 ) <= s i g n a l i n e x t d i f f e r e n t i a t o r ( 0 ) ; for i i n 1 to N1 loop

d i f f e r e n t i a t o r ( i ) <= p i p e l i n e ( i 1) ; p i p e l i n e ( i ) <= p i p e l i n e ( i 1) d i f f e r e n t i a t o r ( i ) ; end loop ;

66

131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164

end pro c e ss ; I n t e g r a t o r pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( c l e a r m e = 1 ) then C l e a r for i the integrator . i n 0 to N1 loop

i n t e g r a t o r ( i ) <= ( o the rs = > 0 ) ; end loop ; e l s i f ( ( e n a b l e = 1 ) and ( s t r o b e o u t = 1 ) ) then i f ( s t r o b e i n = 1 ) then Grab t h e end i f ; I n t e g r a t e ! m ovin g i The i n t e g r a t o r adds the newest sample to the output of t h e comb filters into the integrator . i n t e g r a t o r ( 0 ) <= i n t e g r a t o r ( 0 ) + p i p e l i n e (N 1) ;

average .

y [ n ] = y [ n 1] + c [ n ] for i n 1 to N1 loop i n t e g r a t o r ( i ) <= i n t e g r a t o r ( i ) + i n t e g r a t o r ( i 1) ; end loop ; end i f ; end i f ; end pro c e ss ; N o r m a l i z e the output to bw bits .

s i g n a l o u t u n n o r m <= i n t e g r a t o r (N 1) ;

cic int shifter0

cic int shifter signal in = > signal out unnorm , signal out = > signal out ) ;

g e ne ri c map( bw = > bw) port map ( r a t e = > rate , end b e h a v i o r a l ;

Listing A.10: Interpolation shifter to account for bitgain in the interpolation process. (cic int shifter.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CIC I n t e r p o l a t i o n L a s t C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t This pr ogr am is distributed in the hope that it will be useful , This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows . VHDL A u t h o r : Steve Shifter Olivieri M o d i f i e d : 20 J u l y 2010

under

terms

t h e GNU G e n e r a l P u b l i c later version .

L ic e n s e as the

published

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

67

20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c You s h o u l d along with have this License

without

even

the

implied

warranty See

of

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more of details .

the

r e c e i v e d a copy pr ogr am ; if n ot ,

t h e GNU G e n e r a l P u b l i c to the Free

License

write

Software 02110 1301 USA

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

T h i s only works f o r N=4 , max i n t e r p rate actual of 128.

S i g n a l r a t e l i b r a r y IEEE ;

i s ONE LESS THAN t h e

rate .

use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; cic int shifter

entity

is

g e ne ri c ( bw maxbitgain ); port ( rate signal in signal out ); end c i c i n t s h i f t e r ; : in : in s t d l o g i c v e c t o r ( 7 downto 0 ) ; s t d l o g i c v e c t o r ( bw+m axb i t gai n 1 downto 0 ) ; s t d l o g i c v e c t o r ( bw1 downto 0 ) : : i n t e g e r := 1 6 ;

i n t e g e r := 21

: out

architecture b e h a v i o r a l signal shift : : signal rate1 begin

of

cic int shifter

is

s t d l o g i c v e c t o r ( 4 downto 0 ) ; s t d l o g i c v e c t o r ( 7 downto 0 ) ; original it here . Verilog But source is uses really r a t e 1 i n the the top

I don t know why t h e m odu le and t h e n r a t e . r a t e 1 <= r a t e + 1 ; The a c t u a l bit gain fixes

this

interpolation

is

determined equal

by to

the

rate ,

where

b i t g a i n = (N 1) l o g 2 (R) rate .

We f i x N a t 4 h e r e and R i s with c o n v i n t e g e r ( r a t e 1 ) select

s h i f t <= c o n v s t d l o g i c v e c t o r ( 6 , 5 ) when 4 , conv std logic vector (9 , c o n v s t d l o g i c v e c t o r (12 , c o n v s t d l o g i c v e c t o r (15 , c o n v s t d l o g i c v e c t o r (18 , c o n v s t d l o g i c v e c t o r (21 , conv std logic vector (7 , conv std logic vector (8 , conv std logic vector (9 , c o n v s t d l o g i c v e c t o r (10 , c o n v s t d l o g i c v e c t o r (11 , c o n v s t d l o g i c v e c t o r (12 , c o n v s t d l o g i c v e c t o r (13 , c o n v s t d l o g i c v e c t o r (14 , c o n v s t d l o g i c v e c t o r (15 , 5 ) when 8 , 5 ) when 1 6 , 5 ) when 3 2 , 5 ) when 6 4 , 5 ) when 1 2 8 , 5 ) when 5 , 5 ) when 6 , 5 ) when 7 , 5 ) when 9 | 5 ) when 11 | 10 , 12 , | 15 , 20 , 24 | 25 , | 31 , 29 | 30 | 19 | | 23 | | 28 |

5 ) when 13 | 14 5 ) when 17 | 18 5 ) when 21 | 22 5 ) when 26 | 27

68

77 78 79 80

c o n v s t d l o g i c v e c t o r (16 , c o n v s t d l o g i c v e c t o r (17 , | | 50 , c o n v s t d l o g i c v e c t o r (18 , 60 | 61 | 62 | 63 , c o n v s t d l o g i c v e c t o r (19 , | 74 | 75 90 | 91 | 76 | | 92 |

5 ) when 33 | 34 5 ) when 41 | 42 5 ) when 51 | 52 5 ) when 65 | 66 | 79 | | 95 | 80 ,

| 35 | | 43 | | 53 | | 67 |

36 | 37 44 | 45 54 | 55 68 | 69

| 38 | | 46 | | 56 | | 70 |

39 |

40 , | 49 | 59 | 73

47 | 48 57 | 58 71 | 72

77 | 78 93 | 94

81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 end b e h a v i o r a l ; Wouldn t Index this

c o n v s t d l o g i c v e c t o r (20 , | c o n v s t d l o g i c v e c t o r (21 , be nice ? does Xilinx

5 ) when 81 | 82 5 ) when o the rs ; the following simulation

| 83 |

84 | 85 99 |

| 86 | 100 |

87 | 88

| 89

96 | 97

| 98 |

101 ,

ISE t h r o w s

warning : m ism at ch . conv integer ( s h i f t ) ) ;

value ( s )

n o t m at ch a r r a y

range ,

s i g n a l o u t <= s i g n a l i n ( c o n v i n t e g e r ( s h i f t )+bw 1 dow n t o So i n s t e a d , we r e stuck with this .

s i g n a l o u t <= s i g n a l i n (6+bw1 downto 6 ) when s h i f t = 6 e l s e s i g n a l i n (9+bw1 downto 9 ) when s h i f t = 9 e l s e s i g n a l i n (12+bw1 downto 1 2 ) when s h i f t = 12 e l s e s i g n a l i n (15+bw1 downto 1 5 ) when s h i f t = 15 e l s e s i g n a l i n (18+bw1 downto 1 8 ) when s h i f t = 18 e l s e s i g n a l i n (21+bw1 downto 2 1 ) when s h i f t = 21 e l s e s i g n a l i n (7+bw1 downto 7 ) when s h i f t = 7 e l s e s i g n a l i n (8+bw1 downto 8 ) when s h i f t = 8 e l s e s i g n a l i n (10+bw1 downto 1 0 ) when s h i f t = 10 e l s e s i g n a l i n (11+bw1 downto 1 1 ) when s h i f t = 11 e l s e s i g n a l i n (13+bw1 downto 1 3 ) when s h i f t = 13 e l s e s i g n a l i n (14+bw1 downto 1 4 ) when s h i f t = 14 e l s e s i g n a l i n (16+bw1 downto 1 6 ) when s h i f t = 16 e l s e s i g n a l i n (17+bw1 downto 1 7 ) when s h i f t = 17 e l s e s i g n a l i n (19+bw1 downto 1 9 ) when s h i f t = 19 e l s e s i g n a l i n (20+bw1 downto 2 0 ) when s h i f t = 20 e l s e s i g n a l i n (21+bw1 downto 2 1 ) ;

Listing A.11: A basic clock divider module. (clk divider.vhd)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 C l o c k L a s t C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t This pr ogr am is distributed in the hope that it will be useful , This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows . Divider M o d i f i e d : 21 J u l y 2010 Steve Olivieri

VHDL A u t h o r :

under

terms

t h e GNU G e n e r a l P u b l i c later version .

L ic e n s e as the

published

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

69

20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c You s h o u l d along with have this License

without

even

the

implied

warranty See

of

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more of details .

the

r e c e i v e d a copy pr ogr am ; if n ot ,

t h e GNU G e n e r a l P u b l i c to the Free

License

write

Software 02110 1301 USA

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; entity c l k d i v i d e r port ( reset in clk out clk ratio ); end c l k d i v i d e r ; architecture b e h a v i o r a l O r i g i n a l Verilog : : : clk divider [7:0] , but : in : in std logic ; std logic ; std logic ; in s t d l o g i c v e c t o r ( 7 downto 0 )

is

: out :

of had

is it was w r on g .

signal counter

s t d l o g i c v e c t o r ( 7 downto 0 ) ; std logic ; std logic ;

signal o u t c l k t s i g n a l cou n t t m p begin

o u t c l k <= o u t c l k t ; cou n t t m p <= 1 when ( ( r a t i o ( 0 ) = 1 ) and ( o u t c l k t = 1 ) ) Use a down c o u n t e r pro c e ss ( i n c l k , begin i f ( r e s e t = 1 ) then c o u n t e r <= ( o the rs = > 0 ) ; e l s i f ( i n c l k EVENT and i n c l k = 1 ) then i f ( c o u n t e r = 0 ) then I f counter ugly is zero h e r e , we a r e f o r c e s XST t o diving in clk by 2. adder like it should . T h i s notation generate a carry reset ) to count clocks between each toggle of else 0 ; out clk .

c o u n t e r <= c o n v s t d l o g i c v e c t o r ( c o n v i n t e g e r ( r a t i o ( 7 downto 1 ) ) + c o n v i n t e g e r ( cou n t t m p ) 1 , 8 ) ;

61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

else c o u n t e r <= c o u n t e r 00000001 ; end i f ; end i f ; end pro c e ss ;

T o g g l e

out clock

when

the

counter

hits

zero .

pro c e ss ( i n c l k , begin

reset )

i f ( r e s e t = 1 ) then o u t c l k t <= 0 ; e l s i f ( i n c l k EVENT and i n c l k = 1 ) then i f ( c o u n t e r = 0 ) then o u t c l k t <= ( not end i f ; out clk t ) ;

70

76 77 78

end i f ; end pro c e ss ; end b e h a v i o r a l ;

Listing A.12: Memory for storing the halfband lter coecients. (coe rom.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then architecture b e h a v i o r a l signal data t begin d a t a <= c o n v s t d l o g i c v e c t o r ( d a t a t , 16) ; : of coeff rom is s i g n e d ( 1 5 downto 0 ) ; ); end c o e f f r o m ; entity c o e f f r o m port ( clock ad d r data : : in in std logic ; s t d l o g i c v e c t o r ( 2 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) is TODO: Migrate this m odu le to t h e new n u m e r i c s t d library standard . l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; C o e f f i c i e n t ROM f o r L a s t the Halfband Decimation Filter M o d i f i e d : 14 F e b r u a r y 2011 Steve Olivieri

VHDL A u t h o r :

C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA write Software 02110 1301 This pr ogr am is distributed in the hope even that the it will be useful , of the b u t WITHOUT ANY WARRANTY; without implied warranty See This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can redistribute it and / o r modify by under Free your terms t h e GNU G e n e r a l P u b l i c either L ic e n s e as the published or C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows .

S o f t w a r e Foundation ; o p t i o n ) any later

version 2 of

License ,

version .

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. GNU G e n e r a l P u b l i c License f o r more details .

I n c . , 51 F r a n k l i n

Street ,

: out

71

51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

c a se c o n v i n t e g e r ( ad d r ) when 0 = >

is

d a t a t <= c o n v s i g n e d ( 49 , 1 6 ) ; when 1 = > d a t a t <= c o n v s i g n e d ( 1 6 5 , 1 6 ) ; when 2 = > d a t a t <= c o n v s i g n e d ( 412 , 1 6 ) ; when 3 = > d a t a t <= c o n v s i g n e d ( 8 7 3 , 1 6 ) ; when 4 = > d a t a t <= c o n v s i g n e d ( 1681 , 1 6 ) ; when 5 = > d a t a t <= c o n v s i g n e d ( 3 1 3 5 , when 6 = > d a t a t <= c o n v s i g n e d ( 6282 , 1 6 ) ; when 7 = > d a t a t <= c o n v s i g n e d ( 2 0 6 2 8 , 1 6 ) ; when o the rs = > end c a se ; end i f ; end pro c e ss ; end b e h a v i o r a l ; 16) ;

Listing A.13: The next six les are conguration headers, implemented in VHDL as packages. This particular le contains information common to all USRP congurations. (common cong.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 l i b r a r y WOR K; T h i s is t h e common t a i l in for the standard u se configuration . Uncomment a single USRP Common C o n f i g u r a t i o n L a s t C o p y r i g h t (C) 2010 COSMIAC You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA This pr ogr am is distributed in the hope even that the it will be useful , of the b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License without implied warranty See This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c later version . L ic e n s e as the published M o d i f i e d : 21 J u l y 2010 Steve Olivieri VHDL A u t h o r :

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

Tx/Rx c o n f i g u r a t i o n l i b r a r y IEEE ;

section .

use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ;

72

30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

use WOR K. FUNCS . ALL ; C o n f i g u r a t i o n s go here . Uncomment o n l y on e configuration !

use WOR K. COMMON CONFIG 1RXHB 1TX . ALL ; u s e WORK. COMMON CONFIG 2RX 0TX . ALL ; u s e WORK. COMMON CONFIG 2RXHB 0TX . ALL ; u s e WORK. COMMON CONFIG 2RXHB 2TX . ALL ; u s e WORK. COMMON CONFIG 4RX 0TX . ALL ; You s h o u l d not need the to is should be conditionalized only in terms of : edit below this line !

package com m on con fi g ALL o f

remaining code

TX EN , TX EN 0 , TX EN 1 , TX EN 2 , TX EN 3 , TX CAP NCHAN, TX CAP HB , RX EN , RX EN 0 , RX EN 1 , RX EN 2 , RX EN 3 , RX CAP NCHAN, RX CAP HB , RX NCO EN , RX CIC EN b o o l e a n := TX ON ; b o o l e a n := (TX EN and ( TX SINGLE or TX DUAL or TX QUAD) ) ; b o o l e a n := (TX EN and (TX DUAL or TX QUAD) ) ; b o o l e a n := (TX EN and TX QUAD) ; b o o l e a n := (TX EN and TX QUAD) ; b o o l e a n := (TX EN and TX HB ON) ; s t d l o g i c v e c t o r ( 2 downto 0 ) := ( c o n v s t d l o g i c (TX EN and TX QUAD) & c o n v s t d l o g i c (TX EN and TX DUAL)

constant TX EN :

constant TX EN 0 : constant TX EN 1 : constant TX EN 2 : constant TX EN 3 :

constant TX CAP HB :

constant TX CAP NCHAN :

54

& c o n v s t d l o g i c (TX EN and TX SINGLE ) ) ;

55 56 57 58 59 60 61 62 63 constant RX EN : b o o l e a n := RX ON ; b o o l e a n := (RX EN and ( RX SINGLE or RX DUAL or RX QUAD) ) ; b o o l e a n := (RX EN and (RX DUAL or RX QUAD) ) ; b o o l e a n := (RX EN and RX QUAD) ; b o o l e a n := (RX EN and RX QUAD) ; b o o l e a n := (RX EN and RX HB ON) ; s t d l o g i c v e c t o r ( 2 downto 0 ) := ( c o n v s t d l o g i c (RX EN and RX QUAD) & c o n v s t d l o g i c (RX EN and RX DUAL) 64 & c o n v s t d l o g i c (RX EN and RX SINGLE ) ) ; 65 66 67 68 constant RX NCO EN : constant RX CIC EN : end com m on con fi g ; b o o l e a n := (RX EN and RX NCO ON) ; b o o l e a n := (RX EN and RX CIC ON ) ; constant RX EN 0 : constant RX EN 1 : constant RX EN 2 : constant RX EN 3 :

constant RX CAP HB :

constant RX CAP NCHAN :

Listing A.14: Conguration for one transmit channel and one receive channel with halfband lter. (common cong 1rxhb 1tx.vhd)
1 2 3 4 5 6 USRP C o n f i g u r a t i o n L a s t C o p y r i g h t (C) 2010 COSMIAC VHDL A u t h o r : Steve w i t h 1 Rx ( H a l f b a n d ) and 1 Tx Olivieri M o d i f i e d : 21 J u l y 2010

73

7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

You s h o u l d along with have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free License This pr ogr am is distributed in the hope even that the it will be useful , of the This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c later version . L ic e n s e as the published

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

write

Software 02110 1301 USA

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; package c o m m o n c o n f i g 1 r x h b 1 t x I f TX ON i s not defined , constant TX ON :

is there i s no t r a n s m i t circuitry built .

b o o l e a n := t r u e ;

D e f i n e e n a b l e [ P l e a s e

1 and o n l y 1 o f TX SINGLE , TX DUAL , and TX QUAD t o 1 , 2 , or 4 t r a n s m it note that channels . currently o n l y TX SINGLE and TX DUAL a r e b o o l e a n := t r u e ; false ; false ; the transmit halfband filter .

respectively valid .]

constant TX SINGLE : constant TX DUAL : constant TX QUAD :

b o o l e a n := b o o l e a n := enable

D e f i n e TX HB ON t o [ n o t i m p l e m e n t e d ] constant TX HB ON :

b o o l e a n := f a l s e ;

I f RX ON i s

not

defined ,

there

i s no r e c e i v e

circuitry

built .

constant RX ON : D e f i n e e n a b l e

b o o l e a n := t r u e ; respectively

1 and o n l y 1 o f RX SINGLE , RX DUAL , and TX QUAD t o 1 , 2 , or 4 receive channels . b o o l e a n := t r u e ; false ; false ; the receive halfband filter .

constant RX SINGLE : constant RX DUAL : constant RX QUAD :

b o o l e a n := b o o l e a n := enable

D e f i n e RX HB ON t o constant RX HB ON :

b o o l e a n := t r u e ;

D e f i n e RX NCO ON t o constant RX NCO ON :

enable

the

receive

Numerical

C o n t r o l l e d Osc .

b o o l e a n := t r u e ; enable the receive Cascaded I n t e g r a t o r Comb f i l t e r .

D e f i n e RX CIC ON t o constant RX CIC ON :

b o o l e a n := t r u e ;

end c o m m o n c o n f i g 1 r x h b 1 t x ;

Listing A.15: Conguration for zero transmit channels and two receive channel with halfband lters. (common cong 2rxhb 0tx.vhd)

74

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

USRP C o n f i g u r a t i o n L a s t C o p y r i g h t (C) 2010 COSMIAC You s h o u l d along with have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free License This pr ogr am is distributed in the hope even that the it will be useful , of the This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c later version . L ic e n s e as the published VHDL A u t h o r : Steve w i t h 2 Rx ( H a l f b a n d ) and 0 Tx Olivieri M o d i f i e d : 21 J u l y 2010

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

write

Software 02110 1301 USA

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; package c o m m o n c o n f i g 2 r x h b 0 t x I f TX ON i s not defined , constant TX ON : b o o l e a n :=

is there false ; i s no t r a n s m i t circuitry built .

D e f i n e e n a b l e [ P l e a s e

1 and o n l y 1 o f TX SINGLE , TX DUAL , and TX QUAD t o 1 , 2 , or 4 t r a n s m it note that channels . currently o n l y TX SINGLE and TX DUAL a r e b o o l e a n := false ; false ; false ; the transmit halfband filter .

respectively valid .]

constant TX SINGLE : constant TX DUAL : constant TX QUAD :

b o o l e a n := b o o l e a n := enable

D e f i n e TX HB ON t o [ n o t i m p l e m e n t e d ] constant TX HB ON :

b o o l e a n := f a l s e ;

I f RX ON i s

not

defined ,

there

i s no r e c e i v e

circuitry

built .

constant RX ON : D e f i n e e n a b l e

b o o l e a n := t r u e ; respectively

1 and o n l y 1 o f RX SINGLE , RX DUAL , and TX QUAD t o 1 , 2 , or 4 receive channels . false ; b o o l e a n :=

constant RX SINGLE : constant RX DUAL : constant RX QUAD :

b o o l e a n := t r u e ; b o o l e a n := enable false ; the receive halfband filter .

D e f i n e RX HB ON t o constant RX HB ON :

b o o l e a n := t r u e ;

D e f i n e RX NCO ON t o constant RX NCO ON :

enable

the

receive

Numerical

C o n t r o l l e d Osc .

b o o l e a n := t r u e ; enable the receive Cascaded I n t e g r a t o r Comb f i l t e r .

D e f i n e RX CIC ON t o

75

58 59

constant RX CIC ON :

b o o l e a n := t r u e ;

end c o m m o n c o n f i g 2 r x h b 0 t x ;

Listing A.16: Conguration for two transmit channels and two receive channels with halfband lters. (common cong 2rxhb 2tx.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 D e f i n e RX HB ON t o enable the receive halfband filter . D e f i n e e n a b l e 1 and o n l y 1 o f RX SINGLE , RX DUAL , and TX QUAD t o 1 , 2 , or 4 receive channels . false ; respectively I f RX ON i s not defined , there i s no r e c e i v e circuitry built . constant RX ON : b o o l e a n := t r u e ; D e f i n e TX HB ON t o [ n o t i m p l e m e n t e d ] constant TX HB ON : b o o l e a n := f a l s e ; enable the transmit halfband filter . D e f i n e e n a b l e [ P l e a s e 1 and o n l y 1 o f TX SINGLE , TX DUAL , and TX QUAD t o 1 , 2 , or 4 t r a n s m it note that channels . currently valid .] o n l y TX SINGLE and TX DUAL a r e b o o l e a n := false ; respectively package c o m m o n c o n f i g 2 r x h b 2 t x I f TX ON i s not defined , is there i s no t r a n s m i t circuitry built . l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; USRP C o n f i g u r a t i o n L a s t C o p y r i g h t (C) 2010 COSMIAC You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA write Software 02110 1301 This pr ogr am is distributed in the hope even that the it will be useful , of the b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License without implied warranty See This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c L ic e n s e as the published VHDL A u t h o r : Steve w i t h 2 Rx ( H a l f b a n d ) and 2 Tx Olivieri M o d i f i e d : 21 J u l y 2010

S o f t w a r e Foundation ; o p t i o n ) any later

version 2 of

version .

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

I n c . , 51 F r a n k l i n

Street ,

constant TX ON :

b o o l e a n := t r u e ;

constant TX SINGLE : constant TX DUAL : constant TX QUAD :

b o o l e a n := t r u e ; b o o l e a n := false ;

constant RX SINGLE : constant RX DUAL : constant RX QUAD :

b o o l e a n :=

b o o l e a n := t r u e ; b o o l e a n := false ;

76

52 53 54 55 56 57 58 59

constant RX HB ON :

b o o l e a n := t r u e ; enable the receive Numerical C o n t r o l l e d Osc .

D e f i n e RX NCO ON t o constant RX NCO ON :

b o o l e a n := t r u e ; enable the receive Cascaded I n t e g r a t o r Comb f i l t e r .

D e f i n e RX CIC ON t o constant RX CIC ON :

b o o l e a n := t r u e ;

end c o m m o n c o n f i g 2 r x h b 2 t x ;

Listing A.17: Conguration for zero transmit channels and two receive channels with no halfband lters. (common cong 2rx 0tx.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 D e f i n e 1 and o n l y 1 o f RX SINGLE , RX DUAL , and TX QUAD t o respectively I f RX ON i s not defined , there i s no r e c e i v e circuitry built . constant RX ON : b o o l e a n := t r u e ; D e f i n e TX HB ON t o [ n o t i m p l e m e n t e d ] constant TX HB ON : b o o l e a n := f a l s e ; enable the transmit halfband filter . D e f i n e e n a b l e [ P l e a s e 1 and o n l y 1 o f TX SINGLE , TX DUAL , and TX QUAD t o 1 , 2 , or 4 t r a n s m it note that channels . currently valid .] o n l y TX SINGLE and TX DUAL a r e b o o l e a n := false ; respectively package c o m m o n c o n f i g 2 r x 0 t x I f TX ON i s not is there false ; i s no t r a n s m i t circuitry built . l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; USRP C o n f i g u r a t i o n L a s t VHDL A u t h o r : C o p y r i g h t (C) 2010 COSMIAC You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA write Software 02110 1301 This pr ogr am is distributed in the hope even that the it will be useful , of the b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License without implied warranty See This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c L ic e n s e as the published Steve w i t h 2 Rx and 0 Tx Olivieri M o d i f i e d : 21 J u l y 2010

S o f t w a r e Foundation ; o p t i o n ) any later

version 2 of

version .

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

I n c . , 51 F r a n k l i n

Street ,

defined ,

constant TX ON :

b o o l e a n :=

constant TX SINGLE : constant TX DUAL : constant TX QUAD :

b o o l e a n := b o o l e a n :=

false ; false ;

77

46 47 48 49 50 51 52 53 54 55 56 57 58 59

e n a b l e

1 , 2 , or 4

receive

channels . false ;

constant RX SINGLE : constant RX DUAL : constant RX QUAD :

b o o l e a n :=

b o o l e a n := t r u e ; b o o l e a n := enable false ; the receive halfband filter .

D e f i n e RX HB ON t o constant RX HB ON :

b o o l e a n := f a l s e ; enable the receive Numerical C o n t r o l l e d Osc .

D e f i n e RX NCO ON t o constant RX NCO ON :

b o o l e a n := t r u e ; enable the receive Cascaded I n t e g r a t o r Comb f i l t e r .

D e f i n e RX CIC ON t o constant RX CIC ON :

b o o l e a n := t r u e ;

end c o m m o n c o n f i g 2 r x 0 t x ;

Listing A.18: Conguration for zero transmit channels and four receive channels with no halfband lters. (common cong 4rx 0tx.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 D e f i n e TX HB ON t o [ n o t i m p l e m e n t e d ] enable the transmit halfband filter . D e f i n e e n a b l e [ P l e a s e 1 and o n l y 1 o f TX SINGLE , TX DUAL , and TX QUAD t o 1 , 2 , or 4 t r a n s m it note that channels . currently valid .] o n l y TX SINGLE and TX DUAL a r e b o o l e a n := false ; respectively package c o m m o n c o n f i g 4 r x 0 t x I f TX ON i s not is there false ; i s no t r a n s m i t circuitry built . l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; USRP C o n f i g u r a t i o n L a s t VHDL A u t h o r : C o p y r i g h t (C) 2010 COSMIAC You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA write Software 02110 1301 This pr ogr am is distributed in the hope even that the it will be useful , of the b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License without implied warranty See This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c L ic e n s e as the published Steve w i t h 4 Rx and 0 Tx Olivieri M o d i f i e d : 21 J u l y 2010

S o f t w a r e Foundation ; o p t i o n ) any later

version 2 of

version .

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

I n c . , 51 F r a n k l i n

Street ,

defined ,

constant TX ON :

b o o l e a n :=

constant TX SINGLE : constant TX DUAL : constant TX QUAD :

b o o l e a n := b o o l e a n :=

false ; false ;

78

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

constant TX HB ON : I f RX ON i s not

b o o l e a n := f a l s e ; defined , there i s no r e c e i v e circuitry built .

constant RX ON : D e f i n e e n a b l e

b o o l e a n := t r u e ; respectively

1 and o n l y 1 o f RX SINGLE , RX DUAL , and TX QUAD t o 1 , 2 , or 4 receive channels . false ; false ;

constant RX SINGLE : constant RX DUAL : constant RX QUAD :

b o o l e a n :=

b o o l e a n :=

b o o l e a n := t r u e ; enable the receive halfband filter .

D e f i n e RX HB ON t o constant RX HB ON :

b o o l e a n := f a l s e ; enable the receive Numerical C o n t r o l l e d Osc .

D e f i n e RX NCO ON t o constant RX NCO ON :

b o o l e a n := t r u e ; enable the receive Cascaded I n t e g r a t o r Comb f i l t e r .

D e f i n e RX CIC ON t o constant RX CIC ON :

b o o l e a n := t r u e ;

end c o m m o n c o n f i g 4 r x 0 t x ;

Listing A.19: Cordic numerically-controlled oscillator (NCO) module for the complex multiplier that translates received data from intermediate frequency to baseband. (cordic.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC SIGNED . ALL ; C o r d i c L a s t M o d i f i e d : 20 J u l y 2010 Steve Olivieri VHDL A u t h o r : C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA write Software 02110 1301 This pr ogr am is distributed in the hope even that the it will be useful , of the b u t WITHOUT ANY WARRANTY; without implied warranty See This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can redistribute it and / o r modify by under Free your terms t h e GNU G e n e r a l P u b l i c either L ic e n s e as the published or C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows .

S o f t w a r e Foundation ; o p t i o n ) any later

version 2 of

License ,

version .

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. GNU G e n e r a l P u b l i c License f o r more details .

I n c . , 51 F r a n k l i n

Street ,

79

34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

l i b r a r y WOR K; use WOR K. FUNCS . ALL ; T h i s t o NOTE : a b l e to is the first stage in t h e Rx c h a i n . actually o f CORDIC . has We move t h e signal fr om IF ban d and we m i g h t b e

baseband . The S par t an 3A u s e them is 1400 hardware multipliers

instead

entity c o r d i c g e ne ri c (

bitwidth zwidth ); :

i n t e g e r := 1 6 ;

i n t e g e r := 16

port ( clock reset enable xi yi xo yo zi zo ); end c o r d i c ; architecture b e h a v i o r a l constant STAGES : type c o n s t r o m constant c o n s t s cordic loop : in : : in in : : in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( zwi d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( zwi d t h 1 downto 0 )

: out : out : in : out

of

is to generate constants . . .

FIXME Need t o somehow

i n t e g e r := 1 7 ; integer ;

i s array ( 0 to STAGES 1) o f : c o n s t r o m := (

8192 , 4836 , 2555 , 1297 , 651 , 326 , 163 , 81 , 41 , 20 , 10 , 5 , 3 , 1 , 1 , 0 , 0) ; component c o r d i c s t a g e g e ne ri c ( bitwidth zwidth shift ); port ( clock reset enable xi yi zi const xo yo zo ); end component ; FIXME T h i s type x y v e c type z v e c should probably be of variable , too . : in : : : : in in in in : : in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( zwi d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( zwi d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( zwi d t h 1 downto 0 ) : : : i n t e g e r := 1 6 ; i n t e g e r := 1

is

i n t e g e r := 1 6 ;

: out : out : out

i s array ( 0 to 1 2 )

s t d l o g i c v e c t o r ( b i t w i d t h +1 downto 0 ) ; s t d l o g i c v e c t o r ( zwi d t h 2 downto 0 ) ;

i s array ( 0 to 1 2 ) o f

80

91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141

signal x : signal y : signal z :

xy vec ; xy vec ; z vec ; : : s t d l o g i c v e c t o r ( b i t w i d t h +1 downto 0 ) ; s t d l o g i c v e c t o r ( b i t w i d t h +1 downto 0 ) ;

signal x i e x t signal y i e x t

signal begin S i g n

zi t

s t d l o g i c v e c t o r ( 1 downto 0 ) ; the inputs ! x i ( b i t w i d t h 1) ) & x i ; y i ( b i t w i d t h 1) ) & y i ;

extend

x i e x t <= r e p e a t ( 2 , y i e x t <= r e p e a t ( 2 ,

Q u adr an t z i t <= z i ( zwi d t h 1 downto zwi d t h 2) ; pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( r e s e t = 1 ) then C l e a r the first stage inputs . x ( 0 ) <= ( o the rs = > 0 ) ; y ( 0 ) <= ( o the rs = > 0 ) ; z ( 0 ) <= ( o the rs = > 0 ) ; e l s i f ( e n a b l e = 1 ) then The Z i s first the two bits are the quadrant , so take the rest here . phase .

z ( 0 ) <= z i ( zwi d t h 2 downto 0 ) ;

X and Y a r e c a se zi t is

the

I and Q c o m p o n e n t s o f

the

sample .

when 00 | 11 = > x ( 0 ) <= x i e x t ; y ( 0 ) <= y i e x t ; when 01 | 10 = > x ( 0 ) <= x i e x t ; y ( 0 ) <= y i e x t ; when o the rs = > null ; end c a se ; end i f ; end i f ; end pro c e ss ; FIXME l o o p cordic stages cs : should be for : i be variable , t o n ar r ow not strict 0:11.

FIXME s h o u l d

able

zwidth ?

i n 0 to 11 generate

cordic stage g e ne ri c map( b i t w i d t h +2 , zwi d t h 1, i ) port map ( c l o c k = > clock , = > z( i ) , const = > c o n v s t d l o g i c v e c t o r ( c o n s t s ( i ) , zwi d t h 1) , xo = > x ( i +1) , yo = > y ( i +1) , zo = > z ( i +1) ) ; reset = > reset , enable = > enable , xi = > x( i ) , yi = > y( i ) , zi

142 143 144 145

end generate c o r d i c s t a g e s ; xo <= x ( 1 2 ) ( b i t w i d t h downto 1 ) ; yo <= y ( 1 2 ) ( b i t w i d t h downto 1 ) ;

81

146 147

zo <= 0 & z ( 1 2 ) ; end b e h a v i o r a l ;

Listing A.20: One stage of the Cordic NCO. (cordic stage.vhd)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 port ( clock reset enable xi yi zi const : : : : : : : in in in in in in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( zwi d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( zwi d t h 1 downto 0 ) ; ); entity c o r d i c s t a g e g e ne ri c ( bitwidth zwidth shift : : : i n t e g e r := 1 6 ; i n t e g e r := 1 6 ; i n t e g e r := 1 is l i b r a r y WOR K; use WOR K. FUNCS . ALL ; l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; A S i n g l e L a s t Cordic Stage A p r i l 2011 Olivieri M o d i f i e d : 10 Steve

VHDL A u t h o r :

C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA write Software 02110 1301 This pr ogr am is distributed in the hope even that the it will be useful , of the b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License without implied warranty See This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c L ic e n s e as the published C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows .

S o f t w a r e Foundation ; o p t i o n ) any later

version 2 of

version .

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

I n c . , 51 F r a n k l i n

Street ,

82

52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 );

xo yo zo

: out : out : out

s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( zwi d t h 1 downto 0 )

end c o r d i c s t a g e ;

architecture b e h a v i o r a l signal begin z i s p o s <= ( not pro c e ss ( c l o c k ) begin z is pos :

of

cordic stage

is

std logic ; z i ( zwi d t h 1) ) ;

i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( r e s e t = 1 ) then C l e a r the o u t p u t s on reset . xo <= ( o the rs = > 0 ) ; yo <= ( o the rs = > 0 ) ; zo <= ( o the rs = > 0 ) ; e l s i f ( e n a b l e = 1 ) then B a s i c a l l y , t o get the s i g n e x t e n d and outputs . shift the inputs , t h e n add / s u b t r a c t as necessary

i f ( z i s p o s = 1 ) then Z i s p o s i t i v e , move c o u n t e r c l o c k w i s e .

xo <= x i ( r e p e a t ( s h i f t +1 , y i ( b i t w i d t h 1) ) & y i ( b i t w i d t h 2 downto s h i f t ) ) ; yo <= y i + ( r e p e a t ( s h i f t +1 , x i ( b i t w i d t h 1) ) & x i ( b i t w i d t h 2 downto s h i f t ) ) ; zo <= z i c o n s t ; else Z i s n e g a t i v e , move c l o c k w i s e .

xo <= x i + ( r e p e a t ( s h i f t +1 , y i ( b i t w i d t h 1) ) & y i ( b i t w i d t h 2 downto s h i f t ) ) ; yo <= y i ( r e p e a t ( s h i f t +1 , x i ( b i t w i d t h 1) ) & x i ( b i t w i d t h 2 downto s h i f t ) ) ; zo <= z i + c o n s t ; end i f ; end i f ; end i f ; end pro c e ss ; end b e h a v i o r a l ;

Listing A.21: First-in-rst-out (FIFO) buer, used for both transmit and receive data between the USB2 port and the CIC lters. (fo.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FIFO L a s t M o d i f i e d : 20 F e b r u a r y 2011 Steve Olivieri VHDL A u t h o r : C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t This it the pr ogr am the Free is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c L ic e n s e as the published C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows .

S o f t w a r e Foundation ;

version 2 of

83

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

( at This

your

o p t i o n ) any is

later

version . in the hope even that the it will be useful , of the

pr ogr am

distributed

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

You s h o u l d along with Foundation ,

have this

r e c e i v e d a copy pr ogr am ; if n ot ,

of

t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA

License USA

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; fifo

entity

is

g e ne ri c ( wi d t h d ep t h addr bits ); : : : i n t e g e r := 1 6 ; i n t e g e r := 1 0 2 4 ;

i n t e g e r := 10

port ( data wr r eq rdreq rdclk wrclk aclr q rdfull rdusedw wrfull wrusedw ); end f i f o ; : : : : : : : out : out : out : out in in in in in in s t d l o g i c v e c t o r ( width 1 downto 0 ) ; std logic ; std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( width 1 downto 0 ) ; std logic ; std logic ; s t d l o g i c v e c t o r ( a d d r b i t s 1 downto 0 ) ; std logic ; std logic ; s t d l o g i c v e c t o r ( a d d r b i t s 1 downto 0 )

: out

rdempty : out

wrempty : out

architecture b e h a v i o r a l S e t r e a d this to false tools false , f o r c e s the

of

fifo

is true for rd req . Choosing false here Verilog

for to

rd ack ,

u s e LUTs f o r true

t h e FIFO s i n c e we l l u s e s BRAMs i n s t e a d !

have

asynchronous

operations .

Choosing though .

The o r i g i n a l

s o u r c e had

constant RD REQ :

b o o l e a n := t r u e ;

The a c t u a l

buffer s t d l o g i c v e c t o r ( width 1 downto 0 ) ;

type RAM i s array ( i n t e g e r range <>) o f s i g n a l mem : RAM( 0 to depth 1) ;

P o i n t e r s signal rdptr si g na l wrptr P r o v i d e

for : :

r e a d and

write

s t d l o g i c v e c t o r ( a d d r b i t s 1 downto 0 ) ; s t d l o g i c v e c t o r ( a d d r b i t s 1 downto 0 ) ; access to outputs w i t h temp signals !

read

84

74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130

sig nal rdusedw t s i g n a l wr u sed w t begin E q u a t e

: :

s t d l o g i c v e c t o r ( a d d r b i t s 1 downto 0 ) ; s t d l o g i c v e c t o r ( a d d r b i t s 1 downto 0 ) ; signals with the real outputs .

t h e temp

rdusedw <= r d u s e d w t ; wrusedw <= wr u sed w t ;

W r i t e on e

line

of

data ,

increase

the

write

pointer .

pro c e ss ( w r c l k , begin

aclr )

i f ( w r c l k EVENT and w r c l k = 1 ) then i f ( a c l r = 1 ) then R e s e t the p o i n t e r on aclr .

w r p t r <= ( o the rs = > 0 ) ; e l s i f ( wr r eq = 1 ) then w r p t r <= w r p t r + 1 ; mem( c o n v i n t e g e r ( w r p t r ) ) <= d a t a ; end i f ; end i f ; end pro c e ss ; I f t h e using read : the read request m odel , o u t p u t on request and i n c r e m e n t

pointer . i f (RD REQ) generate aclr )

rd req t

pro c e ss ( r d c l k , begin

i f ( r d c l k EVENT and r d c l k = 1 ) then i f ( a c l r = 1 ) then r d p t r <= ( o the rs = > 0 ) ; e l s i f ( r d r e q = 1 ) then r d p t r <= r d p t r + 1 ; q <= mem( c o n v i n t e g e r ( r d p t r ) ) ; end i f ; end i f ; end pro c e ss ; end generate r d r e q t ; I f t h e using clock : the read a c k m odel , always o u t p u t and u p d a t e the p o i n t e r on

( ack ) . aclr )

rd req f

i f ( not RD REQ) generate

pro c e ss ( r d c l k , begin

i f ( r d c l k EVENT and r d c l k = 1 ) then i f ( a c l r = 1 ) then R e s e t the p o i n t e r on aclr . r d p t r <= ( o the rs = > 0 ) ; e l s i f ( r d r e q = 1 ) then r d p t r <= r d p t r + 1 ; end i f ; end i f ; end pro c e ss ;

q <= mem( c o n v i n t e g e r ( r d p t r ) ) ; end generate r d r e q f ; H o n e s t l y , j u s t I don t know why some these . As f a r of as these I can exist . tell , The o r i g i n a l never Verilog

said f i x

they re

used .

85

131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150

pro c e ss ( w r c l k ) begin i f ( w r c l k EVENT and w r c l k = 1 ) then wr u sed w t <= c o n v s t d l o g i c v e c t o r ( u n s i g n e d ( w r p t r r d p t r ) , wr u sed w t LENGTH) ; end i f ; end pro c e ss ;

pro c e ss ( r d c l k ) begin i f ( r d c l k EVENT and r d c l k = 1 ) then r d u s e d w t <= c o n v s t d l o g i c v e c t o r ( u n s i g n e d ( w r p t r r d p t r ) , r d u s e d w t LENGTH) ; end i f ; end pro c e ss ; wrempty <= 1 when ( wr u sed w t = 0 ) 0 ; else 0 ;

else

w r f u l l <= 1 when ( wr u sed w t = ( depth 1) ) rdempty <= 1 when ( r d u s e d w t = 0 )

else

0 ; else 0 ;

r d f u l l <= 1 when ( r d u s e d w t = ( depth 1) ) end b e h a v i o r a l ;

Listing A.22: A particular conguration of the FIFO module, 4096 lines of 18 bits each. (fo 4k 18.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 entity f i f o 4 k 1 8 port ( is l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; FIFO ( 4 k L a s t l i n e s , 18 b i t Steve width ) M o d i f i e d : 20 J u l y 2010 Olivieri

VHDL A u t h o r :

C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA write Software 02110 1301 This pr ogr am is distributed in the hope even that the it will be useful , of the b u t WITHOUT ANY WARRANTY; without implied warranty See This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can redistribute it and / o r modify by under Free your terms t h e GNU G e n e r a l P u b l i c either L ic e n s e as the published or C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows .

S o f t w a r e Foundation ; o p t i o n ) any later

version 2 of

License ,

version .

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. GNU G e n e r a l P u b l i c License f o r more details .

I n c . , 51 F r a n k l i n

Street ,

86

34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 );

data wr r eq wrclk wrfull wrusedw q rdreq rdclk rdfull rdusedw aclr end f i f o 4 k 1 8 ;

: : : : out : out

in in in

s t d l o g i c v e c t o r ( 1 7 downto 0 ) ; std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 7 downto 0 ) ; std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ;

wrempty : out

: out : : : out : out : in in in

rdempty : out

std logic

architecture b e h a v i o r a l component f i f o g e ne ri c ( wi d t h d ep t h addr bits ); is

of

fifo 4k 18

is

: : :

i n t e g e r := 1 6 ; i n t e g e r := 1 0 2 4 ; i n t e g e r := 10

port ( data wr r eq rdreq rdclk wrclk aclr q rdfull rdusedw wrfull wrusedw ); end component ; begin fifo 4k : fifo > 12) addr bits = rdreq = > rdreq , rdclk = > rdclk , wrclk = > wrclk , rdusedw = > rdusedw , wr r eq = > wr r eq , : : : : : : : out : out : out : out in in in in in in s t d l o g i c v e c t o r ( width 1 downto 0 ) ; std logic ; std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( width 1 downto 0 ) ; std logic ; std logic ; s t d l o g i c v e c t o r ( a d d r b i t s 1 downto 0 ) ; std logic ; std logic ; s t d l o g i c v e c t o r ( a d d r b i t s 1 downto 0 )

: out

rdempty : out

wrempty : out

g e ne ri c map( wi d t h = > 1 8 , d ep t h = > 4096 , port map ( d a t a = > d at a , aclr = > aclr , q = > q, end b e h a v i o r a l ;

rdfull = > r d f u l l , rdempty = > rdempty ,

wrfull = > w r f u l l , wrempty = > wrempty , wrusedw = > wrusedw ) ;

Listing A.23: Denes (fpga regs common.vhd)

1 2 3 4 5 6 D e f i n i t i o n s Common f o r L a s t C o p y r i g h t (C) 2010 COSMIAC VHDL A u t h o r : Steve M o d i f i e d : 21 J u l y 2010 Olivieri

some

of

the

congurations

registers

for

the

USRP.

a l l FPGA C o n f i g u r a t i o n s ( R e g i s t e r s 0 31)

87

7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

The c o p y r i g h t You s h o u l d along with This pr ogr am This it the ( at pr ogr am the Free your

and

license

fr om

the

original

Verilog

implementation

follows .

USRP U n i v e r s a l

S o f t w a r e Radio

Peripheral

C o p y r i g h t (C) 2003 M at t E t t u s

is

free of

s o f t w a r e ; y ou can either

redistribute

it

and / o r License ,

modify by or

under

terms

t h e GNU G e n e r a l P u b l i c later version .

L ic e n s e as the

published

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

is

distributed

in

the

hope even

that the

it

will

be

useful , of the

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c have this License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more of details .

r e c e i v e d a copy pr ogr am ; if n ot ,

t h e GNU G e n e r a l P u b l i c to the Free

License

write

Software 02110 1301 USA

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

T h i s file is derived Someone fr om should too ! the original Verilog file , code w h i c h was to automatically

g e n e r a t e d .

update

t h e GNU Radio

automatically

g e n e r a t e VHDL f i l e s , l i b r a r y IEEE ;

use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ;

package f p g a r e g s c o m m o n The FPGA n e e d s g o i n g to

is rate that samples a r e com in g fr om and

t o know t h e

t h e A/D s and D/A s .

d i v = 128 e6 / s a m p l e r a t e i n t e g e r := 0 ; i n t e g e r := 1 ;

constant FR TX SAMPLE RATE DIV : constant FR RX SAMPLE RATE DIV :

2 and 3 a r e M a s t e r

defined

in

t h e ATR s e c t i o n controls i n t e g e r := 4 ;

e n a b l e and

reset

constant FR MASTER CTRL :

i / o

direction the is

registers makes l o w 16 it

for is

pins

that

go

to

daughterboards . the d board .

S e t t i n g t o p 16

bit

an o u t p u t fr om value s l o t

t h e FPGA t o 0

mask ,

constant FR OE 0 : constant FR OE 1 : constant FR OE 2 : constant FR OE 3 : i / o registers is

i n t e g e r := 5 ; i n t e g e r := 6 ; i n t e g e r := 7 ; i n t e g e r := 8 ; pins that is go

for : : : :

to

daughterboards . 0

t o p 16

a mask ,

l o w 16

value s l o t

constant FR IO 0 constant FR IO 1 constant FR IO 2 constant FR IO 3

i n t e g e r := 9 ; i n t e g e r := 1 0 ; i n t e g e r := 1 1 ; i n t e g e r := 1 2 ; i n t e g e r := 1 3 ;

constant FR MODE :

88

64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 A u t o m a t i c T r a n s m i t / R e c e i v e I f automatic fifo transmit / receive the selects (ATR) or switching absence of is of enabled data for in each in of the the 4 FR ATR CTL r e g i s t e r , t r a n s m i t b a n k s Each d a u g h t e r b o a r d FR ATR MASK { 0 , 1 , 2 , 3 } : FR ATR TXVAL { 0 , 1 , 2 , 3 } : FR ATR RXVAL { 0 , 1 , 2 , 3 } : If t h e Tx fifo contains data , then the bits the fr om TXVAL t h a t bits are selected are b y MASK a r e output . Otherwise , fr om RXVAL t h a t T hese registers determine bit the is which If a of the in daugherboard t h e mask else is i /o pins set , the output are slot h a s 3 16 b i t registers associated with it : FR ATR MASK , FR ATR TXVAL and FR ATR RXVAL of presence t h e FPGA switching o f f s e t corrections f o r ADC s and DAC s i n t e g e r := 1 6 ; i n t e g e r := 1 7 ; i n t e g e r := 1 8 ; i n t e g e r := 1 9 ; ( 2 s com plem en t ) constant FR ADC OFFSET 0 : constant FR ADC OFFSET 1 : constant FR ADC OFFSET 2 : constant FR ADC OFFSET 3 : I f The 4 l o w T h i s control all loop works if the do attached daugherboard This b l o c k s DC . C u r r e n t l y b a s i c rx , daughterboards tv rx , b l o c k DC. includes : ADC0 = ( 1 << 0 ) ADC1 = ( 1 << 1 ) ADC2 = ( 1 << 2 ) ADC3 = ( 1 << 3 ) bits are significant : the corresponding correction bit is set , enable the a u t o m a t i c DC I f the corresponding the i /o pins Typically bit for used is set , i n t e r n a l FPGA d e b u g bank of circuitry c o n t r o l s i / o p i n s . the for associated daughterboard

d e b u g g i n g FPGA d e s i g n s .

constant FR DEBUG EN :

i n t e g e r := 1 4 ;

o f f s e t

control

loop .

dbs rx ,

flex xxx rx . i n t e g e r := 1 5 ;

DC O f f s e t

C o n t r o l Loop E n a b l e

constant FR DC OFFSET CL EN :

b e t w e e n two i /o p in s .

sets

values

daughterboard

affected

b y ATR s w i t c h i n g . i /o n or m al

bit

corresponding

controlled i /o pin

b y ATR, output

it s

v a l u e comes fr om FR IO { 0 , 1 , 2 , 3 } .

register :

selected

b y MASK a r e

output . 0

constant FR ATR MASK 0 : constant FR ATR TXVAL 0 : constant FR ATR RXVAL 0 :

i n t e g e r := 2 0 ; s l o t i n t e g e r := 2 1 ; i n t e g e r := 2 2 ;

89

121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136

constant FR ATR MASK 1 : constant FR ATR TXVAL 1 : constant FR ATR RXVAL 1 : constant FR ATR MASK 2 : constant FR ATR TXVAL 2 : constant FR ATR RXVAL 2 : constant FR ATR MASK 3 : constant FR ATR TXVAL 3 : constant FR ATR RXVAL 3 :

i n t e g e r := 2 3 ; s l o t i n t e g e r := 2 4 ; i n t e g e r := 2 5 ; i n t e g e r := 2 6 ; s l o t i n t e g e r := 2 7 ; i n t e g e r := 2 8 ; i n t e g e r := 2 9 ; s l o t i n t e g e r := 3 0 ; i n t e g e r := 3 1 ;

C l o c k

ticks

to

delay

rising

and

falling

edge

o f T/R s i g n a l

constant FR ATR TX DELAY : constant FR ATR RX DELAY : end f p g a r e g s c o m m o n ;

i n t e g e r := 2 ; i n t e g e r := 3 ;

Listing A.24: Denes (fpga regs standard.vhd)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 package f p g a r e g s s t a n d a r d is T h i s file is derived Someone fr om should too ! D e f i n i t i o n s L a s t C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t You s h o u l d along with have this This pr ogr am is distributed This it the ( at pr ogr am the is free of USRP U n i v e r s a l and license for M o d i f i e d : 21 J u l y 2010 Steve Olivieri

some

of

the

congurations

registers

for

the

USRP.

s t a n d a r d FPGA b u i l d ( r e g s 32+) and c u s t o m (64 95) .

VHDL A u t h o r :

fr om

the

original

Verilog

implementation

follows .

S o f t w a r e Radio

Peripheral

C o p y r i g h t (C) 2003 M at t E t t u s s o f t w a r e ; y ou can redistribute it and / o r modify by

under Free your

terms

t h e GNU G e n e r a l P u b l i c either later version . in the hope even that the

L ic e n s e as the

published or

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

License ,

it

will

be

useful , of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more of details .

the

r e c e i v e d a copy pr ogr am ; if n ot ,

t h e GNU G e n e r a l P u b l i c to the Free

License

write

Software 02110 1301 USA

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

the original Verilog file , code w h i c h was to automatically

g e n e r a t e d .

update

t h e GNU Radio

automatically

g e n e r a t e VHDL f i l e s , l i b r a r y IEEE ;

use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ;

90

38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

DDC / DUC constant FR INTERP RATE : constant FR DECIM RATE : DDC c e n t e r freq i n t e g e r := 3 4 ; i n t e g e r := 3 5 ; i n t e g e r := 3 6 ; i n t e g e r := 3 7 ; P hase i n t e g e r := 3 2 ; [ 1 , 1 0 2 4 ] i n t e g e r := 3 3 ; [ 1 , 2 5 6 ]

constant FR RX FREQ 0 : constant FR RX FREQ 1 : constant FR RX FREQ 2 : constant FR RX FREQ 3 : S e e b e l o w

f o r DDC S t a r t i n g

3 2 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 c o n f i g u r e FPGA Rx mux

+ + + + + + + + | T her e DDC I I f Z == 1 , NCH s p e c i f i e s t h e USB . 8 16 b i t t h e number o f values complex channels that are sent to across 2 , 4 or a l l DDC Q i n p u t s are are set to zero by the two bit f i e l d s Q3 , Q2 , Q1 & Q0 I f Z == 0 , DDC Q i n p u t s specified 0 = DDC i n p u t 1 = DDC i n p u t 2 = DDC i n p u t 3 = DDC i n p u t is is is is fr om ADC 0 fr om ADC 1 fr om ADC 2 fr om ADC 3 inputs are specified by the two bit fields I3 , I2 , I1 & I0 a r e a maximum o f 4 digital inputs , downconverters in I and Q, the t h e FPGA. outputs , I & Q. Each DDC h a s t w o 16 b i t and t w o 16 b i t m u st b e zero | Q3 | I 3 | Q2 | I 2 | Q1 | I 1 | Q0 | I 0 | Z | NCH |

+ + + + + + + +

The l e g a l values .

are 1 , 2 or 4 ,

corresponding

constant FR RX MUX :

i n t e g e r := 3 8 ;

| 3 2 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | DAC3 | DAC2 | DAC1 | DAC0 | 0 | NCH | c o n f i g u r e FPGA Tx Mux .

+ + + + + + + + + + + + + NCH s p e c i f i e s t h e USB . 16 b i t T her e T her e Each 4 b i t DACx f i e l d w h e t h e r or not specifies the source Each for t h e DAC and is coded t h a t DAC i s enabled . subfield a r e two are interpolators with complex i n p u t s and outputs . values . t h e number o f values complex channels that are sent across The l e g a l are 1 or 2 , corresponding t o 2 or 4

f o u r DACs .

(We u s e

t h e DUC i n

e a c h AD9862 . )

91

95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151

l i k e

this :

3 2 1 0 + + + |E| N | + + +

Where E i s N which

set

if

t h e DAC i s is

e n a b l e d , and N s p e c i f i e s to t h i s DAC.

which

i n t e r p o l a t o r

output

connected

interp

output

0 1 2 3

chan 0 I chan 0 Q chan 1 I chan 1 Q i n t e g e r := 3 9 ;

constant FR TX MUX :

REFCLK c o n t r o l C o n t r o l w h e t h e r a r e f e r e n c e and w hat | 3 2 1 frequency . The clock is is sent to the daughterboards , i /o pin 0. refclk s e n t on d b o a r d

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Reserved ( Must b e zero ) |E| DIVISOR |

+ + + + + + + + B i t 7 B i t s 1 t u r n s on 6:0 Divider r e f c l k , 0 a l l o w s IO u s e i n t e g e r := 4 0 ; i n t e g e r := 4 1 ; i n t e g e r := 4 2 ; i n t e g e r := 4 3 ; value

constant FR TX A REFCLK : constant FR RX A REFCLK : constant FR TX B REFCLK : constant FR RX B REFCLK :

DDC S t a r t i n g P hase i n t e g e r := 4 4 ; i n t e g e r := 4 5 ; i n t e g e r := 4 6 ; i n t e g e r := 4 7 ; constant FR RX PHASE 0 : constant FR RX PHASE 1 : constant FR RX PHASE 2 : constant FR RX PHASE 3 :

Tx d a t a | 3 2 1 format control register

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Reserved ( Must b e zero ) | FMT |

+ + + + + + FMT v a l u e s : i n t e g e r := 4 8 ; constant FR TX FORMAT :

92

152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208

Rx d a t a | 3

format

control

register 2 1

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Reserved ( Must b e zero ) | B |Q | WIDTH | SHIFT |

+ + + + + +

+ + + + + + FMT v a l u e s : i n t e g e r := 4 9 ; currently are : constant FR RX FORMAT : The v a l i d B 0 0 Q 1 1 WIDTH 16 8 future bit SHIFT 0 8 values o f WIDTH = { 4 , 2 , 1 } s i n c e we n e e d t o know p a c k e t alignment .

combinations

P o s s i b l e 12

takes a

more work ,

FIXME r e g i s t e r n u m ber s 50 t o 63 a r e available

R e g i s t e r s 64 t o 95 a r e reserved will for not u s e r c u s t o m FPGA b u i l d s . touch these .

The s t a n d a r d USRP s o f t w a r e constant FR USER 0 : constant FR USER 1 : constant FR USER 2 : constant FR USER 3 : constant FR USER 4 : constant FR USER 5 : constant FR USER 6 : constant FR USER 7 : constant FR USER 8 : constant FR USER 9 : constant FR USER 10 : constant FR USER 11 : constant FR USER 12 : constant FR USER 13 : constant FR USER 14 : constant FR USER 15 : constant FR USER 16 : constant FR USER 17 : constant FR USER 18 : constant FR USER 19 : constant FR USER 20 : constant FR USER 21 : constant FR USER 22 : constant FR USER 23 : constant FR USER 24 : constant FR USER 25 : constant FR USER 26 : constant FR USER 27 : constant FR USER 28 : constant FR USER 29 : constant FR USER 30 :

i n t e g e r := 6 4 ; i n t e g e r := 6 5 ; i n t e g e r := 6 6 ; i n t e g e r := 6 7 ; i n t e g e r := 6 8 ; i n t e g e r := 6 9 ; i n t e g e r := 7 0 ; i n t e g e r := 7 1 ; i n t e g e r := 7 2 ; i n t e g e r := 7 3 ; i n t e g e r := 7 4 ; i n t e g e r := 7 5 ; i n t e g e r := 7 6 ; i n t e g e r := 7 7 ; i n t e g e r := 7 8 ; i n t e g e r := 7 9 ; i n t e g e r := 8 0 ; i n t e g e r := 8 1 ; i n t e g e r := 8 2 ; i n t e g e r := 8 3 ; i n t e g e r := 8 4 ; i n t e g e r := 8 5 ; i n t e g e r := 8 6 ; i n t e g e r := 8 7 ; i n t e g e r := 8 8 ; i n t e g e r := 8 9 ; i n t e g e r := 9 0 ; i n t e g e r := 9 1 ; i n t e g e r := 9 2 ; i n t e g e r := 9 3 ; i n t e g e r := 9 4 ;

93

209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225

constant FR USER 31 : R e g i s t e r s Rx M a s t e r / s l a v e needed for

i n t e g e r := 9 5 ; multi usrp master / s l a v e configuration

control

register

(FR RX MASTER SLAVE = FR USER 0 )

constant FR RX MASTER SLAVE : constant bitnoFR RX SYNC :

i n t e g e r := 6 4 ; i n t e g e r := 1 ; i n t e g e r := 2 ; output as v a l u e s on t h e If io lines . which uses these

i n t e g e r := 0 ;

constant bitnoFR RX SYNC MASTER : constant bitnoFR RX SYNC SLAVE : C a u t i o n The m a s t e r They I f The way this is supposed to be inheritely also set as the settings these

will

enable output slave

lines

output .

y ou h a v e a d a u g h t e r c a r d anything if y ou don t

lines y ou

t h e n y ou then register

will

b u r n y o u r u s r p and d a u g h t e r c a r d . connect a master .

bits

y o u r u s r p won t do

Rx M a s t e r / s l a v e

control

used

is

c o n n e c t i n g a ( s h o r t ) 16 p i n to dbsrx slave io rx [8..15]

flatcable

fr om an r x slave usrp

daughterboard 226 227 228 229 230 231 232 233 234 235 236 237 238 d b s r x : b a s i c connect rx : pay line

i n RXA m a s t e r with basic rx

io rx [8..15] b o a r d s or

on RXA o f

T h i s can b e don e connect

boards

m a s t e r J 25 t o J 25 t o to the be

s l a v e J 25 lineup at of your connector . of the daughterboards usrp . since on m a s t e r and slave .

s l a v e J 25 t h e same side will

CAUTION: The r e d I f

attention ( pin1 )

should

y ou t u r n a r o u n d

the

c a b l e on on e en d y ou flatcable io pins . if y ou a r e

burn your

You c a n n o t u s e a 16 p i n these You can You can use a still also lot link of

u s i n g FLEX400 o r FLEX2400 d a u g h t e r b o a r d s , or 1 pin cable the m a s t e r RXA

the

them b u t y ou m u st u s e link . it the the just

only a 2 pin

u s e a 2 w i r e like twist also for

put a 2 pin to

h e a d e r on i o [ 1 5 ] , gn d o f the s l a v e RXA db . on t h e the wire leds

d a u g h t e r b o a r d and c o n n e c t You can u s e a c a b l e Make s u r e y ou don t To b e s a v e y ou c o u l d is not this 239 240 241 242 S i n c e this s t i l l rx io [0] line has the refclk can n o r m a l l y

i o 1 5 , gn d o f found with single otherwise

ones

m a i n b o r d o f a PC . sync output to to ground . io [15] , but io [ 15] slave

cable , use a

y ou c o n n e c t

the

fr om m a s t e r

optimal

signal

integrity .

be

used as a if y ou u s e

refclk the

and

is

not

e x p o r t e d on setup ( it is

all not

daughterboards t o u c h e d by the

function

master / s l a v e

master / s l a v e 243 244 245 246

settings ) . circuitry will only use io p i n 15 and d o e s not t o u c h any of the other io

The m a s t e r / s l a v e pins .

constant bitnoFR RX SYNC INPUT IOPIN : constant bmFR RX SYNC INPUT IOPIN : TODO t h e define output pin is still

i n t e g e r := 1 5 ; FIXME ? the following in the verilog code , make it listen to

i n t e g e r := 2 bitnoFR RX SYNC INPUT IOPIN ;

hardcoded

247 248 249 250 251 252 253 254 255 256

constant bitnoFR RX SYNC OUTPUT IOPIN : constant bmFR RX SYNC OUTPUT IOPIN :

i n t e g e r := 1 5 ;

i n t e g e r := 2 bitnoFR RX SYNC OUTPUT IOPIN ;

======================================================================= READBACK R e g i s t e r s ======================================================================= r e a d b a c k a s i d e r e a d b a c k b s i d e i /o pins i n t e g e r := 1 ; i n t e g e r := 2 ; i /o pins constant FR RB IO RX A IO TX A : constant FR RB IO RX B IO TX B :

94

257 258 259 260 261 262 263 264 265 266 267 268 269 270 FPGA C a p a b i l i t y 3 2 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 register

+ + + + + + | Bottom 4 b i t s N e x t 4 b i t s a r e Rx a r e Tx capabilities capabilities Reserved ( Must b e zero ) | T | NDUC | R | NDDC | + + + + + +

constant FR RB CAPS : end f p g a r e g s s t a n d a r d ;

i n t e g e r := 3 ;

Listing A.25: This package contains a few functions that VHDL lacks, but which make code easier to read and write. (funcs.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 C o n v e r t s a std logic vector logic vector into a signed logic vector of equal width . func ti o n c o n v s i g n e d ( S : s t d l o g i c v e c t o r ) return s i g n e d ; C o n v e r t s a signed logic vector into a std logic vector logic vector of equal width . package f u n c s is Verilog replication natural ; B : operator . For e x a m p l e , r e pe a t (3 , 1 ) returns 111. M im ics t h e T h i s a r e u s e file should in of probably not exist . I think that m ost o f these functions eventually available instead n u m e r i c s t d and n u m e r i c e x t r a , w h i c h we s h o u l d A c o l l e c t i o n L a s t VHDL A u t h o r : C o p y r i g h t (C) 2010 COSMIAC You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA write Software 02110 1301 This pr ogr am is distributed in the hope even that the it will be useful , of the b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License without implied warranty See This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c L ic e n s e as the published of useful functions that should really be built i n t o VHDL ! M o d i f i e d : 21 J u l y 2010 Steve Olivieri

S o f t w a r e Foundation ; o p t i o n ) any later

version 2 of

version .

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

I n c . , 51 F r a n k l i n

Street ,

std logic arith .

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ;

func ti o n r e p e a t (N :

s t d l o g i c ) return

std logic vector ;

func ti o n c o n v s t d l o g i c v e c t o r ( S :

s i g n e d ) return

std logic vector ;

95

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

C o n v e r t s a end f u n c s ; package body f u n c s

boolean

to a

std logic

element ,

where

t r u e = 1 and

false =

0 .

func ti o n c o n v s t d l o g i c (B :

b o o l e a n ) return

std logic ;

is natural ; B: std logic )

func ti o n r e p e a t (N : return is begin

std logic vector

return (N1 downto 0 = > B) ; end ;

func ti o n c o n v s t d l o g i c v e c t o r ( S : return is v a r i a b l e tmp : begin for i i n S R A N G E loop std logic vector

signed )

A N G E) ; s t d l o g i c v e c t o r ( S R

tmp ( i ) := S ( i ) ; end loop ; return tmp ; end ; func ti o n c o n v s i g n e d ( S : return s i g n e d is v a r i a b l e tmp : begin for i i n S R A N G E loop s i g n e d ( S R A N G E) ; std logic vector )

tmp ( i ) := S ( i ) ; end loop ; return tmp ; end ; func ti o n c o n v s t d l o g i c (B : return is begin i f (B) then return else return end i f ; end ; end f u n c s ; 0 ; 1 ; std logic boolean )

Listing A.26: Halfband decimation lter. Decimates baseband data by a factor of two. (halfband decim.vhd)
1 2 3 4 5 6 7 8 H a l f b a n d L a s t C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t and license fr om the original Verilog implementation follows . Decimator M o d i f i e d : 21 J u l y 2010 Steve Olivieri

VHDL A u t h o r :

96

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA write Software 02110 1301 This pr ogr am is distributed in the hope even that the it will be useful , of b u t WITHOUT ANY WARRANTY; without implied warranty See This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can redistribute it and / o r modify by C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral

under Free your

terms

t h e GNU G e n e r a l P u b l i c either later version .

L ic e n s e as the

published or

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

License ,

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. GNU G e n e r a l P u b l i c License f o r more details .

the

I n c . , 51 F r a n k l i n

Street ,

T h i s The S e e t h u s c o e f f r o m . vhd the middle for the full 1.0. set . The t a p s are the scaled middle relative tap , to 32768 , are 8 middle ... , 1468 , 0 , 2 9 5 0 , 0 , 6158 , 0 , 2 0 5 8 5 , 3 2 7 6 8 , 2 0 5 8 5 , 0 , 6158 , 0 , 2 9 5 0 , 0 , 1468 , | tap + ... e v e r y i m p l e m e n t s a 31 t a p coefficients other coefficient halfband is zero . filter that the d e c i m a t e s by two . exception section of of the middle looks tap , this : taps like

a r e s y m m e t r i c , and w i t h

The m i d d l e

tap

equals side , for

Not c o u n t i n g are tap .

there

non z e r o r e q u i r e s r e p l a c e 2 we Abou t 8 we can r a t e , On t h e just

t a p s on e a c h a mulitply multiplies to

and t h e y

symmetric . Because Since

A naive to

implementation output 1.0 ,

e a c h non z e r o

o f symmetry , we can com pu t e e a c h middle tap is the

w i t h 1 add and 1 m u l t i p l y . multiplications . delay line value .

Thus ,

s a m p l e , we n e e d add t h e

perform 8

corresponding

t i m i n g : We i m p l e m e n t t o com pu t e a a c c e p t a new i n p u t sample s t r o b e i n may b e output

this value

with a every 4 less

single However ,

multiplier , s i n c e we r e strobe in than once

so is

it

takes when

cycles

single

output .

d e c i m a t i n g by two asserted decimation

cycles .

t h e r e s a new i n p u t

available .

D e p e n d i n g on t h e frequently

overall

asserted

every 4 clocks .

s i d e , we a s s e r t Every time We s p l i t for

strobe out is line

when o u t p u t

c o n t a i n s a new s a m p l e . t h e new d a t a on e delay of for the line into the for

I m p l e m e n t a t i o n : t h e e v e n t h e i s delay line .

strobe in the delay

a s s e r t e d we s t o r e into r am 16 odd is

t w o com pon en t s , assertion product . while

s a m p l e s , and on e odd s a m p l e s .

t h e odd s a m p l e s .

T h i s ram i s clock

w r i t t e n on e a c h odd computing the at even the dot

s t r o b e i n , and is read incoming

r e a d on e a c h fr om

when we r e it

ram16 even able to writing the

s i m i l a r , e v e n

although

because different

holds

s a m p l e s we m u st b e

t w o s a m p l e s l i b r a r y IEEE ;

addresses

t h e same t i m e ,

s a m p l e s . Thus i t s t r i p l e p o r t e d .

use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; l i b r a r y WOR K;

97

66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122

use WOR K.REDUCE PACK . ALL ; use WOR K. FUNCS . ALL ; entity hal fband deci m port ( clock reset enable strobe in strobe out data in data out debugctrl ); end h a l f b a n d d e c i m ; architecture b e h a v i o r a l component c o e f f r o m port ( clock ad d r data ); end component ; : : in in std logic ; s t d l o g i c v e c t o r ( 2 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) of halfband decim is : : : in in : : in in std logic ; std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; : out : out s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

is

: out in

s t d l o g i c v e c t o r ( 1 5 downto 0 )

is

: out

component ram16 2sum i s port ( clock write in wr addr wr data rd addr1 rd addr2 sum ); end component ; component ram16 i s port ( clock write in wr addr wr data rd addr rd data ); end component ; : : : in in in : : in in std logic ; std logic ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) : : in in : : : out in in : : in in std logic ; std logic ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 )

: out

component mult i s port ( clock x y product enable in enable out ); : : : : : out in : out in in in std logic ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 3 0 downto 0 ) ; std logic ; std logic

98

123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179

end component ; component a c c port ( clock reset clear enable in enable out addend sum ); end component ; signal rd addr1 signal rd addr2 si g na l phase : signal base addr : : : s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; : : in : : : : out in : out in in in std logic ; std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 3 0 downto 0 ) ; s t d l o g i c v e c t o r ( 3 3 downto 0 )

is

s t d l o g i c v e c t o r ( 3 downto 0 ) ;

s i g n a l

mac out

s i g n e d ( 1 5 dow n t o 0 ) ; : s i g n e d ( 1 5 downto 0 ) ;

signal middle data s i g n a l sum : signal coeff :

s i g n e d ( 1 5 downto 0 ) ; s i g n e d ( 1 5 downto 0 ) ; : : s i g n e d ( 3 0 downto 0 ) ; s i g n e d ( 3 3 downto 0 ) ; conversion of the o p e r a t o r s on o u t p u t s , signed signals . 0) ; s o we n e e d

si g na l product s i g n a l su m even VHDL doesn t s i g n a l

support :

s t d l o g i c v e c t o r mac out t

versions

s t d l o g i c v e c t o r ( 1 5 dow n t o :

signal middle data t s i g n a l su m t signal : coeff t :

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; : : s t d l o g i c v e c t o r ( 3 0 downto 0 ) ; s t d l o g i c v e c t o r ( 3 3 downto 0 ) ;

signal product t sig nal sum even t

signal c l e a r

std logic ; : std logic ;

signal store odd signal s t a r t :

std logic ; : : : : : : : : : : : : : std logic ; std logic ; std logic ; std logic ; std logic ; std logic ; std logic ; std logic ; std logic ; std logic ; std logic ; std logic ; std logic ;

signal s t a r t d 1 signal s t a r t d 2 signal s t a r t d 3 signal s t a r t d 4 signal s t a r t d 5 signal s t a r t d 6 signal s t a r t d 7 signal s t a r t d 8 signal s t a r t d 9 signal start dA signal start dB signal start dC signal start dD

signal mult en

std logic ; : : std logic ; std logic ;

signal mult en pre latch result

signal

99

180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236

signal acc en s i g n a l d ou t :

std logic ;

s i g n e d ( 3 3 downto 0 ) ; : s t d l o g i c v e c t o r ( 2 downto 0 ) ; : : : : std logic ; std logic ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; std logic ; with each strobe .

s i g n a l cr om ad d r

signal w r it e in e v e n signal w rit e in o dd signal rd addr odd signal s t r o b e o u t t begin F l i p

b e t w e e n odd and e v e n

pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( r e s e t = 1 ) then s t o r e o d d <= 0 ; e l s i f ( s t r o b e i n = 1 ) then s t o r e o d d <= ( not s t o r e o d d ) ; end i f ; end i f ; end pro c e ss ; s t a r t <= 1 when ( ( s t r o b e i n = 1 ) and ( s t o r e o d d = 1 ) ) 0 ;

else

pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( r e s e t = 1 ) then b a s e a d d r <= ( o the rs = > 0 ) ; e l s i f ( s t a r t = 1 ) then b a s e a d d r <= b a s e a d d r + 1 ; end i f ; end i f ; end pro c e ss ; P hase control logic .

pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( r e s e t = 1 ) then p h a s e <= c o n v s t d l o g i c v e c t o r ( 8 , e l s i f ( s t a r t = 1 ) then p h a s e <= c o n v s t d l o g i c v e c t o r ( 0 , e l s i f ( p h a s e /= 8 ) then p h a s e <= p h a s e + 1 ; end i f ; end i f ; end pro c e ss ; R e c a l l that each signal is updated concurrently ! 4) ; 4) ;

pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then s t a r t d 1 <= s t a r t ; s t a r t d 2 <= s t a r t d 1 ;

100

237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293

s t a r t d 3 <= s t a r t d 2 ; s t a r t d 4 <= s t a r t d 3 ; s t a r t d 5 <= s t a r t d 4 ; s t a r t d 6 <= s t a r t d 5 ; s t a r t d 7 <= s t a r t d 6 ; s t a r t d 8 <= s t a r t d 7 ; s t a r t d 9 <= s t a r t d 8 ; s t a r t d A <= s t a r t d 9 ; s t a r t d B <= s t a r t d A ; s t a r t d C <= s t a r t d B ; s t a r t d D <= s t a r t d C ; end i f ; end pro c e ss ; pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( p h a s e /= 8 ) then m u l t e n p r e <= 1 ; else m u l t e n p r e <= 0 ; end i f ; m u l t e n <= m u l t e n p r e ; end i f ; end pro c e ss ; T hese comments w e r e i n c l e a r <= s t a r t d 4 ; the original Verilog source . I copied them h e r e .

was dC was dC was dD phase .

l a t c h r e s u l t <= s t a r t d 4 ; s t r o b e o u t t <= s t a r t d 5 ; The t w o

v a l u e s we r e a d d e p e n d on t h e base addr )

pro c e ss ( p h ase , begin

c a se c o n v i n t e g e r ( p h a s e ( 2 downto 0 ) ) when 0 = > r d a d d r 1 <= b a s e a d d r + 0 ; r d a d d r 2 <= b a s e a d d r + 1 5 ; when 1 = > r d a d d r 1 <= b a s e a d d r + 1 ; r d a d d r 2 <= b a s e a d d r + 1 4 ; when 2 = > r d a d d r 1 <= b a s e a d d r + 2 ; r d a d d r 2 <= b a s e a d d r + 1 3 ; when 3 = > r d a d d r 1 <= b a s e a d d r + 3 ; r d a d d r 2 <= b a s e a d d r + 1 2 ; when 4 = > r d a d d r 1 <= b a s e a d d r + 4 ; r d a d d r 2 <= b a s e a d d r + 1 1 ; when 5 = > r d a d d r 1 <= b a s e a d d r + 5 ; r d a d d r 2 <= b a s e a d d r + 1 0 ; when 6 = > r d a d d r 1 <= b a s e a d d r + 6 ; r d a d d r 2 <= b a s e a d d r + 9 ;

is

101

294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326

when 7 = > r d a d d r 1 <= b a s e a d d r + 7 ; r d a d d r 2 <= b a s e a d d r + 8 ; when o the rs = > r d a d d r 1 <= b a s e a d d r + 0 ; r d a d d r 2 <= b a s e a d d r + 1 5 ; end c a se ; end pro c e ss ; E q u a t e the temporaries with the signed values .

m a c o u t <= c o n v s i g n e d ( m a c o u t t ) ; m i d d l e d a t a <= c o n v s i g n e d ( m i d d l e d a t a t ) ; sum <= c o n v s i g n e d ( su m t ) ; c o e f f <= c o n v s i g n e d ( c o e f f t ) ; p r o d u c t <= c o n v s i g n e d ( p r o d u c t t ) ; su m even <= c o n v s i g n e d ( s u m e v e n t ) ; cr om ad d r <= p h a s e ( 2 downto 0 ) 1 ;

coeff rom0

coeff rom ad d r = > cr om ad d r , data = > coeff t ) ; 0 ;

port map ( c l o c k = > clock ,

w r i t e i n e v e n <= 1 when ( ( s t r o b e i n = 1 ) and ( s t o r e o d d = 0 ) )

else

r am 16 even

ram16 2sum > write in even , write in = wr addr = > base addr , wr data = >

port map ( c l o c k = > clock , data in , rd addr1 = > rd addr1 ,

rd addr2 = > r d a d d r 2 , sum = > su m t ) ;

w r i t e i n o d d <= 1 when ( ( s t r o b e i n = 1 ) and ( s t o r e o d d = 1 ) ) r d a d d r o d d <= b a s e a d d r + 6 ; ram16 odd : ram16 h o l d s middle items

else

0 ;

port map ( c l o c k = > clock , data in ,

write in = > write in odd ,

wr addr = > base addr ,

wr data = >

327 328 329 330 331 332 333 334 335 336 337 acc0 : mult0 :

> rd addr odd , rd addr = mult product = > product t ,

rd data = > middle data t ) ;

> sum t , port map ( c l o c k = > clock , x = > coeff t , y = enable in = > m u l t en , enable out = > acc en ) ;

acc reset = > reset , > acc en , enable in = enable out = > OPEN, clear = > clear , addend = > p r o d u c t t , sum = > sum even t ) ;

port map ( c l o c k = > clock ,

d ou t <= su m even + c o n v s i g n e d ( ( r e p e a t ( 4 ,

middle data (15) ) & 0 ) ) ) ;

c o n v s t d l o g i c v e c t o r ( middle data ) & repeat (14 , 338 339 340 341 342 343 344 345 pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( r e s e t = 1 ) then d a t a o u t <= ( o the rs = > 0 ) ; e l s i f ( l a t c h r e s u l t = 1 ) then

i f ( ( d ou t ( 3 3 ) = 1 ) and ( o r r e d u c e ( c o n v s t d l o g i c v e c t o r ( d ou t ( 1 4 downto 0 ) ) ) = 1 ) ) then

102

346 347 348 349 350 351 352 353 354 355 356 end i f ; end pro c e ss ; end i f ; else

d a t a o u t <= c o n v s t d l o g i c v e c t o r ( d ou t ( 3 0 downto 1 5 ) + 1 ) ; d a t a o u t <= c o n v s t d l o g i c v e c t o r ( d ou t ( 3 0 downto 1 5 ) ) ; end i f ;

s t r o b e o u t <= s t r o b e o u t t ; d e b u g c t r l <= r e p e a t ( 3 , end b e h a v i o r a l ; 0 ) & c l o c k & r e s e t & acc en & mult en & c l e a r & l a t c h r e s u l t & s t o r e o d d & s t r o b e i n & s t r o b e o u t t & phase ;

Listing A.27: Controller for the I/O pins that attach to the daughtercards. (io pins.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 entity i o p i n s port ( io 0 io 1 io 2 : : : inout inout inout s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; is l i b r a r y WOR K; use WOR K.FPGA REGS COMMON. ALL ; l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; T r i S t a t e L a s t C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA This pr ogr am is distributed in the hope even that the it will be useful , of the This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c later version . L ic e n s e as the published C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows . I /O P i n s Steve for Daughtercard Headers M o d i f i e d : 21 J u l y 2010 Olivieri

VHDL A u t h o r :

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

103

42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 );

io 3 reg 0 reg 1 reg 2 reg 3 clock rx reset tx reset serial addr serial data serial strobe : : : in in in

: : : : : : : :

inout in in in in in in in

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic

end i o p i n s ; architecture b e h a v i o r a l component b i d i r r e g port ( tristate oe reg val ); end component ; signal i o 0 o e signal i o 1 o e signal i o 2 o e signal i o 3 o e begin bidir reg 0 : bidir reg tristate = > io 0 , oe = > io 0 oe , reg val = > reg 0 ) ; : : : : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; : in io pins : :

of is

is

inout in

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 )

port map (

bidir reg 1

bidir reg tristate = > io 1 , bidir reg tristate = > io 2 , oe = > io 2 oe , reg val = > reg 2 ) ; oe = > io 1 oe , reg val = > reg 1 ) ;

port map ( bidir reg 2 :

port map (

bidir reg 3

bidir reg tristate = > io 3 , bits is bit a r e a mask high , in set oe = > io 3 oe , for the reg val = > reg 3 ) ; bits . the If a of bit the in the

port map (

The u p p e r 16 u p p e r 16 bits

l o w e r 16 bit to

the

output

value

c o r r e s p o n d i n g pro c e ss ( c l o c k ) begin

the

l o w e r 16

bits .

Otherwise ,

do n o t h i n g .

i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( s e r i a l s t r o b e = 1 ) then c a se c o n v i n t e g e r ( s e r i a l a d d r ) > when FR OE 0 = i o 0 o e <= ( ( i o 0 o e and ( not when FR OE 1 = > i o 1 o e <= ( ( i o 1 o e and ( not s e r i a l d a t a ( 3 1 downto 1 6 ) ) ) or s e r i a l d a t a ( 3 1 downto 1 6 ) ) ) or ( s e r i a l d a t a ( 1 5 downto 0 ) and s e r i a l d a t a ( 3 1 downto 1 6 ) ) ) ; is

( s e r i a l d a t a ( 1 5 downto 0 ) and s e r i a l d a t a ( 3 1 downto 1 6 ) ) ) ; > when FR OE 2 = i o 2 o e <= ( ( i o 2 o e and ( not > when FR OE 3 = s e r i a l d a t a ( 3 1 downto 1 6 ) ) ) or ( s e r i a l d a t a ( 1 5 downto 0 ) and s e r i a l d a t a ( 3 1 downto 1 6 ) ) ) ;

104

99 100 101 102 103 104 105 106 107 end i f ; end i f ; end pro c e ss ; end b e h a v i o r a l ;

i o 3 o e <= ( ( i o 3 o e and ( not when o the rs = > null ; end c a se ;

s e r i a l d a t a ( 3 1 downto 1 6 ) ) ) or

( s e r i a l d a t a ( 1 5 downto 0 ) and s e r i a l d a t a ( 3 1 downto 1 6 ) ) ) ;

Listing A.28: Master control module. Provides enables, clocks, and serial data for the entire system. Also contains most of the conguration registers. (master control.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 entity m a s t e r c o n t r o l port ( master clk usbclk serial addr serial data : : : : in in in in std logic ; std logic ; s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; is l i b r a r y WOR K; use WOR K.FPGA REGS COMMON. ALL ; use WOR K. FPGA REGS STANDARD . ALL ; use WOR K. FUNCS . ALL ; l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; M a s t e r L a s t C o n t r o l System ( c l o c k s , resets , enables , etc .) M o d i f i e d : 21 J u l y 2010 Steve Olivieri

VHDL A u t h o r :

C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA write Software 02110 1301 This pr ogr am is distributed in the hope even that the it will be useful , of the b u t WITHOUT ANY WARRANTY; without implied warranty See This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can redistribute it and / o r modify by under Free your terms t h e GNU G e n e r a l P u b l i c either L ic e n s e as the published or C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows .

S o f t w a r e Foundation ; o p t i o n ) any later

version 2 of

License ,

version .

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. GNU G e n e r a l P u b l i c License f o r more details .

I n c . , 51 F r a n k l i n

Street ,

105

45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 );

serial strobe tx bus reset rx bus reset tx dsp reset rx dsp reset enable tx enable rx interp rate decim rate tx sample strobe strobe interp rx sample strobe strobe decim t x em p t y debug 0 debug 1 debug 2 debug 3 reg 0 reg 1 reg 2 reg 3 end m a s t e r c o n t r o l ;

in

std logic ; std logic ; std logic ; std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 7 downto 0 ) ; s t d l o g i c v e c t o r ( 7 downto 0 ) ; std logic ; std logic ; std logic ; std logic ; in std logic ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; : out : out : out : out s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 )

: out : out : out : out : out : out : out : out : out : out : out : out : : : : : in in in in

architecture b e h a v i o r a l g e ne ri c ( my addr : ); port ( clock reset strobe ad d r d in d out ch an ged ); end component ; : in

of master control is

is

component s e t t i n g r e g

i n t e g e r := 0

: :

in in

std logic ; std logic ; std logic ;

: : : out

in in

std logic vector ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic

: out

component s t r o b e g e n port ( clock reset enable rate strobe in strobe ); end component ; : :

is

: : in : in : out

in in

std logic ; std logic ; std logic ;

in

s t d l o g i c v e c t o r ( 7 downto 0 ) ; std logic ; std logic

component c l k d i v i d e r port ( reset in clk : in :

is

in

std logic ; std logic ;

106

102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 signal signal ??? signal ); );

out clk ratio end component ;

: out : in

std logic ; s t d l o g i c v e c t o r ( 7 downto 0 )

component a t r d e l a y port ( clk i rst i ena i tx empty i tx delay i rx delay i atr tx o end component ;

is

: : : : : : in in in

in in in

std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ;

: out

std logic

FIXME n e e d a s e p a r a t e signal ma s te r co nt ro ls I n t e r n a l s signal signal :

reset

for

all

control

settings

s t d l o g i c v e c t o r ( 7 downto 0 ) ;

s o we can r e a d / w r i t e . : : std logic ; std logic ;

tx dsp reset t rx dsp reset t : : :

signal d s p r e s e t t signal e n a b le t x t signal e n a b le r x t

std logic ; std logic ; std logic ; : : s t d l o g i c v e c t o r ( 7 downto 0 ) ; s t d l o g i c v e c t o r ( 7 downto 0 ) ; : : std logic ; std logic ;

interp rate t

signal de c im r at e t

signal tx s a mp le s t r o be t signal rx s a mp le s t r o be t USB r e s e t signals

signal t x re s e t bu s s y n c 1 signal r x re s e t bu s s y n c 1 signal t x re s e t bu s s y n c 2 signal r x re s e t bu s s y n c 2 I n t e r n a l signal signal signal signal clocks : : : :

: : : :

std logic ; std logic ; std logic ; std logic ;

txa refclk rxa refclk txb refclk rxb refclk : : : :

s t d l o g i c v e c t o r ( 7 downto 0 ) ; s t d l o g i c v e c t o r ( 7 downto 0 ) ; s t d l o g i c v e c t o r ( 7 downto 0 ) ; s t d l o g i c v e c t o r ( 7 downto 0 ) ;

signal txaclk signal rxaclk signal txbclk signal rxbclk

std logic ; std logic ; std logic ; std logic ;

signal debug en signal

s t d l o g i c v e c t o r ( 3 downto 0 ) ; : s t d l o g i c v e c t o r ( 3 downto 0 ) ;

txcvr ctrl

txcvr txlines txcvr rxlines signals

: : for

s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; daughtercard headers

I n t e r n a l

107

159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215

signal signal signal signal

io 0 reg io 1 reg io 2 reg io 3 reg

: : : :

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; transmit / receive : : : : : : : : : : : : : : std logic ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; : : : : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; signals ? switch )

ATR s t u f f

( auto

si g na l transmit now signal atr ctl : signal a t r t x d e la y signal a t r r x d e la y signal atr mask 0 signal a t r t x v a l 0 signal a t r r x v a l 0 signal atr mask 1 signal a t r t x v a l 1 signal a t r r x v a l 1 signal atr mask 2 signal a t r t x v a l 2 signal a t r r x v a l 2 signal atr mask 3 signal a t r t x v a l 3 signal a t r r x v a l 3 :

std logic ;

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

signal signal signal signal

atr selected 0 atr selected 1 atr selected 2 atr selected 3

More d a u g h t e r c a r d signal i o 0 signal i o 1 signal i o 2 signal i o 3 begin A s s i g n internal : : : :

header

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; signals to their outputs .

e n a b l e t x <= e n a b l e t x t ; e n a b l e r x <= e n a b l e r x t ; t x d s p r e s e t <= t x d s p r e s e t t ; r x d s p r e s e t <= r x d s p r e s e t t ; d s p r e s e t t <= ( t x d s p r e s e t t i n t e r p r a t e <= i n t e r p r a t e t ; d e c i m r a t e <= d e c i m r a t e t ; t x s a m p l e s t r o b e <= t x s a m p l e s t r o b e t ; r x s a m p l e s t r o b e <= r x s a m p l e s t r o b e t ; M a s t e r control : assignments . or r x d s p r e s e t t ) ;

sr mstr ctrl

setting reg

> FR MASTER CTRL) g e ne ri c map( my addr = port map ( c l o c k = > master clk , ad d r = > serial addr , reset = > 0 , strobe = > serial strobe , d o u t ( 3 1 downto 8 ) = > OPEN, d in = > serial data ,

d o u t ( 7 downto 0 ) = > master controls ,

ch an ged = > O PEN) ;

C o n t r o l

signals

4:7

are

not used .

e n a b l e t x t <= m a s t e r c o n t r o l s ( 0 ) ; e n a b l e r x t <= m a s t e r c o n t r o l s ( 1 ) ; t x d s p r e s e t t <= m a s t e r c o n t r o l s ( 2 ) ; r x d s p r e s e t t <= m a s t e r c o n t r o l s ( 3 ) ;

108

216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 sr txbref : setting reg > FR TX B REFCLK) g e ne ri c map( my addr = sr rxaref : setting reg reset = > rx dsp reset t , strobe = > serial strobe , g e ne ri c map( my addr = > FR RX A REFCLK) port map ( c l o c k = > master clk , ad d r = > serial addr , sr txaref : setting reg reset = > tx dsp reset t , strobe = > serial strobe , > FR TX A REFCLK) g e ne ri c map( my addr = port map ( c l o c k = > master clk , ad d r = > serial addr , d in = > serial data , d o u t ( 3 1 downto 8 ) = > OPEN, t x b u s r e s e t <= t x r e s e t b u s s y n c 2 ; r x b u s r e s e t <= r x r e s e t b u s s y n c 2 ; R e s e t syncs for side bus ( u s b cl k ) reset isn t side used , t h e TX b u s side on e may n o t b e needed . decim strobe gen : strobe gen reset = > rx dsp reset t , enable = > enable rx t , strobe = > strobe decim ) ; strobe in = > rx sample strobe t , tx strobe gen : strobe gen reset = > tx dsp reset t , enable = > enable tx t , strobe = > strobe interp ) ; strobe in = > tx sample strobe t , port map ( c l o c k = > master clk , rate = > interp rate t , da strobe gen : strobe gen reset = > tx dsp reset t , > 1 , strobe in = enable = > enable tx t , port map ( c l o c k = > master clk , rate = > ( o the rs = > 1 ) , r x s a m p l e s t r o b e t <= 1 ; sr decim : setting reg reset = > rx dsp reset t , strobe = > serial strobe , > FR DECIM RATE) g e ne ri c map( my addr = port map ( c l o c k = > master clk , ad d r = > serial addr , d in = > serial data , d o u t ( 3 1 downto 8 ) = > OPEN, S t r o b e sr interp Generators : setting reg reset = > tx dsp reset t , strobe = > serial strobe ,

g e ne ri c map( my addr = > FR INTERP RATE ) port map ( c l o c k = > master clk , ad d r = > serial addr , d in = > serial data , d o u t ( 3 1 downto 8 ) = > OPEN,

d o u t ( 7 downto 0 ) = > interp rate t ,

ch an ged = > O PEN) ;

> decim rate t , d o u t ( 7 downto 0 ) =

ch an ged = > O PEN) ;

strobe = > tx sample strobe t ) ;

port map ( c l o c k = > master clk , rate = > decim rate t ,

The RX b u s

pro c e ss ( u s b c l k ) begin i f ( u s b c l k EVENT and u s b c l k = 1 ) then t x r e s e t b u s s y n c 1 <= t x d s p r e s e t t ; r x r e s e t b u s s y n c 1 <= r x d s p r e s e t t ; t x r e s e t b u s s y n c 2 <= t x r e s e t b u s s y n c 1 ; r x r e s e t b u s s y n c 2 <= r x r e s e t b u s s y n c 1 ; end i f ; end pro c e ss ;

> txa refclk , d o u t ( 7 downto 0 ) =

ch an ged = > O PEN) ;

d in = > serial data ,

d o u t ( 3 1 downto 8 ) = > OPEN,

> rxa refclk , d o u t ( 7 downto 0 ) =

ch an ged = > O PEN) ;

109

273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329

port map ( c l o c k = > master clk , ad d r = > serial addr ,

reset = > tx dsp reset t , ch an ged = > O PEN) ;

strobe = > serial strobe ,

d in = > serial data ,

d o u t ( 3 1 downto 8 ) = > OPEN,

> txb refclk , d o u t ( 7 downto 0 ) = sr rxbref : setting reg

> FR RX B REFCLK) g e ne ri c map( my addr = port map ( c l o c k = > master clk , ad d r = > serial addr , reset = > rx dsp reset t , ch an ged = > O PEN) ; strobe = > serial strobe ,

d in = > serial data ,

d o u t ( 3 1 downto 8 ) = > OPEN,

d o u t ( 7 downto 0 ) = > rxb refclk , sr debugen : setting reg

g e ne ri c map( my addr = > FR DEBUG EN) port map ( c l o c k = > master clk , ad d r = > serial addr , reset = > dsp reset t , ch an ged = > O PEN) ; strobe = > serial strobe ,

d in = > serial data ,

d o u t ( 3 1 downto 4 ) = > OPEN,

> d eb u g en , d o u t ( 3 downto 0 ) = clk div 0 : clk divider

port map ( r e s e t = > tx dsp reset t , ratio (7) = > 0 , clk div 1 : clk divider

in clk = > master clk ,

out clk = > txaclk ,

r a t i o ( 6 downto 0 ) = > t x a r e f c l k ( 6 downto 0 ) ) ;

port map ( r e s e t = > rx dsp reset t , ratio (7) = > 0 ,

in clk = > master clk ,

out clk = > rxaclk ,

r a t i o ( 6 downto 0 ) = > r x a r e f c l k ( 6 downto 0 ) ) ;

clk div 2

clk divider in clk = > master clk , out clk = > txbclk , r a t i o ( 6 downto 0 ) = > t x b r e f c l k ( 6 downto 0 ) ) ;

port map ( r e s e t = > tx dsp reset t , ratio (7) = > 0 , clk div 3 : clk divider

port map ( r e s e t = > rx dsp reset t , ratio (7) = > 0 , The u p p e r 16 bits

in clk = > master clk ,

out clk = > rxbclk ,

r a t i o ( 6 downto 0 ) = > r x b r e f c l k ( 6 downto 0 ) ) ; for the l o w e r 16 bits .

a r e a mask

pro c e ss ( m a s t e r c l k ) begin i f ( m a s t e r c l k EVENT and m a s t e r c l k = 1 ) then i f ( s e r i a l s t r o b e = 1 ) then c a se c o n v i n t e g e r ( s e r i a l a d d r ) when FR IO 0 = > i o 0 r e g <= ( ( i o 0 r e g and ( not s e r i a l d a t a ( 3 1 downto 1 6 ) ) ) or ( s e r i a l d a t a ( 1 5 downto 0 ) and s e r i a l d a t a ( 3 1 downto 1 6 ) ) ) ; when FR IO 1 = > i o 1 r e g <= ( ( i o 1 r e g and ( not > when FR IO 2 = i o 2 r e g <= ( ( i o 2 r e g and ( not s e r i a l d a t a ( 3 1 downto 1 6 ) ) ) or ( s e r i a l d a t a ( 1 5 downto 0 ) and s e r i a l d a t a ( 3 1 downto 1 6 ) ) ) ; > when FR IO 3 = i o 3 r e g <= ( ( i o 3 r e g and ( not when o the rs = > end c a se ; end i f ; end i f ; end pro c e ss ; ATR s t u f f s e r i a l d a t a ( 3 1 downto 1 6 ) ) ) or ( s e r i a l d a t a ( 1 5 downto 0 ) and s e r i a l d a t a ( 3 1 downto 1 6 ) ) ) ; s e r i a l d a t a ( 3 1 downto 1 6 ) ) ) or ( s e r i a l d a t a ( 1 5 downto 0 ) and s e r i a l d a t a ( 3 1 downto 1 6 ) ) ) ; is

110

330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386

sr atr mask 0

setting reg reset = > 0 , strobe = > serial strobe , d o u t ( 3 1 downto 1 6 ) = > OPEN,

g e ne ri c map( my addr = > FR ATR MASK 0 ) port map ( c l o c k = > master clk , ad d r = > serial addr , d in = > serial data ,

d o u t ( 1 5 downto 0 ) = > atr mask 0 ,

ch an ged = > O PEN) ;

sr atr txval 0

setting reg reset = > 0 , strobe = > serial strobe , d o u t ( 3 1 downto 1 6 ) = > OPEN,

> FR ATR TXVAL 0 ) g e ne ri c map( my addr = port map ( c l o c k = > master clk , ad d r = > serial addr , d in = > serial data ,

d o u t ( 1 5 downto 0 ) = > atr txval 0 ,

ch an ged = > O PEN) ;

sr atr rxval 0

setting reg reset = > 0 , strobe = > serial strobe , d o u t ( 3 1 downto 1 6 ) = > OPEN,

g e ne ri c map( my addr = > FR ATR RXVAL 0 ) port map ( c l o c k = > master clk , ad d r = > serial addr , d in = > serial data ,

> atr rxval 0 , d o u t ( 1 5 downto 0 ) =

ch an ged = > O PEN) ;

sr atr mask 1

setting reg reset = > 0 , strobe = > serial strobe , d o u t ( 3 1 downto 1 6 ) = > OPEN,

g e ne ri c map( my addr = > FR ATR MASK 1 ) port map ( c l o c k = > master clk , ad d r = > serial addr , d in = > serial data ,

d o u t ( 1 5 downto 0 ) = > atr mask 1 ,

ch an ged = > O PEN) ;

sr atr txval 1

setting reg reset = > 0 , strobe = > serial strobe , d o u t ( 3 1 downto 1 6 ) = > OPEN,

> FR ATR TXVAL 1 ) g e ne ri c map( my addr = port map ( c l o c k = > master clk , ad d r = > serial addr , d in = > serial data ,

> atr txval 1 , d o u t ( 1 5 downto 0 ) =

ch an ged = > O PEN) ;

sr atr rxval 1

setting reg reset = > 0 , strobe = > serial strobe , d o u t ( 3 1 downto 1 6 ) = > OPEN,

g e ne ri c map( my addr = > FR ATR RXVAL 1 ) port map ( c l o c k = > master clk , ad d r = > serial addr , d in = > serial data ,

d o u t ( 1 5 downto 0 ) = > atr rxval 1 ,

ch an ged = > O PEN) ;

sr atr mask 2

setting reg reset = > 0 , strobe = > serial strobe , d o u t ( 3 1 downto 1 6 ) = > OPEN,

> FR ATR MASK 2 ) g e ne ri c map( my addr = port map ( c l o c k = > master clk , ad d r = > serial addr , d in = > serial data ,

> atr mask 2 , d o u t ( 1 5 downto 0 ) =

ch an ged = > O PEN) ;

sr atr txval 2

setting reg reset = > 0 , strobe = > serial strobe , d o u t ( 3 1 downto 1 6 ) = > OPEN,

g e ne ri c map( my addr = > FR ATR TXVAL 2 ) port map ( c l o c k = > master clk , ad d r = > serial addr , d in = > serial data ,

d o u t ( 1 5 downto 0 ) = > atr txval 2 ,

ch an ged = > O PEN) ;

sr atr rxval 2

setting reg reset = > 0 , strobe = > serial strobe , d o u t ( 3 1 downto 1 6 ) = > OPEN,

> FR ATR RXVAL 2 ) g e ne ri c map( my addr = port map ( c l o c k = > master clk , ad d r = > serial addr , d in = > serial data ,

d o u t ( 1 5 downto 0 ) = > atr rxval 2 , sr atr mask 3 : setting reg

ch an ged = > O PEN) ;

g e ne ri c map( my addr = > FR ATR MASK 3 ) port map ( c l o c k = > master clk , reset = > 0 , strobe = > serial strobe ,

111

387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432

ad d r = > serial addr ,

d in = > serial data ,

d o u t ( 3 1 downto 1 6 ) = > OPEN,

d o u t ( 1 5 downto 0 ) = > atr mask 3 , sr atr txval 3 : setting reg

ch an ged = > O PEN) ;

g e ne ri c map( my addr = > FR ATR TXVAL 3 ) port map ( c l o c k = > master clk , ad d r = > serial addr , reset = > 0 , strobe = > serial strobe , d o u t ( 3 1 downto 1 6 ) = > OPEN,

d in = > serial data ,

> atr txval 3 , d o u t ( 1 5 downto 0 ) = sr atr rxval 3 : setting reg

ch an ged = > O PEN) ;

g e ne ri c map( my addr = > FR ATR RXVAL 3 ) port map ( c l o c k = > master clk , ad d r = > serial addr , reset = > 0 , strobe = > serial strobe , d o u t ( 3 1 downto 1 6 ) = > OPEN,

d in = > serial data ,

d o u t ( 1 5 downto 0 ) = > atr rxval 3 , sr atr ctl : setting reg

ch an ged = > O PEN) ;

g e n e r i c map ( m y addr => FR ATR CTL ) p o r t map ( c l o c k => m a s t e r c l k , a d d r => s e r i a l a d d r , d o u t ( 0 ) => a t r c t l ) ; sr atr tx delay : setting reg reset = > 0 , strobe = > serial strobe , d o u t ( 3 1 downto 1 2 ) = > OPEN, r e s e t => 0 , s t r o b e => s e r i a l s t r o b e , d o u t ( 3 1 dow n t o 1 ) => OPEN,

d i n => s e r i a l d a t a ,

g e ne ri c map( my addr = > FR ATR TX DELAY) port map ( c l o c k = > master clk , ad d r = > serial addr ,

d in = > serial data ,

> atr tx delay , d o u t ( 1 1 downto 0 ) = sr atr rx delay : setting reg

ch an ged = > O PEN) ;

> FR ATR RX DELAY) g e ne ri c map( my addr = port map ( c l o c k = > master clk , ad d r = > serial addr , reset = > 0 , strobe = > serial strobe , d o u t ( 3 1 downto 1 2 ) = > OPEN,

d in = > serial data ,

d o u t ( 1 1 downto 0 ) = > atr rx delay , a t r c t l <= 1 ;

ch an ged = > O PEN) ;

atr delay 0

atr delay rst i = > tx dsp reset t , ena i = > atr ctl , rx delay i = > atr rx delay , tx delay i = > atr tx delay ,

port map ( c l k i = > master clk , > t x em p t y , tx empty i = atr tx o = > transmit now ) ;

a t r s e l e c t e d 0 <= a t r t x v a l 0 when t r a n s m i t n o w = 1 a t r s e l e c t e d 1 <= a t r t x v a l 1 when t r a n s m i t n o w = 1 a t r s e l e c t e d 2 <= a t r t x v a l 2 when t r a n s m i t n o w = 1 a t r s e l e c t e d 3 <= a t r t x v a l 3 when t r a n s m i t n o w = 1 i o 0 <= ( r e p e a t ( 1 6 ,

else else else else

atr rxval 0 ; atr rxval 1 ; atr rxval 2 ; atr rxval 3 ; atr ctl )

a t r c t l ) and a t r m a s k 0 and a t r s e l e c t e d 0 ) or ( ( not ( r e p e a t ( 1 6 ,

and a t r m a s k 0 ) ) and i o 0 r e g ) ; 433 434 435 i o 1 <= ( r e p e a t ( 1 6 , i o 2 <= ( r e p e a t ( 1 6 , i o 3 <= ( r e p e a t ( 1 6 , a t r c t l ) and a t r m a s k 1 and a t r s e l e c t e d 1 ) or ( ( not ( r e p e a t ( 1 6 , a t r c t l ) and a t r m a s k 2 and a t r s e l e c t e d 2 ) or ( ( not ( r e p e a t ( 1 6 , a t r c t l ) and a t r m a s k 3 and a t r s e l e c t e d 3 ) or ( ( not ( r e p e a t ( 1 6 , atr ctl ) atr ctl ) atr ctl )

and a t r m a s k 1 ) ) and i o 1 r e g ) ; and a t r m a s k 2 ) ) and i o 2 r e g ) ;

and a t r m a s k 3 ) ) and i o 3 r e g ) ; 436 437 r e g 0 <= d e b u g 0 when d e b u g e n ( 0 ) = 1 = 1 else io 0 ; else ( i o 0 ( 1 5 downto 1 ) & t x a c l k ) when t x a r e f c l k ( 7 )

112

438 439 440

r e g 1 <= d e b u g 1 when d e b u g e n ( 1 ) = 1 = 1 = 1 = 1 else io 1 ; r e g 2 <= d e b u g 2 when d e b u g e n ( 2 ) = 1 else io 2 ; r e g 3 <= d e b u g 3 when d e b u g e n ( 3 ) = 1 else io 3 ;

else

( i o 1 ( 1 5 downto 1 ) & r x a c l k ) when r x a r e f c l k ( 7 ) ( i o 2 ( 1 5 downto 1 ) & t x b c l k ) when t x b r e f c l k ( 7 ) ( i o 3 ( 1 5 downto 1 ) & r x b c l k ) when r x b r e f c l k ( 7 )

else

else

441

end b e h a v i o r a l ;

Listing A.29: A 16x16 bit multiplier, used in conjunction with the acc module to create a MAC for the halfband lter. (mult.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 ); end mult ; e n t i t y mult i s port ( clock x y product enable in enable out : : : : : out in : out in in in std logic ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 3 0 downto 0 ) ; std logic ; std logic l i b r a r y WOR K; use WOR K. FUNCS . ALL ; l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC SIGNED . ALL ; 16 x 1 6 L a s t C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA This pr ogr am is distributed in the hope even that the it will be useful , of the b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License without implied warranty See This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c later version . L ic e n s e as the published C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows . Multiplier M o d i f i e d : 21 J u l y 2010 Steve Olivieri

VHDL A u t h o r :

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

113

47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 I guess this lets u s know if a result is valid ? end i f ; end pro c e ss ; else p r o d u c t t <= ( o the rs = > 0 ) ; end i f ; M u l t i p l e on e a c h pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( e n a b l e i n = 1 ) then p r o d u c t t <= x t y t ; clock cycle , if enabled . I w on der if the : original V e r i l o g was i n error using 30:0. architecture b e h a v i o r a l signal x t signal y t : : o f mult i s s i g n e d ( 1 5 downto 0 ) ; s i g n e d ( 1 5 downto 0 ) ;

signal product t begin

s i g n e d ( 3 1 downto 0 ) ;

x t <= c o n v s i g n e d ( c o n v i n t e g e r ( x ) , x t LENGTH) ; y t <= c o n v s i g n e d ( c o n v i n t e g e r ( y ) , y t LENGTH) ; p r o d u c t <= c o n v s t d l o g i c v e c t o r ( p r o d u c t t ( 3 0 downto 0 ) , p r od u ct LENGTH) ;

pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then e n a b l e o u t <= e n a b l e i n ; end i f ; end pro c e ss ; end b e h a v i o r a l ;

Listing A.30: Phase accumulator module for the NCO. (phase acc.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 B a s i c P hase A c c u m u l a t o r ( f o r DDS) L a s t M o d i f i e d : 20 J u l y 2010 Steve Olivieri

VHDL A u t h o r :

C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t This pr ogr am is distributed in the hope even that the it will be useful , of the b u t WITHOUT ANY WARRANTY; without implied warranty See This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can redistribute it and / o r modify by under Free your terms t h e GNU G e n e r a l P u b l i c either L ic e n s e as the published or C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows .

S o f t w a r e Foundation ; o p t i o n ) any later

version 2 of

License ,

version .

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE.

114

22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

GNU G e n e r a l P u b l i c You s h o u l d along with Foundation , have this

License

f o r more of

details . t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA

r e c e i v e d a copy pr ogr am ; if n ot ,

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ;

entity phase acc g e ne ri c ( FREQADDR PHASEADDR

is

: : :

i n t e g e r := 0 ;

i n t e g e r := 0 ; i n t e g e r range 0 to 32 := 32

resolution );

port ( clk reset enable strobe serial addr serial data serial strobe phase ); end p h a s e a c c ; architecture b e h a v i o r a l g e ne ri c ( my addr : ); port ( clock reset strobe ad d r d in d out ch an ged ); end component ; : in : : : out in in : : in in std logic ; std logic ; std logic ; std logic vector ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic i n t e g e r := 0 of phase acc is : : : : : in in in in in : in : in std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic ; : out s t d l o g i c v e c t o r ( r e s o l u t i o n 1 downto 0 )

is

component s e t t i n g r e g

: out

signal fr e q

s t d l o g i c v e c t o r ( r e s o l u t i o n 1 downto 0 ) ; : s t d l o g i c v e c t o r ( r e s o l u t i o n 1 downto 0 ) ;

signal phase t begin

p h a s e <= p h a s e t ;

Note , you l l

d o u t => f r e q value like

only

w o r k s when to

resol u ti on = 32. wire part of d out

Else , use t o OPEN is not

g e t a w i d t h m ism at ch . Xilinx

U n f o r t u n a t e l y , we can t r a n g e on

a g e n e r i c b e c a u s e

resolution

t h r o w s an e r r o r , D i s c r e t e

slice

115

79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

l o c a l l y sr rxfreq0

s t a t i c . : setting reg reset = > 0 , strobe = > serial strobe , ch an ged = > O PEN) ; ad d r = > serial addr ,

> FREQADDR) g e ne ri c map( my addr = port map ( c l o c k = > clk , d in = > serial data , d out = > freq ,

pro c e ss ( c l k ) begin i f ( c l k EVENT and c l k = 1 ) then i f ( r e s e t = 1 ) then R e s e t the accumulator . p h a s e t <= ( o the rs = > 0 ) ; e l s i f ( ( s e r i a l s t r o b e = 1 ) and ( s e r i a l a d d r = PHASEADDR) ) then I n i t i a l p h a s e comes fr om serial input . p h a s e t <= s e r i a l d a t a ; e l s i f ( ( e n a b l e = 1 ) and ( s t r o b e = 1 ) ) then A c c u m u l a t e on e a c h strobe , where freq is the center frequency . p h a s e t <= p h a s e t + f r e q ; end i f ; end i f ; end pro c e ss ; end b e h a v i o r a l ;

Listing A.31: A 16-bit RAM used in the halfband lter. (ram16.vhd)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; RAM16 L a s t C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t You s h o u l d along with have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free License write Software 02110 1301 USA This pr ogr am is distributed in the hope even that the it will be useful , of This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows . M o d i f i e d : 21 J u l y 2010 Steve Olivieri

VHDL A u t h o r :

under

terms

t h e GNU G e n e r a l P u b l i c later version .

L ic e n s e as the

published

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

the

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

116

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

use IEEE . STD LOGIC UNSIGNED. ALL ; e n t i t y ram16 i s port ( clock write in wr addr wr data rd addr rd data ); end ram16 ; : : : in in in : : in in std logic ; std logic ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 )

: out

architecture b e h a v i o r a l C r e a t e a 16 x 1 6 si g na l ram array begin

o f ram16 i s s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

b i t RAM. : ram ( 0 to 1 5 ) ;

type ram i s array ( i n t e g e r range <>) o f

Read fr om RAM on e v e r y pro c e ss ( c l o c k ) begin

clock .

i f ( c l o c k EVENT and c l o c k = 1 ) then r d d a t a <= r a m a r r a y ( c o n v i n t e g e r ( r d a d d r ) ) ; end i f ; end pro c e ss ; W r i t e t o RAM o n l y when write in is asserted .

pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( w r i t e i n = 1 ) then r a m a r r a y ( c o n v i n t e g e r ( w r a d d r ) ) <= w r d a t a ; end i f ; end i f ; end pro c e ss ; end b e h a v i o r a l ;

Listing A.32: A 16-bit RAM with two read ports. This RAM sums the two read values together. (ram16 2sum.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 RAM16 2SUM L a s t C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c later version . L ic e n s e as the published C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows . M o d i f i e d : 14 F e b r u a r y 2011 Steve Olivieri VHDL A u t h o r :

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

117

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA This pr ogr am is distributed in the hope even that the it will be useful , of the b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License without implied warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

TODO: Convert to the n ew er numeric std library . is t h e sum o f the two r e a d

T r i p o r t RAM ( 2 v a l u e s . Sort of . l i b r a r y IEEE ;

reads , 1 w ri te ) .

The o u t p u t

use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC SIGNED . ALL ;

e n t i t y ram16 2sum i s port ( clock write in wr addr wr data rd addr1 rd addr2 sum ); end ram16 2sum ; architecture b e h a v i o r a l C r e a t e a 16 x 1 6 si g na l ram array o f ram16 2sum i s : : in in : : : out in in : : in in std logic ; std logic ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 )

b i t RAM. : ram ( 0 to 1 5 ) ;

type ram i s array ( i n t e g e r range <>) o f s i g n e d ( 1 5 downto 0 ) ;

signal a : signal b :

s i g n e d ( 1 5 downto 0 ) ; s i g n e d ( 1 5 downto 0 ) ; : s i g n e d ( 1 6 downto 0 ) ; write in is high .

sig nal sum int begin O n ly w r i t e pro c e ss ( c l o c k ) begin

t o RAM i f

i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( w r i t e i n = 1 ) then I s n t this horrible? I think it s horrible . VHDL n e e d s to fix this . r a m a r r a y ( c o n v i n t e g e r ( c o n v u n s i g n e d ( c o n v i n t e g e r ( w r a d d r ) , wr ad d r LENGTH) ) ) <= c o n v s i g n e d ( c o n v i n t e g e r ( w r d a t a ) , wr d at a LENGTH) ;

65 66 67 68 69 70 71 72 73

end i f ; end i f ; end pro c e ss ;

Read t w o

values

fr om RAM on e v e r y

clock

cycle .

pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then a <= r a m a r r a y ( c o n v i n t e g e r ( c o n v u n s i g n e d ( c o n v i n t e g e r ( r d a d d r 1 ) , r d a d d r 1 LENGTH) ) ) ;

118

74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

b <= r a m a r r a y ( c o n v i n t e g e r ( c o n v u n s i g n e d ( c o n v i n t e g e r ( r d a d d r 2 ) , r d a d d r 2 LENGTH) ) ) ; end i f ; end pro c e ss ; S i g n e d addition of the two r e a d values .

s u m i n t <= ( a ( 1 5 ) & a ) + ( b ( 1 5 ) & b ) ;

O u t p u t t h e sum on e v e r y pro c e ss ( c l o c k ) begin

clock

cycle .

If

t h e sum i s

negative

and odd ,

add 1 .

i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( ( s u m i n t ( 1 6 ) = 1 ) and ( s u m i n t ( 0 ) = 1 ) ) then sum <= c o n v s t d l o g i c v e c t o r ( c o n v s i g n e d ( s u m i n t ( 1 6 downto 1 ) + 1 , sum LENGTH) , sum LENGTH) ; else sum <= c o n v s t d l o g i c v e c t o r ( c o n v s i g n e d ( s u m i n t ( 1 6 downto 1 ) , sum LENGTH) , sum LENGTH) ; end i f ; end i f ; end pro c e ss ; end b e h a v i o r a l ;

Listing A.33: Received signal strength indicator (RSSI) and over/underow detector module. (rssi.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; R e c e i v e L a s t Signal Strength Indicator ( RSSI ) M o d i f i e d : 26 F e b r u a r y 2011 Steve Olivieri

VHDL A u t h o r :

C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA write Software 02110 1301 This pr ogr am is distributed in the hope even that the it will be useful , of b u t WITHOUT ANY WARRANTY; without implied warranty See This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can redistribute it and / o r modify by C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows .

under Free your

terms

t h e GNU G e n e r a l P u b l i c either later version .

L ic e n s e as the

published or

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

License ,

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. GNU G e n e r a l P u b l i c License f o r more details .

the

I n c . , 51 F r a n k l i n

Street ,

119

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 T r ack signal strength fr om ADCs . pro c e ss ( c l o c k ) begin A b s o l u t e value of adc ( s o r t of ) . e l s e ad c ; o v e r c o u n t <= o v e r c o u n t i n t ( 2 5 downto 1 0 ) ; end i f ; end pro c e ss ; else o v e r c o u n t i n t <= o v e r c o u n t i n t + over t m p o v e r c o u n t i n t ( 2 5 downto 1 0 ) ; end i f ; T r ack overflows and underflows fr om t h e ADCs . pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( r e s e t = 1 or e n a b l e = 0 ) then C l e a r on reset . The o r i g i n a l d i f f e r e n t l y . Verilog This is did this inside the process , logic . b u t XST t r a n s l a t e s that b a s e d on t h e rssi S i m p l e OR g a t e to determine overflows and u n d e r f l o w s . o v e r <= o v e r h i or o v e r l o ; Minimum v a l u e for 12 s i g n e d bits . 0 ; architecture b e h a v i o r a l signal o v e r hi signal o v e r lo si g na l over : : : of rssi is ); end r s s i ; entity rssi is port ( clock reset enable ad c rssi over count : : in in : : in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; : out : out s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 )

std logic ; std logic ; : s t d l o g i c v e c t o r ( 2 5 downto 0 ) ;

std logic ; : : : s t d l o g i c v e c t o r ( 2 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 2 5 downto 0 ) ; for 12 s i g n e d bits . 0 ;

signal o ve r c o u nt in t s i g n a l over t m p signal abs adc signal begin Maximum v a l u e rssi int

o v e r h i <= 1 when ( ad c = 16#7FF#) e l s e

o v e r l o <= 1 when ( ad c = 16#800#) e l s e

d26 6 5 5 3 5 = b26 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 . over t m p <= 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 when o v e r = 1 00000000000000000000000000 ; else

o v e r c o u n t i n t <= ( o the rs = > 0 ) ;

a b s a d c <= ( not ad c ) when ad c ( 1 1 ) = 1

120

90 91 92 93 94 95 96 97 98 99 100 101

i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( r e s e t = 1 or e n a b l e = 0 ) then C l e a r on reset . r s s i i n t <= ( o the rs = > 0 ) ; else r s s i i n t <= r s s i i n t + a b s a d c r s s i i n t ( 2 5 downto 1 0 ) ; end i f ; end i f ; end pro c e ss ; r s s i <= r s s i i n t ( 2 5 downto 1 0 ) ; end b e h a v i o r a l ;

Listing A.34: Controls the FIFO buer and USB interface on the receive side. (rx buer.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 entity r x b u f f e r is l i b r a r y WOR K; use WOR K. FPGA REGS STANDARD . ALL ; use WOR K.REDUCE PACK . ALL ; I n t e r f a c e A p a c k e t to is C y p r e s s FX2 b u s . 512 B y t e s . lines . Each FIFO l i n e is 2 bytes . R e c e i v e L a s t C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA This pr ogr am is distributed in the hope even that the it will be useful , of the This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c later version . L ic e n s e as the published C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows . Buffer (USB <> DSP) Olivieri M o d i f i e d : 20 J u l y 2010 Steve

VHDL A u t h o r :

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

FIFO h a s 4096 l i b r a r y IEEE ;

use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ;

121

42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

port ( Read /USB s i d e usbclk bus reset usbdata RD have pkt rdy rx overrun clear status : : : in in std logic ; std logic ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; std logic ; std logic ; std logic ; std logic ;

: out in

: out : out : in

W r i t e /DSP s i d e rxclk reset rxstrobe channels ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 : : : : : : : : : : : : in in in in in in in in in in in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; DSP s i d e reset , not for registers

S e t t i n g s , serial addr serial data serial strobe reset regs d eb u gb u s ); end r x b u f f e r ;

also : : : :

using in in in in

rxclk s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic ; std logic ; O n ly resets regs

: out

s t d l o g i c v e c t o r ( 3 1 downto 0 )

architecture b e h a v i o r a l

of

rx buffer :

is

func ti o n r o u n d 8 ( i n v a l return is begin

s t d l o g i c v e c t o r ( 1 5 downto 0 ) )

std logic vector

i f ( i n v a l ( 1 5 ) = 1 and o r r e d u c e ( i n v a l ( 7 dow n t o return else return en d if ; i n v a l ( 1 5 dow n t o 8 ) ; i n v a l ( 1 5 dow n t o 8 ) + 1 ;

0) ) = 1 )

then

return i n v a l ( 1 5 downto 8 ) + ( i n v a l ( 1 5 ) and o r r e d u c e ( i n v a l ( 7 downto 0 ) ) ) ; end func ti o n ; component s e t t i n g r e g g e ne ri c ( my addr : ); port ( clock reset strobe ad d r d in : : : : : in in in in in std logic ; std logic ; std logic ; std logic vector ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; i n t e g e r := 0

is

122

99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 Temps signal signal signal signal ); );

d out ch an ged end component ;

: out : out

s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic

component f i f o 4 k 1 8 port ( data wr r eq wrclk wrfull : : : in in in

is

s t d l o g i c v e c t o r ( 1 7 downto 0 ) ; std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 7 downto 0 ) ; std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; std logic

: out

wrempty : out wrusedw q rdreq rdclk rdfull : out : out : : in in

: out

rdempty : out rdusedw aclr end component ; fifodata : : out : in

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; : : : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ;

fifodata 8

signal f i f o d a t a 1 6 rxfifolevel rx full :

std logic ;

si g na l bypass hb s i g n a l wan t q : signal bitwidth signal bitshift : :

std logic ; s t d l o g i c v e c t o r ( 4 downto 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 ) ;

std logic ;

signal read count si g na l phase signal ch0 in signal ch0 out signal iq o u t : : : :

s t d l o g i c v e c t o r ( 8 downto 0 ) ;

s t d l o g i c v e c t o r ( 3 downto 0 ) ; std logic ; std logic ; std logic ;

signal have pkt rdy t signal r x o v er run t signal wr req t signal r d r e q t signal u s bc lk t : : : :

std logic ;

std logic ;

std logic ; std logic ; std logic ; : s t d l o g i c v e c t o r ( 3 downto 0 ) ;

signal channels h signal c h 0 r eg signal c h 1 r eg signal c h 2 r eg signal c h 3 r eg signal c h 4 r eg signal c h 5 r eg : : : : : :

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

123

156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210

signal c h 6 r eg signal c h 7 r eg s i g n a l t op :

: :

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

s i g n a l bottom :

signal c l e a r s t a t u s d s p signal rx overrun dsp Temporary signal signal top8 : values : :

std logic ;

std logic ; g e t t i n g 8 b i t fifodata . 0) ;

for

s t d l o g i c v e c t o r ( 7 dow n t o

bottom8

s t d l o g i c v e c t o r ( 7 dow n t o 0 ) ;

begin h a v e p k t r d y <= h a v e p k t r d y t ; r x o v e r r u n <= r x o v e r r u n t ; sr rxformat : setting reg

g e ne ri c map( my addr = > FR RX FORMAT) port map ( c l o c k = > rxclk , serial addr , d in = > serial data , want q , d o u t ( 8 downto 4 ) = > bitwidth , d o u t ( 3 downto 0 ) = > bitshift , ch an ged = > O PEN) ; d o u t ( 3 1 downto 1 1 ) = > OPEN, d out (10) = > bypass hb , d out ( 9 ) = > reset = > reset regs , strobe = > serial strobe , ad d r = >

USB r e a d

side

o f FIFO

pro c e ss ( u s b c l k ) begin i f ( u s b c l k EVENT and u s b c l k = 0 ) then i f ( r x f i f o l e v e l >= 0 0 0 1 0 0 0 0 0 0 0 0 ) then h a v e p k t r d y t <= 1 ; else h a v e p k t r d y t <= 0 ; end i f ; end i f ; end pro c e ss ; 256

257 b u g

fix

pro c e ss ( u s b c l k ) begin i f ( u s b c l k EVENT and u s b c l k = 0 ) then i f ( b u s r e s e t = 1 ) then r e a d c o u n t <= ( o the rs = > 0 ) ; e l s i f (RD = 1 ) then r e a d c o u n t <= r e a d c o u n t + 1 ; else r e a d c o u n t <= ( o the rs = > 0 ) ; end i f ; end i f ; end pro c e ss ; FIFO c h 0 i n <= 1 when ( p h a s e = 1 ) else 0 ; else 0 ; else 0 ;

w r r e q t <= 1 when ( ( r x f u l l = 0 ) and ( p h a s e /= 0 ) ) u s b c l k t <= ( not u s b c l k ) ; rxfifo : fifo 4k 18 port map ( d a t a ( 1 7 ) = > ch0 in ,

r d r e q t <= 1 when ( (RD = 1 ) and ( r e a d c o u n t ( 8 ) = 0 ) )

data (16) = > p h a s e ( 0 ) , d a t a ( 1 5 downto 0 ) = > fifodata ,

124

211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264

wr r eq = > wr req t , OPEN,

wrclk = > rxclk ,

wrfull = > r x f u l l , wrempty = > OPEN, wrusedw = > rdreq = > rd req t , aclr = >

q (17) = > ch0 out , q (16) = > i q o u t , q ( 1 5 downto 0 ) = > u sb d at a , rdclk = > usbclk t , reset ) ; rdfull = > OPEN, rdempty = > OPEN,

rdusedw = > rxfifolevel ,

DSP w r i t e

side

o f FIFO

pro c e ss ( r x c l k ) begin i f ( r x c l k EVENT and r x c l k = 1 ) then i f ( r x s t r o b e = 1 ) then c h 0 r e g <= c h 0 ; c h 1 r e g <= c h 1 ; c h 2 r e g <= c h 2 ; c h 3 r e g <= c h 3 ; c h 4 r e g <= c h 4 ; c h 5 r e g <= c h 5 ; c h 6 r e g <= c h 6 ; c h 7 r e g <= c h 7 ; end i f ; end i f ; end pro c e ss ; c h a n n e l s h <= 0 & c h a n n e l s ( 3 downto 1 ) ; pro c e ss ( r x c l k ) begin i f ( r x c l k EVENT and r x c l k = 1 ) then i f ( r e s e t = 1 ) then p h a s e <= ( o the rs = > 0 ) ; e l s i f ( p h a s e = 0 ) then i f ( r x s t r o b e = 1 ) then p h a s e <= 0001 ; end i f ; e l s i f ( r x f u l l = 0 ) then i f ( ( ( b i t w i d t h = 8 ) and ( p h a s e = c h a n n e l s h ) ) or ( p h a s e = c h a n n e l s ) ) then p h a s e <= 0000 ; else p h a s e <= p h a s e + 1 ; end i f ; end i f ; end i f ; end pro c e ss ; f i f o d a t a <= f i f o d a t a 8 when ( b i t w i d t h = 8 ) t o p 8 <= t o p ( 1 5 dow n t o t o p ( 1 5 dow n t o fifodata 16 ; 0 ) /= 0 0 0 0 0 0 0 0 ) ) else c h a n n e l s >> 1 ;

else

8 ) + 1 when ( ( t o p ( 1 5 ) = 1 ) and ( t o p ( 7 dow n t o 8) ;

b o t t o m 8 <= b o t t o m ( 1 5 00000000) ) else

dow n t o 8 ) + 1 when 8) ;

( ( b o t t o m ( 1 5 ) = 1 ) and ( b o t t o m ( 7 dow n t o 0 ) /=

b o t t o m ( 1 5 dow n t o

f i f o d a t a 8 <= r o u n d 8 ( t op ) & r o u n d 8 ( bottom ) ; f i f o d a t a 8 <= t o p 8 & b o t t o m 8 ; pro c e ss ( p h ase , begin ch 0 reg , ch 1 reg , ch 2 reg , ch 3 reg , ch 4 reg , ch 5 reg , ch 6 reg , ch 7 reg )

125

265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321

c a se c o n v i n t e g e r ( p h a s e ) when 1 = >

is

bottom <= c h 0 r e g ; t op <= c h 1 r e g ; when 2 = > bottom <= c h 2 r e g ; t op <= c h 3 r e g ; when 3 = > bottom <= c h 4 r e g ; t op <= c h 5 r e g ; when 4 = > t op <= c h 6 r e g ; bottom <= c h 7 r e g ; when o the rs = > t op <= ( o the rs = > 1 ) ; bottom <= ( o the rs = > 1 ) ; end c a se ; end pro c e ss ;

pro c e ss ( p h ase , begin

ch 0 reg ,

ch 1 reg ,

ch 2 reg ,

ch 3 reg ,

ch 4 reg ,

ch 5 reg ,

ch 6 reg ,

ch 7 reg )

c a se c o n v i n t e g e r ( p h a s e ) when 1 = >

is

f i f o d a t a 1 6 <= c h 0 r e g ; when 2 = > f i f o d a t a 1 6 <= c h 1 r e g ; when 3 = > f i f o d a t a 1 6 <= c h 2 r e g ; when 4 = > f i f o d a t a 1 6 <= c h 3 r e g ; when 5 = > f i f o d a t a 1 6 <= c h 4 r e g ; when 6 = > f i f o d a t a 1 6 <= c h 5 r e g ; when 7 = > f i f o d a t a 1 6 <= c h 6 r e g ; when 8 = > f i f o d a t a 1 6 <= c h 7 r e g ; when o the rs = > f i f o d a t a 1 6 <= ( o the rs = > 1 ) ; end c a se ; end pro c e ss ; D e t e c t overrun

pro c e ss ( r x c l k ) begin i f ( r x c l k EVENT and r x c l k = 1 ) then c l e a r s t a t u s d s p <= c l e a r s t a t u s ; end i f ; end pro c e ss ; pro c e ss ( u s b c l k ) begin i f ( u s b c l k EVENT and u s b c l k = 0 ) then r x o v e r r u n t <= r x o v e r r u n d s p ; end i f ; end pro c e ss ;

126

322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 d eb u gb u s ( 1 6 ) d eb u gb u s ( 1 7 ) d eb u gb u s ( 1 8 ) d eb u gb u s ( 1 9 ) d eb u gb u s ( 2 0 ) d eb u gb u s ( 2 1 ) d eb u gb u s ( 2 2 ) d eb u gb u s ( 2 3 ) d eb u gb u s ( 2 4 ) d eb u gb u s ( 3 0 downto 2 5 ) d eb u gb u s ( 3 1 ) end b e h a v i o r a l ; <= b u s r e s e t ; <= RD; <= h a v e p k t r d y t ; <= r x o v e r r u n t ; <= r e a d c o u n t ( 0 ) ; <= r e a d c o u n t ( 8 ) ; <= c h 0 o u t ; <= i q o u t ; <= c l e a r s t a t u s ; <= 000000 ; <= u s b c l k ; Debug b u s 1 5 : 0 3 1 : 1 6 d eb u gb u s ( 0 ) d eb u gb u s ( 1 ) d eb u gb u s ( 2 ) d eb u gb u s ( 6 downto 3 ) d eb u gb u s ( 7 ) d eb u gb u s ( 1 1 downto 8 ) d eb u gb u s ( 1 2 ) d eb u gb u s ( 1 3 ) d eb u gb u s ( 1 4 ) d eb u gb u s ( 1 5 ) rxclk usbclk domain => TXA( 1 5 : 0 ) domain => RXA( 1 5 : 0 ) <= r e s e t ; <= r e s e t r e g s ; <= r x s t r o b e ; <= c h a n n e l s ; <= r x f u l l ; <= p h a s e ; <= c h 0 i n ; <= c l e a r s t a t u s d s p ; <= r x o v e r r u n d s p ; <= r x c l k ; end i f ; end pro c e ss ; pro c e ss ( r x c l k ) begin i f ( r x c l k EVENT and r x c l k = 1 ) then i f ( r e s e t = 1 ) then r x o v e r r u n d s p <= 0 ; e l s i f ( ( r x s t r o b e = 1 ) and ( p h a s e /= 0 ) ) then r x o v e r r u n d s p <= 1 ; e l s i f ( c l e a r s t a t u s d s p = 1 ) then r x o v e r r u n d s p <= 0 ; end i f ;

Listing A.35: Controls the IF to BB conversion and the decimation lters for received data. (rx chain.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 R e c e i v e L a s t C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows . C hain Steve Olivieri M o d i f i e d : 20 J u l y 2010

VHDL A u t h o r :

127

14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

This it the ( at This

pr ogr am the Free your

is

free of

s o f t w a r e ; y ou can either

redistribute

it

and / o r License ,

modify by or

under

terms

t h e GNU G e n e r a l P u b l i c later version . in the hope even that the

L ic e n s e as the

published

S o f t w a r e Foundation ; o p t i o n ) any is

version 2 of

pr ogr am

distributed

it

will

be

useful , of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c You s h o u l d along with have this License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more of details .

the

r e c e i v e d a copy pr ogr am ; if n ot ,

t h e GNU G e n e r a l P u b l i c to the Free

License

write

Software 02110 1301 USA

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; l i b r a r y WOR K; use WOR K.COMMON CONFIG . ALL ; entity r x c h a i n g e ne ri c ( FREQADDR : PHASEADDR : ); i n t e g e r := 0 ; i n t e g e r := 0

is

port ( clock reset enable decim rate sample strobe decimator strobe hb strobe serial addr serial data serial strobe i in q in i out q out d eb u gd at a debugctrl ); end r x c h a i n ; architecture b e h a v i o r a l component p h a s e a c c g e ne ri c ( FREQADDR PHASEADDR resolution ); : : : i n t e g e r := 0 ; i n t e g e r := 0 ; i n t e g e r range 0 to 32 := 32 of rx chai n is : : : : : : : : : : : in in in in in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 7 downto 0 ) ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 )

: out in in in in in

: out : out : out : out

is

128

71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127

port ( clk reset enable strobe serial addr serial data serial strobe phase ); end component ; : : : : : : : in in in in in in in std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic ; s t d l o g i c v e c t o r ( r e s o l u t i o n 1 downto 0 )

: out

component c o r d i c g e ne ri c ( bitwidth zwidth ); :

is

i n t e g e r := 1 6 ;

i n t e g e r := 16

port ( clock reset enable xi yi xo yo zi zo ); end component ; component c i c d e c i m g e ne ri c ( bw : N : i n t e g e r := 1 6 ; i n t e g e r := 4 ; : i n t e g e r := 7 ; N l o g 2 o f m a x r a t e : : : : : in in in in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( zwi d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( zwi d t h 1 downto 0 )

: out : out : in : out

is

log2 of max rate maxbitgain ); port ( clock reset enable rate strobe in strobe out signal in signal out ); end component ; component h a l f b a n d d e c i m port ( clock reset enable strobe in : : : : in in in in : : : : : : : in in in in in in in :

i n t e g e r := 28

std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 7 downto 0 ) ; std logic ; std logic ; s t d l o g i c v e c t o r ( bw1 downto 0 ) ; s t d l o g i c v e c t o r ( bw1 downto 0 )

: out

is

std logic ; std logic ; std logic ; std logic ;

129

128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 rx nco t );

strobe out data in data out debugctrl end component ;

: out : in : out : out

std logic ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 )

si g na l phase signal bb i si g na l bb q : :

s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

signal h b i n i signal hb in q E n a b l e

: :

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; r e a d on o u t p u t s . : std logic ;

w r i t e on i n p u t s , :

signal s a mple s tr o be t

std logic ;

signal d ec ima t o r s tr o be t begin d eb u gd at a <= h b i n i ; :

i f (RX NCO EN) generate

s a m p l e s t r o b e t <= s a m p l e s t r o b e ;

rx phase acc

phase acc resolution = > 32) serial addr = > serial addr , strobe = > reset = > reset , enable = > enable ,

g e ne ri c map(FREQADDR = > FREQADDR, PHASEADDR = > PHASEADDR, port map ( c l k = > clock , serial data = > serial data , sample strobe t ,

serial strobe = > serial strobe ,

156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 rx cic f : end generate rx cic t : rx nco f :

phase = > phase ) ; rx cordic : cordic reset = > reset , enable = > enable , xi = > i in , yi = > q in , zo = > O PEN) ;

port map ( c l o c k = > clock , end generate r x n c o t ;

zi = > p h a s e ( 3 1 downto 1 6 ) , xo = > b b i , yo = > bb q ,

i f ( not RX NCO EN) generate

b b i <= i i n ; b b q <= q i n ; s a m p l e s t r o b e t <= 1 ; end generate r x n c o f ;

i f ( RX CIC EN ) generate

d e c i m a t o r s t r o b e t <= d e c i m a t o r s t r o b e ; cic decim i 0 : cic decim reset = > reset , enable = > enable , rate = > decim rate , signal in = > bb i ,

port map ( c l o c k = > clock ,

> sample strobe , strobe in = signal out = > hb in i ) ; cic decim q 0 : cic decim

strobe out = > decimator strobe t ,

port map ( c l o c k = > clock ,

reset = > reset ,

enable = > enable ,

rate = > decim rate , signal in = > bb q ,

strobe in = > sample strobe , > hb in q ) ; signal out = rx cic t ;

strobe out = > decimator strobe t ,

i f ( not RX CIC EN ) generate

130

184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204

h b i n i <= b b i ; h b i n q <= b b q ; d e c i m a t o r s t r o b e t <= s a m p l e s t r o b e ; end generate rx cic f ;

rx hb t

i f (RX CAP HB) generate : halfband decim reset = > reset , enable = > enable , > strobe in = debugctrl = > decimator strobe , > hb strobe , strobe out = debugctrl ) ; data in = > hb in i , data out = > i out ,

hbd i 0

port map ( c l o c k = > clock ,

hbd q 0

halfband decim reset = > reset , enable = > enable , strobe in = > debugctrl = > O PEN) ; decimator strobe ,

port map ( c l o c k = > clock , strobe out = > OPEN, end generate r x h b t ;

data in = > hb in q ,

data out = > q out ,

rx hb f

i f ( not RX CAP HB) generate

i o u t <= h b i n i ; q o u t <= h b i n q ; h b s t r o b e <= d e c i m a t o r s t r o b e ; end generate r x h b f ; end b e h a v i o r a l ;

Listing A.36: Removes the codec-imposed DC oset from received data. (rx dcoset.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 TODO: The r e d u c e p a c k license is probably not compatible with t h e GPL . Rx DC O f f s e t L a s t C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA This pr ogr am is distributed in the hope even that the it will be useful , of the b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License without implied warranty See This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c later version . L ic e n s e as the published C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows . M o d i f i e d : 20 J u l y 2010 Steve Olivieri VHDL A u t h o r :

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

131

30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC SIGNED . ALL ; l i b r a r y WOR K; use WOR K.REDUCE PACK . ALL ; entity r x d c o f f s e t g e ne ri c ( MYADDR ); : i n t e g e r := 0

is

port ( clock enable reset adc in adc out serial addr serial data serial strobe ); end r x d c o f f s e t ; : in : in : in : in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic

: out : : : in in in

architecture b e h a v i o r a l signal a d c in t signal adc out t signal signal : :

of

rx dcoffset

is

s i g n e d ( 1 5 downto 0 ) ; s i g n e d ( 1 5 downto 0 ) ; : : u n s i g n e d ( 6 downto 0 ) ; u n s i g n e d ( 3 1 downto 0 ) ; : s i g n e d ( 1 5 downto 0 ) ; to outputs , with conversions .

serial addr t serial data t :

signal in t e g r a t o r

s i g n e d ( 3 1 downto 0 ) ;

signal s c a l e d i n t e g r a t o r begin A s s i g n

temporary s i g n a l s

a d c i n t <= c o n v s i g n e d ( c o n v i n t e g e r ( a d c i n ) , 1 6 ) ; s e r i a l a d d r t <= c o n v u n s i g n e d ( c o n v i n t e g e r ( s e r i a l a d d r ) , 7 ) ; s e r i a l d a t a t <= c o n v u n s i g n e d ( c o n v i n t e g e r ( s e r i a l d a t a ) , 3 2 ) ; a d c o u t <= c o n v s t d l o g i c v e c t o r ( a d c o u t t , The o r i g i n a l c h e c k i n g if Verilog the code used the zero . or 16) ; operator , but this is equivalent to

reduction

vector

equals

s c a l e d i n t e g r a t o r <= i n t e g r a t o r ( 3 1 downto 1 6 ) + 1 when ( ( i n t e g r a t o r ( 3 1 ) = 1 ) and ( i n t e g r a t o r ( 1 5 downto 0 ) /= 0 ) ) else i n t e g r a t o r ( 3 1 downto 1 6 ) ; a d c o u t t <= a d c i n t s c a l e d i n t e g r a t o r ; FIXME do we n e e d signed ? clipping ?

FIXME What do we do when pro c e ss ( c l o c k ) begin

i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( r e s e t = 1 ) then C l e a r on reset .

i n t e g r a t o r <= ( o the rs = > 0 ) ; e l s i f ( s e r i a l s t r o b e = 1 and (MYADDR = s e r i a l a d d r t ) ) then Read new v a l u e T h i s is ugly , fr om but it the serial bus . see a s i n g l e 32 b i t register instead of f o r c e s XST t o

132

86 87 88 89 90 91 92 93 94

32 1 b i t

registers .

i n t e g r a t o r <= c o n v s i g n e d ( s e r i a l d a t a t ( 1 5 downto 0 ) , 1 6 ) & 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ; e l s i f ( e n a b l e = 1 ) then O t h e r w i s e , end i f ; end i f ; end pro c e ss ; end b e h a v i o r a l ; just keep accumulating . i n t e g r a t o r <= i n t e g r a t o r + a d c o u t t ;

Listing A.37: A very basic serial bus controller to receive SPI messages from the host, usually to conigure registers. (serial io.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 entity serial io is port ( master clk serial clock serial data in enable reset serial data out serial addr serial data serial strobe : out : : : : in in in in : : out : out : out in std logic ; std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic ; std logic ; l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; S e r i a l L a s t I /O Bus M o d i f i e d : 21 J u l y 2010 Steve Olivieri

VHDL A u t h o r :

C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA write Software 02110 1301 This pr ogr am is distributed in the hope even that the it will be useful , of the b u t WITHOUT ANY WARRANTY; without implied warranty See This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can redistribute it and / o r modify by under Free your terms t h e GNU G e n e r a l P u b l i c either L ic e n s e as the published or C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows .

S o f t w a r e Foundation ; o p t i o n ) any later

version 2 of

License ,

version .

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. GNU G e n e r a l P u b l i c License f o r more details .

I n c . , 51 F r a n k l i n

Street ,

133

45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 );

readback 0 readback 1 readback 2 readback 3 readback 4 readback 5 readback 6 readback 7 end s e r i a l i o ; architecture b e h a v i o r a l signal i s r e a d ser ctr : :

: : : : : : : :

in in in in in in in in

s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 )

of

serial io

is

std logic ; : std logic ; : : s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 7 downto 0 ) ;

signal write done signal

signal s e r ia l d a ta tm p signal s er ia l ad dr t mp signal enable d1 signal enable d2 begin : :

std logic ; std logic ; Z ;

s e r i a l d a t a o u t <= s e r i a l d a t a t m p ( 3 1 ) when i s r e a d = 1 s e r i a l d a t a <= s e r i a l d a t a t m p ; s e r i a l a d d r <= s e r i a l a d d r t m p ;

else

pro c e ss ( s e r i a l c l o c k , begin

reset ,

enable )

i f ( r e s e t = 1 ) then s e r c t r <= ( o the rs = > 0 ) ; e l s i f ( e n a b l e = 0 ) then s e r c t r <= ( o the rs = > 0 ) ; e l s i f ( s e r i a l c l o c k EVENT and s e r i a l c l o c k = 1 ) then A s e r i a l 0 f o r The f i n a l transaction 32 bits are is up t o 40 seven the bits to value bits . are write The the first bit is 1 for r e a d and write . The n e x t actual register address .

in a w r it e

operation .

i f ( s e r c t r = 3 9 ) then > 0 ) ; s e r c t r <= ( o the rs = else s e r c t r <= s e r c t r + 1 ; end i f ; end i f ; end pro c e ss ;

pro c e ss ( s e r i a l c l o c k , begin

reset ,

enable )

i f ( r e s e t = 1 ) then i s r e a d <= 0 ; e l s i f ( e n a b l e = 0 ) then i s r e a d <= 0 ; e l s i f ( s e r i a l c l o c k EVENT and s e r i a l c l o c k = 1 ) then C heck t h e f i n a l first bit we shifted in just b e f o r e we shift in the address bit .

i f ( ( s e r c t r = 7 ) and ( s e r i a l a d d r t m p ( 6 ) = 1 ) ) then i s r e a d <= 1 ; end i f ; end i f ; end pro c e ss ;

134

102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158

pro c e ss ( s e r i a l c l o c k , begin

enable ,

reset )

i f ( r e s e t = 1 ) then s e r i a l a d d r t m p <= ( o the rs = > 0 ) ; s e r i a l d a t a t m p <= ( o the rs = > 0 ) ; w r i t e d o n e <= 0 ; e l s i f ( e n a b l e = 0 ) then s e r i a l a d d r t m p <= ( o t h e r s => 0 ) ; s e r i a l d a t a t m p <= ( o t h e r s => 0 ) ; w r i t e d o n e <= 0 ; e l s i f ( s e r i a l c l o c k EVENT and s e r i a l c l o c k = 1 ) then On t h e final if clock , we d i d indicate t h a t we p e r f o r m e d a w r i t e operation .

o p e r a t i o n

not perform a read

i f ( i s r e a d = 0 and s e r c t r = 3 9 ) then w r i t e d o n e <= 1 ; else w r i t e d o n e <= 0 ; end i f ;

8 b 0 0 0 0 1 0 0 0 = 8 d8 i f ( i s r e a d = 1 and s e r c t r = 00001000 ) then A f t e r 8 t h e s h i f t s , we know address bits . is that So , i t s a r e a d op and we h a v e read the proper register . seven

c a se s e r i a l a d d r t m p when 0000001 = >

s e r i a l d a t a t m p <= r e a d b a c k 0 ; when 0000010 = > s e r i a l d a t a t m p <= r e a d b a c k 1 ; when 0000011 = > s e r i a l d a t a t m p <= r e a d b a c k 2 ; when 0000100 = > s e r i a l d a t a t m p <= r e a d b a c k 3 ; when 0000101 = > s e r i a l d a t a t m p <= r e a d b a c k 4 ; when 0000110 = > s e r i a l d a t a t m p <= r e a d b a c k 5 ; when 0000111 = > s e r i a l d a t a t m p <= r e a d b a c k 6 ; when 0001000 = > s e r i a l d a t a t m p <= r e a d b a c k 7 ; when o the rs = > s e r i a l d a t a t m p <= ( o the rs = > 0 ) ; end c a se ; e l s i f ( s e r c t r >= 00001000 ) then On t h e 9 t h+ s h i f t , a w r i t e op . write to the serial data because this is

s e r i a l d a t a t m p <= s e r i a l d a t a t m p ( 3 0 downto 0 ) & s e r i a l d a t a i n ; e l s i f ( s e r c t r < 00001000 ) then For t h e r e g i s t e r t h e first 8 shifts , collect the read/ wr i te the bit and t h e n bit the into address . vector . We t e m p o r a r i l y store read / w r it e

address

s e r i a l a d d r t m p <= s e r i a l a d d r t m p ( 5 downto 0 ) & s e r i a l d a t a i n ; end i f ; end i f ; end pro c e ss ; pro c e ss ( m a s t e r c l k )

135

159 160 161 162 163 164 165 166 167 168 169

begin i f ( m a s t e r c l k EVENT and m a s t e r c l k = 1 ) then e n a b l e d 1 <= e n a b l e ; e n a b l e d 2 <= e n a b l e d 1 ; end i f ; end pro c e ss ;

A s s e r t t h e n

serial

strobe

for

on e

clock

after

the

enable

is

asserted

and

deasserted .

s e r i a l s t r o b e <= ( e n a b l e d 2 and ( not e n a b l e d 1 ) ) ; end b e h a v i o r a l ;

Listing A.38: A conguration register module. (setting reg.vhd)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 port ( clock reset strobe : in : : in in std logic ; std logic ; std logic ; ); entity s e t t i n g r e g g e ne ri c ( my addr : i n t e g e r := 0 is l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; S e t t i n g L a s t C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t You s h o u l d along with have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free License This pr ogr am is distributed in the hope even that the it will be useful , of This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows . Register Steve Olivieri

M o d i f i e d : 20 J u l y 2010

VHDL A u t h o r :

under

terms

t h e GNU G e n e r a l P u b l i c later version .

L ic e n s e as the

published

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

the

write

Software 02110 1301 USA

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

136

43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 );

ad d r d in d out ch an ged end s e t t i n g r e g ;

: : : out

in in

s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic

: out

architecture b e h a v i o r a l begin Each t o register in

of

setting reg

is

the

system has a unique control signals .

address ,

but

all

are

connected

t h e same d a t a

b u s and

pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( r e s e t = 1 ) then C l e a r on reset ! d o u t <= ( o the rs = > 0 ) ; ch an ged <= 0 ; else I f the serial bu s , strobe to is high ( see s e r i a l i o ) and o u r a d d r e s s is

on t h e

write

this

register .

i f ( s t r o b e = 1 and ( my addr = ad d r ) ) then d o u t <= d i n ; ch an ged <= 1 ; else ch an ged <= 0 ; end i f ; end i f ; end i f ; end pro c e ss ; end b e h a v i o r a l ;

Listing A.39: A module to sign extend data. (sign extend.vhd)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 S i g n L a s t Extension M o d i f i e d : 20 J u l y 2010 Steve Olivieri

VHDL A u t h o r :

C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t This pr ogr am is distributed in the hope even that the it will be useful , of the b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License without implied warranty See This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c L ic e n s e as the published C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows .

S o f t w a r e Foundation ; o p t i o n ) any later

version 2 of

version .

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

137

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA write Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

We p r o b a b l y don t l e f t it in place l i b r a r y IEEE ;

need to

this the

m odu le

s i n c e VHDL h a s as close to

the the

sxt () Verilog

function . as

keep

project

possible .

use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ;

entity s i g n e x t e n d g e ne ri c ( bits in bits out ); :

is

i n t e g e r := 0 ; : i n t e g e r := 0

port ( d in d out ); end s i g n e x t e n d ; : in s t d l o g i c v e c t o r ( b i t s i n 1 downto 0 ) ; s t d l o g i c v e c t o r ( b i t s o u t 1 downto 0 ) : out

architecture b e h a v i o r a l begin Copy d i n to the

of si gn extend lower bits in

is

bits .

d o u t ( b i t s i n 1 downto 0 ) <= d i n ;

F i l l

the

upper

bits out bits in

bits

with

t h e MSB fr om

d in .

d o u t ( b i t s o u t 1 downto b i t s i n ) <= ( o the rs = > d i n ( b i t s i n 1) ) ; end b e h a v i o r a l ;

Listing A.40: Generates strobes. These are used for read and write operations, decimation, and interpolation. (strobe gen.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 S t r o b e L a s t C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t This pr ogr am is distributed in the hope even that the it will be useful , of b u t WITHOUT ANY WARRANTY; without implied warranty This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can redistribute it and / o r modify by C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows . Generator M o d i f i e d : 21 J u l y 2010 Steve Olivieri

VHDL A u t h o r :

under Free your

terms

t h e GNU G e n e r a l P u b l i c either later version .

L ic e n s e as the

published or

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

License ,

138

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. GNU G e n e r a l P u b l i c You s h o u l d along with Foundation , have this License f o r more of details .

See

the

r e c e i v e d a copy pr ogr am ; if n ot ,

t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA

License USA

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

TODO: The l i c e n s e for reduce pack is probably not valid with t h e GPL .

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; l i b r a r y WOR K; use WOR K.REDUCE PACK . ALL ; entity s t r o b e g e n port ( clock reset enable rate ratio : in : in : : in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 7 downto 0 ) ; 1 less than desired divide

is

44 45 46 47 48 49 50 51 52 53 );

strobe in strobe end s t r o b e g e n ;

in

std logic ; std logic

: out

architecture b e h a v i o r a l signal counter begin Not e that :

of strobe gen

is

s t d l o g i c v e c t o r ( 7 downto 0 ) ;

n o r r e d u c e = 1 when c o u n t e r = 0 0 0 0 0 0 0 0 .

s t r o b e <= 1 when ( ( n o r r e d u c e ( c o u n t e r ) = 1 ) and ( e n a b l e = 1 ) and ( s t r o b e i n = 1 ) ) else 0 ;

54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 end i f ; end pro c e ss ; end b e h a v i o r a l ; end i f ; else c o u n t e r <= c o u n t e r 1 ; end i f ; T h i s is basically clocks that just a clock is divider that u s e s a down c o u n t e r . strobe . For e v e r y r a t e strobe in a s s e r t e d , we a s s e r t

pro c e ss ( c l o c k ) begin i f ( c l o c k EVENT and c l o c k = 1 ) then i f ( r e s e t = 1 or e n a b l e = 0 ) then c o u n t e r <= ( o the rs = > 0 ) ; e l s i f ( s t r o b e i n = 1 ) then i f ( c o u n t e r = 0 ) then c o u n t e r <= r a t e ;

Listing A.41: Controls the FIFO buer and USB interface on the transmit side. (tx buer.vhd)

139

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

T r a n s m i t L a s t C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t You s h o u l d along with have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free License This pr ogr am is distributed in the hope even that the it will be useful , of the This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c later version . L ic e n s e as the published C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows . Buffer (DSP <> USB ) Olivieri M o d i f i e d : 20 J u l y 2010 Steve

VHDL A u t h o r :

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

write

Software 02110 1301 USA

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

I n t e r f a c e A p a c k e t to is C y p r e s s FX2 b u s . 512 B y t e s . lines . Each FIFO l i n e is 2 bytes .

FIFO h a s 4096 l i b r a r y IEEE ;

use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ;

entity t x b u f f e r port (

is

USB s i d e usbclk bus reset usbdata W R have space tx underrun clear status : : : in in in : : out : out : in in std logic ; std logic ; 257 Hack t o f i x FX2 b u g

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; std logic ; std logic ; std logic ; std logic ;

DSP s i d e txclk reset channels tx i 0 tx q 0 tx i 1 tx q 1 txstrobe t x em p t y : : : : out : out : out : out : in in in in std logic ; std logic ; s t a n d a r d DSP s i d e reset s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; std logic ; std logic ;

: out

140

58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 );

d eb u gb u s end t x b u f f e r ; architecture b e h a v i o r a l component f i f o 4 k 1 8 port ( data wr r eq wrclk wrfull : : : in in in

: out

s t d l o g i c v e c t o r ( 3 1 downto 0 )

of is

tx buffer

is

s t d l o g i c v e c t o r ( 1 7 downto 0 ) ; std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 7 downto 0 ) ; std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; std logic

: out

wrempty : out wrusedw q rdreq rdclk rdfull : out : out : : in in

: out

rdempty : out rdusedw aclr ); end component ; txfifolevel fifodata : : : : : : : : out : in

signal signal

s t d l o g i c v e c t o r ( 1 1 downto 0 ) ;

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

signal rdreq si g na l phase signal s o p f signal iq f

std logic ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; std logic ; std logic ;

s i g n a l sop USB s i d e

std logic ; of : t h e FIFO : : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 8 downto 0 ) ; std logic ;

signal usbdata reg signal wr reg signal write count

Temporary

f o r FIFO : std logic ; : std logic ; : : std logic ; std logic ;

signal wr req t

signal tx empty t

signal have space t signal tx underrun t

signal c l e a r s t a t u s d s p signal tx underrun dsp begin t x em p t y <= t x e m p t y t ; :

std logic ; std logic ;

h a v e s p a c e <= h a v e s p a c e t ; t x u n d e r r u n <= t x u n d e r r u n t ; pro c e ss ( u s b c l k ) begin i f ( u s b c l k EVENT and u s b c l k = 1 ) then Be c o n s e r v a t i v e ! (4092 256)

i f ( t x f i f o l e v e l < 1 1 1 0 1 1 1 1 1 1 0 0 ) then h a v e s p a c e t <= 1 ; else h a v e s p a c e t <= 0 ;

141

115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 FIFO

end i f ; end i f ; end pro c e ss ; pro c e ss ( u s b c l k ) begin i f ( u s b c l k EVENT and u s b c l k = 1 ) then w r r e g <= W R; u s b d a t a r e g <= u s b d a t a ; end i f ; end pro c e ss ;

pro c e ss ( u s b c l k ) begin i f ( u s b c l k EVENT and u s b c l k = 1 ) then i f ( b u s r e s e t = 1 ) then > 0 ) ; w r i t e c o u n t <= ( o the rs = e l s i f ( w r r e g = 1 ) then w r i t e c o u n t <= w r i t e c o u n t + 1 ; else w r i t e c o u n t <= ( o the rs = > 0 ) ; end i f ; end i f ; end pro c e ss ;

pro c e ss ( u s b c l k ) begin i f ( u s b c l k EVENT and u s b c l k = 1 ) then sop <= W R and ( not w r r e g ) ; e d g e end i f ; end pro c e ss ; detect

w r r e q t <= ( w r r e g and ( not w r i t e c o u n t ( 8 ) ) ) ; txfifo : fifo 4k 18 > usbdata reg , data (16) = > w r i t e c o u n t ( 0 ) , d a t a ( 1 5 downto 0 ) = wrfull = > OPEN, wrempty = > OPEN, rdempty = > tx empty t , rdusedw = >

port map ( d a t a ( 1 7 ) = > sop , wr r eq = > wr req t , rdreq = > rdreq , OPEN, aclr = > reset ) ;

wrclk = > usbclk ,

> i q f , q ( 1 5 downto 0 ) = > fifodata , wrusedw = > t x f i f o l e v e l , q (17) = > sop f , q (16) = rdclk = > txclk , rdfull = > OPEN,

DAC s i d e

of

t h e FIFO

pro c e ss ( t x c l k ) begin i f ( t x c l k EVENT and t x c l k = 1 ) then i f ( r e s e t = 1 ) then t x i 0 <= ( o the rs = > 0 ) ; t x q 0 <= ( o the rs = > 0 ) ; > 0 ) ; t x i 1 <= ( o the rs = t x q 1 <= ( o the rs = > 0 ) ; p h a s e <= 0000 ; e l s i f ( p h a s e = c h a n n e l s ) then i f ( t x s t r o b e = 1 ) then p h a s e <= 0000 ; end i f ; e l s i f ( t x e m p t y t = 0 ) then

142

171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 end i f ; end pro c e ss ; D e t e c t end i f ; end pro c e ss ;

c a se p h a s e i s when 0000 = > t x i 0 <= f i f o d a t a ; when 0001 = > t x q 0 <= f i f o d a t a ; when 0010 = > t x i 1 <= f i f o d a t a ; when 0011 = > t x q 1 <= f i f o d a t a ; when o the rs = > null ; end c a se ;

p h a s e <= p h a s e + 1 ; end i f ;

r d r e q <= 1 when ( ( p h a s e /= c h a n n e l s ) and ( t x e m p t y t = 0 ) ) underruns , cross clock dom ain s

else

0 ;

pro c e ss ( t x c l k ) begin i f ( t x c l k EVENT and t x c l k = 1 ) then c l e a r s t a t u s d s p <= c l e a r s t a t u s ; end i f ; end pro c e ss ; pro c e ss ( u s b c l k ) begin i f ( u s b c l k EVENT and u s b c l k = 1 ) then t x u n d e r r u n t <= t x u n d e r r u n d s p ; end i f ; end pro c e ss ;

pro c e ss ( t x c l k ) begin i f ( t x c l k EVENT and t x c l k = 1 ) then i f ( r e s e t = 1 ) then t x u n d e r r u n d s p <= 0 ; e l s i f ( t x s t r o b e = 1 and ( p h a s e /= c h a n n e l s ) ) then t x u n d e r r u n d s p <= 1 ; e l s i f ( c l e a r s t a t u s d s p = 1 ) then t x u n d e r r u n d s p <= 0 ; end i f ;

TX d e b u g b u s 1 5 : 0 3 1 : 1 6 d eb u gb u s ( 0 ) d eb u gb u s ( 1 ) d eb u gb u s ( 2 ) d eb u gb u s ( 6 downto 3 ) d eb u gb u s ( 7 ) d eb u gb u s ( 8 ) txclk usbclk domain => TXA( 1 5 : 0 ) domain => RXA( 1 5 : 0 ) <= r e s e t ; <= t x s t r o b e ; <= r d r e q ; <= p h a s e ; <= t x e m p t y t ; <= t x u n d e r r u n d s p ;

143

228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243

d eb u gb u s ( 9 ) d eb u gb u s ( 1 0 ) d eb u gb u s ( 1 4 downto 1 1 ) d eb u gb u s ( 1 5 ) d eb u gb u s ( 1 6 ) d eb u gb u s ( 1 7 ) d eb u gb u s ( 1 8 ) d eb u gb u s ( 1 9 ) d eb u gb u s ( 2 0 ) d eb u gb u s ( 2 1 ) d eb u gb u s ( 2 2 ) d eb u gb u s ( 2 3 ) d eb u gb u s ( 3 0 downto 2 4 ) d eb u gb u s ( 3 1 ) end b e h a v i o r a l ;

<= i q f ; <= s o p f ; <= 0000 ; <= t x c l k ; <= b u s r e s e t ; <= W R; <= w r r e g ; <= h a v e s p a c e t ; <= w r i t e c o u n t ( 8 ) ; <= w r i t e c o u n t ( 0 ) ; <= sop ; <= t x u n d e r r u n t ; <= 0000000 ; <= u s b c l k ;

Listing A.42: Controls the interpolation lters for transmit data. (tx chain.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 entity t x c h a i n port ( is The o r i g i n a l u s e d and t r a n s l a t i o n The freq Verilog s o u r c e had to partial support for to cordic , but it was n o t the relied on o u t d a t e d modules . According documentation , T r a n s m i t C hain L a s t C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t You s h o u l d along with have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free License write Software 02110 1301 USA This pr ogr am is distributed in the hope even that the it will be useful , of This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can redistribute it and / o r modify by C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows . M o d i f i e d : 22 F e b r u a r y 2011 Steve Olivieri

VHDL A u t h o r :

under Free your

terms

t h e GNU G e n e r a l P u b l i c either later version .

L ic e n s e as the

published or

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

License ,

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

the

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

fr om b a s e b a n d input is

t h e IF ban d fr om the old

i s now don e on t h e AD9862 c o d e c s . c o r d i c DUC.

a legacy

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ;

144

38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 );

clock reset enable interp rate sample strobe interpolator strobe freq i in q in i out q out : in : : : in in in

: :

in in

std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 7 downto 0 ) ; std logic ;

std logic ; : : : in in in s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 )

: out : out

end t x c h a i n ; architecture b e h a v i o r a l component c i c i n t e r p g e ne ri c ( bw N log2 of max rate maxbitgain ); port ( clock reset enable rate strobe in strobe out signal in signal out ); end component ; : : : in in in : in : in : : in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 7 downto 0 ) ; std logic ; std logic ; s t d l o g i c v e c t o r ( bw1 downto 0 ) ; s t d l o g i c v e c t o r ( bw1 downto 0 ) : : : : i n t e g e r := 1 6 ; # o f bits for input of tx chai n is

is

i n t e g e r := 4 ; # o f

filter

stages rate

i n t e g e r := 7 ; l o g 2

o f max s a m p l i n g

i n t e g e r := 21 (N 1) l o g 2 o f m a x r a t e

: out

signal bb i si g na l bb q begin cic interp i

: : :

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; cic interp reset = > reset , enable = > enable , rate = > interp rate , signal in = > i in , strobe out = > sample strobe ,

port map ( c l o c k = > clock ,

> interpolator strobe , strobe in = signal out = > bb i ) ; cic interp q : cic interp

port map ( c l o c k = > clock , signal out = > bb q ) ;

reset = > reset ,

enable = > enable ,

rate = > interp rate , signal in = > q in ,

strobe in = > interpolator strobe ,

strobe out = > sample strobe ,

i o u t <= b b i ; q o u t <= b b q ; end b e h a v i o r a l ;

Listing A.43: Multiplexer for the usrp std module that replaces a large ternary expression from the original Verilog source. No Verilog version exists. (usrp mux.vhd)
1 2 S p e c i a l MUX f o r USRP T o p l e v e l Signals

145

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

L a s t

M o d i f i e d : 20 J u l y 2010 Steve Olivieri

VHDL A u t h o r :

C o p y r i g h t (C) 2010 COSMIAC You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA write Software 02110 1301 This pr ogr am is distributed in the hope even that the it will be useful , of b u t WITHOUT ANY WARRANTY; without implied warranty See This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can redistribute it and / o r modify by

under Free your

terms

t h e GNU G e n e r a l P u b l i c either later version .

L ic e n s e as the

published or

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

License ,

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. GNU G e n e r a l P u b l i c License f o r more details .

the

I n c . , 51 F r a n k l i n

Street ,

The o r i g i n a l V e r i l o g , this l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; e n t i t y usrp mux port ( dac mux i out 0 q out 0 i out 1 q out 1 d out ); end usrp mux ; architecture b e h a v i o r a l begin Not e that dac m u x ( 2 ) is intentionally statement is : ? ( dac m u x [ 0 ] ? q o u t 1 : : : i out 0 , 1 6 b0 ; q out 0 , i out 1 , q out 1 ) : i out 1 ) i out 0 ) ) ( dac m u x [ 0 ] ? q o u t 0 not used . I don t know why . o f usrp mux : : : : : in in in in in s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; : out s t d l o g i c v e c t o r ( 1 5 downto 0 ) V e r i l o g USRP1 c o n t a i n s no logic is trivial to equivalent with for the this com pon en t . ?: In

implement

ternary

operator .

is

is

The e q u i v a l e n t pro c e ss ( dac mux , begin

Verilog

d o u t = dac m u x [ 3 ]

? ( dac m u x [ 1 ]

i f ( dac mux ( 3 ) = 1 ) then i f ( dac mux ( 1 ) = 1 ) then i f ( dac mux ( 0 ) = 1 ) then d o u t <= q o u t 1 ; else d o u t <= i o u t 1 ; end i f ; else

146

60 61 62 63 64 65 66 67 68 69 70 else

i f ( dac mux ( 0 ) = 1 ) then d o u t <= q o u t 0 ; else d o u t <= i o u t 0 ; end i f ; end i f ;

d o u t <= ( o the rs = > 0 ) ; end i f ; end pro c e ss ; end b e h a v i o r a l ;

Listing A.44: The top-level module for the USRP. Connects the other components together. (usrp std.vhd)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 entity u s r p s t d port ( MYSTERY SIGNAL master clk : out : in std logic ; std logic ; is l i b r a r y WOR K; use WOR K.COMMON CONFIG . ALL ; use WOR K.FPGA REGS COMMON. ALL ; use WOR K. FPGA REGS STANDARD . ALL ; l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; USRP1 S t a n d a r d L a s t C o p y r i g h t (C) 2010 COSMIAC The c o p y r i g h t You s h o u l d along with have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free License This pr ogr am is distributed in the hope even that the it will be useful , of This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or C o p y r i g h t (C) 2003 M at t E t t u s USRP U n i v e r s a l S o f t w a r e Radio Peripheral and license fr om the original Verilog implementation follows . VHDL A u t h o r : Toplevel Olivieri M o d i f i e d : 21 J u l y 2010 Steve

under

terms

t h e GNU G e n e r a l P u b l i c later version .

L ic e n s e as the

published

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

the

write

Software 02110 1301 USA

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

147

43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 component t x b u f f e r port ( USB s i d e usbclk bus reset usbdata W R have space tx underrun clear status : : : : in in in in std logic ; std logic ; 257 Hack t o f i x FX2 b u g is ); end component ; architecture b e h a v i o r a l component b u s t r i port ( data enabledt tridata : : in in s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; std logic ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) is of usrp std is ); end u s r p s t d ; GPIOs t o io tx a io tx b io rx a io rx b the daughtercard : : : : inout inout inout inout slots s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) USB i n t e r f a c e usbclk usbctl u sb r d y usbdata : : : in in std logic ; s t d l o g i c v e c t o r ( 2 downto 0 ) ; s t d l o g i c v e c t o r ( 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; TXSYNC A TXSYNC B : out : out std logic ; std logic ; tx a tx b : out : out s t d l o g i c v e c t o r ( 1 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 3 downto 0 ) ; Codec rx a a rx b a rx a b rx b b interface : : : : in in in in s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; USB i n t e r f a c e FX2 1 FX2 2 FX2 3 : in std logic ; std logic ; std logic ; : out : out SPI i n t e r f a c e SCLK SDI SDO SEN FPGA : : : : in in inout in std logic ; std logic ; std logic ; std logic ;

: out inout

: out

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; std logic ; std logic ; std logic ; std logic ;

: out : out : in

148

100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 ); end component ; component usrp mux port ( dac mux i out 0 q out 0 i out 1 q out 1 d out : : : : : in in in in in s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) is ); end component ; port ( clock reset strobe ad d r d in d out ch an ged : : : : : in in in in in std logic ; std logic ; std logic ; std logic vector ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic ); component s e t t i n g r e g g e ne ri c ( my addr : i n t e g e r := 0 is ); end component ; component t x c h a i n port ( clock reset enable interp rate sample strobe interpolator strobe freq i in q in i out q out : : : : : : : : : in in in in in in in in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 7 downto 0 ) ; std logic ; std logic ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) is ); end component ; DSP s i d e txclk reset channels tx i 0 tx q 0 tx i 1 tx q 1 txstrobe t x em p t y d eb u gb u s : : : in in in std logic ; std logic ; s t a n d a r d DSP s i d e reset s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; std logic ; std logic ; s t d l o g i c v e c t o r ( 3 1 downto 0 )

: out : out : out : out : in : out : out

: out : out

: out : out

: out

149

157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 S e t t i n g s , serial addr serial data also : : using in in rxclk s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; W r i t e /DSP s i d e rxclk reset rxstrobe channels ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 : : : : : : : : : : : : in in in in in in in in in in in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; DSP s i d e reset , not for registers component r x b u f f e r port ( Read /USB s i d e usbclk bus reset usbdata RD have pkt rdy rx overrun clear status : : in in std logic ; std logic ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; std logic ; std logic ; std logic ; std logic ; is ); end component ; component a d c i n t e r f a c e port ( clock reset enable serial addr serial data serial strobe rx a a rx b a rx a b rx b b rssi 0 rssi 1 rssi 2 rssi 3 ddc0 in i ddc0 in q ddc1 in i ddc1 in q ddc2 in i ddc2 in q ddc3 in i ddc3 in q rx numchan : : : : : : : : : : in in in in in in in in in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 ) is

: out : out : out : out : out : out : out : out : out : out : out : out : out

: out : in

: out : out : in

150

214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 ); ); ); );

serial strobe reset regs d eb u gb u s end component ;

: :

in in

std logic ; std logic ; O n ly resets regs s t d l o g i c v e c t o r ( 3 1 downto 0 )

: out

component r x c h a i n g e ne ri c ( FREQADDR : PHASEADDR :

is

i n t e g e r := 0 ; i n t e g e r := 0

port ( clock reset enable decim rate sample strobe decimator strobe hb strobe serial addr serial data serial strobe i in q in i out q out d eb u gd at a debugctrl : : : : : : : : : : : in in in in in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 7 downto 0 ) ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 )

: out in in in in in

: out : out : out : out

end component ; component s e r i a l i o port ( master clk serial clock serial data in enable reset serial data out serial addr serial data serial strobe readback 0 readback 1 readback 2 readback 3 readback 4 readback 5 readback 6 readback 7 : : : : : in in in in in std logic ; std logic ; std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 )

is

: out : out : out : out : : : : : : : : in in in in in in in in

end component ; component m a s t e r c o n t r o l port ( master clk : in std logic ;

is

151

271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 ); );

usbclk serial addr serial data serial strobe tx bus reset rx bus reset tx dsp reset rx dsp reset enable tx enable rx interp rate decim rate tx sample strobe strobe interp rx sample strobe strobe decim t x em p t y debug 0 debug 1 debug 2 debug 3 reg 0 reg 1 reg 2 reg 3 end component ; component i o p i n s port ( io 0 io 1 io 2 io 3 reg 0 reg 1 reg 2 reg 3 clock rx reset tx reset serial addr serial data serial strobe end component ; : : : : : : : : : : : : : :

: : : :

in in in in

std logic ; s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic ; std logic ; std logic ; std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 7 downto 0 ) ; s t d l o g i c v e c t o r ( 7 downto 0 ) ; std logic ; std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 )

: out : out : out : out : out : out : out : out : out : out : out : out : : : : : in in in in in

: out : out : out : out

is

inout inout inout inout in in in in in in in in in in

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic

s i g n a l d eb u gd at a signal debugctrl signal clk64 signal clk128 : :

: :

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

std logic ; std logic ;

signal W R : s i g n a l RD : s i g n a l OE :

std logic ; std logic ; std logic ;

152

328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384

signal have space

std logic ; : std logic ; std logic ; std logic ; : std logic ;

signal have pkt rdy signal tx underrun : signal rx overrun signal : clear status

signal usbdata out s i g n a l dac0mux s i g n a l dac1mux s i g n a l dac2mux s i g n a l dac3mux : : : :

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; : std logic ;

signal

tx realsignals : :

s i g n a l rx numchan s i g n a l tx numchan

s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 2 downto 0 ) ;

signal i n t e r p r a t e signal decim rate si g na l tx debugbus si g na l rx debugbus :

s t d l o g i c v e c t o r ( 7 downto 0 ) ; s t d l o g i c v e c t o r ( 7 downto 0 ) ;

: :

s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ;

signal enable tx signal enable rx

: :

std logic ; std logic ; : : : : std logic ; std logic ; std logic ; std logic ;

signal t x d s p r e s e t signal r x d s p r e s e t signal t x b u s r e s e t signal r x b u s r e s e t signal s e t t i n g s si g na l ch0tx si g na l ch1tx si g na l ch2tx si g na l ch3tx si g na l ch0rx si g na l ch1rx si g na l ch2rx si g na l ch3rx si g na l ch4rx si g na l ch5rx si g na l ch6rx si g na l ch7rx : : : : : : : : : : : : :

s t d l o g i c v e c t o r ( 7 downto 0 ) ;

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

TX signal i o u t 0 signal i o u t 1 signal q out 0 signal q out 1 signal b b t x i0 signal bb tx q0 signal b b t x i1 : : : : : : : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

153

385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441

signal bb tx q1

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; : std logic ; : std logic ;

signal s t r o b e i n t e r p s i g n a l t x em p t y :

signal tx sample strobe

std logic ;

signal signal signal

serial strobe serial addr serial data : :

std logic ;

s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; : : : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

signal debug counter signal lo o p ba c k i 0 signal loopback q 0 signal t x a a signal tx b a signal tx a b signal tx b b : : : :

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

signal txsync RX

std logic ;

signal rx sample strobe signal strobe decim signal hb strobe signal b b r x i0 signal bb rx q0 signal b b r x i1 signal bb rx q1 signal b b r x i2 signal bb rx q2 signal b b r x i3 signal bb rx q3 : : : : : : : : : :

std logic ;

std logic ;

std logic ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

si g na l loopback signal counter :

std logic ; std logic ; : : : : : : : : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

signal d d c 0 i n i signal ddc0 in q signal d d c 1 i n i signal ddc1 in q signal d d c 2 i n i signal ddc2 in q signal d d c 3 i n i signal ddc3 in q

signal signal signal signal

rssi 0 rssi 1 rssi 2 rssi 3

: : : :

s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ;

signal

capabilities : : :

s t d l o g i c v e c t o r ( 3 1 downto 0 ) ;

signal reg 0 signal reg 1 signal reg 2

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

154

442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475

signal reg 3 begin

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

MYSTERY SIGNAL <= 0 ; USB STUFF W R <= u s b c t l ( 0 ) ; RD <= u s b c t l ( 1 ) ; OE <= u s b c t l ( 2 ) ; u sb r d y ( 0 ) <= h a v e s p a c e ; u sb r d y ( 1 ) <= h a v e p k t r d y ;

c l e a r s t a t u s <= FX2 1 ; FX2 2 <= r x o v e r r u n ; FX2 3 <= t x u n d e r r u n ; T r i s t a t e bustri 0 : b u s macro

bustri enabledt = > OE, tridata = > usbdata ) ;

port map ( d a t a = > usbdata out , c l k 6 4 <= m a s t e r c l k ;

TRANSMIT SIDE tx en t : i f (TX EN) generate

b b t x i 0 <= c h 0 t x ; b b t x q 0 <= c h 1 t x ; b b t x i 1 <= c h 2 t x ; b b t x q 1 <= c h 3 t x ;

tx buffer 0

tx buffer > tx bus reset , bus reset = usbdata = > u sb d at a , W R = > WR, clear status = > tx underrun = > tx underrun ,

port map ( u s b c l k = > usbclk , clear status , txclk = > clk64 ,

have space = > have space ,

reset = > tx dsp reset , tx i 0 = > ch 0t x ,

c h a n n e l s ( 3 downto 1 ) = > tx numchan , tx i 1 = > ch 2t x , tx q 1 = >

channels (0) = > 0 , ch 3t x ,

tx q 0 = > ch 1t x ,

476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495

txstrobe = > strobe interp , FIXME S h o u l d tx en 0 t : tx chain 0 : freq really b e 0?

t x em p t y = > t x em p t y ,

d eb u gb u s = > tx debugbus ) ;

i f ( TX EN 0 ) generate tx chain reset = > tx dsp reset , enable = > enable tx , i in = >

port map ( c l o c k = > clk64 ,

> interp rate , interp rate = bb tx i0 , q in = > bb tx q0 , end generate t x e n 0 t ;

sample strobe = > tx sample strobe , freq = > ( o the rs = > 0 ) ,

interpolator strobe = > strobe interp , i out = > i out 0 ,

q out = > q out 0 ) ;

tx en 0 f

i f ( not TX EN 0 ) generate

> 0 ) ; i o u t 0 <= ( o the rs = q o u t 0 <= ( o the rs = > 0 ) ; end generate t x e n 0 f ;

FIXME s h o u l d tx en 1 t : tx chain 1 :

freq

really

b e 0?

i f ( TX EN 1 ) generate tx chain reset = > tx dsp reset , enable = > enable tx ,

port map ( c l o c k = > clk64 ,

155

496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 sr txmux : tx en 1 f :

> interp rate , interp rate = bb tx i1 , q in = > bb tx q1 , end generate t x e n 1 t ;

sample strobe = > tx sample strobe , freq = > ( o the rs = > 0 ) , i in = >

interpolator strobe = > strobe interp , i out = > i out 1 ,

q out = > q out 1 ) ;

i f ( not TX EN 1 ) generate

> 0 ) ; i o u t 1 <= ( o the rs = q o u t 1 <= ( o the rs = > 0 ) ; end generate t x e n 1 f ; setting reg

> FR TX MUX) g e ne ri c map( my addr = port map ( c l o c k = > clk64 , serial addr , d in = > serial data , = > dac0mux , d o u t ( 3 1 downto 2 0 ) = > OPEN, d o u t ( 1 9 downto 1 6 ) = > dac3mux , d o u t ( 7 downto 4 ) > dac2mux , d o u t ( 1 5 downto 1 2 ) = d o u t ( 1 1 downto 8 ) = > dac1mux , reset = > tx dsp reset , strobe = > serial strobe , ad d r = >

511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 tx en f : tx mux 3 tx mux 2 tx mux 1 tx mux 0

d out ( 3 ) = > tx realsignals , : usrp mux

d o u t ( 2 downto 0 ) = > tx numchan ,

ch an ged = > O PEN) ;

> dac0mux , port map ( dac mux = i out 1 , > q out 1 , q out 1 =

i out 0 = > i out 0 ,

q out 0 = > q out 0 ,

i out 1 = >

d out = > tx a a ) ;

: usrp mux i out 0 = > i out 0 , q out 0 = > q out 0 , i out 1 = > i out 1 , > q out 1 , q out 1 = d out = > tx b a ) ;

port map ( dac mux = > dac1mux ,

: usrp mux i out 0 = > i out 0 , q out 0 = > q out 0 , i out 1 = > i out 1 , q out 1 = > q out 1 , d out = > tx a b ) ;

port map ( dac mux = > dac2mux ,

: usrp mux i out 0 = > i out 0 , q out 0 = > q out 0 , i out 1 = > i out 1 , q out 1 = > q out 1 , d out = > tx b b ) ;

port map ( dac mux = > dac3mux ,

t x s y n c <= t x s a m p l e s t r o b e ; TXSYNC A <= t x s y n c ; TXSYNC B <= t x s y n c ; t x a <= t x b a ( 1 5 downto 2 ) when t x s y n c = 1 t x b <= t x b b ( 1 5 downto 2 ) when t x s y n c = 1 end generate t x e n t ; t x a a ( 1 5 downto 2 ) ; t x a b ( 1 5 downto 2 ) ;

else else

i f ( not TX EN) generate signals !

TODO A s s i g n

end generate t x e n f ;

RECEIVE SIDE rx en t : i f (RX EN) generate l o o p b a c k <= s e t t i n g s ( 0 ) ; c o u n t e r <= s e t t i n g s ( 1 ) ;

156

546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569

pro c e ss ( c l k 6 4 ) begin i f ( c l k 6 4 EVENT and c l k 6 4 = 1 ) then i f ( r x d s p r e s e t = 1 ) then d e b u g c o u n t e r <= ( o the rs = > 0 ) ; e l s i f ( e n a b l e r x /= 1 ) then

d e b u g c o u n t e r <= ( o the rs = > 0 ) ; e l s i f ( h b s t r o b e = 1 ) then d e b u g c o u n t e r <= d e b u g c o u n t e r + 2 ; end i f ; end i f ; end pro c e ss ;

pro c e ss ( c l k 6 4 ) begin i f ( c l k 6 4 EVENT and c l k 6 4 = 1 ) then i f ( s t r o b e i n t e r p = 1 ) then l o o p b a c k i 0 <= c h 0 t x ; l o o p b a c k q 0 <= c h 1 t x ; end i f ; end i f ; end pro c e ss ; c h 0 r x <= d e b u g c o u n t e r when ( c o u n t e r = 1 ) bb rx i0 ; l o o p b a c k i 0 when ( l o o p b a c k = 1 )

else

else

570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589

c h 1 r x <= d e b u g c o u n t e r + 1 when ( c o u n t e r = 1 ) else bb rx q0 ; c h 2 r x <= b b r x i 1 ; c h 3 r x <= b b r x q 1 ; c h 4 r x <= b b r x i 2 ; c h 5 r x <= b b r x q 2 ; c h 6 r x <= b b r x i 3 ; c h 7 r x <= b b r x q 3 ; adc interface 0 : adc interface

else

l o o p b a c k q 0 when ( l o o p b a c k = 1 )

port map ( c l o c k = > clk64 , serial addr ,

reset = > rx dsp reset ,

enable = > 1 ,

serial addr = > rx a a = > rx a a ,

> serial data , serial data = rx b a = > rx b a , rssi 1 = > rssi 1 ,

serial strobe = > serial strobe , rx b b = > rx b b , rssi 3 = > rssi 3 ,

rx a b = > rx a b , rssi 2 = > rssi 2 ,

rssi 0 = > rssi 0 , ddc0 in i = > ddc0 in i ,

> ddc0 in q , ddc0 in q = ddc2 in i = > ddc2 in i ,

ddc1 in i = > ddc1 in i , ddc2 in q = > ddc2 in q ,

ddc1 in q = > ddc1 in q , ddc3 in i = > ddc3 in i ,

> d d c 3 i n q , rx numchan = > rx numchan ) ; ddc3 in q = rx buffer 0 : rx buffer bus reset = > rx bus reset , reset = > rx dsp reset , have pkt rdy = > usbdata = > u s b d a t a o u t , RD = > RD,

port map ( u s b c l k = > usbclk ,

reset regs = > rx dsp reset , have pkt rdy ,

590 591 592 593 594 595 596

rx overrun = > rx overrun , > ch 2r x , ch 2 = = > ch 7r x , rxclk = > clk64 ,

channels = > rx numchan , ch 4 = > ch 4r x ,

ch 0 = > ch 0r x ,

ch 1 = > ch 1r x , ch 7

ch 3 = > ch 3r x ,

ch 5 = > ch 5r x ,

ch 6 = > ch 6r x ,

rxstrobe = > hb strobe ,

clear status = > clear status , serial strobe = >

serial addr = > serial addr , serial strobe , d eb u gb u s = > rx debugbus ) ; rx en 0 t : i f ( RX EN 0 ) generate

serial data = > serial data ,

157

597 598 599 600 601

rx chain 0

rx chain reset = > 0 , enable = > enable rx , decim rate = >

g e ne ri c map (FREQADDR = > FR RX FREQ 0 , PHASEADDR = > FR RX PHASE 0 ) port map ( c l o c k = > clk64 , decim rate , sample strobe = > rx sample strobe , > hb strobe , hb strobe = serial data , decimator strobe = > strobe decim , serial data = > serial addr = > serial addr ,

602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 rx en 3 t : rx en 2 f : rx en 2 t : rx en 1 f : rx en 1 t : rx en 0 f :

> serial strobe , serial strobe = = > bb rx i0 , > bb rx q0 , q out = end generate r x e n 0 t ;

i in = > ddc0 in i ,

q in = > ddc0 in q ,

i out

d eb u gd at a = > d eb u gd at a ,

debugctrl = > debugctrl ) ;

i f ( not RX EN 0 ) generate

b b r x i 0 <= ( o the rs = > 0 ) ; > 0 ) ; b b r x q 0 <= ( o the rs = end generate r x e n 0 f ; i f ( RX EN 1 ) generate : rx chain reset = > 0 , enable = > enable rx , decim rate = >

rx chain 1

g e ne ri c map (FREQADDR = > FR RX FREQ 1 , PHASEADDR = > FR RX PHASE 1 ) port map ( c l o c k = > clk64 , decim rate , sample strobe = > rx sample strobe , > OPEN, hb strobe = decimator strobe = > strobe decim , serial data = > serial data , q in = > ddc1 in q , i out serial addr = > serial addr ,

serial strobe = > serial strobe , = > bb rx i1 , q out = > bb rx q1 , end generate r x e n 1 t ;

i in = > ddc1 in i ,

d eb u gd at a = > OPEN,

debugctrl = > O PEN) ;

i f ( not RX EN 1 ) generate

> 0 ) ; b b r x i 1 <= ( o the rs = b b r x q 1 <= ( o the rs = > 0 ) ; end generate r x e n 1 f ; i f ( RX EN 2 ) generate : rx chain reset = > 0 , enable = > enable rx , decim rate = >

rx chain 2

g e ne ri c map (FREQADDR = > FR RX FREQ 2 , PHASEADDR = > FR RX PHASE 2 ) port map ( c l o c k = > clk64 , decim rate , sample strobe = > rx sample strobe , > OPEN, hb strobe = decimator strobe = > strobe decim , serial data = > serial data , q in = > ddc2 in q , i out serial addr = > serial addr ,

serial strobe = > serial strobe , = > bb rx i2 , q out = > bb rx q2 , end generate r x e n 2 t ; i f ( not RX EN 2 ) generate

i in = > ddc2 in i ,

d eb u gd at a = > OPEN,

debugctrl = > O PEN) ;

> 0 ) ; b b r x i 2 <= ( o the rs = b b r x q 2 <= ( o the rs = > 0 ) ; end generate r x e n 2 f ; i f ( RX EN 3 ) generate : rx chain reset = > 0 , enable = > enable rx , decim rate = >

rx chain 3

> FR RX PHASE 3 ) g e ne ri c map (FREQADDR = > FR RX FREQ 3 , PHASEADDR = port map ( c l o c k = > clk64 , decim rate , > rx sample strobe , sample strobe = decimator strobe = > strobe decim ,

158

646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 rx en f : rx en 3 f :

> OPEN, hb strobe = = > bb rx i3 , q out = > bb rx q3 , end generate r x e n 3 t ;

serial addr = > serial addr ,

serial data = > serial data , q in = > ddc3 in q , i out

serial strobe = > serial strobe ,

i in = > ddc3 in i ,

d eb u gd at a = > OPEN,

debugctrl = > O PEN) ;

i f ( not RX EN 3 ) generate

> 0 ) ; b b r x i 3 <= ( o the rs = b b r x q 3 <= ( o the rs = > 0 ) ; end generate r x e n 3 f ; end generate r x e n t ;

i f ( not RX EN) generate signals !

TODO A s s i g n

end generate r x e n f ; CONTROL SIGNALS c a p a b i l i t i e s ( 3 1 downto 8 ) <= ( o the rs = > 0 ) ; c a p a b i l i t i e s ( 7 ) <= 1 when TX CAP HB e l s e c a p a b i l i t i e s ( 6 downto 4 ) <= TX CAP NCHAN; c a p a b i l i t i e s ( 3 ) <= 1 when RX CAP HB e l s e c a p a b i l i t i e s ( 2 downto 0 ) <= RX CAP NCHAN; r e a d b a c k 3 : 0 xF0F0931A serial io 0 : serial io serial clock = > SCLK, serial data in = > SDI , enable = > is greater than i n te rg e r high , so I used binary notation instead . 0 ; 0 ;

> clk64 , port map ( m a s t e r c l k = SEN FPGA , reset = > 0 ,

serial data out = > SDO,

serial addr = > serial addr ,

serial data = >

serial data , 672 673 674 675 676 677 678 679 680 681 master control 0 : master control usbclk = > usbclk , serial addr = > serial addr , tx bus reset = > rx dsp reset = > serial strobe = > serial strobe , tx dsp reset = > tx dsp reset , > clk64 , port map ( m a s t e r c l k = tx bus reset , > rx bus reset , rx bus reset = rx dsp reset , 682 683 684 > enable tx , enable tx = strobe interp , rx sample strobe = > rx sample strobe , t x em p t y , 685 686 687 688 689 690 691 io pins 0 : io pins io 1 = > io rx a , io 2 = > io tx b , io 3 = > io rx b , reg 0 = > > t x d e b u g b u s ( 1 5 downto 0 ) , d e b u g 1 = > t x d e b u g b u s ( 3 1 downto 1 6 ) , debug 0 = debug 2 = > r x d e b u g b u s ( 1 5 downto 0 ) , d e b u g 3 = > r x d e b u g b u s ( 3 1 downto 1 6 ) , reg 0 , reg 1 = > reg 1 , reg 2 = > reg 2 , reg 3 = > reg 3 ) ; reg 0 = > strobe decim = > strobe decim , t x em p t y = > enable rx = > enable rx , interp rate = > interp rate , strobe interp = > decim rate = > decim rate , tx sample strobe = > tx sample strobe , serial strobe = > serial strobe , r e a d b a c k 0 ( 3 1 downto 1 6 ) = > io rx a , r e a d b a c k 1 ( 3 1 downto 1 6 ) = > io rx b , readback 2 = > capabilities , readback 4 = > rssi 0 , readback 5 = >

> io tx a , r e a d b a c k 0 ( 1 5 downto 0 ) = r e a d b a c k 1 ( 1 5 downto 0 ) = > io tx b , rssi 1 , readback 6 = > rssi 2 ,

> 11110000111100001001001100011010 , readback 3 = readback 7 = > rssi 3 ) ;

serial data = > serial data ,

> io tx a , port map ( i o 0 = reg 0 , reg 1 = > reg 1 ,

reg 2 = > reg 2 ,

reg 3 = > reg 3 ,

clock = > clk64 ,

rx reset = >

rx dsp reset ,

159

692 693 694 695 696 697 698 699 700 701

> tx dsp reset , tx reset =

serial addr = > serial addr ,

serial data = > serial data ,

serial strobe = > serial strobe ) ; MISC SETTINGS sr misc : setting reg > FR MODE) g e ne ri c map( my addr = port map ( c l o c k = > clk64 , serial addr , d in = > serial data , ch an ged = > O PEN) ; end b e h a v i o r a l ; d o u t ( 3 1 downto 8 ) = > OPEN, d o u t ( 7 downto 0 ) = > settings , reset = > rx dsp reset , strobe = > serial strobe , ad d r = >

160

Appendix B

FPGA Board Description (XBD)

This appendix contains the Xilinx Board Denition [21] le for the COSMIAC FPGA board. This le is meant for use with Xilinx EDK. Please note that ash memory support is missing and that the DDR2 memory needs more information from the Memory Interface Generator (MIG). Listing B.1: COSMIAC FPGA Board Description (XBD)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 # ## TODO ### # USB R e s e t (H/L? P in ? ) # DDR2 Memory (MIG o u t p u t ) # F l a s h Memory # I2C C o n t r o l l e r # # Xilinx # Last Board Definition April Steve for 2011 t h e SPAU FPGA Board M o d i f i e d : 13

# XBD A u t h o r : #

Olivieri

# C o p y r i g h t (C) 2010 COSMIAC # # # # # # # # # # # # # # You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , Franklin of t h e GNU G e n e r a l P u b l i c to the B ost on , MA License USA write Free S o ft w a r e 02110 1301 T h i s pr ogr am is distributed in the hope even that the it will be useful , of b u t WITHOUT ANY WARRANTY; without implied warranty T h i s pr ogr am it the ( at under Free your the is free of software ; y ou can redistribute License the it as and / o r m o d i f y published or by terms t h e GNU G e n e r a l P u b l i c either

Software

Foundation ; later

version 2 of

License ,

o p t i o n ) any

version .

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. GNU G e n e r a l Public License f o r more details .

See t h e

I n c . , 51

Street ,

161

28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

# F i x SPI SS Bus (USRP , # o f SS ) # Vendor Information

ATTRIBUTE VENDOR = COSMIAC ATTRIBUTE SPEC URL = www. c o s m i a c . com ATTRIBUTE CONTACT INFO URL = h t t p : / /www. c o s m i a c . com/

# Board

Information

ATTRIBUTE NAME = SPAU FPGA Board ATTRIBUTE REVISION = B ATTRIBUTE DESC = SPAU FPGA Board ATTRIBUTE LONG DESC = The SPAU FPGA Board XCS1400A 5FG484 d e v i c e and h as DDR2 memory , E t h e r n e t , and GPIO c a p a b i l i t i e s . # P r im ar y C l o c k ( 5 0MHz) utilizes a X i l i n x S p ar t an 3A

f l a s h memory , USB2 , I2C , SPI , RS232 ,

BEGIN IO INTERFACE ATTRIBUTE IOTYPE = XIL CLOCK V1 ATTRIBUTE INSTANCE = CLOCK 50MHZ PARAMETER CLK FREQ = 5 0 0 0 0 0 0 0 , I O I S = c l k f r e q , RANGE = ( 5 0 0 0 0 0 0 0 ) PORT CLK = OSC 50 MHZ , END IO IS = e x t c l k

# S e c o n d C l o c k ( 7 5MHz) BEGIN IO INTERFACE ATTRIBUTE IOTYPE = XIL CLOCK V1 ATTRIBUTE INSTANCE = CLOCK 75MHZ

PARAMETER CLK FREQ = 7 5 0 0 0 0 0 0 , I O I S = c l k f r e q , RANGE = ( 7 5 0 0 0 0 0 0 ) PORT CLK = OSC 75 MHZ , END IO IS = e x t c l k

# Third

Clock

( 1 0 0MHz)

BEGIN IO INTERFACE ATTRIBUTE IOTYPE = XIL CLOCK V1 ATTRIBUTE INSTANCE = CLOCK 100MHZ PARAMETER CLK FREQ = 1 0 0 0 0 0 0 0 0 , I O I S = c l k f r e q , RANGE = ( 1 0 0 0 0 0 0 0 0 )

PORT CLK = OSC 100 MHZ , END # Reset Button

IO IS = e x t c l k

BEGIN IO INTERFACE ATTRIBUTE IOTYPE = XIL RESET V1 ATTRIBUTE INSTANCE = RESET PARAMETER RST POLARITY = 1 , I O I S = p o l a r i t y , VALUE NOTE = A c t i v e High

PORT RESET = CONN RESET, END # P r im ar y UART BEGIN IO INTERFACE

IO IS = e x t r s t

162

85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141

ATTRIBUTE IOTYPE = XIL UART V1 ATTRIBUTE INSTANCE = RS232 PRIMARY PORT FROM RS232 = CONN FROM RS232 , PORT TO RS232 = CONN TO RS232 , END IO IS = s e r i a l i n

I O I S = s e r i a l o u t , INITIALVAL = GND

# AT90 UART BEGIN IO INTERFACE ATTRIBUTE IOTYPE = XIL UART V1 ATTRIBUTE INSTANCE = RS232 AT90

PORT AT90 RXD1 = CONN AT90 RXD1 , PORT AT90 TXD1 = CONN AT90 TXD1 , END # LEDs BEGIN IO INTERFACE ATTRIBUTE IOTYPE = XIL GPIO V1 ATTRIBUTE INSTANCE = LEDs 8BIT

IO IS = s e r i a l i n I O I S = s e r i a l o u t , INITIALVAL = GND

PARAMETER n u m b i t s = 8 , I O I S = n u m b i t s PARAMETER i s d u a l = 0 , I O I S = i s d u a l PARAMETER b i d i r d a t a = 0 , I O I S = i s b i d i r PARAMETER a l l i n p u t s = 0 , I O I S = a l l i n p u t s PORT LED0 = CONN LED0, PORT LED1 = CONN LED1, PORT LED2 = CONN LED2, PORT LED3 = CONN LED3, PORT LED4 = CONN LED4, PORT LED5 = CONN LED5, PORT LED6 = CONN LED6, PORT LED7 = CONN LED7, END I O I S = g p i o d a t a o u t [ 0 ] , INITIALVAL = VCC I O I S = g p i o d a t a o u t [ 1 ] , INITIALVAL = VCC I O I S = g p i o d a t a o u t [ 2 ] , INITIALVAL = VCC I O I S = g p i o d a t a o u t [ 3 ] , INITIALVAL = VCC I O I S = g p i o d a t a o u t [ 4 ] , INITIALVAL = VCC I O I S = g p i o d a t a o u t [ 5 ] , INITIALVAL = VCC I O I S = g p i o d a t a o u t [ 6 ] , INITIALVAL = VCC I O I S = g p i o d a t a o u t [ 7 ] , INITIALVAL = VCC

# Push B u t t o n # The b u t t o n # # # # # # # # # PORT BUTTON = CONN BUTTON, IO IS = g p i o d a t a i n [ 0 ] PARAMETER n u m b i t s = 1 , I O I S = n u m b i t s PARAMETER i s d u a l = 0 , I O I S = i s d u a l PARAMETER b i d i r d a t a = 0 , I O I S = i s b i d i r PARAMETER a l l i n p u t s = 1 , I O I S = a l l i n p u t s is currently used for the system reset . #BEGIN IO INTERFACE ATTRIBUTE IOTYPE = XIL GPIO V1 ATTRIBUTE INSTANCE = PUSH BUTTON

#END # AT90 I /O P o r t A BEGIN IO INTERFACE ATTRIBUTE IOTYPE = XIL GPIO V1 ATTRIBUTE INSTANCE = AT90 PA PARAMETER n u m b i t s = 8 , I O I S = n u m b i t s PARAMETER i s d u a l = 0 , I O I S = i s d u a l

163

142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198

PARAMETER b i d i r d a t a = 0 , I O I S = i s b i d i r PARAMETER a l l i n p u t s = 0 , I O I S = a l l i n p u t s PORT AT PA0 = CONN AT PA0 , PORT AT PA1 = CONN AT PA1 , PORT AT PA2 = CONN AT PA2 , PORT AT PA3 = CONN AT PA3 , PORT AT PA4 = CONN AT PA4 , PORT AT PA5 = CONN AT PA5 , PORT AT PA6 = CONN AT PA6 , PORT AT PA7 = CONN AT PA7 , END I O I S = g p i o d a t a o u t [ 0 ] , INITIALVAL = GND I O I S = g p i o d a t a o u t [ 1 ] , INITIALVAL = GND I O I S = g p i o d a t a o u t [ 2 ] , INITIALVAL = GND I O I S = g p i o d a t a o u t [ 3 ] , INITIALVAL = GND I O I S = g p i o d a t a o u t [ 4 ] , INITIALVAL = GND I O I S = g p i o d a t a o u t [ 5 ] , INITIALVAL = GND I O I S = g p i o d a t a o u t [ 6 ] , INITIALVAL = GND I O I S = g p i o d a t a o u t [ 7 ] , INITIALVAL = GND

# AT90 I /O P o r t C BEGIN IO INTERFACE ATTRIBUTE IOTYPE = XIL GPIO V1 ATTRIBUTE INSTANCE = AT90 PC

PARAMETER n u m b i t s = 8 , I O I S = n u m b i t s PARAMETER i s d u a l = 0 , I O I S = i s d u a l PARAMETER b i d i r d a t a = 0 , I O I S = i s b i d i r PARAMETER a l l i n p u t s = 0 , I O I S = a l l i n p u t s PORT AT PC0 = CONN AT PC0 , PORT AT PC1 = CONN AT PC1 , PORT AT PC2 = CONN AT PC2 , PORT AT PC3 = CONN AT PC3 , PORT AT PC4 = CONN AT PC4 , PORT AT PC5 = CONN AT PC5 , PORT AT PC6 = CONN AT PC6 , PORT AT PC7 = CONN AT PC7 , END # AT90 I /O P o r t F BEGIN IO INTERFACE ATTRIBUTE IOTYPE = XIL GPIO V1 ATTRIBUTE INSTANCE = AT90 PF PARAMETER n u m b i t s = 4 , I O I S = n u m b i t s PARAMETER i s d u a l = 0 , I O I S = i s d u a l PARAMETER b i d i r d a t a = 0 , I O I S = i s b i d i r PARAMETER a l l i n p u t s = 0 , I O I S = a l l i n p u t s PORT AT PF0 = CONN AT PF0 , PORT AT PF1 = CONN AT PF1 , PORT AT PF2 = CONN AT PF2 , PORT AT PF3 = CONN AT PF3 , END # Ethernet BEGIN IO INTERFACE ATTRIBUTE IOTYPE = XIL ETHERNET V1 I O I S = g p i o d a t a o u t [ 0 ] , INITIALVAL = GND I O I S = g p i o d a t a o u t [ 1 ] , INITIALVAL = GND I O I S = g p i o d a t a o u t [ 2 ] , INITIALVAL = GND I O I S = g p i o d a t a o u t [ 3 ] , INITIALVAL = GND I O I S = g p i o d a t a o u t [ 0 ] , INITIALVAL = GND I O I S = g p i o d a t a o u t [ 1 ] , INITIALVAL = GND I O I S = g p i o d a t a o u t [ 2 ] , INITIALVAL = GND I O I S = g p i o d a t a o u t [ 3 ] , INITIALVAL = GND I O I S = g p i o d a t a o u t [ 4 ] , INITIALVAL = GND I O I S = g p i o d a t a o u t [ 5 ] , INITIALVAL = GND I O I S = g p i o d a t a o u t [ 6 ] , INITIALVAL = GND I O I S = g p i o d a t a o u t [ 7 ] , INITIALVAL = GND

ATTRIBUTE INSTANCE = ETHERNET PORT E COL = CONN E COL , PORT E CRS = CONN E CRS , PORT E MDC = CONN E MDC, I O I S = ETH COL I O I S = ETH CRS I O I S = ETH MDC

164

199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 #

PORT E MDIO = CONN E MDIO, PORT E NRST = CONN E NRST,

I O I S = ETH MDIO I O I S = PHY RESETn I O I S = ETH RXC

PORT E RX CLK = CONN E RX CLK , PORT E RX DV = CONN E RX DV , PORT E RXD0 = CONN E RXD0, PORT E RXD1 = CONN E RXD1, PORT E RXD2 = CONN E RXD2, PORT E RXD3 = CONN E RXD3,

I O I S = ETH RXDV

I O I S = ETH RXD [ 0 ] I O I S = ETH RXD [ 1 ] I O I S = ETH RXD [ 2 ] I O I S = ETH RXD [ 3 ] I O I S = ETH RXER I O I S = ETH TXC

PORT E RX ER = CONN E RX ER ,

PORT E TX CLK = CONN E TX CLK , PORT E TX EN = CONN E TX EN , PORT E TXD0 = CONN E TXD0 , PORT E TXD1 = CONN E TXD1 , PORT E TXD2 = CONN E TXD2 , PORT E TXD3 = CONN E TXD3 ,

I O I S = ETH TXEN

I O I S = ETH TXD [ 0 ] I O I S = ETH TXD [ 1 ] I O I S = ETH TXD [ 2 ] I O I S = ETH TXD [ 3 ] I O I S = ETH TXER

PORT E TX ER = CONN E TX ER , END # USB C o n t r o l l e r BEGIN IO INTERFACE

ATTRIBUTE IOTYPE = XIL USB2DEVICE V4 ATTRIBUTE INSTANCE = USB CONTROLLER

PARAMETER C INCLUDE DMA = 1 , I O I S = C INCLUDE DMA PARAMETER C PHY RESET TYPE = 1 , I O I S = C PHY RESET TYPE PORT USB CLKOUT = CONN USB CLKOUT, PORT USB DIR = CONN USB DIR , PORT USB NXT = CONN USB NXT, PORT USB STP = CONN USB STP , PORT USB RESET = n e t g n d , I O I S = ULPI Clock

I O I S = ULPI Dir I O I S = ULPI Next I O I S = ULPI Stop IO IS = ULPI Reset

PORT USB RESET = CONN USB RESET ,

I O I S = U L P I R eset

PORT USB D0 = CONN USB D0 , PORT USB D1 = CONN USB D1 , PORT USB D2 = CONN USB D2 , PORT USB D3 = CONN USB D3 , PORT USB D4 = CONN USB D4 , PORT USB D5 = CONN USB D5 , PORT USB D6 = CONN USB D6 , PORT USB D7 = CONN USB D7 , END # DDR2 Memory BEGIN IO INTERFACE

I O I S = ULPI Data [ 0 ] I O I S = ULPI Data [ 1 ] I O I S = ULPI Data [ 2 ] I O I S = ULPI Data [ 3 ] I O I S = ULPI Data [ 4 ] I O I S = ULPI Data [ 5 ] I O I S = ULPI Data [ 6 ] I O I S = ULPI Data [ 7 ]

ATTRIBUTE IOTYPE = XIL MEMORY V1 ATTRIBUTE INSTANCE = DDR2 SDRAM # Controller Settings

PARAMETER C NUM PORTS = 1 , I O I S = C NUM PORTS

# M icr on MT47H128M16HG3IT : A PARAMETER C MEM TYPE = DDR2, I O I S = C MEM TYPE PARAMETER C MEM PARTNO=CUSTOM , I O I S=C MEM PARTNO

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# 256MB PARAMETER C BASEADDR = 0 x00000000 , PARAMETER C HIGHADDR = 0 x 0 f f f f f f f , # Memory /DIMM S e t t i n g s PARAMETER C MEM ADDR WIDTH = 1 4 , I O I S = C MEM ADDR WIDTH PARAMETER C MEM BANKADDR WDITh = 3 , I O I S = C MEM BANKADDR WIDTH PARAMETER C MEM DM WIDTH = 2 , I O I S = C MEM DM WIDTH PARAMETER C MEM DQS WIDTH = 2 , I O I S = C MEM DQS WIDTH PARAMETER C MEM DATA WIDTH = 1 6 , I O I S = C MEM DATA WIDTH PARAMETER C DDR2 DQSN ENABLE = 1 , I O I S = C DDR2 DQSN ENABLE PARAMETER C MPMC CLK0 PERIOD PS = 3 0 0 0 , I O I S = C MPMC CLK0 PERIOD PS # ps I O I S = C BASEADDR I O I S = C HIGHADDR

# Memory P a r t

Settings

PARAMETER C MEM PART DATA DEPTH = 1 2 8 , I O I S = C MEM PART DATA DEPTH PARAMETER C MEM PART DATA WIDTH = 1 6 , I O I S = C MEM PART DATA WIDTH PARAMETER C MEM PART NUM BANK BITS = 3 , I O I S = C MEM PART NUM BANK BITS PARAMETER C MEM PART NUM ROW BITS = 1 4 , I O I S = C MEM PART NUM ROW BITS PARAMETER C MEM PART NUM COL BITS = 1 0 , I O I S = C MEM PART NUM COL BITS # Memory T im in g Settings I O I S = C MEM PART CAS A FMAX # ps # MHz

PARAMETER C MEM PART CAS A FMAX = 6 6 7 .

PARAMETER C MEM PART CAS A = 5 , I O I S = C MEM PART CAS A PARAMETER C MEM PART TRRD = 1 0 0 0 0 , I O I S = C MEM PART TRRD PARAMETER C MEM PART TMRD = 2 , I O I S = C MEM PART TMRD PARAMETER C MEM PART TCCD = 2 , I O I S = C MEM PART TCCD PARAMETER C MEM PART TWR = 1 5 0 0 0 , I O I S = C MEM PART TWR

# tCK # ps # tCK # ps

PARAMETER C MEM PART TRCD = 1 5 0 0 0 , I O I S = C MEM PART TRCD

PARAMETER C MEM PART TWTR = 7 5 0 0 , I O I S = C MEM PART TWTR # p s PARAMETER C MEM PART TREFI = 3 9 0 0 0 0 0 , I O I S = C MEM PART TREFI PARAMETER C MEM PART TRFC = 1 9 5 0 0 0 , I O I S = C MEM PART TRFC PARAMETER C MEM PART TRP = 1 5 0 0 0 , I O I S = C MEM PART TRP PARAMETER C MEM PART TRC = 6 0 0 0 0 , I O I S = C MEM PART TRC # ps # ps # ps # ps # ps # ps

PARAMETER C MEM PART TRASMAX = 7 0 0 0 0 0 0 0 , I O I S = C MEM PART TRASMAX PARAMETER C MEM PART TRAS = 4 0 0 0 0 , I O I S = C MEM PART TRAS

PORT DDR ODT = d d r 2 d d r o d t 0 ,

IO IS = ddr2 odt IO IS = ddr2 address [ 0 ] IO IS = ddr2 address [ 1 ] IO IS = ddr2 address [ 2 ] IO IS = ddr2 address [ 3 ] IO IS = ddr2 address [ 4 ] IO IS = ddr2 address [ 5 ] IO IS = ddr2 address [ 6 ] IO IS = ddr2 address [ 7 ] IO IS = ddr2 address [ 8 ] IO IS = ddr2 address [ 9 ] IO IS = ddr2 address [ 1 0 ] IO IS = ddr2 address [ 1 1 ] IO IS = ddr2 address [ 1 2 ]

PORT DDR Addr 0 = d d r 2 d d r a d d r 0 , PORT DDR Addr 1 = d d r 2 d d r a d d r 1 , PORT DDR Addr 2 = d d r 2 d d r a d d r 2 , PORT DDR Addr 3 = d d r 2 d d r a d d r 3 , PORT DDR Addr 4 = d d r 2 d d r a d d r 4 , PORT DDR Addr 5 = d d r 2 d d r a d d r 5 , PORT DDR Addr 6 = d d r 2 d d r a d d r 6 , PORT DDR Addr 7 = d d r 2 d d r a d d r 7 , PORT DDR Addr 8 = d d r 2 d d r a d d r 8 , PORT DDR Addr 9 = d d r 2 d d r a d d r 9 ,

PORT DDR Addr 10 = d d r 2 d d r a d d r 1 0 , PORT DDR Addr 11 = d d r 2 d d r a d d r 1 1 , PORT DDR Addr 12 = d d r 2 d d r a d d r 1 2 ,

PORT DDR BankAddr 0 = d d r 2 d d r b a n k a d d r 0 , PORT DDR BankAddr 1 = d d r 2 d d r b a n k a d d r 1 , PORT DDR CASn = d d r 2 d d r c a s n , PORT DDR RASn = d d r 2 d d r r a s n ,

I O I S = ddr2 BankAddr [ 0 ] I O I S = ddr2 BankAddr [ 1 ]

IO IS = d d r 2 c o l a d d r s e l e c t IO IS = d d r 2 r o w a d d r se l e c t

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PORT DDR CKE = d d r 2 d d r c k e , PORT DDR CSn = d d r 2 d d r c s n , PORT DDR WEn = d d r 2 d d r w e n , PORT DDR CLK = d d r 2 c l k ,

IO IS = d d r 2 c l k e n a b l e IO IS = d d r 2 c h i p s e l e c t IO IS = d d r 2 w r i t e e n ab l e

IO IS = d d r 2 c l k IO IS = d d r 2 c l k n

PORT DDR CLK n = d d r 2 c l k n ,

PORT DDR DM 0 = d d r 2 d d r d m 0 , PORT DDR DM 1 = d d r 2 d d r d m 1 ,

IO IS = ddr2 data mask [ 0 ] IO IS = ddr2 data mask [ 1 ] IO IS = d d r 2 d at a st r ob e [ 0 ] IO IS = d d r 2 d at a st r ob e [ 1 ] IO IS = d d r 2 d at a st r ob e n [ 0 ] IO IS = d d r 2 d at a st r ob e n [ 1 ] IO IS = ddr2 data [ 0 ] IO IS = ddr2 data [ 1 ] IO IS = ddr2 data [ 2 ] IO IS = ddr2 data [ 3 ] IO IS = ddr2 data [ 4 ] IO IS = ddr2 data [ 5 ] IO IS = ddr2 data [ 6 ] IO IS = ddr2 data [ 7 ] IO IS = ddr2 data [ 8 ] IO IS = ddr2 data [ 9 ] IO IS = ddr2 data [ 1 0 ] IO IS = ddr2 data [ 1 1 ] IO IS = ddr2 data [ 1 2 ] IO IS = ddr2 data [ 1 3 ] IO IS = ddr2 data [ 1 4 ] IO IS = ddr2 data [ 1 5 ] IO IS = d d r 2 d q s d i v i IO IS = d d r 2 d q s d i v o

PORT DDR DQS 0 = d d r 2 d d r d q s 0 , PORT DDR DQS 1 = d d r 2 d d r d q s 1 ,

PORT DDR DQSn 0 = d d r 2 d d r d q s n 0 , PORT DDR DQSn 1 = d d r 2 d d r d q s n 1 , PORT DDR DQ 0 = PORT DDR DQ 1 = PORT DDR DQ 2 = PORT DDR DQ 3 = PORT DDR DQ 4 = PORT DDR DQ 5 = PORT DDR DQ 6 = PORT DDR DQ 7 = PORT DDR DQ 8 = PORT DDR DQ 9 = ddr2 ddr dq 0 ddr2 ddr dq 1 ddr2 ddr dq 2 ddr2 ddr dq 3 ddr2 ddr dq 4 ddr2 ddr dq 5 ddr2 ddr dq 6 ddr2 ddr dq 7 ddr2 ddr dq 8 ddr2 ddr dq 9 , , , , , , , , , ,

PORT DDR DQ 10 = d d r 2 d d r d q 1 0 , PORT DDR DQ 11 = d d r 2 d d r d q 1 1 , PORT DDR DQ 12 = d d r 2 d d r d q 1 2 , PORT DDR DQ 13 = d d r 2 d d r d q 1 3 , PORT DDR DQ 14 = d d r 2 d d r d q 1 4 , PORT DDR DQ 15 = d d r 2 d d r d q 1 5 ,

PORT DDR DQS DIV I = d d r 2 d d r d q s d i v i , PORT DDR DQS DIV O = d d r 2 d d r d q s d i v o , END

# SPI C o n t r o l l e r BEGIN IO INTERFACE ATTRIBUTE IOTYPE = XIL SPI V1 ATTRIBUTE INSTANCE = SPI CONTROLLER PARAMETER C FIFO EXIST = 1 , I O I S= f i f o e x i s t PARAMETER C SCK RATIO = 3 2 , I O I S=c l k f r e q PARAMETER C NUM TRANSFER BITS = 8 , I O I S = n u m t r a n s f e r b i t s PARAMETER C NUM SS BITS = 4 , I O I S = s s b i t s PARAMETER C NUM SS BITS = 2 , I O I S = s s b i t s PORT SPISEL = n e t v c c , IO IS = s l a v e s e l e c t n IO IS = d at a i n IO IS = data out IO IS = c l k o u t

PORT SEN SPI RX = CONN SEN SPI RX , PORT SEN SPI TX = CONN SEN SPI TX ,

PORT SEN SPI CLK = CONN SEN SPI CLK , PORT SEN SS 0 = CONN SEN SS 0 , PORT SEN SS 1 = CONN SEN SS 1 , PORT SEN SS 2 = CONN SEN SS 2 , PORT SEN SS 3 = CONN SEN SS 3 ,

IO IS = s l a v e s e l e c t [ 0 ] IO IS = s l a v e s e l e c t [ 1 ] IO IS = s l a v e s e l e c t [ 2 ] IO IS = s l a v e s e l e c t [ 3 ] # SEN OE IO

END

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# FPGA D e f i n i t i o n BEGIN FPGA ATTRIBUTE INSTANCE ATTRIBUTE FAMILY ATTRIBUTE DEVICE ATTRIBUTE PACKAGE ATTRIBUTE SPEED GRADE = fpga 0 = spartan3a = xc3s1400a = fg484 = 5

ATTRIBUTE JTAG POSITION = 2 # ## CLOCKS ### PORT CLOCK ) = CONN OSC 50 MHZ , UCF NET STRING = ( LOC = V12 , IOSTANDARD = LCVMOS33

381 382 383 384 385 386 387 388

PORT CLOCK PORT CLOCK

= CONN OSC 75 MHZ = CONN OSC 100 MHZ

, UCF NET STRING = ( LOC = AA12 , IOSTANDARD = , UCF NET STRING = ( LOC = C12 , IOSTANDARD =

LCVMOS33 , CLOCK DEDICATED ROUTE = FALSE ) LCVMOS33 , CLOCK DEDICATED ROUTE = FALSE ) # ## RESET ### Used PORT RESET PULLDOWN ) # ## UARTS ### PORT FROM RS232 ) 389 390 391 PORT AT90 RXD1 ) 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 # ## AT90 I /O P o r t s ### PORT AT PA0 PORT AT PA1 PORT AT PA2 PORT AT PA3 PORT AT PA4 PORT AT PA5 PORT AT PA6 PORT AT PA7 = CONN AT PA0 = CONN AT PA1 = CONN AT PA2 = CONN AT PA3 = CONN AT PA4 = CONN AT PA5 = CONN AT PA6 = CONN AT PA7 , UCF NET STRING = ( LOC = A6 , IOSTANDARD = LVCMOS33 ) , UCF NET STRING = ( LOC = A7 , IOSTANDARD = LVCMOS33 ) , UCF NET STRING = ( LOC = C7 , IOSTANDARD = LVCMOS33 ) , UCF NET STRING = ( LOC = D7 , IOSTANDARD = LVCMOS33 ) , UCF NET STRING = ( LOC = A5 , IOSTANDARD = LVCMOS33 ) , UCF NET STRING = ( LOC = B6 , IOSTANDARD = LVCMOS33 ) , UCF NET STRING = ( LOC = D6 , IOSTANDARD = LVCMOS33 ) , UCF NET STRING = ( LOC = C6 , IOSTANDARD = LVCMOS33 ) # # ## PUSH BUTTON ### PORT BUTTON PULLDOWN ) = CONN BUTTON , UCF NET STRING = ( LOC = U7 , IOSTANDARD = LVCMOS33 , # ## LEDS ### PORT LED0 PORT LED1 PORT LED2 PORT LED3 PORT LED4 PORT LED5 PORT LED6 PORT LED7 = CONN LED0 = CONN LED1 = CONN LED2 = CONN LED3 = CONN LED4 = CONN LED5 = CONN LED6 = CONN LED7 , UCF NET STRING = ( LOC = AA19 , IOSTANDARD = LVCMOS33 ) , UCF NET STRING = ( LOC = AB19 , IOSTANDARD = LVCMOS33 ) , UCF NET STRING = ( LOC = V17 , IOSTANDARD = LVCMOS33 ) , UCF NET STRING = ( LOC = W18 , IOSTANDARD = LVCMOS33 ) , UCF NET STRING = ( LOC = W17 , IOSTANDARD = LVCMOS33 ) , UCF NET STRING = ( LOC = Y18 , IOSTANDARD = LVCMOS33 ) , UCF NET STRING = ( LOC = AA21 , IOSTANDARD = LVCMOS33 ) , UCF NET STRING = ( LOC = AB21 , IOSTANDARD = LVCMOS33 ) PORT AT90 TXD1 ) = CONN AT90 TXD1 , UCF NET STRING = ( LOC = D19 , IOSTANDARD = LVCMOS33 = CONN AT90 RXD1 , UCF NET STRING = ( LOC = D18 , IOSTANDARD = LVCMOS33 PORT TO RS232 ) = CONN TO RS232 , UCF NET STRING = ( LOC = Y22 , IOSTANDARD = LVCMOS33 = CONN FROM RS232 , UCF NET STRING = ( LOC = R15 , IOSTANDARD = LVCMOS33 the south button , UCF NET STRING = ( LOC = U7 , IOSTANDARD = LVCMOS33 ,

= CONN RESET

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PORT AT PC0 ) PORT AT PC1 ) PORT AT PC2 PORT AT PC3 PORT AT PC4 ) PORT AT PC5 ) PORT AT PC6 PORT AT PC7

= CONN AT PC0 = CONN AT PC1 = CONN AT PC2 = CONN AT PC3 = CONN AT PC4 = CONN AT PC5 = CONN AT PC6 = CONN AT PC7

, UCF NET STRING = ( LOC = C10 , IOSTANDARD = LVCMOS33 , UCF NET STRING = ( LOC = A10 , IOSTANDARD = LVCMOS33 , UCF NET STRING = ( LOC = A8 , IOSTANDARD = LVCMOS33 ) , UCF NET STRING = ( LOC = A9 , IOSTANDARD = LVCMOS33 ) , UCF NET STRING = ( LOC = E10 , IOSTANDARD = LVCMOS33 , UCF NET STRING = ( LOC = D10 , IOSTANDARD = LVCMOS33 , UCF NET STRING = ( LOC = C9 , IOSTANDARD = LVCMOS33 ) , UCF NET STRING = ( LOC = B9 , IOSTANDARD = LVCMOS33 )

PORT AT PF0 ) PORT AT PF1 ) PORT AT PF2 )

= CONN AT PF0 = CONN AT PF1 = CONN AT PF2

, UCF NET STRING = ( LOC = B17 , IOSTANDARD = LVCMOS33 , UCF NET STRING = ( LOC = A17 , IOSTANDARD = LVCMOS33 , UCF NET STRING = ( LOC = D15 , IOSTANDARD = LVCMOS33

429 430 431 432

PORT AT PF3 ) # ## E t h e r n e t ### PORT E COL

= CONN AT PF3

, UCF NET STRING = ( LOC = C15 , IOSTANDARD = LVCMOS33

= CONN E COL

, UCF NET STRING = ( LOC = AB3 , IOSTANDARD =

LVCMOS33 , PULLDOWN ) 433 434 PORT E CRS PORT E MDC ) 435 436 437 438 439 PORT E MDIO ) PORT E NRST PORT E RX CLK PORT E RX DV PORT E RXD0 = CONN E NRST = CONN E RX CLK = CONN E RX DV = CONN E RXD0 , UCF NET STRING = ( LOC = Y5 , IOSTANDARD = LVCMOS33 ) , UCF NET STRING = ( LOC = W7 , IOSTANDARD = LVCMOS33 ) , UCF NET STRING = ( LOC = Y7 , IOSTANDARD = LVCMOS33 ) , UCF NET STRING = ( LOC = AB7 , IOSTANDARD = = CONN E MDIO , UCF NET STRING = ( LOC = AB5 , IOSTANDARD = LVCMOS33 = CONN E CRS = CONN E MDC , UCF NET STRING = ( LOC = AA4 , IOSTANDARD = , UCF NET STRING = ( LOC = AB4 , IOSTANDARD = LVCMOS33 LVCMOS33 , PULLDOWN )

LVCMOS33 , PULLUP ) 440 441 442 PORT E RXD1 PULLUP ) PORT E RXD2 PULLUP ) PORT E RXD3 = CONN E RXD3 , UCF NET STRING = ( LOC = AA6 , IOSTANDARD = = CONN E RXD2 , UCF NET STRING = ( LOC = Y6 , IOSTANDARD = LVCMOS33 , = CONN E RXD1 , UCF NET STRING = ( LOC = W6 , IOSTANDARD = LVCMOS33 ,

LVCMOS33 , PULLUP ) 443 444 445 PORT E RX ER ) PORT E TC CLK ) PORT E TX EN ) 446 447 PORT E TXD0 LVCMOS33 ) PORT E TXD1 LVCMOS33 ) 448 449 PORT E TXD2 ) PORT E TXD3 ) = CONN E TXD3 , UCF NET STRING = ( LOC = V10 , IOSTANDARD = LVCMOS33 = CONN E TXD2 , UCF NET STRING = ( LOC = Y10 , IOSTANDARD = LVCMOS33 = CONN E TXD1 , UCF NET STRING = ( LOC = AA10 , IOSTANDARD = = CONN E TXD0 , UCF NET STRING = ( LOC = AB10 , IOSTANDARD = = CONN E TX EN , UCF NET STRING = ( LOC = AB6 , IOSTANDARD = LVCMOS33 = CONN E TX CLK , UCF NET STRING = ( LOC = AA8 , IOSTANDARD = LVCMOS33 = CONN E RX ER , UCF NET STRING = ( LOC = AB8 , IOSTANDARD = LVCMOS33

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PORT E TX ER

= CONN E TX ER

, UCF NET STRING = ( LOC = AA3 , IOSTANDARD =

LVCMOS33 , PULLUP ) # ## USB ### PORT USB CLKOUT = CONN USB CLKOUT , UCF NET STRING = ( LOC = E13 , IOSTANDARD = LVCMOS33 , PULLDOWN ) 454 455 456 PORT USB DIR PORT USB NXT PORT USB STP = CONN USB DIR = CONN USB NXT = CONN USB STP , UCF NET STRING = ( LOC = C13 , IOSTANDARD = , UCF NET STRING = ( LOC = D13 , IOSTANDARD = , UCF NET STRING = ( LOC = F13 , IOSTANDARD =

LVCMOS33 , PULLDOWN ) LVCMOS33 , PULLDOWN ) LVCMOS33 , PULLDOWN ) 457 458 459 # PORT USB RESET PORT USB D0 PORT USB D1 = CONN USB RESET = CONN USB D0 = CONN USB D1 , UCF NET STRING = ( LOC = , IOSTANDARD = LVCMOS33 , , UCF NET STRING = ( LOC = B20 , IOSTANDARD = , UCF NET STRING = ( LOC = A10 , IOSTANDARD =

PULLDOWN , TIG ) LVCMOS33 , PULLDOWN ) LVCMOS33 , PULLDOWN ) 460 461 462 PORT USB D2 PORT USB D3 PORT USB D4 = CONN USB D2 = CONN USB D3 = CONN USB D4 , UCF NET STRING = ( LOC = E15 , IOSTANDARD = , UCF NET STRING = ( LOC = F15 , IOSTANDARD = , UCF NET STRING = ( LOC = C18 , IOSTANDARD =

LVCMOS33 , PULLDOWN ) LVCMOS33 , PULLDOWN ) LVCMOS33 , PULLDOWN ) 463 464 465 PORT USB D5 PORT USB D6 PORT USB D7 = CONN USB D5 = CONN USB D6 = CONN USB D7 , UCF NET STRING = ( LOC = A18 , IOSTANDARD = , UCF NET STRING = ( LOC = B19 , IOSTANDARD = , UCF NET STRING = ( LOC = A19 , IOSTANDARD =

LVCMOS33 , PULLDOWN ) LVCMOS33 , PULLDOWN )

LVCMOS33 , PULLDOWN ) 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 PORT DDR2 DDR BANKADDR0 = d d r 2 d d r b a n k a d d r 0 , UCF NET STRING=(LOC =P3 , IOSTANDARD = SSTL18 I ) # ## DDR2 (FPGA S e c t i o n ) PORT DDR2 ODT PORT DDR2 DDR ADDR0 PORT DDR2 DDR ADDR1 PORT DDR2 DDR ADDR2 PORT DDR2 DDR ADDR3 PORT DDR2 DDR ADDR4 PORT DDR2 DDR ADDR5 PORT DDR2 DDR ADDR6 PORT DDR2 DDR ADDR7 PORT DDR2 DDR ADDR8 PORT DDR2 DDR ADDR9 PORT DDR2 DDR ADDR10 PORT DDR2 DDR ADDR11 PORT DDR2 DDR ADDR12 = ddr2 ddr odt 0 = ddr2 ddr addr 0 = ddr2 ddr addr 1 = ddr2 ddr addr 2 = ddr2 ddr addr 3 = ddr2 ddr addr 4 = ddr2 ddr addr 5 = ddr2 ddr addr 6 = ddr2 ddr addr 7 = ddr2 ddr addr 8 = ddr2 ddr addr 9 = ddr2 ddr addr 10 = ddr2 ddr addr 11 = ddr2 ddr addr 12 , UCF NET STRING=(LOC =P1 , IOSTANDARD = SSTL18 I ) , UCF NET STRING=(LOC =R2 , IOSTANDARD = SSTL18 I ) , UCF NET STRING=(LOC =T4 , IOSTANDARD = SSTL18 I ) , UCF NET STRING=(LOC =R1 , IOSTANDARD = SSTL18 I ) , UCF NET STRING=(LOC =U3 , IOSTANDARD = SSTL18 I ) , UCF NET STRING=(LOC =U2 , IOSTANDARD = SSTL18 I ) , UCF NET STRING=(LOC =U4 , IOSTANDARD = SSTL18 I ) , UCF NET STRING=(LOC =U1 , IOSTANDARD = SSTL18 I ) , UCF NET STRING=(LOC =Y1 , IOSTANDARD = SSTL18 I ) , UCF NET STRING=(LOC = W1 , IOSTANDARD = SSTL18 I ) , UCF NET STRING=(LOC = W2 , IOSTANDARD = SSTL18 I ) , UCF NET STRING=(LOC =T3 , IOSTANDARD = SSTL18 I ) , UCF NET STRING=(LOC =V1 , IOSTANDARD = SSTL18 I ) , UCF NET STRING=(LOC =Y2 , IOSTANDARD = SSTL18 I ) # ## SPI ### PORT SEN SPI RX PORT SEN SPI TX PORT SEN SPI CLK PORT SEN SS 0 # FIXME PORT SEN SS 1 = CONN SEN SS 1 , UCF NET STRING = ( LOC = M22 , IOSTANDARD = LVTTL ) = CONN SEN SPI RX = CONN SEN SPI TX = CONN SEN SPI CLK = CONN SEN SS 0 , UCF NET STRING = ( LOC = M18 , IOSTANDARD = LVTTL ) , UCF NET STRING = ( LOC = L22 , IOSTANDARD = LVTTL ) , UCF NET STRING = ( LOC = K17 , IOSTANDARD = LVTTL ) , UCF NET STRING = ( LOC = T19 , IOSTANDARD = LVTTL )

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491 492 493 494 495 496 497 498 499

=R3 , IOSTANDARD = PORT DDR2 DDR BANKADDR1 = d d r 2 d d r b a n k a d d r 1 , UCF NET STRING=(LOC SSTL18 I ) PORT DDR2 DDR CASN PORT DDR2 DDR CKE PORT DDR2 DDR CSN PORT DDR2 DDR RASN PORT DDR2 DDR WEN PORT DDR2 DDR CLK DIFF SSTL18 I ) PORT DDR2 DDR CLKn DIFF SSTL18 I ) = ddr2 clk n , UCF NET STRING=(LOC =M2 , IOSTANDARD = = ddr2 ddr casn = ddr2 ddr cke = ddr2 ddr csn = ddr2 ddr rasn = ddr2 ddr wen = ddr2 clk , UCF NET STRING=(LOC =M4 , IOSTANDARD = SSTL18 I ) , UCF NET STRING=(LOC =N3 , IOSTANDARD = SSTL18 I ) , UCF NET STRING=(LOC =M5 , IOSTANDARD = SSTL18 I ) , UCF NET STRING=(LOC =M3 , IOSTANDARD = SSTL18 I ) , UCF NET STRING=(LOC =N4 , IOSTANDARD = SSTL18 I ) , UCF NET STRING=(LOC =M1 , IOSTANDARD =

500 501 502 503 504 PORT DDR2 DQS DIV I S S TL 18 II ) 505 506 507 508 PORT DDR2 DDR DQS0 D IFF S S TL 18 II ) PORT DDR2 DDR DQS1 D IFF S S TL 18 II ) 509 510 511 PORT DDR2 DDR DQSn0 D IFF S S TL 18 II ) PORT DDR2 DDR DQSn1 D IFF S S TL 18 II ) 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 PORT DDR2 DDR DQ0 PORT DDR2 DDR DQ1 PORT DDR2 DDR DQ2 PORT DDR2 DDR DQ3 PORT DDR2 DDR DQ4 PORT DDR2 DDR DQ5 PORT DDR2 DDR DQ6 PORT DDR2 DDR DQ7 PORT DDR2 DDR DQ8 PORT DDR2 DDR DQ9 PORT DDR2 DDR DQ10 PORT DDR2 DDR DQ11 PORT DDR2 DDR DQ12 PORT DDR2 DDR DQ13 PORT DDR2 DDR DQ14 PORT DDR2 DDR DQ15 END = = = = = = = = = = = = = = = = ddr2 ddr dq 0 ddr2 ddr dq 1 ddr2 ddr dq 2 ddr2 ddr dq 3 ddr2 ddr dq 4 ddr2 ddr dq 5 ddr2 ddr dq 6 ddr2 ddr dq 7 ddr2 ddr dq 8 ddr2 ddr dq 9 ddr2 ddr dq 10 ddr2 ddr dq 11 ddr2 ddr dq 12 ddr2 ddr dq 13 ddr2 ddr dq 14 ddr2 ddr dq 15 , UCF NET STRING=(LOC =H1 , IOSTANDARD = S S TL 18 II ) , UCF NET STRING=(LOC =K5 , IOSTANDARD = S S TL 18 II ) , UCF NET STRING=(LOC =K1 , IOSTANDARD = S S TL 18 II ) , UCF NET STRING=(LOC =L3 , IOSTANDARD = S S TL 18 II ) , UCF NET STRING=(LOC =L5 , IOSTANDARD = S S TL 18 II ) , UCF NET STRING=(LOC =L1 , IOSTANDARD = S S TL 18 II ) , UCF NET STRING=(LOC =K4 , IOSTANDARD = S S TL 18 II ) , UCF NET STRING=(LOC =H2 , IOSTANDARD = S S TL 18 II ) , UCF NET STRING=(LOC =F2 , IOSTANDARD = S S TL 18 II ) , UCF NET STRING=(LOC =G4 , IOSTANDARD = S S TL 18 II ) , UCF NET STRING=(LOC =G1 , IOSTANDARD = S S TL 18 II ) , UCF NET STRING=(LOC =H6 , IOSTANDARD = S S TL 18 II ) , UCF NET STRING=(LOC =H5 , IOSTANDARD = S S TL 18 II ) , UCF NET STRING=(LOC =F1 , IOSTANDARD = S S TL 18 II ) , UCF NET STRING=(LOC =G3 , IOSTANDARD = S S TL 18 II ) , UCF NET STRING=(LOC =F3 , IOSTANDARD = S S TL 18 II ) = ddr2 ddr dqsn 1 , UCF NET STRING=(LOC =J5 , IOSTANDARD = = ddr2 ddr dqsn 0 , UCF NET STRING=(LOC =K2 , IOSTANDARD = = ddr2 ddr dqs 1 , UCF NET STRING=(LOC =K6 , IOSTANDARD = = ddr2 ddr dqs 0 , UCF NET STRING=(LOC =K3 , IOSTANDARD = PORT DDR2 DQS DIV O S S TL 18 II ) = ddr2 ddr dqs div o , UCF NET STRING=(LOC =H3 , IOSTANDARD = = ddr2 ddr dqs div i , UCF NET STRING=(LOC =H4 , IOSTANDARD = PORT DDR2 DDR DM0 PORT DDR2 DDR DM1 = ddr2 ddr dm 0 = ddr2 ddr dm 1 , UCF NET STRING=(LOC =J3 , IOSTANDARD = SSTL18 I ) , UCF NET STRING=(LOC =E3 , IOSTANDARD = SSTL18 I )

171

Appendix C

USRP Test Benches

This appendix contains the test code for the CubeSat SDR system. Each test bench is called TB <module>.vhd, where <module> is the name of the entity under test. The code listed in this appendix is licensed under the GPL2. Listing C.1: TB TB acc.vhd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 e n t i t y TB acc i s end TB acc ; T e s t Bench L a s t for acc M o d i f i e d : 22 F e b r u a r y 2011 Steve Olivieri Institute redistribute it and / o r modify by

VHDL A u t h o r :

C o p y r i g h t (C) 2011 W o r c e s t e r P o l y t e c h n i c You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of This pr ogr am is distributed in the hope even This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can under Free your terms

t h e GNU G e n e r a l P u b l i c either

L ic e n s e as the

published or

S o f t w a r e Foundation ; o p t i o n ) any later

version 2 of

License ,

version . that the it will be useful , of

b u t WITHOUT ANY WARRANTY;

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. GNU G e n e r a l P u b l i c License f o r more details .

the

t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA

License USA

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC SIGNED . ALL ;

172

29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 C l e a r the accumulator . r e s e t <= 0 ; c l e a r <= 1 ; addend <= ( o the rs = > 0 ) ; A s s e r t the reset . r e s e t <= 1 ; wait f o r clock period ; S t i m u l u s stim proc begin Do n o t h i n g wait f o r for on e clock period . : Process pro c e ss C l o c k Process : pro c e ss C l o c k Period : t i m e := 10 n s ; constant c l o c k p e r i o d begin I n s t a n t i a t e UUT : acc reset = > reset , clear = > clear , enable in = > enable in , > e n a b l e o u t , addend = > addend , sum = > sum ) ; enable out = t h e UUT . O u t p u t s signal enable out s i g n a l sum : : std logic ; I n p u t s signal clock signal r e s e t signal c l e a r : : : s t d l o g i c := s t d l o g i c := s t d l o g i c := : 0 ; 0 ; 0 ; 0 ; ); end component a c c ; architecture b e h a v i o r a l component a c c port ( clock reset clear enable in enable out addend sum : : in : : : : out in : out in in in std logic ; std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 3 0 downto 0 ) ; s t d l o g i c v e c t o r ( 3 3 downto 0 ) o f TB acc i s for the U n i t Under T e s t (UUT) Component d e c l a r a t i o n is

signal e na ble in s i g n a l addend :

s t d l o g i c :=

s t d l o g i c v e c t o r ( 3 0 downto 0 ) := ( o the rs = > 0 ) ;

s t d l o g i c v e c t o r ( 3 3 downto 0 ) ;

port map ( c l o c k = > clock ,

clock process begin

c l o c k <= 0 ; wait f o r clock period / 2; clock period / 2; c l o c k <= 1 ; wait f o r

end pro c e ss c l o c k p r o c e s s ;

clock period ;

173

86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127

wait f o r

clock period ; values .

Add some

c l e a r <= 0 ; e n a b l e i n <= 1 ; for i i n 1 to 15 loop

addend <= c o n v s t d l o g i c v e c t o r ( i , addend LENGTH) ; wait f o r end loop ; C l e a r the accumulator . clock period ;

e n a b l e i n <= 0 ; c l e a r <= 1 ; addend <= ( o the rs = > 0 ) ; wait f o r clock period ; negative values .

Add some

c l e a r <= 0 ; e n a b l e i n <= 1 ; for i i n 1 downto 15 loop clock period ; addend <= c o n v s t d l o g i c v e c t o r ( i , addend LENGTH) ; wait f o r end loop ;

C l e a r

the

accumulator .

e n a b l e i n <= 0 ; c l e a r <= 1 ; addend <= ( o the rs = > 0 ) ; wait f o r clock period ;

T e s t

overflow .

c l e a r <= 0 ; e n a b l e i n <= 1 ; for i i n 0 to 8 loop addend <= 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ; wait f o r end loop ; End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ; clock period ;

Listing C.2: TB adc mux.vhd

1 2 3 4 5 6 7 8 9 10 11 T e s t Bench L a s t C o p y r i g h t (C) 2011 W o r c e s t e r P o l y t e c h n i c This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c later version . L ic e n s e as the published Institute for adc m u x Olivieri M o d i f i e d : 14 F e b r u a r y 2011 Steve

VHDL A u t h o r :

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

174

12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA This pr ogr am is distributed in the hope even that the it will be useful , of the b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License without implied warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; e n t i t y TB adc mux i s end TB adc mux ;

architecture b e h a v i o r a l component adc mux i s port ( clock

o f TB adc mux i s for the U n i t Under T e s t (UUT)

Component d e c l a r a t i o n

: : : : : : : in in in in in in

in

std logic ; std logic ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

rx realsignals ddc mux adc3 corr adc2 corr adc1 corr adc0 corr ddc i ddc q ); end component adc mux ; I n p u t s signal clock signal :

: out : out

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 )

s t d l o g i c := :

0 ; 0 ;

rx realsignals : : : :

s t d l o g i c :=

s i g n a l ddc mux : signal adc3 corr signal adc2 corr signal adc1 corr signal adc0 corr O u t p u t s signal ddc i signal ddc q : :

s t d l o g i c v e c t o r ( 3 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ;

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

C l o c k

Period : t i m e := 10 n s ;

constant c l o c k p e r i o d begin I n s t a n t i a t e UUT : adc mux

t h e UUT .

port map ( c l o c k = > clock ,

rx realsignals = > r x r e a l s i g n a l s , ddc mux = > ddc mux , adc2 corr = > adc2 corr , ddc i = > ddc i , adc1 corr = > adc1 corr , ddc q = > ddc q ) ;

> adc3 corr , adc3 corr = adc0 corr = > adc0 corr , C l o c k Process

175

69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103

clock process begin

pro c e ss

c l o c k <= 0 ; wait f o r clock period / 2; clock period / 2; c l o c k <= 1 ; wait f o r

end pro c e ss c l o c k p r o c e s s ; S t i m u l u s stim proc begin A s s i g n some values to the registers . : Process pro c e ss

a d c 0 c o r r <= 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ; a d c 1 c o r r <= 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ; a d c 2 c o r r <= 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ; a d c 3 c o r r <= 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ; Try e v e r y possible input for ddc m u x w i t h rx realsignals low .

r x r e a l s i g n a l s <= 0 ; for i i n 0 to 15 loop clock period ; ddc mux <= c o n v s t d l o g i c v e c t o r ( i , ddc mux LENGTH) ; wait f o r end loop ;

Try e v e r y i

possible

input

for

ddc m u x w i t h

rx realsignals

high .

r x r e a l s i g n a l s <= 1 ; for i n 0 to 15 loop clock period ; ddc mux <= c o n v s t d l o g i c v e c t o r ( i , ddc mux LENGTH) ; wait f o r end loop ; End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ;

Listing C.3: TB atr delay.vhd

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 T e s t Bench L a s t C o p y r i g h t (C) 2010 W o r c e s t e r P o l y t e c h n i c You s h o u l d have r e c e i v e d a copy of t h e GNU G e n e r a l P u b l i c License This pr ogr am is distributed in the hope even that the it will be useful , of the This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c later version . L ic e n s e as the published Institute for atr delay Olivieri M o d i f i e d : 14 F e b r u a r y 2011 Steve

VHDL A u t h o r :

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

176

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

along

with

this

pr ogr am ;

if

n ot ,

write

to

the

Free

Software 02110 1301 USA

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ;

entity TB atr del ay end T B a t r d e l a y ;

is

architecture b e h a v i o r a l component a t r d e l a y port ( clk i rst i ena i tx empty i tx delay i rx delay i atr tx o );

of TB atr delay for the

is

Component d e c l a r a t i o n is

U n i t Under T e s t (UUT)

: : : : : : in in in

in in in

std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ;

: out

std logic

end component a t r d e l a y ; I n p u t s signal signal clk i rst i : : : s t d l o g i c := s t d l o g i c := s t d l o g i c := : : : 0 ; 0 ; 0 ; 0 ;

signal e n a i

signal tx empty i signal signal tx delay i rx delay i

s t d l o g i c :=

s t d l o g i c v e c t o r ( 1 1 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) := ( o the rs = > 0 ) ;

O u t p u t s signal a t r t x o C l o c k constant begin I n s t a n t i a t e UUT : atr delay rst i = > rst i , ena i = > ena i , tx empty i = > tx empty i , atr tx o = > atr tx o ) ; > tx delay i , tx delay i = rx delay i = > rx delay i , t h e UUT . Period clk i period : t i m e := 10 n s ; : std logic ;

port map ( c l k i = > clk i ,

C l o c k

Process : pro c e ss

clk i process begin

c l k i <= 0 ; wait f o r clk i period / 2;

c l k i <= 1 ; wait f o r clk i period / 2; end pro c e ss c l k i p r o c e s s ; S t i m u l u s stim proc begin Do n o t h i n g wait f o r for on e clock period . : Process pro c e ss

clk i period ;

177

76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116

A s s e r t

the

reset .

r s t i <= 1 ; wait f o r clk i period ; the reset , assert the enable .

D e a s s e r t

r s t i <= 0 ; e n a i <= 1 ; D e l a y values o f 2 and 3.

t x d e l a y i <= 0 0 0 0 0 0 0 0 0 0 1 0 ; r x d e l a y i <= 0 0 0 0 0 0 0 0 0 0 1 1 ;

B e c a u s e We l l

tx empty i

is

low , we s h o u l d

switch

t o TX DELAY and t h e n TX.

stay

i n TX u n t i l we a s s e r t

tx empty i .

wait f o r 10 c l k i p e r i o d ; Now , assert tx empty i . in The a t r t x o signal should r em ain it high for

r x d e l a y

w h i l e we r e

t h e RX DELAY s t a t e

and t h e n

should

go l o w

when we r e a c h RX. t x e m p t y i <= 1 ; wait f o r 10 c l k i p e r i o d ; L et s c h a n g e get the back to t h e TX s t a t e values s o we can test the reset again . We l l

delay

t o 4 and 7 , a s

well .

t x e m p t y i <= 0 ; t x d e l a y i <= 0 0 0 0 0 0 0 0 0 1 0 0 ; r x d e l a y i <= 0 0 0 0 0 0 0 0 0 1 1 1 ; wait f o r 10 c l k i p e r i o d ;

A s s e r t

the

reset .

This

should

put us back

t o RX.

r s t i <= 1 ; wait f o r 10 c l k i p e r i o d ; D e l a y u n t i l TX a g a i n .

r s t i <= 0 ; wait f o r 10 c l k i p e r i o d ; End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ;

Listing C.4: TB bidir reg.vhd

1 2 3 4 5 6 7 8 9 10 11 12 T e s t Bench L a s t C o p y r i g h t (C) 2010 W o r c e s t e r P o l y t e c h n i c This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c later version . L ic e n s e as the published Institute for bidir reg Olivieri M o d i f i e d : 14 F e b r u a r y 2011 Steve

VHDL A u t h o r :

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

178

13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

This

pr ogr am

is

distributed

in

the

hope even

that the

it

will

be

useful , of the

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c You s h o u l d along with have this License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more of details .

r e c e i v e d a copy pr ogr am ; if n ot ,

t h e GNU G e n e r a l P u b l i c to the Free

License

write

Software 02110 1301 USA

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ;

entity T B b i d i r r e g end T B b i d i r r e g ;

is

architecture b e h a v i o r a l component b i d i r r e g port ( tristate oe reg val ); : in

of TB bi di r reg for the

is

Component d e c l a r a t i o n is

U n i t Under T e s t (UUT)

: :

inout in

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 )

end component b i d i r r e g ;

I n p u t s s i g n a l oe : s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ; : s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ; signal r e g v a l

B i d i r e c t i o n a l s signal begin I n s t a n t i a t e UUT : bidir reg oe = > oe , reg val = > reg val ) ; t h e UUT . tristate : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

port map ( t r i s t a t e = > tristate ,

S t i m u l u s stim proc begin :

Process pro c e ss

Do n o t h i n g wait f o r 10 n s ;

for

10 n s .

Keep

the

enables

off ,

but

change

the

input

values .

oe <= ( o the rs = > 0 ) ; r e g v a l <= 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 ; wait f o r 10 n s ;

Turn on

all

enables .

oe <= ( o the rs = > 1 ) ; wait f o r 10 n s ; Change some o f the inputs while leaving all e n a b l e s on .

r e g v a l <= 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ; wait f o r 10 n s ; Turn o f f some e n a b l e s , leave o t h e r s on .

oe <= 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 ;

179

70 71 72 73 74 75 76 77 78 79 80 81 82 83

wait f o r 10 n s ; Change some o f wait f o r 10 n s ; the inputs again .

r e g v a l <= 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ;

D i s a b l e

all

outputs .

oe <= ( o the rs = > 0 ) ; wait f o r 10 n s ; End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ;

Listing C.5: TB bustri.vhd

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 I n p u t s si g na l data : s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ; ); end component b u s t r i ; architecture b e h a v i o r a l component b u s t r i port ( data enabledt tridata : : : out in in s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; std logic ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) of TB bustri for the is U n i t Under T e s t (UUT) entity TB bustri end T B b u s t r i ; is T e s t Bench L a s t for bustri Olivieri M o d i f i e d : 13 F e b r u a r y 2011 Steve

VHDL A u t h o r :

C o p y r i g h t (C) 2010 W o r c e s t e r P o l y t e c h n i c You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of This pr ogr am is distributed in the hope even This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either

Institute redistribute it and / o r License , modify by or

under

terms

t h e GNU G e n e r a l P u b l i c

L ic e n s e as the

published

S o f t w a r e Foundation ; o p t i o n ) any later

version 2 of

version . that the it will be useful , of the

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA

License USA

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ;

Component d e c l a r a t i o n

180

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

signal enabledt O u t p u t s signal t r id a t a begin I n s t a n t i a t e UUT : bustri :

s t d l o g i c :=

0 ;

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

t h e UUT .

port map ( d a t a = > d at a , S t i m u l u s stim proc begin Do n o t h i n g wait f o r 10 n s ; S e t data , turn off for 10 n s . : Process pro c e ss

enabledt = > enabledt ,

tridata = > tridata ) ;

output .

d a t a <= 1 0 1 0 0 1 0 1 1 1 1 1 0 0 0 0 ; e n a b l e d t <= 0 ; wait f o r 10 n s ; Turn on o u t p u t . e n a b l e d t <= 1 ; wait f o r 10 n s ;

Change

data

with

output

still

enabled .

d a t a <= 0 0 0 0 1 1 1 1 0 1 0 1 1 0 1 0 ; wait f o r 10 n s ; D i s a b l e output .

e n a b l e d t <= 0 ; wait f o r 10 n s ; Change data with output disabled .

d a t a <= 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 ; wait f o r 10 n s ;

E n a b l e

output .

e n a b l e d t <= 1 ; wait f o r 10 n s ; End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ;

Listing C.6: TB cic decim.vhd

1 2 3 4 5 6 7 8 9 T e s t Bench L a s t for cic decim M o d i f i e d : 22 F e b r u a r y 2011 Steve Olivieri Institute redistribute it and / o r modify by

VHDL A u t h o r :

C o p y r i g h t (C) 2011 W o r c e s t e r P o l y t e c h n i c This it pr ogr am the is free of s o f t w a r e ; y ou can under terms

t h e GNU G e n e r a l P u b l i c

L ic e n s e as

published

181

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

the ( at This

Free your

S o f t w a r e Foundation ; o p t i o n ) any is later

either

version 2 of

the

License ,

or

version . in the hope even that the it will be useful , of the

pr ogr am

distributed

b u t WITHOUT ANY WARRANTY;

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. GNU G e n e r a l P u b l i c You s h o u l d along with Foundation , have this License f o r more of details .

r e c e i v e d a copy pr ogr am ; if n ot ,

t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA

License USA

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; entity TB cic decim end T B c i c d e c i m ; architecture b e h a v i o r a l component c i c d e c i m g e ne ri c ( bw N log2 of max rate maxbitgain ); : : : : i n t e g e r := 1 6 ; # o f bits for input rate of TB cic decim for the

is

is

Component d e c l a r a t i o n is

U n i t Under T e s t (UUT)

i n t e g e r := 4 ; # o f

filter

stages

i n t e g e r := 7 ; l o g 2

o f max s a m p l i n g

i n t e g e r := 28 N l o g 2 o f m a x r a t e

port ( clock reset enable rate strobe in strobe out signal in signal out ); end component c i c d e c i m ; : : : in in in : in : in : : in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 7 downto 0 ) ; std logic ; std logic ; s t d l o g i c v e c t o r ( bw1 downto 0 ) ; s t d l o g i c v e c t o r ( bw1 downto 0 )

: out

I n p u t s signal clock signal r e s e t signal enable signal rate : : : : s t d l o g i c := s t d l o g i c := s t d l o g i c := 0 ; 0 ; 0 ;

s t d l o g i c v e c t o r ( 7 downto 0 ) := ( o the rs = > 0 ) ; : : : s t d l o g i c := s t d l o g i c := 0 ; 0 ;

signal s t r o be i n signal s tro be o ut signal signal in

s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ;

O u t p u t s signal s ig n a l o u t C l o c k Period : t i m e := 10 n s ; : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

constant c l o c k p e r i o d begin

182

67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123

I n s t a n t i a t e UUT : cic decim

t h e UUT . reset = > reset , enable = > enable , rate = > rate ,

port map ( c l o c k = > clock ,

strobe in = > strobe in ,

strobe out = > strobe out ,

signal in = > signal in ,

signal out = > signal out ) ;

C l o c k

Process : pro c e ss

clock process begin

c l o c k <= 0 ; wait f o r clock period / 2; c l o c k <= 1 ; wait f o r clock period / 2;

end pro c e ss c l o c k p r o c e s s ; S t r o b e Process : pro c e ss

strobe proc begin

wait f o r 7 c l o c k p e r i o d ; s t r o b e o u t <= 1 ; wait f o r clock period ; s t r o b e o u t <= 0 ; end pro c e ss s t r o b e p r o c ;

We h a v e a s a m p l e on e v e r y s t r o b e i n <= 1 ; S t i m u l u s stim proc begin Do n o t h i n g wait f o r for on e : Process pro c e ss

clock ,

so

just

keep

strobe out

enabled .

clock

period .

clock period ; the reset .

A s s e r t

r e s e t <= 1 ; wait f o r clock period ; the filter .

E n a b l e

r e s e t <= 0 ; e n a b l e <= 1 ;

S e t

the

rate

to

7.

This

is

actually is

a rate

o f 32 b e c a u s e

of

the

c o d e c s

t h a t we u s e .

The f o r m u l a

( r a t e +1) 4 .

r a t e <= c o n v s t d l o g i c v e c t o r ( 7 , T e s t values of

r a t e LENGTH) ;

1 , max , min , and 1.

s i g n a l i n <= 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ; wait f o r 100 c l o c k p e r i o d ; s i g n a l i n <= 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ; wait f o r 100 c l o c k p e r i o d ; s i g n a l i n <= 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ; wait f o r 100 c l o c k p e r i o d ; s i g n a l i n <= 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ; wait f o r 100 c l o c k p e r i o d ; End t e s t . wait ;

183

124 125

end pro c e ss s t i m p r o c ; end b e h a v i o r a l ;

Listing C.7: TB cic dec shifter.vhd

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 O u t p u t s signal s ig n a l o u t begin : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; I n p u t s signal rate signal : s t d l o g i c v e c t o r ( 7 downto 0 ) := ( o the rs = > 0 ) ; : s t d l o g i c v e c t o r ( 4 3 downto 0 ) := ( o the rs = > 0 ) ; ); end component c i c d e c s h i f t e r ; port ( rate signal in signal out : in : in s t d l o g i c v e c t o r ( 7 downto 0 ) ; s t d l o g i c v e c t o r ( bw+m axb i t gai n 1 downto 0 ) ; s t d l o g i c v e c t o r ( bw1 downto 0 ) ); architecture b e h a v i o r a l of TB cic dec shifter for is the is Component d e c l a r a t i o n component c i c d e c s h i f t e r g e ne ri c ( bw maxbitgain : : i n t e g e r := 1 6 ; U n i t Under T e s t (UUT) entity T B c i c d e c s h i f t e r end T B c i c d e c s h i f t e r ; is T e s t Bench L a s t for cic dec shifter Olivieri M o d i f i e d : 22 F e b r u a r y 2011 Steve

VHDL A u t h o r :

C o p y r i g h t (C) 2011 W o r c e s t e r P o l y t e c h n i c You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of This pr ogr am is distributed in the hope even This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either

Institute redistribute it and / o r License , modify by or

under

terms

t h e GNU G e n e r a l P u b l i c

L ic e n s e as the

published

S o f t w a r e Foundation ; o p t i o n ) any later

version 2 of

version . that the it will be useful , of the

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA

License USA

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ;

i n t e g e r := 28

: out

signal in

184

52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

I n s t a n t i a t e UUT :

t h e UUT .

cic dec shifter signal in = > signal in , signal out = > signal out ) ;

g e ne ri c map( bw = > 16 , maxbitgain = > 28) port map ( r a t e = > rate , S t i m u l u s stim proc begin Do n o t h i n g wait f o r 10 n s ; S e t signal in to a constant value ( 0 x0123456789AB ) . for 10 n s . : Process pro c e ss

s i g n a l i n <= 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 ; i i n 4 to 127 loop r a t e LENGTH) ;

for

r a t e <= c o n v s t d l o g i c v e c t o r ( i , wait f o r 10 n s ; end loop ;

End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ;

Listing C.8: TB cic interp.vhd

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 T h i s test bench is inspired by the justinterp tb .v test included with the entity T B c i c i n t e r p end T B c i c i n t e r p ; is T e s t Bench L a s t C o p y r i g h t (C) 2011 W o r c e s t e r P o l y t e c h n i c You s h o u l d along with have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free License This pr ogr am is distributed in the hope even that the it will be useful , of the This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or Institute for cic interp Olivieri

M o d i f i e d : 21 F e b r u a r y 2011 Steve

VHDL A u t h o r :

under

terms

t h e GNU G e n e r a l P u b l i c later version .

L ic e n s e as the

published

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

write

Software 02110 1301 USA

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ;

185

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87

o r i g i n a l USRP s o u r c e c o d e . architecture b e h a v i o r a l component c i c i n t e r p g e ne ri c ( bw N log2 of max rate maxbitgain ); port ( clock reset enable rate strobe in strobe out signal in signal out ); end component c i c i n t e r p ; I n p u t s signal clock signal r e s e t signal enable signal rate : : : : s t d l o g i c := s t d l o g i c := s t d l o g i c := : : : 0 ; 0 ; 0 ; 0 ; 0 ; : : : in in in : in : in : : in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 7 downto 0 ) ; std logic ; std logic ; s t d l o g i c v e c t o r ( bw1 downto 0 ) ; s t d l o g i c v e c t o r ( bw1 downto 0 ) : : : : i n t e g e r := 1 6 ; # o f bits for input of TB ci c i nterp for the is Component d e c l a r a t i o n is U n i t Under T e s t (UUT)

i n t e g e r := 4 ; # o f

filter

stages rate

i n t e g e r := 7 ; l o g 2

o f max s a m p l i n g

i n t e g e r := 21 (N 1) l o g 2 o f m a x r a t e

: out

s t d l o g i c v e c t o r ( 7 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c := s t d l o g i c :=

signal s t r o be i n signal s tro be o ut signal signal in

s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ;

O u t p u t s signal s ig n a l o u t : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

C l o c k

Period : t i m e := 10 n s ;

constant c l o c k p e r i o d begin I n s t a n t i a t e UUT :

t h e UUT . reset = > reset , enable = > enable , rate = > rate ,

cic interp

port map ( c l o c k = > clock ,

strobe in = > strobe in ,

strobe out = > strobe out ,

signal in = > signal in ,

> signal out ) ; signal out = C l o c k Process : pro c e ss

clock process begin

c l o c k <= 0 ; wait f o r clock period / 2; clock period / 2; c l o c k <= 1 ; wait f o r end pro c e ss c l o c k p r o c e s s ;

S t r o b e

Process : pro c e ss

strobe proc begin

wait f o r 7 c l o c k p e r i o d ;

186

88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127

s t r o b e i n <= 1 ; wait f o r clock period ; s t r o b e i n <= 0 ; end pro c e ss s t r o b e p r o c ; We w an t a s a m p l e on e v e r y s t r o b e o u t <= 1 ; S t i m u l u s stim proc begin Do n o t h i n g wait f o r for on e clock period . : Process pro c e ss clock , so just keep strobe out enabled .

clock period ; the reset .

A s s e r t

r e s e t <= 1 ; wait f o r clock period ;

E n a b l e

the

filter .

r e s e t <= 0 ; e n a b l e <= 1 ; S e t the rate to 7. This is actually is a rate o f 32 b e c a u s e of the

c o d e c s

t h a t we u s e .

The f o r m u l a

( r a t e +1) 4 .

r a t e <= c o n v s t d l o g i c v e c t o r ( 7 , T e s t values of

r a t e LENGTH) ;

1 , max , min , and 1.

s i g n a l i n <= 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ; wait f o r 100 c l o c k p e r i o d ; s i g n a l i n <= 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ; wait f o r 100 c l o c k p e r i o d ; s i g n a l i n <= 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ; wait f o r 100 c l o c k p e r i o d ; s i g n a l i n <= 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ; wait f o r 100 c l o c k p e r i o d ;

End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ;

Listing C.9: TB cic int shifter.vhd

1 2 3 4 5 6 7 8 9 10 11 12 13 T e s t Bench L a s t C o p y r i g h t (C) 2011 W o r c e s t e r P o l y t e c h n i c This pr ogr am is distributed in the hope that it will be useful , This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or Institute for cic int shifter Olivieri

M o d i f i e d : 20 F e b r u a r y 2011 Steve

VHDL A u t h o r :

under

terms

t h e GNU G e n e r a l P u b l i c later version .

L ic e n s e as the

published

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

187

14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c You s h o u l d along with have this License

without

even

the

implied

warranty See

of

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more of details .

the

r e c e i v e d a copy pr ogr am ; if n ot ,

t h e GNU G e n e r a l P u b l i c to the Free

License

write

Software 02110 1301 USA

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ;

entity T B c i c i n t s h i f t e r end T B c i c i n t s h i f t e r ; architecture b e h a v i o r a l

is

of

TB cic int shifter for is the

is

Component d e c l a r a t i o n component c i c i n t s h i f t e r g e ne ri c ( bw maxbitgain ); : :

U n i t Under T e s t (UUT)

i n t e g e r := 1 6 ;

i n t e g e r := 21

port ( rate signal in signal out ); end component c i c i n t s h i f t e r ; I n p u t s signal rate signal : > 0 ) ; s t d l o g i c v e c t o r ( 7 downto 0 ) := ( o the rs = : s t d l o g i c v e c t o r ( 3 6 downto 0 ) := ( o the rs = > 0 ) ; signal in : in : : out in s t d l o g i c v e c t o r ( 7 downto 0 ) ; s t d l o g i c v e c t o r ( bw+m axb i t gai n 1 downto 0 ) ; s t d l o g i c v e c t o r ( bw1 downto 0 )

O u t p u t s signal s ig n a l o u t begin I n s t a n t i a t e UUT : t h e UUT . : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

cic int shifter

g e ne ri c map( bw = > 16 , maxbitgain = > 21) port map ( r a t e = > rate , S t i m u l u s stim proc begin Do n o t h i n g wait f o r 10 n s ; S e t signal in to a constant value (0 x0123456789 ) . for 10 n s . : Process pro c e ss signal in = > signal in , signal out = > signal out ) ;

s i g n a l i n <= 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 ;

T e s t e a c h for i

sample

rate .

The minimum

possible

value

is

4.

i n 4 to 127 loop r a t e LENGTH) ;

r a t e <= c o n v s t d l o g i c v e c t o r ( i , wait f o r 10 n s ; end loop ;

188

71 72 73 74 75 End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ;

Listing C.10: TB clk divider.vhd

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 C l o c k constant Period in clk period : t i m e := 10 n s ; O u t p u t s signal o u t c lk : std logic ; I n p u t s signal r e s e t signal in clk : signal r a t i o : : s t d l o g i c := s t d l o g i c := 0 ; 0 ; ); end component c l k d i v i d e r ; architecture b e h a v i o r a l of TB cl k di vi der for the is Component d e c l a r a t i o n component c l k d i v i d e r port ( reset in clk out clk ratio : in : : out : in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 7 downto 0 ) is U n i t Under T e s t (UUT) entity T B c l k d i v i d e r end T B c l k d i v i d e r ; is T e s t Bench L a s t C o p y r i g h t (C) 2010 W o r c e s t e r P o l y t e c h n i c You s h o u l d along with have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free License write Software 02110 1301 USA This pr ogr am is distributed in the hope even that the it will be useful , of This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or Institute for clk divider Olivieri

M o d i f i e d : 14 F e b r u a r y 2011 Steve

VHDL A u t h o r :

under

terms

t h e GNU G e n e r a l P u b l i c later version .

L ic e n s e as the

published

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

the

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ;

s t d l o g i c v e c t o r ( 7 downto 0 ) := ( o the rs = > 0 ) ;

189

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

begin I n s t a n t i a t e UUT : t h e UUT . in clk = > in clk , out clk = > out clk , ratio = > ratio ) ;

clk divider

port map ( r e s e t = > reset , C l o c k Process : pro c e ss

in clk process begin

i n c l k <= 0 ; wait f o r in clk period / 2; in clk period / 2; i n c l k <= 1 ; wait f o r

end pro c e ss i n c l k p r o c e s s ; S t i m u l u s stim proc begin Do n o t h i n g wait f o r for on e clock period . : Process pro c e ss

in clk period ; the reset .

A s s e r t

r e s e t <= 1 ; wait f o r in clk period ;

D e a s s e r t

the

reset .

Set

the

ratio

to

2.

r e s e t <= 0 ; r a t i o <= 00000010 ; wait f o r 8 i n c l k p e r i o d ;

A s s e r t

the

reset .

r e s e t <= 1 ; wait f o r 4 i n c l k p e r i o d ; New r a t i o r e s e t <= 0 ; r a t i o <= 00000011 ; wait f o r 12 i n c l k p e r i o d ; End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ; of 3.

Listing C.11: TB coe rom.vhd

1 2 3 4 5 6 7 8 9 10 11 T e s t Bench L a s t C o p y r i g h t (C) 2010 W o r c e s t e r P o l y t e c h n i c This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c later version . L ic e n s e as the published Institute for coeff rom Olivieri M o d i f i e d : 14 F e b r u a r y 2011 Steve

VHDL A u t h o r :

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

190

12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA This pr ogr am is distributed in the hope even that the it will be useful , of the b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License without implied warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ; entity TB coeff rom end T B c o e f f r o m ;

is

architecture b e h a v i o r a l component c o e f f r o m port ( clock ad d r data ); : : in in

of TB coeff rom for the

is

Component d e c l a r a t i o n is

U n i t Under T e s t (UUT)

std logic ; s t d l o g i c v e c t o r ( 2 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 )

: out

end component c o e f f r o m ; I n p u t s signal clock s i g n a l ad d r O u t p u t s si g na l data : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; : : s t d l o g i c := 0 ;

> 0 ) ; s t d l o g i c v e c t o r ( 2 downto 0 ) := ( o the rs =

C l o c k

Period : t i m e := 10 n s ;

constant c l o c k p e r i o d begin I n s t a n t i a t e UUT : coeff rom

t h e UUT . ad d r = > addr , data = > data ) ;

port map ( c l o c k = > clock ,

C l o c k

Process : pro c e ss

clock process begin

c l o c k <= 0 ; wait f o r clock period / 2;

c l o c k <= 1 ; wait f o r clock period / 2; end pro c e ss c l o c k p r o c e s s ; S t i m u l u s stim proc begin Do n o t h i n g wait f o r for on e clock period . : Process pro c e ss

clock period ;

191

69 70 71 72 73 74 75 76 77 78

T e s t e a c h for i

possible

address . addr LENGTH) ;

i n 0 to 7 loop clock period ;

ad d r <= c o n v s t d l o g i c v e c t o r ( i , wait f o r end loop ;

End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ;

Listing C.12: TB cordic.vhd

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 port ( clock reset enable xi yi : in : : in in : : in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; ); architecture b e h a v i o r a l of TB cordic for the is U n i t Under T e s t (UUT) Component d e c l a r a t i o n component c o r d i c g e ne ri c ( bitwidth zwidth : : i n t e g e r := 1 6 ; i n t e g e r := 16 is entity TB cordic end T B c o r d i c ; is T e s t Bench L a s t C o p y r i g h t (C) 2011 W o r c e s t e r P o l y t e c h n i c You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA write Software 02110 1301 This pr ogr am is distributed in the hope even that the it will be useful , of b u t WITHOUT ANY WARRANTY; without implied warranty See This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can redistribute it and / o r modify by Institute for cordic

M o d i f i e d : 23 F e b r u a r y 2011 Steve Olivieri

VHDL A u t h o r :

under Free your

terms

t h e GNU G e n e r a l P u b l i c either later version .

L ic e n s e as the

published or

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

License ,

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. GNU G e n e r a l P u b l i c License f o r more details .

the

I n c . , 51 F r a n k l i n

Street ,

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ;

192

44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 for C l o c k C l o c k );

xo yo zi zo

: out : out : in : out

s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( zwi d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( zwi d t h 1 downto 0 )

end component c o r d i c ;

I n p u t s signal clock signal r e s e t signal enable signal xi signal yi signal z i O u t p u t s s i g n a l xo : s i g n a l yo : s i g n a l zo : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; : : : : : : s t d l o g i c := s t d l o g i c := s t d l o g i c := 0 ; 0 ; 0 ;

s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ; > 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ;

Period : t i m e := 10 n s ;

constant c l o c k p e r i o d begin I n s t a n t i a t e UUT : cordic

t h e UUT .

g e ne ri c map( b i t w i d t h = > 16 , zwidth = > 16) port map ( c l o c k = > clock , reset = > reset , enable = > enable , zo = > zo ) ; xi = > xi , yi = > y i , xo = > xo , yo = > yo , zi = > zi ,

Process : pro c e ss

clock process begin

c l o c k <= 0 ; wait f o r clock period / 2; c l o c k <= 1 ; wait f o r clock period / 2;

end pro c e ss c l o c k p r o c e s s ; S t i m u l u s stim proc begin Do n o t h i n g wait f o r for on e clock period . : Process pro c e ss

clock period ; the reset .

A s s e r t

r e s e t <= 1 ; wait f o r clock period ;

E n a b l e

the

unit .

r e s e t <= 0 ; e n a b l e <= 1 ; wait f o r clock period ;

i n 0 to 255 loop

x i <= c o n v s t d l o g i c v e c t o r ( i mod 2 , x i LENGTH) ; y i <= c o n v s t d l o g i c v e c t o r ( 2 ( i mod 2 ) , y i LENGTH) ;

193

101 102 103 104 105 106 107 108 109

z i ( 1 3 downto 0 ) <= 0 1 1 1 1 1 1 1 1 1 1 1 1 1 ; z i ( 1 5 downto 1 4 ) <= c o n v s t d l o g i c v e c t o r ( i mod 4 , 2 ) ; wait f o r end loop ; End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ; clock period ;

Listing C.13: TB cordic stage.vhd

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 port ( clock reset enable xi yi : in : : in in : : in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; ); architecture b e h a v i o r a l of TB cordi c stage for the is Component d e c l a r a t i o n component c o r d i c s t a g e g e ne ri c ( bitwidth zwidth shift : : : i n t e g e r := 1 6 ; i n t e g e r := 1 i n t e g e r := 1 6 ; is U n i t Under T e s t (UUT) entity T B c o r d i c s t a g e end T B c o r d i c s t a g e ; is T e s t Bench L a s t for cordic stage M o d i f i e d : 23 F e b r u a r y 2011 Steve Olivieri Institute redistribute it and / o r modify by

VHDL A u t h o r :

C o p y r i g h t (C) 2011 W o r c e s t e r P o l y t e c h n i c You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of This pr ogr am is distributed in the hope even This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can under Free your terms

t h e GNU G e n e r a l P u b l i c either

L ic e n s e as the

published or

S o f t w a r e Foundation ; o p t i o n ) any later

version 2 of

License ,

version . that the it will be useful , of the

b u t WITHOUT ANY WARRANTY;

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. GNU G e n e r a l P u b l i c License f o r more details .

t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA

License USA

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ;

194

45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 C l o c k C l o c k );

zi const xo yo zo

: :

in in

s t d l o g i c v e c t o r ( zwi d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( zwi d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( b i t w i d t h 1 downto 0 ) ; s t d l o g i c v e c t o r ( zwi d t h 1 downto 0 )

: out : out : out

end component c o r d i c s t a g e ; I n p u t s signal clock signal r e s e t signal enable signal xi signal yi signal z i : : : : : : s t d l o g i c := s t d l o g i c := s t d l o g i c := 0 ; 0 ; 0 ;

> 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ; > 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = : s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ;

signal const O u t p u t s s i g n a l xo : s i g n a l yo : s i g n a l zo :

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

Period : t i m e := 10 n s ;

constant c l o c k p e r i o d begin I n s t a n t i a t e UUT :

t h e UUT . shift = > 3) enable = > enable , xi = > xi , zo = > zo ) ;

cordic stage reset = > reset ,

g e ne ri c map( b i t w i d t h = > 16 , zwidth = > 16 , port map ( c l o c k = > clock , yi = > yi , Process : pro c e ss zi = > zi ,

const = > c o n s t , xo = > xo , yo = > yo ,

clock process begin

c l o c k <= 0 ; wait f o r clock period / 2; clock period / 2;

c l o c k <= 1 ; wait f o r end pro c e ss c l o c k p r o c e s s ; S t i m u l u s stim proc begin Do n o t h i n g wait f o r for on e clock period . : Process pro c e ss

clock period ; the reset .

A s s e r t

r e s e t <= 1 ; wait f o r clock period ; the unit .

E n a b l e

r e s e t <= 0 ; e n a b l e <= 1 ; Use on e o f the constants fr om c o r d i c . vhd t o test .

c o n s t <= c o n v s t d l o g i c v e c t o r ( 1 2 9 7 , c o n s t LENGTH) ;

195

102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153

T e s t +x , +y , +z . x i <= c o n v s t d l o g i c v e c t o r ( 3 0 0 , x i LENGTH) ; y i <= c o n v s t d l o g i c v e c t o r ( 2 5 0 , y i LENGTH) ; z i <= c o n v s t d l o g i c v e c t o r ( 2 0 0 0 , wait f o r clock period ; z i LENGTH) ;

T e s t +x , +y , z . x i <= c o n v s t d l o g i c v e c t o r ( 3 0 0 , x i LENGTH) ; y i <= c o n v s t d l o g i c v e c t o r ( 2 5 0 , y i LENGTH) ; z i <= c o n v s t d l o g i c v e c t o r ( 2000 , z i LENGTH) ; wait f o r clock period ;

T e s t +x , y , +z . x i <= c o n v s t d l o g i c v e c t o r ( 3 0 0 , x i LENGTH) ; y i <= c o n v s t d l o g i c v e c t o r ( 250 , y i LENGTH) ; z i <= c o n v s t d l o g i c v e c t o r ( 2 0 0 0 , wait f o r clock period ; z i LENGTH) ;

T e s t +x , y , z . x i <= c o n v s t d l o g i c v e c t o r ( 3 0 0 , x i LENGTH) ; y i <= c o n v s t d l o g i c v e c t o r ( 250 , y i LENGTH) ; z i <= c o n v s t d l o g i c v e c t o r ( 2000 , z i LENGTH) ; wait f o r clock period ;

T e s t x , +y , +z . x i <= c o n v s t d l o g i c v e c t o r ( 300 , x i LENGTH) ; y i <= c o n v s t d l o g i c v e c t o r ( 2 5 0 , y i LENGTH) ; z i <= c o n v s t d l o g i c v e c t o r ( 2 0 0 0 , wait f o r clock period ; z i LENGTH) ;

T e s t x , +y , z . x i <= c o n v s t d l o g i c v e c t o r ( 300 , x i LENGTH) ; y i <= c o n v s t d l o g i c v e c t o r ( 2 5 0 , y i LENGTH) ; z i <= c o n v s t d l o g i c v e c t o r ( 2000 , z i LENGTH) ; wait f o r clock period ;

T e s t x , y , +z . x i <= c o n v s t d l o g i c v e c t o r ( 300 , x i LENGTH) ; y i <= c o n v s t d l o g i c v e c t o r ( 250 , y i LENGTH) ; z i <= c o n v s t d l o g i c v e c t o r ( 2 0 0 0 , wait f o r clock period ; z i LENGTH) ;

T e s t x , y , z . x i <= c o n v s t d l o g i c v e c t o r ( 300 , x i LENGTH) ; y i <= c o n v s t d l o g i c v e c t o r ( 250 , y i LENGTH) ; z i <= c o n v s t d l o g i c v e c t o r ( 2000 , z i LENGTH) ; wait f o r clock period ;

End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ;

Listing C.14: TB fo.vhd

1

196

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

T e s t Bench L a s t

for

fifo Olivieri Institute

M o d i f i e d : 19 F e b r u a r y 2011 Steve

VHDL A u t h o r :

C o p y r i g h t (C) 2010 W o r c e s t e r P o l y t e c h n i c You s h o u l d along with have this r e c e i v e d a copy pr ogr am ; if n ot , of This pr ogr am is distributed in the hope even This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either

redistribute

it

and / o r License ,

modify by or

under

terms

t h e GNU G e n e r a l P u b l i c later version . that the

L ic e n s e as the

published

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

it

will

be

useful , of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

the

t h e GNU G e n e r a l P u b l i c to the Free

License

write

Software 02110 1301 USA

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ;

entity T B f i f o end T B f i f o ;

is

architecture b e h a v i o r a l

of TB fi fo for

is U n i t Under T e s t (UUT)

Component d e c l a r a t i o n component f i f o g e ne ri c ( wi d t h d ep t h addr bits ); port ( data wr r eq rdreq rdclk wrclk aclr q rdfull : : : : : : : out in in in in in in : : : is

the

i n t e g e r := 1 6 ; i n t e g e r := 1 0 2 4 ;

i n t e g e r := 10

s t d l o g i c v e c t o r ( width 1 downto 0 ) ; std logic ; std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( width 1 downto 0 ) ; std logic ; std logic ; s t d l o g i c v e c t o r ( a d d r b i t s 1 downto 0 ) ; std logic ; std logic ; s t d l o g i c v e c t o r ( a d d r b i t s 1 downto 0 )

: out

rdempty : out rdusedw wrfull wrusedw ); end component f i f o ; I n p u t s si g na l data s i g n a l wr r eq : : : out : out : out

wrempty : out

s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c := 0 ;

197

59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115

signal rdreq signal rdclk si g na l wrclk signal a c l r O u t p u t s signal q : signal :

: : :

s t d l o g i c := s t d l o g i c := s t d l o g i c := s t d l o g i c :=

0 ; 0 ; 0 ; 0 ;

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; : : : std logic ; std logic ; s t d l o g i c v e c t o r ( 6 downto 0 ) ; std logic ; std logic ; s t d l o g i c v e c t o r ( 6 downto 0 ) ;

rdfull

s i g n a l rdempty : s i g n a l rdusedw signal w r f u ll

s i g n a l wrempty : s i g n a l wrusedw C l o c k Period :

constant r d c l k p e r i o d constant w r c l k p e r i o d begin I n s t a n t i a t e UUT : fifo

: :

t i m e := 10 n s ; t i m e := 10 n s ;

t h e UUT . addr bits = > 7) rdreq = > rdreq , rdclk = > rdclk , rdempty = > rdempty , rdfull = > rdfull ,

g e ne ri c map( wi d t h = > 1 6 , d ep t h = > 128 , port map ( d a t a = > d at a , wrclk = > wrclk , rdusedw = > rdusedw , wr r eq = > wr r eq ,

aclr = > aclr , q = > q,

wrfull = > w r f u l l , wrempty = > wrempty , wrusedw = > wrusedw ) ;

C l o c k

Process :

( rdclk ) pro c e ss

rdclk process begin

r d c l k <= 0 ; wait f o r rdclk period / 2; rdclk period / 2;

r d c l k <= 1 ; wait f o r end pro c e ss r d c l k p r o c e s s ; wrclk process begin w r c l k <= 0 ; wait f o r wrclk period / 2; wrclk period / 2; w r c l k <= 1 ; wait f o r end pro c e ss w r c l k p r o c e s s ; :

pro c e ss

S t i m u l u s stim proc begin :

Process pro c e ss

Do n o t h i n g wait f o r

for

on e

clock

period .

rdclk period ;

A s s e r t

the

reset .

a c l r <= 1 ; wait f o r rdclk period ; a c l r <= 0 ;

W r i t e a f e w wr r eq <= 1 ; wait f o r

items

into

t h e FIFO .

d a t a <= 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ; wrclk period ;

198

116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 W r i t e a f e w r d r e q <= 0 ; for i i n 0 to 3 loop 16) ; d a t a <= c o n v s t d l o g i c v e c t o r ( i , wr r eq <= 1 ; wait f o r wrclk period ; values back into t h e FIFO . Read b a c k wr r eq <= 0 ; for i i n 0 to 127 loop the e n t i r e FIFO . W r i t e on e extra value to t h e FIFO . What h a p p e n s ? d a t a <= 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ; wr r eq <= 1 ; wait f o r wrclk period ; Wait an e x t r a wr r eq <= 0 ; wait f o r rdclk period ; clock to examine t h e output signals . Now , completely fill t h e FIFO . a c l r <= 0 ; r d r e q <= 0 ; for i i n 0 to 127 loop 16) ; S en d a c l e a r a c l r <= 1 ; wait f o r rdclk period ; to t h e FIFO . What i f we r e a d extra ? Read b a c k fr om wr r eq <= 0 ; r d r e q <= 1 ; wait f o r 4 r d c l k p e r i o d ; t h e FIFO . d a t a <= 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ; wr r eq <= 1 ; wait f o r wrclk period ; d a t a <= 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 ; wr r eq <= 1 ; wait f o r wrclk period ; d a t a <= 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ; wr r eq <= 1 ; wait f o r wrclk period ;

r d r e q <= 1 ; wait f o r rdclk period ;

d a t a <= c o n v s t d l o g i c v e c t o r ( i , wr r eq <= 1 ; wait f o r end loop ; wrclk period ;

r d r e q <= 1 ; wait f o r end loop ; rdclk period ;

199

173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194

end loop ; Now , for i r e a d and write simultaneously for 10 clocks .

i n 0 to 9 loop

d a t a <= c o n v s t d l o g i c v e c t o r ( i + 1 0 , 1 6 ) ; wr r eq <= 1 ; r d r e q <= 1 ; wait f o r end loop ; S en d a c l e a r a c l r <= 1 ; wait f o r rdclk period ; we r e a d now ? signal . wrclk period ;

What i f

r d r e q <= 1 ; wait f o r 3 r d c l k p e r i o d ;

End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ;

Listing C.15: TB io pins.vhd

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 entity TB i o pi ns end T B i o p i n s ; is l i b r a r y WOR K; use WOR K.FPGA REGS COMMON. ALL ; T e s t Bench L a s t C o p y r i g h t (C) 2010 W o r c e s t e r P o l y t e c h n i c You s h o u l d along with have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free License write Software 02110 1301 USA This pr ogr am is distributed in the hope even that the it will be useful , of This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can redistribute it and / o r modify by Institute for io pins

M o d i f i e d : 14 F e b r u a r y 2011 Steve Olivieri

VHDL A u t h o r :

under Free your

terms

t h e GNU G e n e r a l P u b l i c either later version .

L ic e n s e as the

published or

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

License ,

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

the

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ;

200

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 C l o c k Process : pro c e ss C l o c k Period : t i m e := 10 n s ; B i d i r e c t i o n a l s signal i o 0 signal i o 1 signal i o 2 signal i o 3 : : : : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; I n p u t s signal reg 0 signal reg 1 signal reg 2 signal reg 3 signal clock signal signal signal signal signal : : : : : s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c := : : 0 ; 0 ; 0 ; s t d l o g i c := s t d l o g i c := : : ); end component i o p i n s ; architecture b e h a v i o r a l component i o p i n s port ( io 0 io 1 io 2 io 3 reg 0 reg 1 reg 2 reg 3 clock rx reset tx reset serial addr serial data serial strobe : : : in in in : : : : : : : : : : : inout inout inout inout in in in in in in in s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic of TB io pins for the is U n i t Under T e s t (UUT) Component d e c l a r a t i o n is

rx reset tx reset

serial addr serial data

s t d l o g i c v e c t o r ( 6 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) := ( o the rs = > 0 ) ; : s t d l o g i c := 0 ;

serial strobe

constant c l o c k p e r i o d begin I n s t a n t i a t e UUT : io pins

t h e UUT . io 1 = > io 1 , io 2 = > io 2 , reg 2 = > reg 2 , io 3 = > io 3 , reg 3 = > reg 3 ,

port map ( i o 0 = > io 0 , reg 0 = > reg 0 , clock = > clock ,

reg 1 = > reg 1 ,

> rx reset , rx reset =

tx reset = > tx reset ,

serial addr = > serial addr ,

serial data = > serial data ,

> serial strobe ) ; serial strobe =

clock process begin

c l o c k <= 0 ; wait f o r clock period / 2; c l o c k <= 1 ;

201

89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145

wait f o r

clock period / 2;

end pro c e ss c l o c k p r o c e s s ; S t i m u l u s stim proc begin Do n o t h i n g wait f o r for on e clock period . : Process pro c e ss

clock period ; initial values for the input registers .

S e t some

r e g 0 <= 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ; r e g 1 <= 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ; r e g 2 <= 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ; r e g 3 <= 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ; E n a b l e all all outputs for each register .

> 1 ) ; s e r i a l d a t a <= ( o the rs =

s e r i a l a d d r <= c o n v s t d l o g i c v e c t o r ( FR OE 0 , s e r i a l s t r o b e <= 1 ; wait f o r clock period ; clock period ; s e r i a l s t r o b e <= 0 ; wait f o r

s e r i a l a d d r LENGTH) ;

s e r i a l a d d r <= c o n v s t d l o g i c v e c t o r ( FR OE 1 , s e r i a l s t r o b e <= 1 ; wait f o r clock period ; clock period ; s e r i a l s t r o b e <= 0 ; wait f o r

s e r i a l a d d r LENGTH) ;

s e r i a l a d d r <= c o n v s t d l o g i c v e c t o r ( FR OE 2 , s e r i a l s t r o b e <= 1 ; wait f o r clock period ; clock period ; s e r i a l s t r o b e <= 0 ; wait f o r

s e r i a l a d d r LENGTH) ;

s e r i a l a d d r <= c o n v s t d l o g i c v e c t o r ( FR OE 3 , s e r i a l s t r o b e <= 1 ; wait f o r clock period ; clock period ; s e r i a l s t r o b e <= 0 ; wait f o r

s e r i a l a d d r LENGTH) ;

Change

the

values

of

each

register .

r e g 0 <= 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ; wait f o r clock period ;

r e g 1 <= 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ; wait f o r clock period ;

r e g 2 <= 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ; wait f o r clock period ;

r e g 3 <= 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ; wait f o r clock period ; the o u t p u t m asks for each register .

Change

s e r i a l d a t a <= 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ;

202

146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190

s e r i a l a d d r <= c o n v s t d l o g i c v e c t o r ( FR OE 0 , s e r i a l s t r o b e <= 1 ; wait f o r clock period ; clock period ; s e r i a l s t r o b e <= 0 ; wait f o r

s e r i a l a d d r LENGTH) ;

s e r i a l d a t a <= 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ; s e r i a l a d d r <= c o n v s t d l o g i c v e c t o r ( FR OE 1 , s e r i a l s t r o b e <= 1 ; wait f o r clock period ; clock period ; s e r i a l s t r o b e <= 0 ; wait f o r s e r i a l a d d r LENGTH) ;

s e r i a l d a t a <= 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ; s e r i a l a d d r <= c o n v s t d l o g i c v e c t o r ( FR OE 2 , s e r i a l s t r o b e <= 1 ; wait f o r clock period ; s e r i a l s t r o b e <= 0 ; wait f o r clock period ; s e r i a l a d d r LENGTH) ;

s e r i a l d a t a <= 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ; s e r i a l a d d r <= c o n v s t d l o g i c v e c t o r ( FR OE 3 , s e r i a l s t r o b e <= 1 ; wait f o r clock period ; s e r i a l a d d r LENGTH) ;

s e r i a l s t r o b e <= 0 ; wait f o r clock period ; reset signals are never used in io pins , b u t we l l test them

The t w o anyway .

t x r e s e t <= 1 ; wait f o r clock period ;

r x r e s e t <= 1 ; wait f o r clock period ;

t x r e s e t <= 0 ; wait f o r clock period ;

r x r e s e t <= 0 ; wait f o r clock period ;

End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ;

Listing C.16: TB mult.vhd

1 2 3 4 5 6 7 8 T e s t Bench L a s t C o p y r i g h t (C) 2010 W o r c e s t e r P o l y t e c h n i c This pr ogr am is free s o f t w a r e ; y ou can redistribute it and / o r modify Institute for mult

M o d i f i e d : 15 F e b r u a r y 2011 Steve Olivieri

VHDL A u t h o r :

203

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

it the ( at

under Free your

the

terms

of

t h e GNU G e n e r a l P u b l i c either later version . in the hope even that the

L ic e n s e as the

published or

by

S o f t w a r e Foundation ; o p t i o n ) any is

version 2 of

License ,

This

pr ogr am

distributed

it

will

be

useful , of

b u t WITHOUT ANY WARRANTY;

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. GNU G e n e r a l P u b l i c You s h o u l d along with Foundation , have this License f o r more of details .

the

r e c e i v e d a copy pr ogr am ; if n ot ,

t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA

License USA

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; e n t i t y TB mult i s end TB mult ;

architecture b e h a v i o r a l component mult i s port ( clock x y product enable in enable out ); end component mult ; I n p u t s signal clock signal x : signal y : :

o f TB mult i s for the U n i t Under T e s t (UUT)

Component d e c l a r a t i o n

: : : : out : in : out

in in in

std logic ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 3 0 downto 0 ) ; std logic ; std logic

s t d l o g i c :=

0 ;

s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ; > 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = : s t d l o g i c := 0 ;

signal e na ble in O u t p u t s si g na l product :

s t d l o g i c v e c t o r ( 3 0 downto 0 ) ; : std logic ;

signal enable out

C l o c k

Period : t i m e := 10 n s ;

constant c l o c k p e r i o d begin I n s t a n t i a t e UUT : mult

t h e UUT .

port map ( c l o c k = > clock , x = > x, y = > y, enable in = > enable in , C l o c k Process : pro c e ss

product = > p r od u ct ,

enable out = > enable out ) ;

clock process begin

c l o c k <= 0 ; wait f o r clock period / 2; clock period / 2; c l o c k <= 1 ; wait f o r

204

66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104

end pro c e ss c l o c k p r o c e s s ; S t i m u l u s stim proc begin Do n o t h i n g wait f o r for on e clock period . : Process pro c e ss

clock period ; multiplications .

E n a b l e

e n a b l e i n <= 1 ; M u l t i p l y two positive n u m ber s .

x <= 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 ; y <= 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 ; wait f o r clock period ; on e positive and on e n e g a t i v e number .

M u l t i p l y

x <= 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 ; y <= 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 ; wait f o r clock period ; two negative n u m ber s .

M u l t i p l y

x <= 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 ; y <= 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 ; wait f o r clock period ; by zero .

M u l t i p l y

x <= 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ; y <= 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 ; wait f o r clock period ; h a p p e n s when enable in is low .

E n s u r e n o t h i n g e n a b l e i n <= 0 ;

wait f o r 3 c l o c k p e r i o d ;

End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ;

Listing C.17: TB phase acc.vhd

1 2 3 4 5 6 7 8 9 10 11 12 13 14 T e s t Bench L a s t C o p y r i g h t (C) 2011 W o r c e s t e r P o l y t e c h n i c This pr ogr am is distributed in the hope even that the it will be useful , of b u t WITHOUT ANY WARRANTY; without implied warranty This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can redistribute it and / o r modify by Institute for phase acc

M o d i f i e d : 23 F e b r u a r y 2011 Steve Olivieri

VHDL A u t h o r :

under Free your

terms

t h e GNU G e n e r a l P u b l i c either later version .

L ic e n s e as the

published or

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

License ,

205

15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. GNU G e n e r a l P u b l i c You s h o u l d along with Foundation , have this License f o r more of details .

See

the

r e c e i v e d a copy pr ogr am ; if n ot ,

t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA

License USA

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ;

l i b r a r y WOR K; use WOR K. FPGA REGS STANDARD . ALL ; entity TB phase acc end T B p h a s e a c c ;

is

architecture b e h a v i o r a l component p h a s e a c c g e ne ri c ( FREQADDR PHASEADDR resolution ); port ( clk reset enable strobe serial addr serial data

of TB phase acc for the

is

Component d e c l a r a t i o n is

U n i t Under T e s t (UUT)

: : :

i n t e g e r := 0 ;

i n t e g e r := 0 ; i n t e g e r range 0 to 32 := 32

in : in

std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic ; : out s t d l o g i c v e c t o r ( r e s o l u t i o n 1 downto 0 )

: : : : :

in in in in in

serial strobe phase ); end component p h a s e a c c ; I n p u t s signal clk :

s t d l o g i c := : : :

0 ; 0 ; 0 ; 0 ;

signal r e s e t signal enable signal strobe signal signal signal

s t d l o g i c := s t d l o g i c := s t d l o g i c := : :

serial addr serial data

s t d l o g i c v e c t o r ( 6 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) := ( o the rs = > 0 ) ; : s t d l o g i c := 0 ;

serial strobe

O u t p u t s si g na l phase C l o c k : s t d l o g i c v e c t o r ( 3 1 downto 0 ) ;

Period : t i m e := 10 n s ;

constant c l k p e r i o d begin I n s t a n t i a t e UUT : phase acc

t h e UUT .

> FR RX PHASE 0 ) g e ne ri c map(FREQADDR = > FR RX FREQ 0 , PHASEADDR =

206

72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

port map ( c l k = > clk ,

reset = > reset ,

enable = > enable , phase = > phase ) ;

strobe = > strobe ,

serial addr = > serial addr ,

serial data = > serial data ,

> serial strobe , serial strobe = C l o c k Process : pro c e ss

clk process begin

c l k <= 0 ; wait f o r clk period / 2; clk period / 2; c l k <= 1 ; wait f o r end pro c e ss c l k p r o c e s s ;

S t r o b e We l l v a l u e

Process just will u s e a 1/4 be : strobe by rate the for testing purposes . In practice , this determined pro c e ss decimation rate .

strobe process begin

s t r o b e <= 0 ; wait f o r 3 c l k p e r i o d ; s t r o b e <= 1 ; wait f o r clk period ; end pro c e ss s t r o b e p r o c e s s ;

S t i m u l u s stim proc begin :

Process pro c e ss

Do n o t h i n g wait f o r

for

on e

clock

period .

clk period ;

A s s e r t

the

reset .

r e s e t <= 1 ; wait f o r clk period ; frequency to 45. s e r i a l a d d r LENGTH) ;

S e t

the

s e r i a l a d d r <= c o n v s t d l o g i c v e c t o r ( FR RX FREQ 0 , s e r i a l d a t a <= c o n v s t d l o g i c v e c t o r ( 4 5 , s e r i a l s t r o b e <= 1 ; wait f o r clk period ; the unit .

s e r i a l d a t a LENGTH) ;

E n a b l e

r e s e t <= 0 ; e n a b l e <= 1 ; s e r i a l s t r o b e <= 0 ; wait f o r 3 c l k p e r i o d ; S e t a new s t a r t i n g phase of 90. s e r i a l a d d r LENGTH) ;

s e r i a l a d d r <= c o n v s t d l o g i c v e c t o r ( FR RX PHASE 0 , s e r i a l d a t a <= c o n v s t d l o g i c v e c t o r ( 9 0 , s e r i a l s t r o b e <= 1 ; wait f o r clk period ;

s e r i a l d a t a LENGTH) ;

A c c u m u l a t e

for a while .

s e r i a l s t r o b e <= 0 ; wait f o r 10 c l k p e r i o d ; End t e s t .

207

129 130 131

wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ;

Listing C.18: TB ram16.vhd

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 O u t p u t s I n p u t s signal clock : s t d l o g i c := : : : : 0 ; 0 ; ); end component ram16 ; architecture b e h a v i o r a l component ram16 i s port ( clock write in wr addr wr data rd addr rd data : : : in in in : : in in std logic ; std logic ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) o f TB ram16 i s for the U n i t Under T e s t (UUT) Component d e c l a r a t i o n e n t i t y TB ram16 i s end TB ram16 ; T e s t Bench L a s t f o r ram16 M o d i f i e d : 14 F e b r u a r y 2011 Steve Olivieri Institute redistribute it and / o r modify by

VHDL A u t h o r :

C o p y r i g h t (C) 2010 W o r c e s t e r P o l y t e c h n i c You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of This pr ogr am is distributed in the hope even This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can under Free your terms

t h e GNU G e n e r a l P u b l i c either

L ic e n s e as the

published or

S o f t w a r e Foundation ; o p t i o n ) any later

version 2 of

License ,

version . that the it will be useful , of the

b u t WITHOUT ANY WARRANTY;

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. GNU G e n e r a l P u b l i c License f o r more details .

t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA

License USA

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ;

: out

signal w r i t e i n si g na l wr addr si g na l wr data signal rd addr

s t d l o g i c :=

s t d l o g i c v e c t o r ( 3 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 ) := ( o the rs = > 0 ) ;

208

51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102

signal rd data C l o c k Period

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

constant c l o c k p e r i o d begin I n s t a n t i a t e UUT : ram16

t i m e := 10 n s ;

t h e UUT .

port map ( c l o c k = > clock , wr data = > wr d at a , C l o c k Process : pro c e ss

write in = > write in , rd addr = > rd addr ,

wr addr = > wr ad d r ,

rd data = > rd data ) ;

clock process begin

c l o c k <= 0 ; wait f o r clock period / 2; clock period / 2; c l o c k <= 1 ; wait f o r end pro c e ss ;

S t i m u l u s stim proc begin :

Process pro c e ss

Do n o t h i n g wait f o r

for

on e

clock

period .

clock period ;

W r i t e t o i

all

16 memory l o c a t i o n s .

w r i t e i n <= 1 ; for i n 0 to 15 loop wr ad d r LENGTH) ; wr d at a LENGTH) ; w r a d d r <= c o n v s t d l o g i c v e c t o r ( i ,

w r d a t a <= c o n v s t d l o g i c v e c t o r ( 1 5 i , wait f o r end loop ; Now r e a d b a c k fr om e a c h memory l o c a t i o n . clock period ;

w r i t e i n <= 0 ; for i i n 0 to 15 loop r d a d d r LENGTH) ; clock period ;

r d a d d r <= c o n v s t d l o g i c v e c t o r ( i , wait f o r end loop ; Make s u r e t h a t we can t w r i t e when

write in

is

low .

w r a d d r <= 0100 ; w r d a t a <= 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ; wait f o r clock period ;

r d a d d r <= 0100 ; wait f o r clock period ;

End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ;

Listing C.19: TB ram16 2sum.vhd

1

209

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

T e s t Bench L a s t

for

ram16 2sum Olivieri Institute

M o d i f i e d : 14 F e b r u a r y 2011 Steve

VHDL A u t h o r :

C o p y r i g h t (C) 2010 W o r c e s t e r P o l y t e c h n i c You s h o u l d along with have this r e c e i v e d a copy pr ogr am ; if n ot , of This pr ogr am is distributed in the hope even This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either

redistribute

it

and / o r License ,

modify by or

under

terms

t h e GNU G e n e r a l P u b l i c later version . that the

L ic e n s e as the

published

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

it

will

be

useful , of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

the

t h e GNU G e n e r a l P u b l i c to the Free

License

write

Software 02110 1301 USA

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ;

e n t i t y TB ram16 2sum i s end TB ram16 2sum ; architecture b e h a v i o r a l o f TB ram16 2sum i s for the U n i t Under T e s t (UUT)

Component d e c l a r a t i o n component ram16 2sum i s port ( clock write in wr addr wr data rd addr1 rd addr2 sum ); end component ram16 2sum ; : : in in : : : out in in : : in in

std logic ; std logic ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 )

I n p u t s signal clock : s t d l o g i c := : : : : : 0 ; 0 ; signal w r i t e i n si g na l wr addr si g na l wr data signal rd addr1 signal rd addr2 O u t p u t s s i g n a l sum : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c :=

s t d l o g i c v e c t o r ( 3 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 3 downto 0 ) := ( o the rs = > 0 ) ;

C l o c k

Period : t i m e := 10 n s ;

constant c l o c k p e r i o d begin I n s t a n t i a t e

t h e UUT .

210

59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114

UUT : ram16 2sum port map ( c l o c k = > clock , > wr d at a , wr data = sum = > sum ) ; C l o c k Process : pro c e ss write in = > write in , rd addr1 = > rd addr1 , wr addr = > wr ad d r , rd addr2 = > rd addr2 ,

clock process begin

c l o c k <= 0 ; wait f o r clock period / 2; clock period / 2; c l o c k <= 1 ; wait f o r end pro c e ss ; S t i m u l u s stim proc begin Do n o t h i n g wait f o r for on e clock period . : Process pro c e ss

clock period ; all 16 memory l o c a t i o n s .

W r i t e t o i

w r i t e i n <= 1 ; for i n 0 to 15 loop wr ad d r LENGTH) ; w r a d d r <= c o n v s t d l o g i c v e c t o r ( i ,

w r d a t a <= c o n v s t d l o g i c v e c t o r ( c o n v i n t e g e r ( c o n v s i g n e d ( i + 7 , wr d at a LENGTH) ) , wr d at a LENGTH) ; wait f o r end loop ; clock period ;

Now r e a d i

b a c k fr om e a c h memory l o c a t i o n .

w r i t e i n <= 0 ; for i n 0 to 15 loop r d a d d r 1 LENGTH) ; r d a d d r 2 LENGTH) ; r d a d d r 1 <= c o n v s t d l o g i c v e c t o r ( i , clock period ;

r d a d d r 2 <= c o n v s t d l o g i c v e c t o r ( 1 5 i , wait f o r end loop ; Make s u r e t h a t we can t w r i t e when write in

is

low .

w r d a t a <= 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ; wait f o r 2 c l o c k p e r i o d ;

F i n a l l y ,

test

the

add 1

part .

w r i t e i n <= 1 ; w r a d d r <= 0010 ; w r d a t a <= 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 ; wait f o r clock period ;

w r a d d r <= 0001 ; w r d a t a <= 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ; wait f o r clock period ;

w r i t e i n <= 0 ; r d a d d r 1 <= 0010 ; r d a d d r 2 <= 0001 ; wait f o r 3 c l o c k p e r i o d ; End t e s t .

211

115 116 117

wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ;

Listing C.20: TB rssi.vhd

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 O u t p u t s signal rssi t : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; I n p u t s signal clock signal r e s e t signal enable s i g n a l ad c : : : : s t d l o g i c := s t d l o g i c := s t d l o g i c := 0 ; 0 ; 0 ; ); end component r s s i ; architecture b e h a v i o r a l component r s s i port ( clock reset enable ad c rssi over count : : in in : : in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) ; : out : out s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; of TB rssi for is U n i t Under T e s t (UUT) Component d e c l a r a t i o n is the entity TB rssi end T B r s s i ; is T e s t Bench L a s t for rssi M o d i f i e d : 26 F e b r u a r y 2011 Steve Olivieri Institute redistribute it and / o r modify by

VHDL A u t h o r :

C o p y r i g h t (C) 2011 W o r c e s t e r P o l y t e c h n i c You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of This pr ogr am is distributed in the hope even This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can under Free your terms

t h e GNU G e n e r a l P u b l i c either

L ic e n s e as the

published or

S o f t w a r e Foundation ; o p t i o n ) any later

version 2 of

License ,

version . that the it will be useful , of the

b u t WITHOUT ANY WARRANTY;

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. GNU G e n e r a l P u b l i c License f o r more details .

t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA

License USA

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ;

s t d l o g i c v e c t o r ( 1 5 downto 0 )

> 0 ) ; s t d l o g i c v e c t o r ( 1 1 downto 0 ) := ( o the rs =

212

51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107

signal over count C l o c k Period

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

constant c l o c k p e r i o d begin I n s t a n t i a t e UUT : rssi

t i m e := 10 n s ;

t h e UUT .

port map ( c l o c k = > clock , rssi = > rssi t , C l o c k Process : pro c e ss

reset = > reset ,

enable = > enable ,

ad c = > adc ,

over count = > over count ) ;

clock process begin

c l o c k <= 0 ; wait f o r clock period / 2; clock period / 2; c l o c k <= 1 ; wait f o r end pro c e ss c l o c k p r o c e s s ;

S t i m u l u s stim proc begin :

Process pro c e ss

Do n o t h i n g wait f o r

for

on e

clock

period .

clock period ;

A s s e r t

the

reset .

r e s e t <= 1 ; wait f o r clock period ;

E n a b l e

the

unit .

r e s e t <= 0 ; e n a b l e <= 1 ; wait f o r clock period ; values . T hese are signed .

T e s t some non e r r o r for i i n 0 to 19 loop

ad c <= c o n v s t d l o g i c v e c t o r ( i 2 0 0 , adc LENGTH) ; wait f o r clock period ; clock period ; ad c <= c o n v s t d l o g i c v e c t o r ( ( i 2 0 0 ) , adc LENGTH) ; wait f o r end loop ;

S i g n a l for i

overflows .

i n 0 to 3 loop clock period ;

ad c <= 0 1 1 1 1 1 1 1 1 1 1 1 ; wait f o r end loop ;

S i g n a l for i

underflows .

i n 0 to 3 loop clock period ;

ad c <= 1 1 1 1 1 1 1 1 1 1 1 1 ; wait f o r end loop ; T e s t the reset again .

r e s e t <= 1 ; wait f o r clock period ;

213

108 109 110 111 112 End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ;

Listing C.21: TB rx dcoset.vhd

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 port ( clock enable reset adc in adc out serial addr serial data serial strobe : : : : in : in : : out in in in in : in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic ); architecture b e h a v i o r a l of TB rx dcoffset for the is Component d e c l a r a t i o n component r x d c o f f s e t g e ne ri c ( MYADDR : i n t e g e r := 0 is U n i t Under T e s t (UUT) entity T B r x d c o f f s e t end T B r x d c o f f s e t ; is l i b r a r y WOR K; use WOR K.FPGA REGS COMMON. ALL ; T e s t Bench L a s t C o p y r i g h t (C) 2011 W o r c e s t e r P o l y t e c h n i c You s h o u l d along with have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free License write Software 02110 1301 USA This pr ogr am is distributed in the hope even that the it will be useful , of This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or Institute for rx dcoffset Olivieri

M o d i f i e d : 28 F e b r u a r y 2011 Steve

VHDL A u t h o r :

under

terms

t h e GNU G e n e r a l P u b l i c later version .

L ic e n s e as the

published

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

the

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC SIGNED . ALL ;

214

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105

); end component r x d c o f f s e t ; I n p u t s signal clock signal enable signal r e s e t signal adc in signal signal signal : : : : s t d l o g i c := s t d l o g i c := s t d l o g i c := : : 0 ; 0 ; 0 ;

s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 6 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) := ( o the rs = > 0 ) ; : s t d l o g i c := 0 ;

serial addr serial data

serial strobe

O u t p u t s signal adc out C l o c k Period : t i m e := 10 n s ; : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

constant c l o c k p e r i o d begin I n s t a n t i a t e UUT :

t h e UUT .

rx dcoffset enable = > enable , reset = > reset , > adc in , adc in =

g e ne ri c map(MYADDR = > FR ADC OFFSET 0 ) port map ( c l o c k = > clock , adc out = > adc out , serial addr = > serial addr , serial data = > serial data ,

> serial strobe ) ; serial strobe =

C l o c k

Process : pro c e ss

clock process begin

c l o c k <= 0 ; wait f o r clock period / 2; clock period / 2;

c l o c k <= 1 ; wait f o r end pro c e ss c l o c k p r o c e s s ; S t i m u l u s stim proc begin Do n o t h i n g wait f o r for on e clock period . : Process pro c e ss

clock period ; the reset .

A s s e r t

r e s e t <= 1 ; wait f o r clock period ; the unit .

E n a b l e

r e s e t <= 0 ; e n a b l e <= 1 ; wait f o r clock period ; serial bus . s e r i a l a d d r LENGTH) ;

S e t up t h e

s e r i a l a d d r <= c o n v s t d l o g i c v e c t o r ( FR ADC OFFSET 0 , s e r i a l d a t a <= 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ; s e r i a l s t r o b e <= 1 ; wait f o r clock period ;

Add some more s a m p l e s . s e r i a l s t r o b e <= 0 ;

215

106 107 108 109 110 111 112 113 114 115 116 117 118 119 120

for

i n 0 to 15 loop clock period ;

a d c i n <= 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ; wait f o r end loop ; Try a n e g a t i v e for i sample or two !

i n 0 to 3 loop clock period ;

a d c i n <= 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ; wait f o r end loop ; End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ;

Listing C.22: TB serial io.vhd

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 architecture b e h a v i o r a l component s e r i a l i o port ( master clk serial clock serial data in enable reset serial data out serial addr : out : : : : in in in in : : out in std logic ; std logic ; std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 6 downto 0 ) ; std logic ; of TB serial io for the is Component d e c l a r a t i o n is U n i t Under T e s t (UUT) entity T B s e r i a l i o end T B s e r i a l i o ; is T e s t Bench L a s t for serial io M o d i f i e d : 14 F e b r u a r y 2011 Steve Olivieri Institute redistribute it and / o r modify by

VHDL A u t h o r :

C o p y r i g h t (C) 2010 W o r c e s t e r P o l y t e c h n i c You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of This pr ogr am is distributed in the hope even This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can under Free your terms

t h e GNU G e n e r a l P u b l i c either

L ic e n s e as the

published or

S o f t w a r e Foundation ; o p t i o n ) any later

version 2 of

License ,

version . that the it will be useful , of the

b u t WITHOUT ANY WARRANTY;

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. GNU G e n e r a l P u b l i c License f o r more details .

t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA

License USA

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ;

216

39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 C l o c k );

serial data serial strobe readback 0 readback 1 readback 2 readback 3 readback 4 readback 5 readback 6 readback 7 end component s e r i a l i o ;

: out : out : : : : : : : : in in in in in in in in

s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; std logic ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 )

I n p u t s signal master clk signal signal : s t d l o g i c := : : 0 ; 0 ; 0 ; serial clock : : s t d l o g i c := 0 ; 0 ;

serial data in

s t d l o g i c :=

signal enable signal r e s e t

s t d l o g i c := s t d l o g i c := : : : : : : : :

signal readback 0 signal readback 1 signal readback 2 signal readback 3 signal readback 4 signal readback 5 signal readback 6 signal readback 7 O u t p u t s signal signal signal signal

s t d l o g i c v e c t o r ( 3 1 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) := ( o the rs = > 0 ) ;

serial data out serial addr serial data : :

std logic ;

s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; : std logic ;

serial strobe Periods

constant m a s t e r c l k p e r i o d constant

t i m e := 10 n s ; : t i m e := 10 n s ;

serial clock period for operation : : : : : : : :

C o n s t a n t s

instructions .

constant r e a d r e g 0 constant r e a d r e g 1 constant r e a d r e g 2 constant r e a d r e g 3 constant r e a d r e g 4 constant r e a d r e g 5 constant r e a d r e g 6 constant r e a d r e g 7 constant w r i t e 1 constant w r i t e 2 : :

s t d l o g i c v e c t o r ( 7 downto 0 ) := 10000001 ; s t d l o g i c v e c t o r ( 7 downto 0 ) := 10000010 ; s t d l o g i c v e c t o r ( 7 downto 0 ) := 10000011 ; s t d l o g i c v e c t o r ( 7 downto 0 ) := 10000100 ; s t d l o g i c v e c t o r ( 7 downto 0 ) := 10000101 ; s t d l o g i c v e c t o r ( 7 downto 0 ) := 10000110 ; s t d l o g i c v e c t o r ( 7 downto 0 ) := 10000111 ; s t d l o g i c v e c t o r ( 7 downto 0 ) := 10001000 ;

s t d l o g i c v e c t o r ( 3 9 downto 0 ) := s t d l o g i c v e c t o r ( 3 9 downto 0 ) :=

0000000011001100110011001100110011001100 ; 0000000000110011001100110011001100110011 ; begin I n s t a n t i a t e UUT : serial io serial clock = > serial clock , enable = > enable , reset = > reset , serial addr = > serial addr , serial data in = > serial data in , t h e UUT .

port map ( m a s t e r c l k = > master clk ,

> serial data out , serial data out =

217

94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 C l o c k C l o c k

> serial data , serial data = readback 0 = > readback 0 , > readback 2 , readback 2 = readback 4 = > readback 4 , readback 6 = > readback 6 ,

serial strobe = > serial strobe ,

readback 1 = > readback 1 , readback 3 = > readback 3 , readback 5 = > readback 5 , readback 7 = > readback 7 ) ;

Process

( master clk ) : pro c e ss

master clk process begin

m a s t e r c l k <= 0 ; wait f o r master clk period / 2; m a s t e r c l k <= 1 ; wait f o r master clk period / 2;

end pro c e ss m a s t e r c l k p r o c e s s ; Process ( serial clock ) : pro c e ss

serial clock process begin

s e r i a l c l o c k <= 0 ; wait f o r serial clock period serial clock period / 2; / 2; s e r i a l c l o c k <= 1 ; wait f o r end pro c e ss s e r i a l c l o c k p r o c e s s ;

S t i m u l u s stim proc begin :

Process pro c e ss

Do n o t h i n g wait f o r

for

on e

clock

period .

master clk period ;

S e t

values

for

the

readback

registers .

r e a d b a c k 0 <= 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ; r e a d b a c k 1 <= 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ; r e a d b a c k 2 <= 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ; r e a d b a c k 3 <= 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ; r e a d b a c k 4 <= 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ; r e a d b a c k 5 <= 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ; r e a d b a c k 6 <= 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 ; r e a d b a c k 7 <= 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 ; E n a b l e the reset .

r e s e t <= 1 ; wait f o r master clk period ; the reset .

D i s a b l e

r e s e t <= 0 ;

Each o p e r a t i o n r e a d b a c k i e n a b l e <= 1 ; for

is

40

cycles .

F i r s t , we

test

reading

of

all

eight

registers .

i n r e a d r e g 0 R A N G E loop

s e r i a l d a t a i n <= r e a d r e g 0 ( i ) ; wait f o r end loop ; master clk period ; serial clock period ;

wait f o r

e n a b l e <= 0 ;

218

151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207

wait f o r

master clk period ;

e n a b l e <= 1 ; i i n r e a d r e g 1 R A N G E loop serial clock period ;

for

s e r i a l d a t a i n <= r e a d r e g 1 ( i ) ; wait f o r end loop ; master clk period ; master clk period ;

wait f o r

e n a b l e <= 0 ; wait f o r e n a b l e <= 1 ;

for

i n r e a d r e g 2 R A N G E loop serial clock period ;

s e r i a l d a t a i n <= r e a d r e g 2 ( i ) ; wait f o r end loop ;

wait f o r

master clk period ; master clk period ;

e n a b l e <= 0 ; wait f o r e n a b l e <= 1 ; i A N G E loop i n r e a d r e g 3 R

for

s e r i a l d a t a i n <= r e a d r e g 3 ( i ) ; wait f o r end loop ; master clk period ; serial clock period ;

wait f o r

e n a b l e <= 0 ; wait f o r master clk period ; e n a b l e <= 1 ; i i n r e a d r e g 4 R A N G E loop

for

s e r i a l d a t a i n <= r e a d r e g 4 ( i ) ; wait f o r end loop ; master clk period ; master clk period ; serial clock period ;

wait f o r

e n a b l e <= 0 ; wait f o r

e n a b l e <= 1 ; i i n r e a d r e g 5 R A N G E loop serial clock period ;

for

s e r i a l d a t a i n <= r e a d r e g 5 ( i ) ; wait f o r end loop ;

wait f o r

master clk period ; master clk period ;

e n a b l e <= 0 ; wait f o r e n a b l e <= 1 ;

for

A N G E loop i n r e a d r e g 6 R serial clock period ;

s e r i a l d a t a i n <= r e a d r e g 6 ( i ) ; wait f o r end loop ;

219

208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ; E n a b l e the reset . r e s e t <= 1 ; wait f o r master clk period ; D i s a b l e the m odu le while altering serial in . e n a b l e <= 0 ; s e r i a l d a t a i n <= 1 ; wait f o r serial clock period ; s e r i a l d a t a i n <= 0 ; wait f o r serial clock period ; serial clock period ; wait f o r master clk period ; master clk period ; e n a b l e <= 0 ; wait f o r for i i n w r i t e 2 R A N G E loop s e r i a l d a t a i n <= w r i t e 2 ( i ) ; wait f o r end loop ; serial clock period ; wait f o r master clk period ; e n a b l e <= 0 ; wait f o r master clk period ; Now , for i p e r fo r m two write tests . i n w r i t e 1 R A N G E loop wait f o r master clk period ; for i i n r e a d r e g 7 R A N G E loop serial clock period ; wait f o r master clk period ; master clk period ; e n a b l e <= 0 ; wait f o r e n a b l e <= 1 ;

s e r i a l d a t a i n <= r e a d r e g 7 ( i ) ; wait f o r end loop ;

e n a b l e <= 0 ; wait f o r master clk period ; e n a b l e <= 1 ;

s e r i a l d a t a i n <= w r i t e 1 ( i ) ; wait f o r end loop ; serial clock period ;

e n a b l e <= 1 ;

s e r i a l d a t a i n <= 1 ; wait f o r

Listing C.23: TB setting reg.vhd

220

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

T e s t Bench L a s t C o p y r i g h t (C) 2010 W o r c e s t e r P o l y t e c h n i c You s h o u l d along with have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free License This pr ogr am is distributed in the hope even that the it will be useful , of the This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or under terms t h e GNU G e n e r a l P u b l i c later version . L ic e n s e as the published Institute for setting reg Olivieri M o d i f i e d : 13 F e b r u a r y 2011 Steve

VHDL A u t h o r :

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

write

Software 02110 1301 USA

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ;

entity T B s e t t i n g r e g end T B s e t t i n g r e g ;

is

architecture b e h a v i o r a l

of TB setti ng reg for the

is

Component d e c l a r a t i o n component s e t t i n g r e g g e ne ri c ( my addr : ); port ( clock reset strobe ad d r d in d out ch an ged ); : in : : in in : : in in is

U n i t Under T e s t (UUT)

i n t e g e r := 0

std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 6 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ;

: out : out

std logic

end component s e t t i n g r e g ; I n p u t s signal clock signal r e s e t signal strobe s i g n a l ad d r signal d in : : : : : s t d l o g i c := s t d l o g i c := s t d l o g i c := 0 ; 0 ; 0 ;

> 0 ) ; s t d l o g i c v e c t o r ( 6 downto 0 ) := ( o the rs = s t d l o g i c v e c t o r ( 3 1 downto 0 ) := ( o the rs = > 0 ) ;

O u t p u t s si g na l d out1 si g na l d out2 si g na l d out3 : : : s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; : std logic ;

s i g n a l ch an ged 1

221

58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114

s i g n a l ch an ged 2 s i g n a l ch an ged 3 C l o c k period

: :

std logic ; std logic ;

constant c l o c k p e r i o d begin I n s t a n t i a t e UUT1 :

t i m e := 10 n s ;

t h e UUTs .

setting reg reset = > reset , strobe = > strobe , ad d r = > addr ,

g e ne ri c map( my addr = > 1) port map ( c l o c k = > clock , d in = > d in , d out = > d out1 , ch an ged = > ch an ged 1 ) ;

UUT2 :

setting reg reset = > reset , strobe = > strobe , ad d r = > addr ,

g e ne ri c map( my addr = > 2) port map ( c l o c k = > clock , > d in , d in = UUT3 : setting reg d out = > d out2 , ch an ged = > ch an ged 2 ) ;

> 3) g e ne ri c map( my addr = port map ( c l o c k = > clock , d in = > d in , C l o c k Process : pro c e ss reset = > reset , strobe = > strobe , ad d r = > addr , d out = > d out3 , ch an ged = > ch an ged 3 ) ;

clock process begin

c l o c k <= 0 ; wait f o r clock period / 2; clock period / 2; c l o c k <= 1 ; wait f o r

end pro c e ss c l o c k p r o c e s s ; S t i m u l u s stim proc begin Do n o t h i n g wait f o r for on e clock . : Process pro c e ss

clock period ; reset . clock period ;

E n a b l e

r e s e t <= 1 ; wait f o r

Change

values

while

reset

is

asserted .

ad d r <= 0000001 ; d i n <= 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 1 0 0 1 0 1 1 0 ; s t r o b e <= 1 ; wait f o r clock period ;

D i s a b l e

reset .

r e s e t <= 0 ; s t r o b e <= 0 ; wait f o r clock period ;

A s s e r t

the

strobe .

s t r o b e <= 1 ; wait f o r clock period ; the strobe .

D e a s s e r t

222

115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153

s t r o b e <= 0 ; wait f o r clock period ; sequential writes to different registers .

Try t h r e e

ad d r <= 0000001 ; d i n <= 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ; s t r o b e <= 1 ; wait f o r clock period ;

ad d r <= 0000010 ; d i n <= 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ; s t r o b e <= 1 ; wait f o r clock period ;

ad d r <= 0000011 ; d i n <= 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ; s t r o b e <= 1 ; wait f o r clock period ;

Try t o

write

to a

register

that

does

not

exist .

ad d r <= 0000100 ; d i n <= 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ; s t r o b e <= 1 ; wait f o r clock period ;

V a l i d

p a r a m e t e r s , no s t r o b e .

ad d r <= 0000001 ; d i n <= 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ; s t r o b e <= 0 ; wait f o r clock period ; the reset .

E n a b l e

r e s e t <= 1 ; wait f o r clock period ;

End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ;

Listing C.24: TB sign extend.vhd

1 2 3 4 5 6 7 8 9 10 11 12 13 14 T e s t Bench L a s t C o p y r i g h t (C) 2010 W o r c e s t e r P o l y t e c h n i c This pr ogr am is distributed in the hope even that the it will be useful , of b u t WITHOUT ANY WARRANTY; without implied warranty This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can redistribute it and / o r modify by Institute for sign extend

M o d i f i e d : 14 F e b r u a r y 2011 Steve Olivieri

VHDL A u t h o r :

under Free your

terms

t h e GNU G e n e r a l P u b l i c either later version .

L ic e n s e as the

published or

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

License ,

223

15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. GNU G e n e r a l P u b l i c You s h o u l d along with Foundation , have this License f o r more of details .

See

the

r e c e i v e d a copy pr ogr am ; if n ot ,

t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA

License USA

write

Software 02110 1301

I n c . , 51 F r a n k l i n

Street ,

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ;

entity TB si gn extend i s end T B s i g n e x t e n d ; architecture b e h a v i o r a l of TB sign extend i s for the U n i t Under T e s t (UUT)

Component d e c l a r a t i o n component s i g n e x t e n d g e ne ri c ( bits in bits out ); port ( d in d out ); : in : is

i n t e g e r := 0 ; : i n t e g e r := 0

s t d l o g i c v e c t o r ( b i t s i n 1 downto 0 ) ; s t d l o g i c v e c t o r ( b i t s o u t 1 downto 0 )

: out

end component s i g n e x t e n d ;

Bus w i d t h s constant b i n 1 constant b ou t 1 constant b i n 2 constant b ou t 2

for : : : :

t h e UUTs . i n t e g e r := 6 ;

i n t e g e r := 4 ;

i n t e g e r := 2 ; i n t e g e r := 5 ;

constant b i n 3 constant b ou t 3 I n p u t s signal d in1 signal d in2 signal d in3 O u t p u t s si g na l d out1 si g na l d out2 si g na l d out3 begin I n s t a n t i a t e UUT1 : : : :

: :

i n t e g e r := 4 ; i n t e g e r := 4 ;

s t d l o g i c v e c t o r ( b i n 1 1 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( b i n 2 1 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( b i n 3 1 downto 0 ) := ( o the rs = > 0 ) ;

: : :

s t d l o g i c v e c t o r ( bout1 1 downto 0 ) ; s t d l o g i c v e c t o r ( bout2 1 downto 0 ) ; s t d l o g i c v e c t o r ( bout3 1 downto 0 ) ; t h e UUTs . bits out = > b ou t 1 )

sign extend

> bin1 , g e ne ri c map( b i t s i n = port map ( d i n = > d in1 , UUT2 : sign extend

d out = > d out1 ) ;

g e ne ri c map( b i t s i n = > bin2 , > d in2 , port map ( d i n =

bits out = > b ou t 2 )

d out = > d out2 ) ;

224

72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ; S e t for i all possible input values . S t i m u l u s stim proc begin Do n o t h i n g wait f o r 10 n s ; for 10 n s . : Process pro c e ss UUT3 : sign extend bits out = > b ou t 3 ) d out = > d out3 ) ; > bin3 , g e ne ri c map( b i t s i n = port map ( d i n = > d in3 ,

i n 0 to 15 loop d i n 1 LENGTH) ; d i n 2 LENGTH) ; d i n 3 LENGTH) ;

d i n 1 <= c o n v s t d l o g i c v e c t o r ( i , d i n 2 <= c o n v s t d l o g i c v e c t o r ( i , d i n 3 <= c o n v s t d l o g i c v e c t o r ( i , wait f o r 10 n s ; end loop ;

Listing C.25: TB strobe gen.vhd

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 architecture b e h a v i o r a l component s t r o b e g e n of TB strobe gen for the is Component d e c l a r a t i o n is U n i t Under T e s t (UUT) entity TB strobe gen end T B s t r o b e g e n ; is T e s t Bench L a s t C o p y r i g h t (C) 2010 W o r c e s t e r P o l y t e c h n i c You s h o u l d along with have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free License This pr ogr am is distributed in the hope even that the it will be useful , of the This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either redistribute it and / o r License , modify by or Institute for strobe gen Olivieri

M o d i f i e d : 14 F e b r u a r y 2011 Steve

VHDL A u t h o r :

under

terms

t h e GNU G e n e r a l P u b l i c later version .

L ic e n s e as the

published

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

write

Software 02110 1301 USA

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ;

225

31 32 33 34 35

port ( clock reset enable rate ratio : in : in : : in in std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 7 downto 0 ) ; 1 less than desired divide

36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 C l o c k C l o c k );

strobe in strobe

in

std logic ; std logic

: out

end component s t r o b e g e n ; I n p u t s signal clock signal r e s e t signal enable signal rate : : : : s t d l o g i c := s t d l o g i c := s t d l o g i c := : 0 ; 0 ; 0 ; 0 ;

s t d l o g i c v e c t o r ( 7 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c :=

signal s t r o be i n

O u t p u t s signal strobe : std logic ;

Period : t i m e := 10 n s ;

constant c l o c k p e r i o d begin I n s t a n t i t a t e UUT : strobe gen

t h e UUT . reset = > reset , enable = > enable , rate = > rate ,

port map ( c l o c k = > clock ,

strobe in = > strobe in ,

strobe = > strobe ) ;

Process : pro c e ss

clock process begin

c l o c k <= 0 ; wait f o r clock period / 2; c l o c k <= 1 ; wait f o r clock period / 2;

end pro c e ss c l o c k p r o c e s s ; S t i m u l u s stim proc begin Do n o t h i n g wait f o r for on e clock period . : Process pro c e ss

clock period ; the reset .

A s s e r t

r e s e t <= 1 ; wait f o r clock period ;

S e t

the

rate

to

16.

r a t e <= 00010000 ; D e a s s e r t the reset , assert the enable .

r e s e t <= 0 ; e n a b l e <= 1 ; wait f o r clock period ; as strobe in is not asserted , nothing will happen .

As l o n g

226

87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119

T e s t

this

by

w a i t i n g 16

clocks .

wait f o r 16 c l o c k p e r i o d ; Now , assert strobe in . We l l just might leave it t h a t way f o r periods of easier

t e s t i n g , s t r o b e i n

b u t n or m al

operation

include

time between

assertions .

s t r o b e i n <= 1 ; wait f o r 16 c l o c k p e r i o d ; Do i t again .

wait f o r 16 c l o c k p e r i o d ;

D i s a b l e . e n a b l e <= 0 ; wait f o r clock period ; assert enable . Wait f o r eight strobes .

S e t a new r a t e , r a t e <= 00000010 ; e n a b l e <= 1 ;

wait f o r 16 c l o c k p e r i o d ; A s s e r t the reset without disabling .

r e s e t <= 1 ; wait f o r clock period ;

D e a s s e r t

the

reset

to

continue

operation .

r e s e t <= 0 ; wait f o r 4 c l o c k p e r i o d ;

End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ;

Listing C.26: TB tx chain.vhd

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 T e s t Bench L a s t C o p y r i g h t (C) 2011 W o r c e s t e r P o l y t e c h n i c You s h o u l d along with Foundation , have this r e c e i v e d a copy pr ogr am ; if n ot , of t h e GNU G e n e r a l P u b l i c to the Free B ost on , MA License USA write Software 02110 1301 This pr ogr am is distributed in the hope even that the it will be useful , of b u t WITHOUT ANY WARRANTY; without implied warranty See This it the ( at pr ogr am the is free of s o f t w a r e ; y ou can redistribute it and / o r modify by Institute for tx chain

M o d i f i e d : 22 F e b r u a r y 2011 Steve Olivieri

VHDL A u t h o r :

under Free your

terms

t h e GNU G e n e r a l P u b l i c either later version .

L ic e n s e as the

published or

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

License ,

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. GNU G e n e r a l P u b l i c License f o r more details .

the

I n c . , 51 F r a n k l i n

Street ,

227

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ;

entity TB tx chain end T B t x c h a i n ;

is

architecture b e h a v i o r a l component t x c h a i n port ( clock reset enable interp rate

of TB tx chain for the

is

Component d e c l a r a t i o n is

U n i t Under T e s t (UUT)

: : : : : : in in in in

in in

std logic ; std logic ; std logic ; s t d l o g i c v e c t o r ( 7 downto 0 ) ; std logic ;

sample strobe interpolator strobe freq i in q in i out q out ); end component t x c h a i n ; I n p u t s signal clock signal r e s e t signal enable : : : s t d l o g i c := s t d l o g i c := s t d l o g i c := : : 0 ; 0 ;

std logic ; : : : in in in s t d l o g i c v e c t o r ( 3 1 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 )

: out : out

0 ; 0 ; 0 ;

signal i n t e r p r a t e

s t d l o g i c v e c t o r ( 7 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c := : s t d l o g i c :=

signal sample strobe signal fr e q signal i in : : :

signal i n t e r p o l a t o r s t r o b e

s t d l o g i c v e c t o r ( 3 1 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ;

signal q in O u t p u t s signal i o u t signal q out

: :

s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

C l o c k

Period : t i m e := 10 n s ;

constant c l o c k p e r i o d begin I n s t a n t i a t e UUT : tx chain

t h e UUT .

port map ( c l o c k = > clock ,

reset = > reset ,

enable = > enable , freq = > freq , q out = > q out ) ;

interp rate = > interp rate , i in = > i in , q in = > q in ,

sample strobe = > sample strobe , i out = > i out ,

> interpolator strobe , interpolator strobe =

C l o c k

Process : pro c e ss

clock process begin

c l o c k <= 0 ; wait f o r clock period / 2;

228

78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129

c l o c k <= 1 ; wait f o r clock period / 2; end pro c e ss c l o c k p r o c e s s ; S t r o b e Process : pro c e ss

strobe proc begin

wait f o r 7 c l o c k p e r i o d ; i n t e r p o l a t o r s t r o b e <= 1 ; wait f o r clock period ; i n t e r p o l a t o r s t r o b e <= 0 ; end pro c e ss s t r o b e p r o c ;

We w an t a s a m p l e on e v e r y s a m p l e s t r o b e <= 1 ; S t i m u l u s stim proc begin Do n o t h i n g wait f o r for on e : Process pro c e ss

clock ,

so

just

keep

sample strobe

enabled .

clock

cycle .

clock period ; the reset .

A s s e r t

r e s e t <= 1 ; wait f o r clock period ; the filter .

E n a b l e

r e s e t <= 0 ; e n a b l e <= 1 ;

S e t

the

rate

to

7.

This

is

actually is

a rate

o f 32 b e c a u s e

of

the

c o d e c s

t h a t we u s e .

The f o r m u l a

( r a t e +1) 4 . i n t e r p r a t e LENGTH) ; Q will go in reverse .

i n t e r p r a t e <= c o n v s t d l o g i c v e c t o r ( 7 , T e s t values of 1 , max , min , and 1.

i i n <= 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ; q i n <= 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ; wait f o r 100 c l o c k p e r i o d ; i i n <= 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ; q i n <= 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ; wait f o r 100 c l o c k p e r i o d ; i i n <= 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ; q i n <= 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ; wait f o r 100 c l o c k p e r i o d ; i i n <= 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ; q i n <= 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ; wait f o r 100 c l o c k p e r i o d ;

End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ;

Listing C.27: TB usrp mux.vhd

1

229

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

T e s t Bench L a s t

for

usrp mux Olivieri Institute

M o d i f i e d : 14 F e b r u a r y 2011 Steve

VHDL A u t h o r :

C o p y r i g h t (C) 2010 W o r c e s t e r P o l y t e c h n i c You s h o u l d along with have this r e c e i v e d a copy pr ogr am ; if n ot , of This pr ogr am is distributed in the hope even This it the ( at pr ogr am the Free your is free of s o f t w a r e ; y ou can either

redistribute

it

and / o r License ,

modify by or

under

terms

t h e GNU G e n e r a l P u b l i c later version . that the

L ic e n s e as the

published

S o f t w a r e Foundation ; o p t i o n ) any

version 2 of

it

will

be

useful , of

b u t WITHOUT ANY WARRANTY; GNU G e n e r a l P u b l i c License

without

implied

warranty See

MERCHANTABILITY o r FITNESS FOR A PARTICULAR PURPOSE. f o r more details .

the

t h e GNU G e n e r a l P u b l i c to the Free

License

write

Software 02110 1301 USA

Foundation ,

I n c . , 51 F r a n k l i n

Street ,

B ost on , MA

l i b r a r y IEEE ; use IEEE . STD LOGIC 1164 . ALL ; use IEEE . STD LOGIC ARITH . ALL ; use IEEE . STD LOGIC UNSIGNED. ALL ;

e n t i t y TB usrp mux i s end TB usrp mux ; architecture b e h a v i o r a l o f TB usrp mux i s for the U n i t Under T e s t (UUT)

Component d e c l a r a t i o n component usrp mux port ( dac mux i out 0 q out 0 i out 1 q out 1 d out ); end component usrp mux ; : : : : : in in in in in is

s t d l o g i c v e c t o r ( 3 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; : out s t d l o g i c v e c t o r ( 1 5 downto 0 )

I n p u t s s i g n a l dac mux signal i o u t 0 signal q out 0 signal i o u t 1 signal q out 1 : : : : : s t d l o g i c v e c t o r ( 3 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ; s t d l o g i c v e c t o r ( 1 5 downto 0 ) := ( o the rs = > 0 ) ;

O u t p u t s si g na l d out begin I n s t a n t i a t e UUT : usrp mux i out 0 = > i out 0 , q out 0 = > q out 0 , i out 1 = > i out 1 , S t i m u l u s Process q out 1 = > q out 1 , d out = > d out ) ; t h e UUT . : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;

> dac mux , port map ( dac mux =

230

59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

stim proc begin

pro c e ss

Do n o t h i n g wait f o r 10 n s ; S e t data

for

10 n s .

inputs .

i o u t 0 <= 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ; q o u t 0 <= 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ; i o u t 1 <= 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ; q o u t 1 <= 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 ; P r o v i d e for i every possible combination for dac m u x .

i n 0 to 15 loop

dac mux <= c o n v s t d l o g i c v e c t o r ( i , dac mux LENGTH) ; wait f o r 10 n s ; end loop ; End t e s t . wait ; end pro c e ss s t i m p r o c ; end b e h a v i o r a l ;

231

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