Electrical Power and Energy Systems 47 (2013) 157167

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Electrical Power and Energy Systems

journal homepage: www.elsevier.com/locate/ijepes

An experimental investigation on a multilevel inverter for solar energy applications

Venkatachalam Kumar Chinnaiyan a,, Jovitha Jerome b, J. Karpagam c
a

Department of Electrical and Electronics Engineering, Dr. NGP Institute of Technology, Coimbatore 641 048, India Department of Instrumentation & Control Systems Engineering, PSG College of Technology, Coimbatore 641 004, India c Department of Electronics and Communication Engineering, Dr. NGP Institute of Technology, Coimbatore 641 048, India
b

a r t i c l e

i n f o

a b s t r a c t
The main objective of the proposed work is to design, develop and test a three phase multilevel inverter with the modern power electronic switches to reduce the power quality issues in solar power conversion system. Due to the increased usage of power electronic converters for processing the power in all walks of our life, the power quality problem become the hot research topic in the recent years. As the power level increases, the voltage level is increased accordingly to obtain satisfactory efciency. The multilevel power converter has shown growing popularity. The fundamental advantages of multilevel converter topologies are low distorted output waveforms and limited voltage stress on the switching devices and hence the reduced electromagnetic interferences. The main disadvantages are higher complexity and more difcult control; it can be overcome by using modern digital controllers. In this paper, the performance parameters are analyzed with the developed prototype of the three phase cascaded multilevel inverter for solar energy conversion designed with digital controller for reduced power quality issues with three phase AC motor drive. The main objective is to obtain the better quality of output waveform on the inverter output with suitable control strategy on the experimental hardware setup. 2012 Elsevier Ltd. All rights reserved.

Article history: Received 10 December 2011 Received in revised form 17 October 2012 Accepted 20 October 2012 Available online 5 December 2012 Keywords: Inverters Power electronics Solar energy Drives Power converters Multi level inverter Field programmable gate array

1. Introduction Consumption of energy has become a daily necessity in modern civilization for the comfort and convenience of humanity, and the amount of energy consumption has served as an indicator for the standard of living and the degree of industrialization. It has long been recognized that associated with this excessive daily energy consumption is an adverse impact on the environment we live in, resulting in deterioration of the local and global environment. However, utilization of energy from different sources tends to have different kinds and different degrees of impact on the environment. The energy from renewable sources may be considered to have minimal or neutral impact on the environment. An energy system is like a double-edged sword; its use would normally bring about economic growth and social advancement as a whole, and comfort and convenience for individuals. On the other hand, a persistent and large-scale use of a particular energy system will also bring about inevitable negative environmental, social and economic impact, and when this negative impact is accumulated beyond a tolerance limit, permanent damage or catastrophe would occur. Since the Industrial Revolution, increased energy use has brought about economic prosperity and an improved standard of living. It is fully expected that this trend would
Corresponding author. Tel.: +91 9942999111.
E-mail addresses: Kumarchinn@hotmail.com (V. Kumar Chinnaiyan), jjovitha@ yahoo.com (Jovitha Jerome), sujisumi@rediffmail.com (J. Karpagam). 0142-0615/$ - see front matter 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.ijepes.2012.10.025

continue without the any degradation on the environment, economic and social growth. The target or objective is then to develop a magic energy system or systems that have no negative environmental, economic and societal impacts, which we refer to as green energy. Any energy system that has reduced or minimal adverse impact might be considered as greener energy. This definition of green energy implies that green energy, as the eventual long-term objective, will provide an important attribute for sustainable development. This is because attaining sustainable development requires the use of energy resources and technologies that do not have adverse environmental, economic and societal impact. Clearly, single energy resources such as fossil fuels are nite and thus lack the characteristics needed for sustainability, while others, such as renewable energy sources, are sustainable over the relatively longer term. Green energy sources are solar, wind, biomass, hydro, nuclear, geothermal, etc. Energy economics in the present era refers to energy market, electricity market, Carbon di-oxide (CO2) credit trading, clean development mechanism, Emission credit/trading, investment and payback time. With the advent of modern materials and the reduction of the cost, the solar energy based power system; it becomes the most preferred eco friendly power generation concept in the recent past [13]. 2. Solar radiation and daylight measurement Systematic measurements of diffuse solar energy and the global (total) irradiation incident on a horizontal surface are usually

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undertaken by a national agency, which is the national meteorological ofce in many countries. The measurement network includes pyranometers, solarimeters, or actinography instruments for this purpose. In practice, it is very important to appreciate the order of measurements prior to any modeling. The present state of solar radiation and daylight models is such that they are approaching the accuracy limits set out by the measuring equipment [20]. Radiation in the visible region of the spectrum is often evaluated with respect to its visual sensation effect on the human eye. In many countries, diurnal bright sunshine duration is measured at a wide number of places. The hours of bright sunshine are the time during which the suns disk is visible. On a clear day with a cloudless sky the burn does not start until 1530 min after sunrise and usually ceases about the same period before sunset. This period varies with the season. On the other hand, under periods of intermittent bright sunshine the burn spreads. Irradiation, which is dened as the solar power per unit area, solar radiation is radiant energy per unit area. Solar radiation is determined by summing solar irradiance over time and it is expressed usually in units of kW/m2 per day. Solar energy has an advantage over other renewable energy sources. It is more efcient in terms of the power that can be produced from a given area of land [12]. According to one estimate, solar power plants can produce about six times more power than bio fuels or wind. Solar powers advantage over water power is even greater.

for only a brief period of time. Most motors use 20% more power and run hotter with modied sine wave than with pure sine wave. Maximum output power is the maximum number of Watts the inverter can produce continuously. Harmonic distortion is distortion of the output waveform (235%). The solar energy is harnessed with the use of Bosch Solar Cell M 3BB C3 1200 which has higher efciency compared to the other solar panels available in the market and the other notable features are High annual yields, even with sub optimal levels of sunlight, thanks to excellent performance in weak light conditions, Pioneering three bus bar technology reduces the series resistance and helps to boost the power output in the module. Fig. 1A and B shows the current voltage characteristics and spectral response of the PV cells respectively. 3.1. Grid tied inverters Grid-tied inverters are widely used in Europe, Japan, and the United States to inter tie PV systems with the electric utility grid. These inverters convert the DC power to AC power in synchronization with the electric grid (UL 1741). When the grid goes down, the inverters go off by design. PV system utility interconnection considerations include safety, anti islanding, and power quality. The inverter should be correctly wired and have proper wire sizes, fusing, and breaker sizes and types. PV system anti islanding protection methods include grid shorted, grid open, anti islanding inversion synchronization, over or under frequency, and over or under voltage. The typical solar power generation with grid tied inverter system is shown in Fig. 2. 3.2. Multi level inverters The multilevel inverters perform power conversion in multilevel voltage steps to obtain improved power quality, lower switching losses, better electromagnetic compatibility, and higher voltage capability [2]. Considering these advantages, multilevel inverters have been gaining considerable popularity in recent years. In the recent past, the multilevel inverters have drawn tremendous interest in the eld of high voltage and high power applications. In the researches of multilevel inverters, its corresponding control strategies are one of the research hot areas. One of the most important problems in controlling a multilevel voltage source inverter is to obtain a variable amplitude and frequency sinusoidal output by employing simple control techniques [15]. Indeed, in voltage source inverters, non fundamental current harmonics cause power losses, electromagnetic interference and pulsating torques in AC motor drives. Harmonic reduction can then be strictly related to the performance of an inverter with any switching strategy. Multilevel inverters can increase the power by (m 1) times than that of two-level inverter through the series and parallel connection of power semiconductor devices [10]. Comparing with two level inverter system having the same power, multilevel inverters has the advantages that the lower harmonic components on the output voltages, Electro Magnetic Interference (EMI) problem could be decreased much. Due to these merits, many studies about multilevel inverters have been performed at simulation level and very few with hardware implementations [1]. 3.3. Types of multilevel inverters The multilevel inverter is best suited for the application which demands the nest quality of the AC supply waveforms. The multilevel inverters have many advantages when compared with conventional two level inverters as listed in Table 1.

3. Inverters Inverters accept an electrical current in one form and output the current in another form. An inverter converts Direct Current (DC) into Alternating Current (AC), whereas a rectier converts AC into DC. There are also DCDC converters, which step up or step down the voltage of a DC current. Inverters convert DC power from the batteries or solar array into 60 or 50 Hz AC power. Inverters can be transformer based or high-frequency switching types. Inverters can stand alone, be utility interconnected, or be a combination of both [14]. As with all power system components, the use of inverters results in energy losses due to inefciencies. Inverters are an interesting option due to the great variety of low-cost appliances that run on AC. Inverters are a key component to most Photo Voltaic (PV) systems installed in grid connected or distributed applications. Aside from the modules themselves, inverters are often the most expensive component of an installed PV system, and frequently are the critical factor in terms of overall system reliability and operation. Utility interactive PV systems installed in residences and commercial buildings will become a small, but important, source of electric generation over the next 50 years. This is a new concept in utility power production, a change from large-scale central generation to small-scale dispersed generation [16]. The basic system is simple; utilizing a PV array producing DC power that is converted to AC power via an inverter to the grid is very simple, yet elegant. The AC produced by inverters can have square, modied sine, or quasi sine waves and pure sine wave outputs. The pure sine wave is high cost, high efciency, and has the best power quality. Modied sine wave is mid-range cost, quality, and efciency. Square wave is low cost and low efciency, and it has poor power quality that is useful for some applications. Square wave signals can be harmful to some electronic appliances due to the high voltage harmonic distortion. All inverters emit electromagnetic noise. The harmonic frequencies and their magnitudes that appear on a system are governed by the shape of the distorted wave. The output capacity of an inverter is expressed in Volt Amperes (VA). During start up, devices such as motors require a VA power input several times greater than continuous power. This demand exists

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Fig. 1. (A) IV characteristic of Bosch Solar Cell M C31200. (B) Spectral response.

Fig. 2. Typical utility interactive PV system components.

This work proposes a different control scheme, which is fully pertained to cascaded multilevel inverters. Multilevel inverter topologies are classied into three categories diode clamped inverters, ying capacitor inverters and cascaded inverters. The detailed comparison among these is tabulated in Table 2. Cascaded inverters by Casadei et al. [21] have structurally not any problem of DC link voltage unbalancing or the requirement of the larger capacitors but it requires many separated DC sources which is considered as a major advantage with the present day rechargeable batteries. The batteries are usually rated for 12 V/24 V, in order to build an inverter system for high voltage motor drive applications for critical loads they are connected in series to obtain the higher voltage ratings. The batteries can be replaced with the array of solar PV cells provided the voltage ratings are matched with the inverter input requirements. The cascaded inverter has been largely studied and used in the elds of Static Volt Ampere Reactive Compensators (SVCs), voltage stabilizers, solar PV systems and so on [18]. It may be noted that due to other advantages of the modularized circuit layout and package, the cascaded inverter could be selected as a
Table 1 Comparison of conventional two level inverters and multilevel inverters. S. no. 1 2 3 4 5 6 7 8 Conventional inverter Higher THD in output voltage More switching stresses on devices Not applicable for high voltage applications Higher voltage levels are not produced Since dv/dt is high, the EMI from system is high Higher switching frequency is used hence switching losses is high Power bus structure, control schemes are simple Reliability is high

good choice in high voltage motor drive and grid interconnection applications [19]. When compared to diode clamped and ying capacitor inverters, cascaded inverter requires the least number of components to achieve the same number of voltage levels. 3.4. Three phase ve level CMLI For low and medium power application single phase inverter may cater the power requirements, for larger power and grid connected application three phase inverters are preferable one [3]. The three phase ve level cascaded multilevel inverter is constructed by combining the H bridges of (n 1) numbers. The three phase output is obtained by combining the H bridges for individual phases as shown in Fig. 3. The individual H bridges are powered by separate PV panels or by DC sources. The phase output voltage is synthesized by the sum of four H bridge inverters outputs, i.e., Van = V1 + V2 + V3 + V4. Each singlephase full bridge inverter can generate three level outputs, +VDC, 0, and VDC. This is made possible by connecting the DC sources

Multilevel inverter Low THD in output voltage Reduced switching stresses on devices Applicable for high voltage applications Higher voltage levels are produced Since dv/dt is low, the EMI from system is low Lower switching frequency can be used and hence reduction in switching losses Control scheme becomes complex as number of levels increases Reliability can be improved, rack swapping of levels is possible

Table 2 Comparison of different multilevel inverter topologies. S. no. 1 2 3 4 5 6 Topology Power semi conductor switches Clamping diodes per phase DC bus capacitors Balancing capacitors per phase Voltage unbalancing Applications Diode clamped 2(m 1) (m 1)(m 2) (m 1) 0 Average Motor drive system, STATCOM Flying capacitor 2(m 1) 0 (m 1) (m 1)(m 2)/2 High Motor drive system, STATCOM Cascaded 2(m 1) 0 (m 1)/2 0 Very small Motor drive system, PV, fuel cells, battery system

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Fig. 3. Structure of three phase ve level cascaded multilevel inverter.

sequentially to the AC side via four power semiconductor power devices. Each level of the full bridge inverter consists of four switches, S1, S2, S3 and S4. Using the top level as the example, turning ON S1 and S4, yields V1 = +VDC. Turing ON S2 and S3, yields V1 = VDC. Turning OFF all power switches yields VDC = 0. Similarly, the AC output voltage at each level can be obtained in the same manner. Minimum harmonic distortion is obtained by controlling the conducting angles by adopting correct control scheme at different inverter levels [4].

triangular waveforms of higher frequencies of several kilo Hertz. They can be categorized as shown in Fig. 4.

4.1. Proposed SVPWM for multilevel inverter The Sinusoidal Pulse Width Modulation (SPWM) technique, when applied to multilevel inverters, uses a number of levelshifted carrier waves to compare with the reference phase voltage signals [8]. The Space Vector Pulse Width Modulation (SVPWM) for multilevel inverters involves mapping of the outer sectors to an inner sub hexagon sector, to determine the switching time duration, for various inverter vectors. Then the switching inverter vectors corresponding to the actual sector are switched, for the time durations calculated from the mapped inner sectors [6,7]. It is obvious that such a scheme, in multilevel inverters, will be very complex, as a large number of sectors and inverter vectors are involved. This

4. Multicarrier PWM techniques Multicarrier Pulse Width Modulation (PWM) techniques entail the natural sampling of a single modulating or reference waveform typically being sinusoidal same as that of output frequency of the inversion system, through several carrier signals typically being

Sinusoidal Pulse Width Modulation

Modulating Signal

Carrier Signal

Pure Sinusoidal

Phase Disposition (PD)

Third Harmonic Injection

Phase Opposition Disposition (POD)

Dead Band

Alternate POD (APOD)

Other techniques

Hybrid (H)

Phase Shift (PS)

Super Imposed Carrier (SIC)

Fig. 4. Classication of SPWM.

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will also considerably increase the computation time for real time implementation. A modulation scheme is developed, where a xed common mode voltage is added to the reference phase voltage throughout the modulation range. It has been shown that this common mode addition will not result in a SVPWM like performance, as it will not center the middle inverter vectors in a sampling interval. The common mode voltage to be added in the reference phase voltages, to achieve SVPWM like performance, is a function of the modulation index for multilevel inverters. A carrier based PWM scheme has been presented, where sinusoidal references are added with a proper offset voltage before being compared with carriers, to achieve the performance of a SVPWM [4]. The offset voltage computation is based on a modulus function depending on the DC link voltage, number of levels and the phase voltage amplitudes. A novel method is developed to obtain an equivalent SVPWM pulses for the proposed multilevel inverter from the conventional Sinusoidal Pulse Width Modulation. To obtain the maximum possible peak amplitude of the fundamental phase voltage in linear modulation, a common mode volt age obtained from the circuit shown in Fig. 5, where V a , V b and V c are the reference phase voltages and, V a SFO , V b SFO and V c SFO are the sampled reference voltages. Voffset1, is added to the reference phase voltages where the magnitude of Voffset1 is given by,

V offset1 V max V min =2

where Vmax is the maximum magnitude of the three sampled reference phase voltages, in a sampling interval, Vmin is the minimum magnitude of the three sampled reference phase voltages, in a sampling interval.

i:e:V max MaxV an ; V bn ; V cn V min MinV an ; V bn ; V cn

The addition of the common mode voltage, Voffset1, results in the active inverter switching vectors being centered in a sampling interval. It makes the SPWM technique equivalent to the SVPWM technique. Eq. (1) is based on the fact that, in a sampling interval, the reference phase which has lowest magnitude (termed the min phase) crosses the triangular carrier rst and causes the rst transition in the inverter switching state. While the reference phase,

which has the maximum magnitude (termed the max phase), crosses the carrier last and causes the last switching transition in the inverter switching states in a two level SVPWM scheme. Thus the switching periods of the active vectors can be determined from the (max phase and min phase) sampled reference phase voltage amplitudes in a two level inverter scheme. The SPWM technique for multilevel inverters, involves comparing the reference phase voltage signals with a number of symmetrical level shifted carrier waves for PWM generation. It has been shown that for an n-level inverter, n 1 level shifted carrier waves are required for comparison with the sinusoidal references. Because of the level shifted multi carriers as shown in Fig. 6, the rst crossing (termed the rst cross) of the reference phase voltage cannot always be the min phase. Similarly, the last crossing (termed the third cross) of the reference phase voltage cannot always be the max phase. Thus the offset voltage computation, based on Eq. (1) is not sufcient to center the middle inverter switching vectors, in a multilevel PWM scheme during a sampling period Ts shown in Fig. 7. In this, a simple technique to determine the offset voltage (to be added to the reference phase voltage for PWM generation for the entire modulation range) is presented, based only on the sampled amplitudes of the reference phase voltages. The proposed scheme is to determine the sampled reference phase, from the three sampled reference phases, which crosses the triangular rst (rst cross) and the reference phase which crosses the triangular carrier last (third cross). Once the rst cross phase and third cross phase are identied, the principles of offset calculation by Eq. (1), for the two level inverters, can easily be adapted for the multilevel SVPWM generation scheme. The proposed SVPWM technique presents a simple way to determine the time instants at which the three reference phases cross the triangular carriers. These time instants are sorted to nd the offset voltage to be added to the reference phase voltages for SVPWM generation for multilevel inverters for the entire linear modulation range, so that the middle inverter switching vectors are centered (during a sampling interval), as in the case of the conventional two level SPWM scheme. 4.2. Determination of inverter leg switching times Fig. 6 shows a reference voltage and four triangular carriers used for PWM generation for a ve-level inverter. The modied reference phase voltages are given by,

V XN V XN V offset;1

X A ; B; C;

Fig. 5. Calculation of Voffset1 from phase voltage samples.

where VAN, VBN, VCN are sampled amplitudes of three reference phase voltages during the current sampling interval. The reference phase voltages are equally spaced between the four carriers, for ve level inverter. For modulation indices less than 0.433 (half of the maximum modulation index in the linear range of modulation for a ve level inverter), the reference phase

Fig. 6. Reference voltages and triangular carriers for a ve level PWM scheme.

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Fig. 7. Determination of the Ta_cross, Tb_cross and Tc_cross during switching interval TS (MI = 0.433).

voltage spans inner two carriers. For modulation index higher than 0.433, the reference phase voltages expand into the outer carrier regions. The addition of Voffset1, obtained from Eq. (1), to the reference phase voltage ensures that the modied reference voltages always remain within the carrier regions through the linear modulation range. The reference phase voltages cross the triangular carriers at different instants in a sampling period Ts shown in Fig. 7. Each time a reference phase voltage crosses the triangular carrier, it causes a change in the inverter state. The sampling time interval Ts, can be divided into four time intervals T01, T1, T2 and T03. T01 and T03 are dened as the time durations for the start and end inverter switching vectors respectively in a sampling time interval Ts, T1 and T2 are dened as the time durations for the middle inverter switching vectors, in a sampling time interval Ts. It should be noted from Fig. 8 that the middle switching vectors are not centered in a sampling interval Ts. So an additional offset (offset2) needs to be added to the reference phase voltages, so that the middle inverter switching vectors can be centered in a sampling interval, similar to a two level SVPWM. The time duration, at which the A phase crosses the triangular carrier, is dened as Ta_cross. Similarly, the time durations, when the B phase and C phase cross the triangular carrier, are dened as Tb_cross and Tc_cross, respectively. When A phase is in the carrier region C1 while the B phase and C phase are in carrier region C2, the time duration, Ta_cross, (measured from the start of the sampling interval) at which the A phase crosses the triangular carrier is directly proportional to the phase voltage amplitudes, VAN. The time duration Tb_cross at which the B phase crosses the triangular carrier V DC is proportional to V and the time duration, Tc_cross, at BN 4 which the C phase crosses the triangular carrier and it is propor V DC tional to V CN 4 . Therefore

Tb

cross

  V DC Ts V V T BN bs T s DC 4 4

where T as ;T bs , T cs are the time equivalents of the phase voltage magnitudes. The proportionality between the time equivalents and corresponding voltage magnitudes is dened as follows:

V DC 4

Ts
V DC 4

V AN T as V BN T as V CN T cs

Ts
V DC 4

Ts

In Fig. 8, where the reference phase voltages span the entire carrier region for a ve level inverter scheme. The time durations, at which the reference phase voltages cross the carrier can be similarly determined. Reference voltages span the entire carrier region, 0.433 < MI < 0.866. V DC Ta_cross is proportional to V AN 4 whereas Tb_cross is propor V DC V DC tional to V BN 2 and Tc_cross is proportional to V CN 4 Therefore, from Eq. (4)

T first cross minT x

cross ; cross ;

T second cross midT x T third cross maxT x

6 X a; b; c

cross ;

Ta Tc

cross

cross

V DC T as 4   V DC Ts V V T CN cs T s DC 4 4 V AN

In the present work, the Ta_cross, Tb_cross and Tc_cross time durations obtained above are used to center the middle switching vectors, as in the case of two level inverters, in the sampling interval Ts. The time duration, at which the reference phases cross the triangular carriers for the rst time, is dened as Trst cross. Similarly, the time durations, at which the reference phases cross the triangular carriers for the second and third time, are dened as, Tsecond cross and Tthird cross, respectively, in a sampling interval Ts.

Fig. 8. Determination of the Ta_cross, Tb_cross and Tc_cross during switching interval TS.

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The time durations, Trst cross, Tsecond cross and Tthird cross, directly decide the switching times for the different inverter voltage vectors, forming a triangular sector, during one sampling interval Ts. The time durations for the start and end vectors are T01 = Trst cross, T03 = Ts Tthird cross, respectively. The middle vectors are centered by adding a time offset, Toffset2 to Trst cross, Tsecond cross and Tthird cross. The time offset, Toffset2 is determined as follows. The time duration for the middle inverter switching vectors, Tmiddle, is given by,

T middle T third cross T first cross

The time duration of the start and end vector is,

Step 4: Determine Teffective. Step 5: Determine Ta_cross, Tb_cross and Tc_cross. Step 6: Sort Ta_cross, Tb_cross and Tc_cross to determine Trst cross, Tsecond cross and Tthird cross. (i) The maximum of Ta_cross, Tb_cross and Tc_cross is Tthird cross. (ii) The minimum of Ta_cross, Tb_cross and Tc_cross is Trst cross and the remaining one is Tsecond cross. Step 7: Assign rst_cross_phase, second_cross_phase and third_cross_phase according to the phase which determines

T first cross ; T second cross and T third cross 8

Step 8: Determine Tga, Tgb and Tgc. 4.4. Modeling of proposed SVPWM The SVPWM is implemented in the MATLAB/SIMULINK environment based on the equations from Eqs. (1)(10). The individual blocks are modeled with the corresponding equations and are linked together to obtain the simulation results [11]. The blocks for individual phases are interconnected and the SVPWM for three phase cascaded multilevel inverter is obtained. The offset voltage waveforms are derived based on the equations for offset voltage and from the sampled intervals of phase voltages. The offset voltages are obtained for individual crosses like rst_cross, second_cross etc., The obtained offset voltage waveform for three phase ve level cascaded multilevel inverter are as shown in Fig. 9. This offset voltage waveform is for the rst_cross in similar way the other offset voltages are obtained for every cross. After obtaining the offset voltages for individual crosses the time equivalents are obtained with the addition of the time, Toffset2 to Ta_cross, Tb_cross and Tc_cross gives the inverter leg switching times Tga, Tgb and Tgc for phases A, B and C, respectively which is shown in Fig. 10. This switching time intervals are given to the respective phase power switches and the effective voltages for all the phases are obtained and the same is captured with the aid of scope block in the MATLAB/SIMULINK editor. The phase sequence for the output effective voltage waveform is A, B and C. The output waveform coincides with the desired pattern which conrms that the respective switches are turned ON and OFF at correct instances without

T 0 T s T middle
Thus the time duration of the start vector is given by,

T 0 =2 T first cross T offset2

Therefore,

T offset2 T 0 =2 T first cross

The addition of the time, Toffset2 to Ta_cross, Tb_cross and Tc_cross gives the inverter leg switching times Tga, Tgb and Tgc for phases A, B and C, respectively.

T ga T a T gb T b T gc T c

cross cross cross

T offset2 T offset2 T offset2 10

The traces of different timing signals, for the proposed PWM scheme were captured for ve level PWM generation. 4.3. Steps involved in the proposed SVPWM The following are the steps involved to nd out the switching periods of inverter legs for n level inverter scheme, Step 1: Read the sampled amplitudes of VAN, VBN and VCN from the current sampling interval. Step 2: Determine the time equivalents of phase voltages, i.e. Tas, Tbs and Tcs. Step 3: Find Toffset1 using Tmax and Tmin, Tmax, Tmin are the maximum and minimum of Tas, Tbs and Tcs.

Fig. 9. Offset voltage waveform.

Fig. 10. Effective voltage waveform.

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Fig. 11. Line voltage waveforms.

any crossovers. Fig. 11 shows the line voltage waveforms for the modeled system with the proposed technique for three phase ve level. The output waveforms were analyzed in terms of percentage of output Total Harmonic Distortion (THD) by varying the modulation index for the different techniques adopted for simulation of the multilevel inverter conguration. The Modulation Index (MI) is varied from 0.1 to 1 and the output THD levels are captured. The percent THD is very higher for lower MI and it is almost seventy percent when the MI = 0.1 and slightly differs for different control

techniques. As MI is increased progressively the output THD levels reduced considerably for the specic technique. As far as the output THD levels are concerned the SVPWM technique is showcasing the better performance when compared to the other control techniques adopted for simulation as shown in Fig. 12. When the modulation index is 0.8, all the control techniques almost draws the same load current but for higher MI the few control strategies gives the better results in terms of the magnitude of the current.

5. System generator simulation blocks

Output Voltage THD in % Output Voltage THD Vs MI

Modulation Index
Fig. 12. Output phase voltage %THD vs modulation index with different control technique.

The proposed algorithm is generated in front end with the aid of system generator editor, the SVM blocks with the necessary supporting blocks and the associated blocks for individual phases are interconnected and the sampling frequency is set to 5 kHz. The entire control algorithm based on SVPWM in the system generator environment is as shown in Fig. 13. For simulation of the system the output supply frequency is varied from 10 Hz to 60 Hz which is decided by the user input value. The wide range of frequency is considered to analysis the output variations with respect to the input and the pulse patterns for all the desired frequencies. The pulse generation process is initiated with the aid of the input frequency value through the switch and the analog to digital converters input to the controller.

Fig. 13. Block diagram for generation of ring pulses for CMLI using system generator.

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The complete system is designed on the Xilinx system generator environment using the blocks for the proposed Field Programmable Gate Array (FPGA) based three phase ve level cascaded multilevel inverter for analysis purpose at simulation level [9]. 5.1. System generator simulation for FPGA implementation The obtained pulses are linked to the individual H bridges of various phases of different levels with the aid of linker block. From the linker block the gate pulses are linked to the individual Insulated Gate Bipolar Transistors (IGBTs) gate terminal to trigger. Once the power switches at different levels are supplied with the triggering pulses it will get turned ON and OFF according to the supplied pulse patterns. The output voltage starts to build up across the bridges corresponding to the phase sequence of the pulse patterns [5]. 6. Hardware specications The complete hardware specication of the proposed system is as follows Multilevel inverter input and output supply specications:  Storage batteries with the combination of producing 72 V output DC.  Isolated photovoltaic panels (Bosch Solar Cell M3BBC31200) with 72 V (3 24 V) output DC.  The input DC is 432 V (6 72 V).  Desired output: 5 kVA, output voltage 415 V, output current 10 A (Max).  Output frequency 4060 Hz, Three phase AC supply conned to IEEE standards. 6.1. Hardware implementation and results The proposed control algorithm is generated in front end with the aid of system generator editor, the SVPWM blocks with the necessary transformation equations and the associated blocks for individual phases are interconnected and the sampling frequency is set to 5 kHz. The entire control algorithm with sampling rate of 5 kHz which is based on modied SVPWM algorithm is implemented in the system generator environment and corresponding code for FPGA controller is generated. The generated code is downloaded into the digital processor Xilinx Spartan 3A XC3S400 and the hardware settings are enabled such that the output SVPWM pulses are available at the output ports. 6.2. Over load protection In order to protect the power circuit components from the over loading and short circuit, current sensors are used to continuously monitor the load current supplied by the Cascaded Multi Level In-

Table 3 Technical parameters of the AC motor used as load for the developed multilevel inverter. S. no. 1 2 3 4 5 6 7 8 9 10 11 12 Parameters Motor type No. of phases Connection Rated power Rated voltage Rated current Rated Frequency Duty cycle Rated speed No. of poles Rs, Ls Make Values Induction motor Three phase Star 1.5 kW 415 V 3.35 A 50 Hz S1 1400RPM 4 3.69 X, 0.26H Kirlosakar

verter (CMLI). Here four numbers of current transducers are employed to monitor the line and neutral currents. The four current transducers are used to protect the power switches. The current transducer LTS-25NP is used. This transducer is capable of operating in three different ranges from 8 A to 25 A depending on the pin connections. It operates on 5 V DC supply and gives the maximum output voltage of 2.5 V depending on the current owing through the transducer. Here it is used to measure the current from 0 A to 8 A and the pins are connected accordingly. The specications of the AC motor used for testing are as listed in Table 3. The rated current of the motor is 3.35 A, considering the overshoot and starting current the protective circuit is designed for 8 A maximum. Pin 1 is used as input and the pin 4 is used as output. For 8 A measurement pins 3 and 5, 2 and 6 are short circuited. This gives the complete protection for power circuit and protects the power devices against overload. After the testing and commissioning of the hardware unit it is subjected to the various experimentations under different loading conditions on its output side with the power harmonic analyzer. In order to load the three phase induction motor in a uniform manner a DC machine is operated as a self excited shunt generator and it is mechanically coupled to it. The DC generator is loaded with the resistive load and this setup constitutes the loading arrangements. The complete hardware setup is as shown in Fig. 14. This set up provides a linear load variation on the inverter side and the performance parameters such as terminal voltage, voltage and current harmonics levels and symmetry of three phase voltages for frequencies 40 Hz, 45 Hz, 50 Hz and 60 Hz are captured with the aid of Fluke make three phase power quality analyzer. Here the Fluke 434 model is used, it is a three phase power quality analyzer, and it complies with the international standards. The power quality analyzer is congured suitably for the testing [17]. The limits for the various power quality issues are set in accordance with the standard EN50160. The developed system is connected to the AC motor i.e. loading arrangements and the readings are captured with the aid of power quality analyzer in the scope mode and the three phase output voltage waveform is as

Fig. 14. Photograph of the experimental hardware setup with loading and measuring equipment.

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Fig. 15. Three phase output voltage waveforms for 50 Hz output.

shown in Fig. 15 for the set frequency of 50 Hz on the digital processor. The output voltages in all the phases i.e. RYB are 396 V and the phases are 120 apart from each other. The neutral potential is within the prescribed limits. The harmonics of the output voltage and the current harmonics are also listed in the harmonics table of the analyzer as shown in Fig. 16. The table shows that the harmonics are very well within the limits prescribed by power quality standards. The same is tested for 40 Hz, 45 Hz and 60 Hz. The phase displacements are captured and the same is shown in Fig. 17. The observations on the output of developed hardware system show that the total harmonics distortions of the system are less than the ve percent, which is the desired outcome. From the obtained values the graph was plotted for different output frequency of 40 Hz, 45 Hz and 60 Hz, Fig. 18 shows the plot for 50 Hz. Fig. 19 shows the waveform obtained across the output with the aid of digital storage oscilloscope. On experimentation the output percentage THD for voltage, current and neutral potential is collected continuously for various load currents and the values were tabulated. 7. Conclusion The implementation and testing of a low cost FPGA based cascaded multilevel inverter with solar energy conversion application for induction motor drive was implemented. The main advantage of this system is the ability to generate SVPWM waveform generation in real time using control algorithm implemented in the Xilinx processor. This reduces the computation time required to determine the switching times for inverter legs, making the system suitable for real-time implementation for larger drives where as the power quality problems are the major considerations. Compared to other control techniques the proposed SVPWM technique shows the better quality of output waveforms. Furthermore during the testing of output of the developed experimental setup with the Fluke 434 model three phase power quality analyzer shows that the results exhibits the good quality of output waveforms with higher fundamental component and also power quality issues are very well within the limits. The %THD on voltage and current waveforms are always less than that of the ve percent. The higher fundamental component on output results in reduced switching losses in semiconductor switches and induction motor. With these results it is concluded that the conventional drives with two level inverters can be replaced with multilevel inverter where ever it is possible in order to maintain the good quality of the power. Acknowledgment The authors are very much grateful to the ofcials of the Department of Science and Technology for their nancial support and their valuable suggestions, help at the critical times of this project. This research work is funded by the Department of Science and Technology (DST), Government of India, New Delhi, under the title of Design Analysis and Experimentation of Low Cost DSP Based Multilevel Inverter for Industrial Applications with Reduced EMI and Other Power Quality Issues Grant order No.: SR/ FTP/ETA-33/2006. References
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Fig. 16. Output current and voltage harmonics of the developed system for 50 Hz output under loading condition.

Fig. 17. Phase displacements for three phase voltages at 45 Hz.

% THD Vs Load Current for 50Hz

% Slip %THDv

% THD, Neutral Voltage

%THDi Neutral Voltage in V

Load Current (A)

Fig. 18. Load current vs %THD for 50 Hz output.

Fig. 19. Output voltage waveform for R phase at rated condition.

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