INTEGRATOR:

In integrator output is integral form of input.If the input voltage is zero, no

input current will flow. Therefore no feedback current can flow and the output
voltage will remain constant. If the input voltage is non-zero, the basic equation
for the output voltage becomes Vout = -Vin/RC + K, where R is the input
resistance in ohms, C is the feedback capacitance in farads, and K is a fixed
constant representing the accumulated voltage from the past.

If the input voltage is constantly changing, the output voltage at any instant
will be the integral of all past input voltage values. For example, a bipolar sine
wave input will actually produce another sine wave as its output, at a phase angle
of 90° from the input sine wave. Technically, the output will be an inverted
cosine wave.

COMPARATOR:
A comparator is a device which compares
two voltages or currents and switches its output to indicate which is
larger.
An operational amplifier has a well balanced difference input
and a very high

gain.
 A standard op-amp operating in open loop configuration (without
negative feedback) can be used as a comparator. When the non-
inverting input (V+) is at a higher voltage than the inverting input
(V-), the high gain of the op-amp causes it to output the most
positive voltage it can. When the non-inverting input (V+) drops
below the inverting input (V-), the op-amp outputs the most
negative voltage it can. Since the output voltage is limited by the
supply voltage, for an op-amp that uses a balanced, split supply.

J-K FLIP FLOP:

To prevent any possibility of a "race" condition occurring when both the S

and R inputs are at logic 1 when the CLK input falls from logic 1 to logic 0, we
must somehow prevent one of those inputs from having an effect on the master
latch in the circuit. At the same time, we still want the flip-flop to be able to
change state on each falling edge of the CLK input, if the input logic signals call
for this. Therefore, the S or R input to be disabled depends on the current state of
the slave latch outputs.

If the Q output is a logic 1 (the flip-flop is in the "Set" state), the S input can't
make it any more set than it already is. Therefore, we can disable the S input
without disabling the flip-flop under these conditions. In the same way, if the Q
output is logic 0 (the flip-flop is Reset), the R input can be disabled without
causing any harm. If we can accomplish this without too much trouble, we will
have solved the problem of the "race" condition.

The circuit below shows the solution. To the RS flip-flop we have added two
new connections from the Q and Q' outputs back to the original input gates.
Remember that a NAND gate may have any number of inputs, so this causes no
trouble. To show that we have done this, we change the designations of the logic
inputs and of the flip-flop itself. The inputs are now designated J (instead of S)
and K (instead of R). The entire circuit is known as a JK flip-flop.
 In most ways, the JK flip-flop behaves just like the RS flip-flop. The Q and Q'
outputs will only change state on the falling edge of the CLK signal, and the J
and K inputs will control the future output state pretty much as before. However,
there are some important differences.

Since one of the two logic inputs is always disabled according to the output
state of the overall flip-flop, the master latch cannot change state back and forth
while the CLK input is at logic 1. Instead, the enabled input can change the state
of the master latch once, after which this latch will not change again. This was
not true of the RS flip-flop.

If both the J and K inputs are held at logic 1 and the CLK signal continues to
change, the Q and Q' outputs will simply change state with each falling edge of
the CLK signal. (The master latch circuit will change state with each rising edge
of CLK.) We can use this characteristic to advantage in a number of ways. A
flip-flop built specifically to operate this way is typically designated as
a T (for Toggle) flip-flop. The lone T input is in fact the CLK input for other
types of flip-flops.

The JK flip-flop must be edge triggered in this manner. Any level-triggered

JK latch circuit will oscillate rapidly if all three inputs are held at logic 1. This is
not very useful. For the same reason, the T flip-flop must also be edge triggered.
For both types, this is the only way to ensure that the flip-flop will change state
only once on any given clock pulse.

Because the behavior of the JK flip-flop is completely predictable under all

conditions, this is the preferred type of flip-flop for most logic circuit designs. The
RS flip-flop is only used in applications where it can be guaranteed that both R and
S cannot be logic 1 at the same time.

At the same time, there are some additional useful configurations of both
latches and flip-flops. In the next pages, we will look first at the major
configurations and note their properties. Then we will see how multiple flip-flops
or latches can be combined to perform useful functions and operations.

THREE PHASE THYRISTOR CONVERTERS:

The advantage of using 3 phase controlled converter over

single phase controlled converter are the same possessed by a 3
phase diode rectifiers over single phase diode rectifiers.3 phase
delta-star transformer employed for delivering power to 3 phase
converters. All three phase converters use line commutation for
turning off thyristors.
Three phase thyristor converters may be classified as:
o Three pulse converters
o Six pulse converters
o Twelve pulse converters
Six pulse converters include 3 phase full converters,3 phase semi converters, and six
pulse mid point converters.
THREE PHASE HALF-WAVE CONTROLLED CONVERTER:

This converter is also called 3 phase 3 pulse converter or 3 phase M-3 converter.