Spring 2014 Microcontroller Lab# 5

ASYNCHRONOUS SERAL !O AN" N#ERRU$#S

O%&EC#'E
The purpose of this experiment is getting familiar with SC module in 68HC11E9. This will be
accomplished by implementing a drier with interrupt and polling based send and receie subroutines
for the SC module which complies with RS2(2 standard. Hardware setup of the serial communication
will also be studied.
$RELMNARY )OR* !"eadline# $th of %ay &'1( %idnight)
Rea+ t,ro-g, ASYNCHRONOUS SERAL N#ER.ACE /ection 0Co11-nication Con2ig-ration3
to obtain bac4gro-n+ in2or1ation on SC 1o+-le5
1. *rite a subroutine to initiali+e the SC module, your subroutine must configure the SC module
as the following#
1 start bit,
8 data bits,
1 stop bit,
interrupts disabled,
-o wa.e up,
/rea. generator off,
/01" rate of 9612,
Transmitter enabled.
&. 3ead through $rote-/ Set-p section, then Connect the 453T016 TE3%5-16 pins as the
following#
'irt-al #er1inal MC67HC11E8
3x" Tx"
Tx" 3x"
Connect the 4irtual terminal pins 3T7 and CT7 to each other.
8. 3ead through 7ection SC tran/1itter to obtain bac.ground information on SC transmitter.
(. *rite a subroutine Sen+C,ar to send the contents of 1ccumulator 1 to the irtual terminal.
2. *rite Sen+Str subroutine that uses Sen+C,ar to send a string to the terminal9 the function
stops sending characters when it reads the first 9 character.
6. 3ead through 7ection 7C5 receier to obtain bac.ground information on SC receier.
$. Change the initiali+ation subroutine from !1) aboe to enable the receier. Then write
Rec:C,ar subroutine to read the user input from the .eyboard and return it in 1ccumulator 1.
8. *rite Rec:Str subroutine that will read the user input string from .eyboard and sae the
receied in memory when the user presses the Enter .ey. "o not forget to append the 9
character to the string saed in memory.
9. *rite an Ec,oC,ar subroutine that uses the Rec:C,ar and Sen+C,ar to echo !display) the
user input on the screen.
1'. *rite an Ec,oStr subroutine by modifying the Rec:Str subroutine to ta.e adantage of the
Ec,oC,ar subroutine from !9).
11. 0$rogra1 1; $olling3 *rite a <elco1e subroutine, using polling approach, that uses Rec:Str
and Sen+Str to as. for the user name and then displays a welcoming message. :or
example#
> What is your name ? (program output)
Joffrey (user input)
Welcome Joffrey (program output)
1&. 7imulate the code you wrote in !11) using ;roteus.
18. 3ead through section nterr-pt/ to obtain bac.ground about 5nterrupts and their
synchroni+ation.
1(. *rite an initiali+ing subroutine nten that enables the interrupt ectors.
12. *rite an 5nterrupt 7erice 3outine !573) /rRec to handle the reception of a character. *rite
another 5nterrupt 7erice 3outine /r#r that handles the completion of transmitting a
character.
16. 0$rogra1 2; nterr-pt3 0sing on the aboe 573s in !12) rewrite the <elco1e subroutine from
!11) using interrupts, instead of relying on polling techni<ue.
1$. 7imulate the code you wrote in !16) using ;roteus.
18. 3ead through %-22alo 7ection to get familiar with the /0::16= management of 5nterrupt
ectors, and thin. about how you would do this in the lab.
$re=)or4 S-b1i//ion;
>S-b1it one $". 2ile incl-+ing $rogra1/ t,at >o- <rote in 0113 an+ 0163? an+ /creen
/,ot/ o2 /i1-lation/5
Note; A++ clear co11ent/ 2or eac, progra15
"ea+line ; @t, o2 Ma> 2014
ASYNCHRONOUS SERAL N#ER.ACE
Co11-nication Con2ig-ration
7erial communication is the process of sending one bit at a time oer a communication channel.
Compared to parallel communication where seeral bits are sent at once, serials communication
saes wiring costs especially for long distances. The Universal Asynchronous Receiver/Transmitter
0UAR#3 is the hardware port that implements the serial data transmission. This is called the
Asynchronous Communications Interface Adapter 0ACA3 or Serial Communication Interface 0SC3 on
68HC11 %C0. The module is implements a receier and a sender that complies with the RS2(2
protocol.
RS2(2 is a standard that defines a simple asynchronous communication protocol. 5t specifies#
Electrical signal characteristics such as oltage leels, signaling rate, timing and slew?rate
of signals, oltage withstand leel, short?circuit behaior, and maximum load capacitance9
5nterface mechanical characteristics, pluggable connectors and pin identification,
:unctions of each circuit module in the interface connector,
7tandard sub?modules of interface circuits for selected telecommunication applications.
To comply with specific physical channel and receiing e<uipment properties, the digital signal has to
be transported by an amplitude and time discrete signal that is optimally tuned. The waeform pattern
of oltage or current used to represent the 1s and 's of a digital signal on a transmission lin. is called
line coding.
RS2(2 applies oltages in the range ?12 to @12 4 to represent the high and low logic and the special
se<uence control bits. These different oltage leels re<uire interface circuits that conert them to
normal oltage leels. MAA2(2 chip can be used for this purpose. This is already placed on the E4/0
and the ;C boards, communicating using a serial lin.. :igure 2.1 shows the connection configuration
defined between the E4/0 and the ;C. 5t is called full duplex as it allows the two parts to receie and
send data at the same time.

:igure 2.1. :ull duplex serial channel
Eenthough RS2(2 standard has many pins and uses the "%25 !&2 pin) interface as the default,
"%8!EA=5@4 !9 pin) interface is used widely for its smaller si+e !lower cost) since it is sufficient when
operating in asynchronous serial mode. :igure 2.& shows the EA=5@4 interface used in the lab and
describes the function of the nine pins.
:igure 2.&. "%8!EA=5@4 male interface !used in the lab)
1s the communication is asynchronous one, extra bits must be sent to group the data bits and to
define the end and start of the communication. Haing more than one configuration for the way that
the data can be sent and receied, the transmitter and receier must agree on the format of the data
that is being exchanged before the communication starts. 1 AframeA pac.s a group of bits to be
transmitted together. Each frame contains special bits to define the start and end, and other optional
bits to help receiers detect any errors in transmitted data due to noise and other factors. :igure 2.8
depicts the data frame contents, the ninth !T8) bit and the ;arity bit are optional. 7tart and 7top bits
identify the start and the end of the data frame as their names imply.
7top ;arity T8 $ 6 2 ( 8 & 1 ' 7tart
1 '
:igure 2.8. "ata :rame
The speed of data transmission must be defined before the communication starts. %ismatches in the
receier and transmitter cloc.s will result in loss of data in the receier buffer. The speed of
communication is measured in /aud 3ate. The programmer must be sure that both end points are
configured to apply the same options.
68HC11 offers a number of control registers to configure 7C5 settings. The critical registers are
described below.
:igure 2.(. Control 3egister 1 !7CC31)
38 ? 3eceie "ata /it 8# 5f % bit is set, 38 stores the ninth bit in the receie data character.
T8 ? Transmit "ata /it 8# 5f % bit is set, T8 stores the ninth bit in the transmit data
character.
/it 2 ? 0nimplemented# 1lways reads '
% ? %ode /it !select character format)#
' B 7tart bit, 8 data bits, 1 stop bit
1 B 7tart bit, 9 data bits, 1 stop bit
*1CE ? *a.eup by 1ddress %ar.D5dle /it
' B *a.eup by 5"6E line recognition
1 B *a.eup by address mar. !most significant data bit set)
/its E&#'F G 0nimplemented# 1lways read '
:igure 2.2. Control 3egister & !7CC3&)
T5E ? Transmit 5nterrupt Enable /it
' B T"3E interrupts disabled
1 B 7C5 interrupt re<uested when T"3E status flag is set
TC5E ? Transmit Complete 5nterrupt Enable /it
' B TC interrupts disabled
1 B 7C5 interrupt re<uested when TC status flag is set
35E ? 3eceier 5nterrupt Enable /it
' B 3"3: and =3 interrupts disabled
1 B 7C5 interrupt re<uested when 3"3: flag or the =3 status flag is set
565E ? 5dle?6ine 5nterrupt Enable /it
' B 5"6E interrupts disabled
1 B 7C5 interrupt re<uested when 5"6E status flag is set
TE ? Transmitter Enable /it# *hen TE goes from ' to 1, one unit of idle character time
!logic 1) is <ueued as a preamble.
' B Transmitter disabled
1 B Transmitter enabled
3E ? 3eceier Enable /it
' B 3eceier disabled
1 B 3eceier enabled
3*0 ? 3eceier *a.eup Control /it
' B -ormal 7C5 receier
1 B *a.eup enabled and receier interrupts inhibited
7/C ? 7end /rea.# 1t least one character time of brea. is <ueued and sent each time 7/C
is written to 1. 1s long as the 7/C bit is set, brea. characters are <ueued and sent. %ore
than one brea. may be sent if the transmitter is idle at the time the 7/C bit is toggled on
and off, as the baud rate cloc. edge could occur between writing the 1 and writing the ' to
7/C.
' B /rea. generator off
1 B /rea. codes generated

:igure 2.6. /10" register
TC63 ? Clear /aud 3ate Counter /it !Test)
7C;E&#'F ? 7C5 /aud 3ate ;rescaler 7elect /its
1CC/ ? 7C5 /aud 3ate Cloc. Chec. /it !Test)
SC #ran/1itter
:igure 2.$ depicts the schematic diagram of the SC transmitter implementation. -otice the distribution
of the SCCR1, SCCR2 and %AU" register bits in the figure.
The transmission cycle starts by waiting for the transmitter module to be freed. The status of the
transmitter can be chec.ed by reading the #C flag in the 7tatus 3egister !7C73). =nce the #C flag
goes high, this means that any preious transmission operation is finished and the transmitter is free
to send another frame of data. The process of waiting for the transmitter to be freed by chec.ing its
status bits continuously is called polling.
Then we write the data to be sent on the "ata 3egister !SC"R), with address H1'&:, which
represents a buffer for the hidden shift register. =nce the data is written to the shift register, the bits
start to be transmitted, starting by the 67/ bit, to the pin buffer using a cloc. speed controlled by the
%AU" register. *hile the transmitter shifts and sends out the bits, the #C flag in the 7tatus 3egister
!SCSR) stays ' to indicate that the transmitter is busy. SCSR details are shown in :igure 2.8.
:igure 2.$. 7C5 transmitter schematic diagram
:igure 2.8. 7tatus 3egister !7C73)
T"3E ? Transmit "ata 3egister Empty :lag# This flag is set when 7C"3 is empty. Clear
the T"3E flag by reading 7C73 with T"3E set and then writing to 7C"3.
' B 7C"3 busy
1 B 7C"3 empty
TC ? Transmit Complete :lag# This flag is set when the transmitter is idle !no data,
preamble, or brea. transmission in progress). Clear the TC flag by reading 7C73 with TC
set and then writing to 7C"3.
' B Transmitter busy
1 B Transmitter idle
3"3: ? 3eceie "ata 3egister :ull :lag# This flag is set if a receied character is ready to
be read from 7C"3. Clear the 3"3: flag by reading 7C73 with 3"3: set and then
reading 7C"3.
' B 7C"3 empty
1 B 7C"3 full
To achiee maximum transmission throughput you can write the next data frame directly to the 7C"3
after it is empty by chec.ing the T"3E flag.
SC Recei:er
:igure 2.9 shows the schematic diagram of the SC receier implementation. The reception cycle
starts by waiting for the receier module to be filled by a full frame of data. The status of the receier
can be chec.ed by reading the R"R. flag in the SCSR. =nce the R"R. flag goes high, this means
that a complete data frame has been receied and the SC"R is full. 1gain we can use the polling
techni<ue to .now if we receied any new data, by chec.ing the receier status bits continuously.
=nce we hae the data, any load operation is sufficient to read the SC"R contents and to clear the
R"R. flag.
nterr-pt/
0p to this point the polling techni<ue has been used to send and receie data using the SC. The
polling techni<ue re<uires continuous chec.ing of the status, and therefore wastes cycles. 5n addition,
it adds challenges to software design especially when the application response latency is an important
factor or when there are mission critical applications with real time re<uirements.
5nterrupt is a hardware based mechanism that forces the processor to execute a piece of code located
at special address, if a deice status meets specific conditions. This piece of code is called 5nterrupt
7erice 3outine !SR). 5n 68HC11 architecture, once an interrupt occurs, it loads an address of one of
the 573s aailable to the ;C register, depending on the type of the deice that re<uested the interrupt.
The addresses of the different 573s are saed in special table, called interrupt ector table, which is
located at the last part of the 6( C/ memory map. Iou are familiar with the first interrupt ector, the
3eset 4ector, which has the highest priority and is located at 9...E=9..... The priority of different
interrupts, when more than one interrupt re<uest occurr at the same time, is decided by hardware. The
decision is made based on their order in memory except for the software interrupts, which hae the
lowest priority.

:igure 2.9. 7C5 receier schematic diagram
68HC11 architecture allows the programmer to control all the interrupts by using SE and CL
instructions. This ma.es it possible to define pieces of code that are not interruptible !preemptie).
Those pieces of code are called critical sections.
The SC module has one interrupt ector located at 9.."6=9.."@5 The contents of this ector will be
loaded to ;C register if any of these eents happen#
3eceie data register full, R"R. B 1
Transmit data register empty, #"RE B 1
Transmit complete, #C B 1
1s many re<uests share the same interrupt ector, the SR executed on an 7C5 interrupt must chec.
those flags to determine the status of the SC module. 5n case there are more than one cause for the
interrupt, the 573 should decide which one has higher priority than the others.
To initiali+e the SC module to ta.e adantage of the interrupts, return to the SCCR2 and ta.e a loo.
at the different bits that control the receier and transmitter interrupt capabilities. RE arms
1
the SC
receier, so it can interrupt once data is receied. #CE is another bit that arms the SC transmitter to
interrupt once the data has been sent. This interrupt is ery useful in case we want to send a group of
data frames. /ear in mind that you hae to disarm the SC transmitter once you finished sending the
data frames. =therwise the last sent frame will re<uest an interrupt and there is no extra data to be
written to clear the #C flag, which causes it to re<uest interrupts indefinitely.
The structure of your code can follow many paradigms to wor. with interrupts9 below is an example#
-----------------------------------------------------------------------------------
ORG $FFD6
FDB SC!SR
ORG $"###
$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
main% initiali&e the stac' (ointer )B*FF+,O ta'es care
initiali&e the SC mo-ule
.- /na0le transmitter an- recei1er
"- Define the communication settin2s as B+*D3 -ata frame characteristics
4- +rm the transmitter an- the recei1er5
C, )/na0le the interru(ts in the (rocessor
Do any other tas's as'e- 0y the user
$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
SC!SR%
S/ )Disa0le the 2eneral interru(ts fla23 6hich -oes not allo6 neste- SRs
to 0e e7ecute-5

f a -ata frame is rece1e- then
ser1e the recei1er 0y callin2 rec1
else
if a -ata frame has 0een sent then
ser1e the transmitter 0y callin2 sen-
C, )/na0le the 2eneral interru(ts fla2
R8 )R8 is -ifferent from R8S3 in SR you shoul- use R85
$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
rec1%
9*S: the re2isters you 6ill use in this su0routine ;to (reser1e them<
Clear the fla2 that re=ueste- the interru(t
Ser1e the interru(t
9*,, the re2isters you (ushe- in this su0routine
R8S
$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
sen-%
9*S: the re2isters you 6ill use in this su0routine ;to (reser1e them<
Clear the fla2 that re=ueste- the interru(t
Ser1e the interru(t
9*,, the re2isters you (ushe- in this su0routine
R8S
---------------------------------------------------------------------------------
1
arm and disarm are used to mean granting the deice ability to re<uest interrupts and ta.ing away that ability.
%U..ALO nterr-pt Manage1ent
7ince the interrupt ector table is implemented in ;3=%, it is not possible to change the alues of
those ectors in the E4/0. Howeer, /0::16= points these ectors to another table that resides in
31% memory space. :or example, 7C5 interrupt ector is filled with the address 900C4. 1ddresses
900C4=900C6 are resered to be filled by a Jump instruction that points to the user SR. 5n this way,
/0::16= allows the user to place the SR code to anywhere in the user accessible memory without
changing the contents of the interrupt ector table.
$rote-/ Set-p
0sing the 4irtual Terminal you can find under 4irtual 5nstruments %ode, ;roteus offers a simplified
method for establishing a serial lin.. 1 full duplex configuration is depicted in :igure 2.1'. The irtual
Terminal accepts normal logic leels, so that there is no need to introduce interface circuits between
transmitters and receiers.
:igure 2.1'. 4irtual Terminal in full duplex mode
To configure the serial communication parameters in the irtual terminal, right clic. on the irtual
terminal symbol and choose properties. :igure 2.11 shows the properties dialog of the 4irtual
Terminal. /e sure to hae hae a consistent configuration at both ends of the serial lin. in order to
aoid communication problems.
EA$ERMEN#AL )OR*
1 %odify the <elco1e subroutine from $rogra1 1 which uses the polling mechanism, to run
under /0::16=. 3un your program and demonstrate your results to the lab instructor.
2 %odify the <elco1e subroutine that uses the interrupt mechanism, from $rogra1 2 to run
under /0::16=. 3un your program and demonstrate your results to the lab instructor.
Re2erence/
1 %68HC11E :amily "ata 7heet
& Embedded %icrocomputer 7ystems, 3eal Time interfacing. 7econd edition. Konathan *.
4alano.

:igure 2.11. 4irtual Terminal properties dialog