01 Vladimirescu MOS-AK06

1
Design and Simulation MOSFET

Models: Closing the Gap
Paul Jespers and Andrei Vladimirescu
Universit Catholique de Louvain
UC Berkeley/BWRC and ISEP
2
P. Jespers, A. Vladimirescu ESSCIRC06
Motivation
Develop a MOSFET model for analog design
Must describe all regions of operation
Simulation models have become
Very accurate, but
Very complex, inadequate for hand calculation!
Design is not done by SPICE!
Model used in design must be simple but relatively accurate
SPICE provides the ultimate accurate verification
Start from physics
Minimize number of parameters
Use Matlab for help!
2
3
Overview
Applications and Requirements
Compact Model Approximation
Basic Equations
Parameters and their Extraction
g
m
/I
D
Analog Design Methodology
Design Example
Opamp Design
Design Verification
Conclusion
4
Applications of Device Models
Estimation/Design
Simple for hand-calculation
Accurate for relevant results!
Examples: Level=1, -Power
Circuit Simulation (SPICE)
Currents and Charges function of terminal voltages
Continuous functions and first derivatives over
All regions of operations
Temperatures
Geometries
Model parameters: physical and scalable
Device Simulation
Semiconductor-device physics carrier concentrations
3
5
Device Model Requirements
for IC Design Applications
Digital Circuits
Very accurate I
ON
and I
OFF
(subthreshold)
No negative conductances
Analog Circuits
Accurate everywhere especially transition regions!
Accurate I
D
in all regions
Accurate values for small-signal
g
m
, g
ds
, g
mbs
, Cgs, Cgd
Correct small-size
6
Application: Analog CMOS Design
Operation at low V
GS
-V
TH
(Moderate Inversion)
Maximum gain according to LEVEL=1 (strong-inversion only)
V
GS
-V
TH
a
v
; V
GS
-V
TH
0, a
v
, better model is needed!
Low-power - moderate or weak inversion
Operation up to the edge of saturation
Max output resistance
Max output swing
Estimation model accuracy needed
from weak to strong inversion
Big Gap with latest simulation models!
a
v
=
g
m
g
o
=
2
V
GS
V
TH
( )
4
7
Overview
Basic Equations
g
m
/I
D
Design Example
Opamp Design
Design Verification
Conclusion
8
Charge Sheet Model (surface potential model) [1]
Compact Model replace
s
by mobile charge density Q
i
by introducing constant parameter n (the slope factor) [2,3]
* [1] Brews J.R.
A charge sheet model for the MOSFET. Solid-State-Electronics. Vol 21, p 345-355, 1978.
* [2] Cunha A.I.A., Scheider M.C. and Galup-Montoro C.
An MOS transistor model for analog circuit design. IEEE. JSCC, vol 33, n 10, p 1510-1519, oct 1998,
* [3] Enz C., Krummenacher F. and Vittoz E.
An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications.
Analog Integrated Circuits and Signal Processing, Vol 8, p 83-114, 1995.
Charge-Based Estimation Model
I
D
d x = W Q
i
d
S
+ U
T
d Q
i
| |
d
Q
i
C
oc
|
\

|
.
|
= n d
S
I
D
dx = C
ox
W
1
n
Q
i
C
ox
|
\

|
.
|
+U
T

(

( d
Q
i
C
ox
|
\

|
.
|
5
9
Charge-Based Estimation Model (Contd)
Define normalized q,
Define the specific current I
S
, the transition point W.I. S.I.
Normalized current charge equation
Forward normalized current
Reverse normalized current
q =
Q
i
2nU
T
C
ox
i =
I
D
I
S
= q
2
+ q
| |
V
D
V
S
= i
F
i
R
i
F
= q
S
2
+ q
S
i
R
= q
D
2
+ q
D
I
S
= 2nU
T
2
C
ox
W
L
= 2nU
T
2
10
Drain, Source Voltage
Charge-voltage equation
(SEMI-COND PHYSICS + CONSTANT n APPROX)
V
P
V =U
T
2 q 1 ( )+ log q ( ) | |
V
P
pinch-off voltage (q = 1)
V is the non-equilibrium voltage along the channel
V = V
S
at the source
V = V
D
at the drain
q
V
P
V
S.I. W.I.
6
11
Gate Voltage
Define V
To
V
P
=
V
G
V
To
n
area 2nU
T
2
i = 2nU
T
2
I
D
I
S
=
I
D
S.I. W.I.
slope n
V
G
V
P
V
2nU
T
q
V
T
= V
G
- 2nU
T
q
nV
P
0
V
To
=V
G
nV
P
Charge-voltage equ. for q very large
non-equilibrium voltage along the channel
2nU
T
q
12
I
D
V
G
Characteristic General Philosophy
The shape of the I
D
(V
G
) characteristic changes little as the channel length
shrinks, displaying weak (W.I.) and strong inversion (S.I.) regions separated
by a moderate inversion region (M.I.).
The gate controls the inversion layer especially, whereas source and drain
control not only the inversion layer but also the regions below and near the
junctions.
Compact models derived from the Charge Sheet representation lend
themselves to better representations for gate-driven configurations than
source- and/or drain-driven.
It is possible to reconstruct I
D
(V
GS
) characteristics with less than 2 to 3 %
error with only three parameters n , I
s
and V
To
and a small-size polynomial (i)
rendering mobility degradation.
n, I
s
,V
To
and the coeffs of poly depend on V
DS
,V
SB
and L, not on V
GS.
7
13
Model Parameters n, V
To
, I
S
and poly
max slope
W.I. approx.
k <= 2 to 3
given V
DS
, V
BS
and L
a) ooo select data in weak-mod inv
b) extract param. n, V
T0
, I
S
c) +++ reconstruct I
Du
(V
G
)
d) find coeff. of fitting
polynomial theta(i(V
G
))
1.2 V low-power 90 nm technology
(by courtesy of IMEC)
reconstr. over exper. data
3d order polynomial fit
+ + +
theta(i(V
G
))
V
G
(V)
+ + + +
experim. data
selected data
reconstr. data
14
Parameter Extraction: n, V
To
and I
S
1) choose I
Du
(V
G
) in weak and moderate inversion
2) n max. of subthreshold slope
3) Iteratively find I
S
that minimizes variance of V
To
for
selected I
Du
s (I
D
for W = 1 m)
weak mod . inv . I
Du
V
G
( )
I
S 2
I
S1
I
Sn
I
S
V
To
threshold voltages
i =
I
Du
I
S
q = 0.5 1+ 4i 1
( )
V
p
=U
T
2 q 1 ( )+ log q ( ) ( )
V
p
=
V
G
V
To
n
V
To
I
S
8
15
Reconstructed I
D
(V
G
)
+ + + +
experim. data
selected data
reconstr. data
V
G
(V)
I
Du
=
i ( )
C
ox
W
L
2nU
T
2
i
16
Model Verification: I
Du
(V
GS
, V
DS
)
model
data IMEC
V
GS
(V)
V
GS
(V) V
DS
(V)
V
DS
(V)
L = 100 nm
I
Du
(compact model) / I
Du
(data IMEC)
error in % V
DS
(V)
V
G
S
(
V
)
9
17
Drain Current I
D
(V
DS
)
V
DS
(V)
L = 100 nm
L = 120 nm
L = 110 nm
I
D
(10
-4
A)
V
GS
= 0.8 V
V
SB
= 0 V
data IMEC
reconstr. data
V
DS
(V)
L = 100 nm
L = 110 nm
L = 120 nm
I
D
(10
-8
A)
V
GS
= 0.2 V
V
SB
= 0 V
(D.I.B.L.)
S.I.
W.I.
18
Model verification: g
m
/I
D
g
m
/I
D
(V
-1
)
V
G
= VGS + VSB (V)
V
SB
= 0 V
0.4 V
0.8 V
data IMEC
reconstr. (no mob degrad)
reconstr. (with mob degrad)
g
m
/I
D
(V
-1
)
I
D
(A) logscale
V
DS
= 0.6 V
L = 100 nm
10
19
Overview
Basic Equations
g
m
/I
D
Design Example
Opamp Design
Design Verification
Conclusion
20
Intrinsic Gain Stage Exploration Phase (1)
f
T
= 1 GHz
C = 1 pF
I
D
C
W/L
g
m
= 2f
T
C
I
D
=
g
m
g
m
I
D
|
\

|
.
|
W
L
=
I
D
I
Du
V
DS
V
SB
L
param q
i = q
2
+ q i ( ) I
Du
=
I
S
(i)
i
g
m
I
D
=
1
nU
T
1
q +1
1
i
i ( )
d i ( )
di
|
\

|
.
|

V
P
=U
T
2 q 1 ( )+ log q ( ) ( )
V
G
= nV
P
+V
To

n I
S
V
To
poly.
model
11
21
Intrinsic Gain Stage Exploration Phase (2)
I
D
(A)
W/L
V
GS
(V)
gain
W/L
V
GS
(V)
gain
I
D
(A)
L = 100 nm L = 160 nm
1000
100
10
1
0.1
0.01
V
DS
= 0.6 V
V
SB
= 0 V
W.I. S.I.
W.I. S.I.
num. synthesis from IMEC data
model driven synthesis
22
g
m
/I
D
methodology* is used to derive sizing and currents of the
desired circuit
g
m
/I
D
= f(I
D
/(W/L))
Relates g
m
, power, MOS geometry
Set source and drain voltages
Fixes n I
s
etc..
Allows the evaluation of g
m
/I
D
versus V
G
Choose current levels as independent variables
Derive I
D
and W/L of MOSFET
Design methodology
* F. Silveira, D. Flandre, and P. G. A. Jespers, A g
m
/I
D
Based Methodology for the Design of CMOS Analog Circuits and Its Application
to the Synthesis of a SOI Micropower OTA IEEE JSSC, vol. 31, pp. 1314 -1319, Sept. 1996.
12
23
Design Flow
*
Exploration phase (Matlab)
Capture circuit performance in analytical expressions
Apply proposed MOSFET estimation model with parameters n, Is, V
To
extracted for
target technology
Plot multi-parametric design space
Design phase (Constrained optimization in Matlab)
Use Matlab Optimization Toolbox to improve performance in selected design point
Selected objective function is optimized
under performance and bias constraints
Verification and Process centering phase (SPICE)
Uses foundry provided process data with simulation MOSFET model
Applies optimization for improving objective performance under constraints
Automated layout from sized schematic
* A. Vladimirescu, R. Zlatanovici and P. G. A. Jespers, Analog Circuit Synthesis using Standard EDA Tools, Proc. Int. Symposium on
Circuit and Systems, May 2006.
24
Overview
Basic Equations
g
m
/I
D
Design Example
Opamp Design
Design Verification
Conclusion
13
25
Design example: CMOS Miller opamp
M
1a,b
are sized based on the desired bandwidth
T
:
Non-dominant pole
NDP
and the zero
Z
-> phase
margin:
M
3a,b
have the same gate voltage as M
2
for
minimizing offset;
M
b
, M
4
and M
5
operate in strong inversion and are
sized to provide the desired current levels in the
differential pair and second stage;
The W/L of the transistors can be computed
from:
Inversion level i
1
for transistors M
1a,b
, and i
2
,
for M
2
, are taken as parameters
in the design space of equal area, gain and current-
supply curves
Transistors L vs. L
min
Symmetry and Matching
g
m1
=
T
C
m
1 ( )
NDP
= NDP
T
;
Z
= Z
T
2 ( )
M1a M1b
M3a M3b
M2
M4
M5
Mb
Ibias CL Cm
VDD
VSS
IN+ IN-
1
2
3
4
L
M1
=3* L
min
; L
M3
=7*L
min
; L
M2
= L
min
; L
M4
=3* L
min
; L
M5,Mb
=10* L
min
( ) ( ) (4)
2 2 1 3
L W I I L W
D D
=
( ) ( ) (5) 2
5 1 2 4
L W I I L W
D D
=
W
L
=
I
D
2 n V
th
2
C'
ox
1
i
3 ( )
26
Exploration phase
Performance space and initial sizing
Design tradeoffs between Gain, Supply
current and Area
Select:
Gain (GBW as
T
is set) = 84 dB
Supply current = 53 A
i
1
=2.9, i
2
=6 in a 0.25m technology
Resulting Wand Ls for this design point
Lead to min Area of 300 m
2
Did not take into account terminal voltages!
Gain [dB]
Supply Current [A]
Area [m
2
]
13.6
15
10.8
W (m)
1.75
0.25
0.75
L (m)
Mb
M5
M4
Transistor
10
10
15
W (m)
2.5
2.5
0.75
L (m)
M3a-b
M2
M1a-b
Transistor
Initial sizes:
14
27
Design phase
Constrained design optimization
Maximize GBW
Parameters: I
D1
, I
D2
, (W/L)
1
, (W/L)
2
, (W/L)
3
Constraints: DC, AC, transient, symmetry
Z
Z
T
Zero
NDP
NDP
T
Non-dominant pole
2I
D1
/ C
m
SR
min
Slew rate
T

min
Unity gain bw
V
GT5
+ V
GT1
V
DD
V
cm,max
V
T,p
M5 bias
V
GT4
V
DD
V
out,max
M4 bias
V
GT2
V
out,,min
M2 bias
V
GT1
V
cm,min
+ V
T,p
V
T,n
M1 bias
( )
(
(
|
|
.
|
\
|
= 1
2
exp log 2
/
2
L W K nU
I
nU V
p n T
D
T GT
28
Verification phase
SPICE verification with actual process parameters
Design objective:
Maximize Gain: 84 dB min
Main constraints
Unity-gain Bandwidth 10 MHz
Slew rate 1V/s
Phase margin 45
O
Matlab design matches simulated circuit within 10% except for f
T
Design point corresponds to both stages operating in moderate
inversion with (I
D
/I
S
)
1
= 2.9 and (I
D
/I
S
)
2
= 6
15
29
SPICE optimization
Simulated Gain, in dB, and Phase for the opamp output VDB(2), VP(2),
GBW (GHz)
fT (MHz)
Gain (dB)
ID2 (A)
ID1 (A)
Cm (pF)
(W/L)b
(W/L)4*
(W/L)3*
(W/L)2
(W/L)1
Parameter
693 303 127
26 16/12.5 15/9
89 91/87.7 84/83
328 18.5/28.6 60
2.6 1.54/1.55 4.5
0.2 0.26 1
1.95 13.79 10/2.5
86.5 82.48 15/0.75
1.13 1.87 13.6/1.75
49 22.4 15/0.25
136.5 13.85 10.8/0.75
Eldo
optimal
Matlab Initial value
* Derived based on Eq. (5) and (6)
SPICE (Eldo) Optimized
Matlab Optimized
Design
Initial Design Point
78.4
60.3
39.2
8.68e6
1.28e7
2.56e7
30
Conclusion
Design model based on charge-sheet is proposed
*
Good match with measurement with just a few parameters
MOSFET models for design differ from simulation ones
Need to be simple enough but accurate
Describe operation in all regions of operation
Contain very few parameters
Closer to physics
g
m
/I
D
methodology based on proposed model is exemplified
Automated design flow
Opamp synthesis using simple model is verified and improved by complete simulation
* P. G. A. Jespers, The gm/ID Methodology, a Synthesis Tool for Low-Voltage Analog CMOS Circuits , Springer, to be published spring 2007

01 Vladimirescu MOS-AK06

Enviado por

Dados do documento

Descrição original:

Direitos autorais

Formatos disponíveis

Compartilhar este documento

Compartilhar ou incorporar documento

Opções de compartilhamento

Você considera este documento útil?

Este conteúdo é inapropriado?

Direitos autorais:

Formatos disponíveis

01 Vladimirescu MOS-AK06

Enviado por

Direitos autorais:

Formatos disponíveis

1

Design and Simulation MOSFET

Você também pode gostar