V

T5
1.914V = V
T5
V
GS5
2 I
D5

K 1 V
DS5
+
( )

:=
V
T4
1.386V = V
T4
V
GS4
2 I
D4

K 1 V
DS4
+
( )

:=
K k'
W
L
= 400
mA
V
2
= Where V
T
V
GS
2 I
D

K 1 V
DS
+
( )

=
- Solve for V
T
:
W
L
20 =
W
L
2 I
D1

k' V
GS1
V
TO

( )
2
1 V
DS1
+
( )

= - From
0.05V
1
=
I
D2
I
D3
1
V
DS2
V
DS3
I
D2
I
D3

:=
V
GS2
V
GS3
= Therefore:
I
D3
I
D2
1 V
DS3
+
1 V
DS2
+
= - From cases 2 and 3:
V
TO
0.8V = V
TO
V
GS2
I
D1
I
D2
V
GS1

I
D1
I
D2
1
:= Hence:
V
BS
0 = & V
DS1
V
DS2
= Therefore:
I
D2
I
D1
V
GS2
V
T0

( )
2
V
GS1
V
T0

( )
2
= - From cases 1 and 2:
V
DS
V
GS
V
T
> - In all cases, the device is in saturation, i.e.:
k' 20
A
V
2
:= 1. Given the data in the following table for an NMOS transistor with
Calculate V
TO
, , , 2|
F
|, and W/L
97.350 Assignment #1 - Solutions
On the other hand, we can write:
V
T4
V
TO
2
F
V
SB4
+ 2
F

( )
+ =
V
T5
V
TO
2
F
V
SB5
+ 2
F

( )
+ =
This can be solved using iteration methods such as Newton's Method, Bisection search or
any computer solver using Matlab, Mathcad, etc...:
1 V :=
F
1V :=
Given
V
T4
V
TO
2
F
V
SB4
+ 2
F

( )
+ =
V
T5
V
TO
2
F
V
SB5
+ 2
F

( )
+ =

F
|

\
|
|

Find
F
,
( )
:=
0.7 V =

F
0.301V =
Solving the above equation for V
OL
:
I K
n
V
OL
5 V
T

V
OL
2

\
|
|

=
5V V
OL

R
= I
R
= I
D
= V
OL
0.26V :=
c) Calculate t
plh
, t
phl
, and t
p
t
plh
0.69 R C := t
plh
155.25ns =
For t
phl
we should calculate I
ave
I
C
I
D
I
R
=
V
out
5V := Hence V
DS
V
out
:= V
GS
5V :=
I
Dsat
k'
2
W
L
|

\
|
|

V
GS
V
T0

( )
2
1 V
DS
+
( )
:= I
Dsat
692.625A =
I
R
0A =
Therefore: I
C1
I
Dsat
:= I
C1
692.625A =
2. For the following NMOS inverter circuit, assume:
V
DD
5V := R 75k :=
W
L
3.6
1.2
= C 3pF :=
Use the following data for an NMOS transistor:
V
T0
0.743V := k' 19.6 10
6

A
V
2
:= 0.06V
1
:=
a) Discuss qualitatively why this circuit behaves as an inverter.
It Works as an inverter because:
if V
in
V
T
<
( )
(i.e. low), NMOS is off, I 0 = , V
out
5V = (i.e. high)
if V
in
is high (i.e. 5 V), NMOS is on, I 0 , V
out
5V I R = (i.e. low)
b) Find V
OH
and V
OL
For V
in
V
T
< --->V
OH
5V =
For V
in
V
OH
= 5V = , NMOS is in linear (or triode) mode
I
D
k'
2
W
L
|

\
|
|

V
GS
V
T0

( )
V
DS

V
DS
2
2

1
1
1
]

1
1
1
]
=
5V V
OL

2
=
then V
out
V
OH
= 5V = and I
Vdd
0 = P
s
0W =
V
DS
0.26V :=
I
D
k'
W
L
|

\
|
|

V
GS
V
T0

( )
V
DS

V
DS
2
2

1
1
1
]
:=
I
D
63.094A =
if V
in
V
OH
= then V
out
V
OL
=
and I
Vdd
63.1A = P
s
I
D
V
DD
:= P
s
0.315mW =
f) Calculate the dynamic power dissipation assuming that the gate is clocked as fast as
possible.
f
max
1
2 t
p

:= f
max
5.922MHz = V
swing
V
DD
V
OL
:=
V
swing
4.74V =
P
d
C V
swing
V
DD
f
max
:= P
d
0.421mW =
V
out
2.5V := Hence V
DS
V
out
:= V
GS
5V :=
I
Dlin
k'
W
L
|

\
|
|

V
GS
V
T0

( )
V
DS

V
DS
2
2

1
1
1
]
:= I
Dlin
442.029A =
I
R
V
out
R
:= I
R
33.333A =
Therefore: I
C2
I
Dlin
I
R
:= I
C2
408.696A =
I
ave
I
C1
I
C2
+
2
:= I
ave
550.66A =
Since C 3pF = is large, we ignore parasitics.
t
phl
2.5V C
I
ave
:= t
phl
13.62ns =
t
p
t
phl
t
plh
+
2
:= t
p
84.435ns =
d) Are the rising and falling delays equal? Why?
t
plh
>>t
phl
because R =75 k is much larger then the effective on-resistance of the NMOS.
e) Calculate the static power dissipation for: (i) Vin =0 V and (ii) Vin =5 V.
if V
in
V
OL
=