Chapter 1 - Analog Integrated Circuit Design by John Choma

LECTURE SUPPLEMENT #1 . . .
[LS #1]
CHAPTER #1

Two-Port And Basic
Amplifier Networks

Dr. John Choma
Professor of Electrical Engineering
University of Southern California
Ming Hsieh Department of Electrical Engineering
USC Viterbi School of Engineering
Los Angeles, California 900890271
2137404692 [USC Office]
2137408677 [USC Fax]
8183841552 [Cell]
johnc@usc.edu

PRELUDE:
In this chapter, we introduce the four fundamental architectures of linear analog
electronics; namely, the transconductance amplifier, the voltage amplifier, the
current amplifier, and the transresistance amplifier. In their idealized realiza-
tions, these four building blocks of analog electronics behave respectively as a
voltage controlled current source, a voltage controlled voltage source, a current
controlled current source, and a current controlled voltage source. Although
these idealized dependent sources are simple enough to encourage their introduc-
tion in a first course on linear circuits, their intended purpose for designing mod-
ern analog electronics can prove initially puzzling. To this end, this chapter
formulates general circuit modeling strategies and associated mathematical
techniques for analyzing analog electronic networks that exploit practical emula-
tions of the aforementioned four idealized generators. We shall then couch the
fruits of these analyses in forms that enable a realistic and meaningful assessment
of network characteristics, operational attributes, and input/output (I/O) response
shortfalls. A byproduct of this development is exposing the reader to several of
the metrics that commonly bracket the achievable performance of analog circuits.
May 2013
Chapter 1 Basic Amplifier Networks

- 2 -
1.1.0. INTRODUCTION
As we launch our journey into the world of electronic circuits, we should be mindful of
a few basic principles and facts. The first of these principles is that circuit design, and especially
the design of analog electronic networks, which process applied input voltages or currents as a
continuous function of time, is rarely a standalone discipline. Instead, circuit design is a venue
contrived to support the realization of practical electrical and electronic systems. Commercial,
military, and space sciences consumers do not buy circuits. Instead, these consumers purchase
and exploit practical systems whose desired input to output (I/O) functionality is determined by
the manner in which the circuits and subcircuits implicit to each system are designed, intercon-
nected, processed, and manufactured. The upshot of this fact is that circuit design cannot be
meaningfully accomplished without an awareness and a conceptual understanding of the opera-
tion of the system for which the design venture is targeted. Thus, for example, an amplifier
required of a cellular telephone is invariably designed differently than is an apparently analogous
amplifier destined for use in a medical sensing device.
A second fact underpinning the task of realizing an electronic circuit is that analog de-
sign is not the simple logical inverse of analysis. Specifically, design does not embrace the
straightforward problem of solving for the n unknown variables in a system whose I/O and
equilibrium characteristics are mathematically identified by n independent equations. A two-fold
complication surrounds this issue. The first is that our ability to write n independent mathemati-
cal equations for a circuit relies on our knowing the actual circuit deemed suitable for the design
project confronting us. But the first design step subsequent to system definition entails stipulat-
ing candidate circuit topologies that we feel can satisfy the I/O performance objectives implicit
to the system definition. For example, amplification of the applied input signal may be required
of a specific block within the considered system. But what kind of amplifier shall we use? To
answer this question, we must know if the input port of the amplifier is driven by a low imped-
ance voltage source or by a high impedance current source. We must also learn if the amplifier
is to drive a low or a high impedance load. Moreover, a knowledge of the maximum and mini-
mum amplitudes associated with the input signal is critical to the completion of the design task.
The latter information is pivotally important, for it establishes the requisite range of I/O linearity
that is consistent with the power dissipation budget allotted to the circuit whose design is our
responsibility. Yet another piece of information we need in order to solve the design puzzle re-
lates to the frequency spectrum implicit to the information carried by the input signal. Do the
frequencies associated with the input signal lie within a narrow band centered about a single, so-
called carrier, frequency or are these frequencies distributed over a broad passband? The
satisfactory resolution of these and other questions relies on our insightful understanding and
appreciation of the general operating characteristics, performance attributes, and performance
shortfalls of a broad sample space of plausible electronic circuit architectures.
Upon resolving the circuit topological choice appropriate to the design task, the most
typical design problem we will encounter is the quandary of having more specifications that must
be satisfied or more variables that need to be determined than there are independent equations
that we can write. Our ninth grade algebra teacher taught us that an algebraic problem for which
the number of unknowns does not equal the number of available independent equations has no
unique solution. We can then blame our algebra instructors for the simple fact that unique de-
sign solutions are rare; indeed, many solutions are generally conceivable. While the non-unique-
ness situation may be exasperating, it actually offers us opportunities to demonstrate engineering
creativity. As engineers, we are paid to innovate and create. We are not paid for our ability

- 3 -
albeit an impressive ability to write and tractably solve algebraic or differential equations.
Design creativity bubbles to the surface when our insightful understanding of fundamental circuit
and system concepts enables our recognition that an optimal solution is embedded among a set of
plausible design candidates. In other words, many of the possible design solutions may yield
workable systems, but some are better, perhaps in the senses of power dissipation, reliability,
manufacturing cost effectiveness, or feature size, than are others. The best of these design solu-
tions are rarely recognized with trial and error design strategies. Instead, optimal designs derive
from the fruits of phenomenological understanding. The task that is necessarily foundational to
this understanding is the conduct of thorough and physically sound mathematical analyses.
These analytical results, which should be ultimately supported and confirmed by computer-based
studies, highlight both the attributes and the limitations of the alternative circuit architectures that
we have explored. The requisite analyses are often premised on realistic approximations that al-
low for a lucid, albeit first order, explanation of results in terms of known physical laws and ba-
sic circuit and system concepts. We are therefore moved to suspect that in a design environment,
computational precision is not a core objective of circuit analyses. A realistically approximated
result that promotes clear conceptual perceptions has far more design value than does an exact
solution whose complicated nature masks satisfying comprehension. Stated succinctly, the
engineering design task does not end when we formulate mathematical disclosures of circuit res-
ponses. Instead, our engineering design task only starts with a mathematical delineation of these
responses. The task continues with the challenge to couch our solutions into forms that in-
sightfully illuminate characteristic advantages and disadvantages. In a word, the comprehension
and meaningful interpretation of analytical results facilitates intelligent and creative design.
Modern electronic systems, such as cellular telephones, iPods, medical monitoring and
sensing devices, and global positioning satellite (GPS) navigation equipment, are comprised of
interconnected mixed signal integrated circuit chips. Mixed signal circuits are integrated circuits
that combine both analog and digital signal processing. Digital circuits dominate the commer-
cial, military, and spacecraft electronics landscape because they offer flexible I/O functionality at
low power dissipation levels. Although operating flexibility may require digital subcircuits
containing thousands, if not millions, of transistors, modern semiconductor device technologies
enable the realization of these cells in very small integrated circuit surface areas (known as sur-
face footprint). But analog circuits, whose necessity is absolute because of the analog nature of
the world in which electronic systems communicate, arguably consume the most design time.
Despite the design time demands, analog cells utilize far fewer active devices than do their digi-
tal counterparts. One reason for the disproportionate level of digital and analog design efforts is
the increased system functionality and operating performance perpetually demanded by consum-
ers. These demands predispose design challenges in that analog networks utilized at the input
front end of a system must process input signals with widely divergent amplitudes, broad fre-
quency passbands, and diverse I/O impedances. A second reason underlying significant analog
design time is that unlike digital technologies, analog technologies have yet to gravitate to a stan-
dard cell design methodology. We shall learn that the myriad of decisions that must be made in
an analog circuit design exercise contributes to this lack of a standard cell methodology. While
the venerable operational amplifier, or op-amp, is a notable standard cell exception in analog cir-
cuit technology, the operational utility of most op-amps is largely limited to relatively low signal
frequencies. Unlike the gates, read only memories, random access memories and other switching
circuits pervasive of digital design initiatives, we are therefore compelled to live with the fact
that there are no standard design rules for radio frequency amplifiers, impedance converters,
oscillators, filters, analog -to- digital converters, and other high performance analog electronic

- 4 -
modules. The good news about the lack of standard cells is that electrical engineers who master
analog design skills are not likely to be usurped by computers and relevant design software.
Accordingly, analog designers remain in demand by industries, despite recessions that may pla-
gue general business economies.
As we suggested in the Prelude, most of the amplification circuits and all of the linear
analog electronic networks deployed in electronic systems are made up of four fundamental
architectures. The most commonly encountered of these four fundamental circuit types is the
transconductance amplifier, or more generically, the transadmittance amplifier. The electrical
properties of this cell emulate an ideal voltage controlled current source, or g
m
V generator.
The voltage amplifier ideally behaves as a voltage controlled voltage source, the current am-
plifier approximates a current controlled current source, and the transresistance, or transimped-
ance, amplifier mirrors a current controlled voltage source. For example and subject to the con-
straint of low signal frequency processing, the op-amp is a good approximation of an ideal
voltage controlled voltage source.
In this first chapter, we focus on the idealized and practical characteristics of these four
fundamental electronic subcircuits. We shall initiate the investigation of general amplifier
configurations by developing two-port network theories as a means of generalizing the behavior
of these amplifier modules and other linear circuits in terms of only the volt-ampere characteris-
tics that we can observe at their external terminals.
1.2.0. LINEAR TWO-PORT NETWORKS
When we design presumably linear amplifiers, we want the output signal voltage or
current response of an amplifier to be linearly related to the amplitude of the applied input signal,
can be either a voltage or current waveform. Since a linear network is incapable of producing
output frequencies that differ from those implicit to the input signal excitation, a linear network
ensures that the frequency spectrum, and thus the information content, of the output voltage or
current response preserves, without spectral modification, the information that is carried by the
original input signal. In other words, the output response to an input signal applied to a linear
system or circuit can be only an amplitude-scaled and invariably time-delayed version of the ap-
plied input. The delay to which we refer and about which we shall have far more to say later de-
rives from the fact that a physically realizable network burdens an input signal with unavoidable
electrical baggage in the form of energy storage elements (capacitances and/or inductances).
Since voltages across capacitances and currents conducted by inductances cannot respond
instantaneously to signal excitations, a network requires time to respond to and process applied
signals. But the core concept we should garner now is that after all transients manifested by the
sudden application of an input signal have subsided, which typifies so-called steady state opera-
tion, the frequency content of the output response of a linear network mirrors that of the ob-
served frequency spectrum of its input. We can therefore postulate that a linear amplifier does
not contaminate the information implicit to the input signal in the sense of creating an output fre-
quency spectrum, and thus information content, which differs from that embraced by the input
signal. In a stereo system, for example, linearity is a crucial design objective for we wish to hear
only that information that is burned on the compact disk we are playing. We do not wish the ste-
reo system to generate any frequencies on its own for to do so amounts to distorting the input
signal and the information that we ultimately wish to hear. Would we not be annoyed if our ste-
reo system made Mick Jagger sound like Donald Duck?

- 5 -
Unfortunately, we shall learn that achieving I/O linearity in electronic circuits is a
challenging undertaking because the transistors embedded within each of the four basic amplifier
blocks have nonlinear volt-ampere (V-I) characteristics. We know from basic circuit theory that
only one nonlinear branch element in a circuit that is otherwise comprised of interconnected li-
near branch elements renders an I/O response nonlinear. Accordingly, strictly linear I/O
relationships can never be guaranteed in practical amplifiers. But we can condition electronic
circuits targeted for linear signal processing applications to deliver nominally linear I/O res-
ponses. The foundation for this conditioning to which we allude is biasing. In turn, the key to
this biasing is the availability of one or more network ports, or pair of terminals, to which static
voltages or currents can be applied to force approximately linear I/O operation over at least a
constrained range of input signal amplitudes. Later in our travels, we shall deal with the design
of suitable biasing subcircuits.
In the electronic network abstraction of Figure (1.1a), the biasing to which the preced-
ing paragraph speaks is implemented by the two power supply voltages, V
aa
and V
bb
, which de-
liver currents i
aa
(t) and i
bb
(t), respectively, to the electronic network. In other network embodi-
ments, we may require only one of these two supplies, which are often realized as simple batte-
ries. In this initial consideration of electronic networks, these static sources of voltage are pre-
sumed ideal so that their Thvenin impedances are zero. Subsequently, however, we shall learn
that parasitic series resistance in the power supply lines can degrade circuit performance, while
parasitic series inductance can produce network instability.
A signal voltage, v
s
(t), whose Thvenin impedance is Z
s
and whose average value is
zero, is applied across the network input port formed of terminal pair [1-2]. In response to this
signal and the two biasing supplies, an output voltage, v
o
(t), is established across load impedance
Z
l
. As shown in Figure (1.1a), this load terminates the output port formed of terminal pair [3-4].
Corresponding to the output port voltage, current i
o
(t) flows through the load impedance.
Consider first the case of no applied input signal, which defines the quiescent state
(meaning a quiet network state in the sense of an absence of signal-related dynamics) of the
considered network. After the transients associated with switching on the power supply voltages
have died, as they ultimately will in stable networks, the resultant quiescent responses to the two
indicated biasing voltages are themselves constant voltages and currents that collectively define
the standby operating conditions of the network. In other words, these constant voltages and cur-
rents are the electrical responses we observe while we hang out waiting for an applied input sig-
nal. If the applied signal has zero average value, the application of v
s
(t) contributes nothing to
the quiescent state of the network. Thus, when signal v
s
(t) is null, which leaves static excitations
V
aa
and V
bb
as the lone sources of energy applied to the network, the resultant I/O port voltages
and currents ultimately assume their steady state values, V
iQ
, V
oQ
, I
iQ
, and I
oQ
. As we indicate in
Figure (1.1b), the power supply currents take on the standby values, I
aaQ
and I
bbQ
, which combine
with their respective applied voltages, V
aa
and V
bb
, to deliver a static network power dissipation
of (V
aa
I
aaQ
+ V
bb
I
bbQ
). Obviously, the numerical values of these standby currents are functions of
V
aa
and V
bb
. But in addition, these currents depend, invariably nonlinearly, on characteristics
presented to the electronic network by the static, or DC, volt-ampere curves of the transistors
embedded within said network. The nonlinear nature of the interrelationships that link quiescent
network voltages and currents to transistor parameters demands that we determine the static re-
sponse through a combination of approximate manual analysis and thoughtfully executed, com-
puter-based circuit simulations.

- 6 -
+
Electronic
Network
i (t)
i
i (t)
bb
i (t)
aa
v (t)
i
1
2
v (t)
o
3
4
i (t)
o
v (t)
s
Z
s
Z
l
(a).
V
b
b
V
a
a
Electronic
Network
I
iQ
I
bbQ
I
aaQ
V
iQ
1
2
3
4
I
oQ
Z
s
Z
l
(b).
V
b
b
V
a
a
+
Linear Model
Of Electronic
Network
i (t)
is
i (t)
bbs
i (t)
aas
v (t)
is
1
2
v (t)
os
3
4
i (t)
os
v (t)
s
Z
s
Z
l
Z
in
Z
out
(c).
V
oQ

Figure (1.1). (a). A general electronic network whose input signal port is formed of terminal pair [1-2]
and whose output load port is established by terminal pair [3-4]. Static voltages V
aa
and
V
bb
are applied to additional network ports to establish appropriate quiescent operating
conditions for the network. (b). The quiescent version of the network in (a); the input sig-
nal source set to zero. (c). The presumably linear model of the network in (a) under signal
conditions. With the power supply voltages short-circuited to ground, the input signal
voltage, v
s
(t), is applied to produce changes in the quiescent voltages and currents of all
ports. The metrics, Z
in
and Z
out
, respectively symbolize the steady state driving point input
and output impedances.

- 7 -
With V
aa
and V
bb
sustained at their required biasing levels, we can rationalize that the
immediate effects of an applied input signal, v
s
(t), are changes about the quiescent values of all
branch currents and all node voltages that are manifested prior to the application of v
s
(t). In
other words, if the time invariant, constant voltages, V
aa
and V
bb
, represent the only sources of
energy applied to the two-port network, all network branch currents and nodal voltages are
necessarily constant in the steady state. Resultantly, the sensible expectations of network res-
ponses to an applied input signal, v
s
(t), are perturbations to the aforementioned quiescent branch
and nodal variables, which renders these electrical variables functions of time. A necessary
condition underpinning approximate I/O signal response linearity is that we implement network
biasing to ensure that the Q-point values of all network branch currents and node voltages forged
with v
s
(t) = 0 be made independent of all signal-induced changes incurred by nonzero v
s
(t). If
we are successful in this endeavor, we can lean on linear circuit theory to determine the compo-
nents of all network responses that are induced exclusively by the input signal. In particular and
subsequent to determining all quiescent variables in the circuit, we can exploit classic superposi-
tion theory to investigate all electrical effects of the applied signal voltage by setting all power
supply voltages to zero. If linearity indeed prevails because of our biasing strategy, the nature of
this secondary analysis entails a linear circuit investigation. Implied by this second computa-
tional step is that the circuit transistors, which are inherently nonlinear beasts, be supplanted by
realistic linear models that attach validity to our superposition strategy.
We can elevate the preceding discourse by noting that if the quiescent voltages and cur-
rents of the considered network are independent of the responses produced by the applied signal,
v
s
(t), the variables indicated in Figure (1.1a) can be expressed in terms of those delineated in Fig-
ures (1.1b) and (1.1c) in accordance with the simple expressions,
o oQ os
o oQ os
v (t) V v (t)
,
i (t) I i (t)
= +
= +
(1-1)
i iQ is
i iQ is
v (t) V v (t)
,
i (t) I i (t)
= +
= +
(1-2)
and
aa aaQ aas
bb bbQ bbs
i (t) I i (t)
.
i (t) I i (t)
= +
= +
(1-3)
In the preceding three disclosures, subscript s signifies a voltage or current signal change in-
curred about a corresponding quiescent current or voltage. This observed change is, of course,
an exclusive result of the signal source that excites the input port of the network. For example,
i
os
(t) in (1-1) is the positive or negative current variation, [i
o
(t) I
oQ
], in net output port current
about the quiescent value of this branch current. Our biasing must be implemented in such a way
as to ensure that this current change does not influence the quiescent current, I
oQ
, (or any other
quiescent current or voltage in the considered network) and that it is identically zero when the
input signal, v
s
(t), is null. These stipulations are foundational to the use of superposition theory,
which (1-1) through (1-3) reflects.
In addition to ensuring the independence of quiescent network variables to the signal
components of these variables, our biasing subcircuit must also guarantee nominally linear
interrelationships among all perturbed voltage and current components. With reference to the
output port current perturbations, [i
o
(t) I
oQ
], signal linearity implies that [i
o
(t) I
oQ
] = gv
is
(t),
where the proportionality factor, g, is a constant, independent of v
is
(t). We further note that

- 8 -
parameter g must have conductance units so that the gods of dimensional consistency are ap-
peased. Despite this foregoing linearity assertion, we expect that net output voltage v
o
(t) in (1-1)
is not a linear function of v
i
(t) in (1-2). Our reasoning is that voltage V
oQ
is likely a nonlinear
function of V
iQ
because of the nonlinear nature of the transistors or other active elements dep-
loyed in the network. In particular, the nonlinear active devices within the electronic network
render V
iQ
and V
oQ
nonlinear functions of the power supply voltages, V
aa
and V
bb
, which bias the
network. But since the power supplies are constant voltages, V
oQ
and V
iQ
should be constant (at
least at a given operating temperature). The ability of the network in Figure (1.1) to process in-
put signals linearly within the foregoing constraints mandates that the adopted biasing scheme
guarantee the linear dependence of v
os
(t) on v
is
(t) and indeed, on every other signal component of
every branch current or node voltage in the network. Thus, for example, we insist that the signal
current flowing in the seventeenth branch of the network be linearly proportional to v
is
(t), to
v
os
(t), to the signal voltage established with respect to ground at the twenty-eighth circuit node,
and to the signal current conducted by the thirty-third network branch.
In due time, we shall appreciate the foregoing biasing assignment as a nontrivial exer-
cise requiring the satisfaction of a pivotally important operating requirement. Specifically, the
biasing to which we ultimately converge as circuit design engineers must be such that for all
operating conditions, every active device in the subject network is forced to operate in a reasona-
bly linear region of its volt-ampere characteristic curves. This stipulation implies that the nonli-
near DC characteristics of all utilized devices must exhibit well defined, if not constrained, re-
gions over which their observed static currents relate to their corresponding static device vol-
tages in a reasonably linear fashion. It is fortuitous that metal oxide semiconductor field effect
transistors (MOSFETs) and bipolar junction transistors (BJTs), which comprise the semiconduc-
tor foci of this text, do indeed exhibit restricted, but viable, quasi linear operating regions. The
quasi linearity requirement speaks to meaningfully representing the static V-I characteristics of a
transistor within our network by a linear Taylor series developed for the immediate neighbor-
hood of the quiescent operating point at which we choose to operate the transistor. If the
characteristic curves exhibit reasonable linearity at, and in the immediate vicinity of, the operat-
ing point, the second and all higher order derivatives of the Taylor series expansion of the device
V-I curve approach zero. The immediate result of this mathematical behavior is a Taylor series
that linearly approximates a device V-I characteristic in a restricted neighborhood of the operat-
ing point. We can presumably ensure that the excursions in device currents and voltages remain
within this region by restricting the amplitude of the applied input signal to a sufficiently small
value. The constraint imposed on input signal amplitude is why linear analysis of analog
electronics is commonly referred to as small signal analysis. But it should be understood that
our general ability to quantify small, is limited because such quantification depends on the de-
gree to which the aforementioned V-I curves are regionally linear.
Let us take the foregoing linearization scenario a step further. We learned in our first
circuits course that the analysis of a linear circuit produces a system of linear equations that de-
fine the equilibrium state of the circuit undergoing study. By equilibrium state, we refer to the
node voltage and/or branch current solutions that satisfy the system of equations for proscribed
input currents and voltages. It is reasonable then that if we can express the characteristics of a
device by linear equations that we deem to be sufficiently accurate for at least constrained values
of device voltages and currents, we should be able to produce a corresponding linear circuit.
This exercise, which is the inverse of circuit analysis, is the essence of device modeling. In
particular, we shall term the equivalent circuit we contrive as a small signal model of the consi-
dered device since its validity is limited to only suitably small input signals that force an active

- 9 -
device to operate over a confined, nominally linear, portion of the characteristics curves of the
device we are examining. Given that the model we deduce from the linearized Taylor series
expansion of the device volt-ampere characteristic pertains to only the immediate neighborhood
of the quiescent point at which the device operates, we naturally expect that the branch parame-
ters of the configured equivalent circuit are dependent on the operating point. This is to say that
different quiescent operating points are likely to produce different Taylor series coefficients at
these Q-points, which in turn affect the branch parameters of the small signal equivalent circuit.
And, of course, changes in the small signal model deliver changes in the small signal responses
whose dynamics we are attempting to understand.
We can now suggest that properly designed biasing gives rise to acceptable I/O re-
sponse linearity of an electronic network as long as the applied input signals confine the opera-
tion of all utilized transistors to an immediate neighborhood of their respective quiescent operat-
ing points. This linearization allows the exploitation of classic superposition theory with respect
to calculating both quiescent and dynamic network branch variables. Figure (1.1b) dramatizes
this contention by depicting quiescent network variables as deriving from the conditions of zero
applied signal and, of course, nonzero power supply voltages. Implicit to this circuit structure is
the presumption that the ultimately applied input signal does not alter any of the standby elec-
trical variables of the network.
Figure (1.1c) is the second part of the superposition game we are playing in that it
mathematically nulls the power supply voltages and applies only the input signal to a linear
model of the considered electronic network. By setting the power supply voltages to zero, we
are not ignoring these static voltages. Instead, we are replacing them with their small signal val-
ues. This allegation derives from the fact that a small signal response is merely a change in vol-
tage or current about a respective quiescent value. Since an ideal power supply voltage is a time
invariant constant, the small signal (or changing) values of voltages V
aa
and V
bb
in Figure (1.1a)
are necessarily zero. It follows that the resultant solutions arising from our analysis of the sys-
tem depicted in Figure (1.1c) are the signal-induced changes of all branch and node variables
about respective Q-points. Since these changes are linearly interrelated, we understand that the
indicated linearized network is a circuit containing only linear resistors, linear capacitors, linear
inductors, and linear controlled sources. We should expect the topology of this model to differ
from that of the original electronic network in Figure (1.1a) because its mathematical relevance
is limited to only a determination of incremental changes in network variables about their Q-
points. In other words, the linearized structure is equivalent to the original electronic
configuration only insofar as concerns the delineation of signal-induced increments in I/O port
variables about specified operating points.
In concert with the foregoing discussion, we offer Figure (1.2) as a simplified version
of the configurations of Figure (1.1). We understand that Figure (1.2) reflects only a linearized
model of the original two-port electronic network and therefore, it can give no information about
the quiescent branch variables of the network. Indeed, the parameters within the model of Figure
(1.2) rely on quiescent conditions ascertained previously. In a word, we cannot construct the
linearized model without knowing the network Q-point. The reason for this important fact is that
the parameters of the model we construct are functionally related to the equations we formulated
as linearized Taylor series expansions of device V-I characteristics about specified operating
points. Because of an exclusive focus on linear I/O transfer and impedance properties, the power
supply ports appearing in Figure (1.1) are omitted. Moreover, we herewith drop the time domain
notations of the applied signal source and all network electrical variables in favor of more conve-

- 10 -
nient peak, root mean square, or phasor designations. As in Figure (1.1), the input port is formed
by the terminal pair, [12], while the output port is the terminal pair, [34]. No energy sources
are contained within the two-port network, which implies that all network capacitors are initially
uncharged, and all network inductors conduct zero initial current. Signal energy is therefore ap-
plied to the linear two-port system at only its input port. In Figure (1.2a), we represent this sig-
nal energy by a Thvenin equivalent circuit comprised of the signal source voltage, V
s
, and its
internal series impedance, Z
s
. Alternatively, the applied energy can be modeled by Thvenins
technological cousin, Norton, where to keep things legal, the Norton, or short circuit, equivalent
input current, I
s
, is
+
Linear Model
Of Electronic
Network
I
1
V
1
1
2
V
2
3
4
I
2
V
s
Z
s
Z
l
(a).
I
1
I
s
1
2
V
2
3
4
I
2
Z
l
(b).
Z
s
V
1
Linear Model
Of Electronic
Network

Figure (1.2). (a). A linear model of a two-port network excited at its input port by a
signal source whose Thvenin voltage is V
s
and whose Thvenin imped-
ance is Z
s
. (b). The system in (a) with the signal source modeled by its
Norton equivalent circuit.
s s s
I V Z . = (1-4)
Because of the input signal excitation, we show a voltage, V
1
, established across the input port, a
current, I
1
, flowing into this port, a current, I
2
flowing into the output port, and a voltage, V
2
,
developed across the output port. Obviously, current I
2
and voltage V
2
are constrained by our
friend, George Ohm; namely,
2 2 l
I V Z . = (1-5)
It is important that we understand that voltage V
1
is the signal or phasor representation of the vol-
tage v
is
(t) in Figure (1.1c), while current I
1
is the phasor representation of current i
is
(t) in the
same figure. Similarly, voltage V
2
is in one to one correspondence with v
os
(t) in Figure (1.1c),
and current I
2
corresponds to i
os
(t).
For any linear two-port system, we can quantify the input and output impedance or
admittance and the I/O transadmittance, voltage gain, current gain, or transimpedance in terms of
model parameters. These parameters can derive from requisite Taylor series expansions applied
to the considered electronic circuit or system. Alternatively, we can deduce them strictly from
measurements performed at the network input and output ports. Interestingly, these impedance,
admittance, and transfer metrics can be quantified even if the circuit architecture implicit to the
two-port configuration of Figure (1.2) is unknown, inaccessible, or simply too messy for a tradi-
tional circuit analyses based on the Kirchhoff laws. Such a situation materializes, for example, if
the two-port network under investigation is an op-amp for which the manufacturer has elected

- 11 -
not to enrich our lives with a detailed schematic diagram. The upshot of the matter is that if we
find that jumping into the linear two-port box to play circuit analysis is impossible, impractical,
or simply too intellectually traumatic, we can determine the aforementioned performance indices
from only two equilibrium equations that we formulate. One of these equations focuses on the
input port, where the source energy, source impedance, and the input port variables, V
1
and I
1
,
are influential, while the other addresses the output port, where the load impedance and the out-
put port variables, V
2
and I
2
, prevail. Since only two equations in the four variables, V
1
, I
1
, V
2
,
and I
2
, can be written without diving into the box, the formulation of a unique network solution
requires that two of these four port variables be viewed as independent and the remaining two be
interpreted as dependent variables. A viable solution also requires that V
2
and I
2
abide by Ohms
law applied to the load termination, while V
1
and I
1
must be constrained by the source excitation
and source impedance. The selection of the independent and dependent variable sets is arbitrary,
subject to the proviso that the corresponding two-port model parameters that define the electrical
properties of the network can be meaningfully defined and measured.
EXAMPLE #1.1:
In order to illustrate the relevance of the Taylor series expansion to the small
signal modeling of a nonlinear element, consider the network in Figure (1.3a).
Under quiescent operating conditions, for which signal v
s
(t) = 0, the indicated
I/O port currents and voltages assume their Q-point values. The optimum
quiescent operating point for the considered network must be determined from
either a careful examination of the static characteristic curves, for which the
equations are given below, or from a study of relevant specification sheets
provided for the network by its manufacturer. Suppose that we converge to an
optimum Q-point that is defined by an input port and an output port voltage,
V
1Q
, and V
2Q
, respectively, and that these quiescent port voltages manifest a Q-
point input port current of I
1Q
and a corresponding output port current, I
2Q
. It
should be noted that these Q-point electrical variables are set and sustained in
the steady state by the battery voltages, V
ii
and V
oo
, which excite the input and
output network ports, respectively. With v
s
(t) = 0 we are advised that the
generalized, low frequency network volt-ampere relationships are

1 f T
1 e T
V n V
V n V
s b s
1
f f
I c I
I 1 1

e e
| |
| |
= +
|
|
|
\ .
\ .
(E1-1)
and

1 f T
V n V
2
2 s
a
V
I I 1 1 ,
V
e
| |
| |
| = +
|
|
|
\ .
\ .
(E1-2)
where
f
, n
f
, n
e
, c
b
, V
a
, and V
T
are known physical parameters that are indepen-
dent of the voltage and current variables observed at the network ports. De-
velop the small signal model of the network and use this model to formulate an
expression for the small signal voltage gain, A
v
= V
os
/V
s
, where V
os
is the small
signal component of the net output response, v
o
(t), and V
s
represents the ampli-
tude of the input signal voltage, v
s
(t).

- 12 -

V
ii

V
oo

+
Nonlinear
Electronic
Network
I
1
V
1
1
2
V
2
3
4
I
2
v (t)
s
v (t)
o
R
l
R
s
(a).

V
ii

V
oo

+
Nonlinear
Electronic
Network
I
1Q
V
1Q
1
2
V
2Q
3
4
I
2Q
0
V
2Q
R
l
R
s
(b).

Figure (1.3). (a). The basic nonlinear network addressed in Example (1.1).
(b). The nonlinear system in (a) under quiescent operating
conditions, for which the input signal, v
s
(t), is set to zero.
SOLUTION #1.1:
(1). We begin by finding the Taylor series expansion of (E1-1) about the presumably optimal Q-
point stipulated by input current I
1Q
and input port voltage V
1Q
. In the interest of clarity, all
quiescent port variables are delineated in the quiescent, or standby, model of Figure (1.3b).
Implicit to this latter diagram is the fact the network static characteristic curves, working in
exclusive concert with the battery voltages, V
ii
, and V
oo
, uniquely determine the I/O port
quiescent variables, I
1Q
, V
1Q
, I
2Q
, and V
2Q
.
If we retain only the linear terms in the Taylor series expansion of (E1-1), we obtain
( )
1
1 1Q 1 1Q
1
Q
I
I I V V .
V
c
= +
c
(E1-3)
The signal component, I
1s
, of the net input port current, I
1
, is
1s 1 1Q
I I I , = (E1-4)
while the signal component, V
1s
, of the corresponding net input port voltage, V
1
, is
1s 1 1Q
V V V . = (E1-5)
The derivative on the right hand side of (E1-3) is a constant since it is evaluated at the quies-
cent operating point of the network before us. Moreover, this derivative is necessarily dimen-
sioned in conductance units. Denoting said derivative by the inverse resistance, 1/r
i
, we find
that
1Q f T 1Q e T
V n V V n V
s b s
1
i 1 f f T f e T
Q
I c I
I 1
.
r V n V n V
e e
c
= = +
c
(E1-6)

- 13 -
The last three expressions collapse the linear Taylor series relationship in (E1-3) to the simple
Ohms law stipulation,
1s
1s
i
V
I .
r
= (E1-7)
(2). Moving on to (E1-2), the linear terms in its Taylor series expansion are those appearing in the
following equation:
( ) ( )
2 2
2 2Q 1 1Q 2 2Q
1 2
Q Q
I I
I I V V V V .
V V
c c
= + +
c c
(E1-8)
The signal component, V
2s
, of output port voltage V
2
is, in analogy to (E1-5),
2s 2 2Q
V V V , = (E1-9)
while the signal component, I
2s
, of output port current I
2
is
2s 2 2Q
I I I . = (E1-10)
We may now write (E1-8) in the form,
2s
2s m 1s
o
V
I g V ,
r
= + (E1-11)
where we understand that
1Q f T
V n V 2Q
s
2Q a
2
m
1 f T f T
Q
V
I 1
I V
I
g ,
V n V n V
e
| |
+
|
c
\ .
= = ~
c
(E1-12)
and
( )
1Q f T
V n V
s
2Q
2
o 2 a a 2Q
Q
I 1
I
I 1
.
r V V V V
e
c
= = =
c +
(E1-13)
While r
o
, like r
i
, is a resistance metric because the derivative from which it derives in (E1-13)
engages only an output port current (I
2
) and an output port voltage (V
2
), g
m
in (E1-12) does
not reflect a model resistance. Because the derivative from which g
m
derives uses an output
port current (I
2
) and an input port voltage (V
1
), g
m
is instead a measure of the degree to which
the input network signal voltage affects the network output port signal current. We term g
m
a
transconductance because in effect it has units of conductance and is a measure of the transfer
relationship between input port signal voltage and output port signal current variables.
Moreover, since the signal output port current flows through the load resistance, R
l
, which
terminates the network output port to establish the resultant output signal voltage of the sys-
tem, we might also view transconductance parameter g
m
as a measure of the achievable net-
work gain.
+
r
i g V
m is
V
is
+
r
o R
l
V
2s
+
V
os
R
s
V
s
I
1s
I
2s

Figure (1.4). The small signal (linear) model of the nonlinear network in Figure
(1.3a). The model is applicable for only sufficiently small signal excur-
sions about the input and output port quiescent operating levels.
(3). The linear equations in (E1-7) and (E1-8) give rise to the linear equivalent circuit provided in

- 14 -
Figure (1.4).
(4). An inspection of the small signal model in Figure (1.4) reveals immediately that
i
is s
i s
r
V V ,
r R
| |
=
|
+
\ .
(E1-14)
and
( )
os 2s m o l is
V V g r R V . = (E1-15)
The I/O voltage gain, A
v
, follows as
( )
os os is i
v m o l
s is s i s
V V V r
A g r R .
V V V r R
| |
= = =
|
+
\ .
(E1-16)
ENGINEERING COMMENTARY:
The purpose of circuit analysis is more than the delineation of accurate and meaningful cir-
cuit and system performance results. In addition to serving as the basis for exacting computer
aided investigations, circuit analysis is conducted primarily in the hope that the analytical re-
sults deduced convey physical and/or design insights that foster the realization of reliable,
reproducible, and cost effectively manufacturable, high performance networks and systems.
To this end, we need to talk about the foregoing disclosures.
Among the first of our observations is the negative sign that appears in the voltage gain
expression of (E1-16). This negative sign is not an algebraic quirk. It indicates that phase
inversion prevails between the applied signal and the output response manifested by this input
signal. By phase inversion is meant that as the input signal, v
s
(t), rises with time, the output
voltage, v
o
(t), diminishes, and vice versa. This phase inversion property is easily confirmed
by a study of Figure (1.3a) in view of (E1-1) and (E1-2). In Figure (1.3a), we observe that
when the signal, v
s
(t), rises with time t, the input port voltage, V
1
, can be expected to increase.
But when voltage V
1
increases, so does the output current, I
2
, as per (E1-2). Figure (1.3a)
also projects that V
2
= V
oo
I
2
R
l
, so that for constant V
oo
, an increase in current I
2
fosters a
decrease in output port voltage V
2
. Since voltage V
2
is identical to the output voltage v
o
(t), we
conclude that the phase inversion property reflects the logic that an increase in signal v
s
(t)
produces a decrease in response v
o
(t). A converse exercise premised on a decrease in v
s
(t) is
easily shown to result in an increase in v
o
(t).
A second observation is that the magnitude of the voltage gain advanced by (E1-16) is
proportional to the transconductance parameter, g
m
. These observations conflate with our
original declaration that g
m
, while certainly not the gain itself, is a measure of the achievable
circuit gain. We also note that the gain is reduced by the voltage divider formed between
model parameter r
i
and signal source resistance R
s
. From Figure (1.4), r
i
is clearly the input
resistance of the amplifier and consequently, we conclude that an input resistance that is
significantly larger than the source resistance promotes maximal voltage gain.
Couching the model resistances and transconductance in terms of the physical parameters
that define the volt-ampere curves of the considered electronic network enjoys an engineering
advantage over discerning these parameters from measurements alone. In particular, the
physical basis of model parameters enables us to relate design requirements to hopefully
controllable physical considerations. To wit, we have already determined that a large input
port resistance, r
i
, facilitates maximal voltage gain. From (E1-6) and (E1-1), we note, for
example, that large
f
supports large r
i
. In the same equation, we also see that small V
iQ
,
which by (E1-1) yields correspondingly smaller quiescent input port current, also gives rise
to large r
i
.
An overriding consideration is that the model used to study the nonlinear network is predi-
cated on the validity of representing the static characteristic curves of the network by only the
linear terms in the pertinent Taylor series expansions. The model in Figure (1.4), can be ex-

- 15 -
pected to deliver reasonably accurate linear relationships among all of its branch currents and
all of its node voltages if and only if a critically important operating condition is imple-
mented and sustained over time. Specifically, the signal excursions, or swings, I
1s
, I
2s
, V
1s
,
and V
2s
must be confined to a nominally linear region about their respective quiescent levels,
which are I
1Q
, I
2Q
, V
1Q
, and V
2Q
. For most practical electronic networks, this restriction in sig-
nal-induced current and voltage swings is small in comparison to the corresponding Q-point
levels, which is why a linearized equivalent circuit deduced from truncated Taylor expan-
sions is dutifully referred to as a small signal model. Since no small signal model can per-
fectly replicate the signal dynamics of a nonlinear network, the analytical results deduced
with the aid of small signal modeling are unavoidably approximate. It is therefore necessary
to support these inherently approximate manual circuit and system analyses with appropriate
computer-based simulations executed in both the time and the frequency domains. In other
words, the manual analysis of an electronic network must be viewed as a precursor to defini-
tive computer aided analyses. These manual analytical endeavors provide us with the in-
sightful understanding that fosters the intelligent, design-oriented use of circuit simulation
software.
1.2.1. SHORT CIRCUIT y-PARAMETERS
If we select the input port and output port voltages, V
1
and V
2
, respectively, as indepen-
dent variables in either of the generalized configurations of Figure (1.2), the linear two-port
model we contrive is termed the short circuit admittance parameter, or simply y-parameter,
equivalent circuit of the generalized network. Designating voltages V
1
and V
2
as the independent
variables of our model leaves us no choice but to view the input port current, I
1
, and the output
port current, I
2
, as dependent variables of our analysis. Since the volt-ampere characteristics of
the two-port network model undergoing scrutiny are linear because of prudent biasing efforts and
our presumption of only sufficiently small, signal-induced, changes about respective Q-points,
each of the dependent variables of our small signal analysis is a linear superposition of the ef-
fects of each of the independent variables. This observation gives rise to input and output port
relationships of the form,
1 11 1 12 2
2 21 1 22 2
I y V y V
,
I y V y V
= +
= +
(1-6)
where the y
ij
are constants, independent of voltages V
1
and V
2
. These constants have units of
admittance (mhos or siemens). Equation (1-6) can be compacted into the matric form,
1 11 12 1
2 21 22 2
I y y V
.
I y y V
( ( (
= = =
( ( (

I YV (1-7)
Although the short circuit admittance parameters, y
ij
in (1-6) and (1-7), are independent of the
signal voltages, V
1
and V
2
, and the signal currents, I
1
and I
2
, it is important for us to respect the
fact that they are functionally dependent on the quiescent network variables for which we have
deduced the linear model in Figure (1.2). Stated more precisely, the y
ij
characterize the nomi-
nally linear volt-ampere properties of the original (nonlinear) two-port electronic network in only
the immediate neighborhoods of predetermined input and output Q-points. Therefore, for prac-
tical electronics, we must be mindful that the linear superposition relationships in (1-6) and (1-7)
are meaningful only for sufficiently small values of the independent voltage variables, V
1
and V
2
.
Recall our assertion to the effect that the analysis of linear circuits produces a linear
system of equations, and conversely, a set of linear equations corresponds to the existence of a
linear network. To this end, (1-6) gives rise to a y-parameter model of the linear two-port net-

- 16 -
work in Figure (1.2) that is the structure offered in Figure (1.5). We must understand two pivotal
issues about this model. The first of these is that the individual y
ij
appearing in the model can be
determined to ensure that the model delivers accurate, small signal volt-ampere relationships at
both its input and output ports. No such solutions, accurate or otherwise, can be postured with
respect to internal branch currents and node voltages because despite analytical accuracy at the
I/O ports, the topology of the equivalent circuit does not embody the physical phenomenology
implicit to the original network. This contention asserts little more than the obvious fact that if
we were to jump into the network box, we would not see a simple branch admittance shunting a
controlled current source connected across both the input and output ports. In short, the model is
neither physically sound nor topologically true, but it is behaviorally correct in that it delivers
meaningful small signal electrical relationships at the input and output ports. The second issue
surrounding Figure (1.5) is that the model in Figure (1.3) mirrors what we presumably learned in
our first circuits course. In particular, we were taught that any port of a linear circuit can be
represented electrically by either a Thvenin or a Norton equivalent circuit. To this end, recall
that the Thvenin and Norton models for a simple one port are cast in terms of independent elec-
trical network variables. We see in Figure (1.5) that the input and output port models reflect
Norton equivalent circuits at these ports. Specifically, the Norton dependent generator, y
21
V
1
,
shunting the output port and the Norton input port current, y
12
V
2
, are respectively proportional to
the variables, V
1
and V
2
, which are the independent electrical variables in the y-parameter
formulation of the two-port network model. Both of these controlled sources are shunted by
admittances. We can take this observation as implying that in general, the I/O ports of linear net-
works can be modeled by non-ideal current sources, albeit non-ideal controlled current sources.
Linear Model
Of Electronic
Network
I
1
I
1
y V
12 2
1
1
2
2
V
2
V
2
3
3
4
4
I
2
I
2
1/y
11
V
1
V
1
y V
21 1
1/y
22

Figure (1.5). The short circuit admittance, or y-parameter, equivalent circuit
of a linear two-port network. All of the admittance parameters,
y
ij
, are in units of mhos.
Measurement procedures for the admittance parameters derive directly from (1-6) or (1-
7). For example, if the output port signal voltage, V
2
, which is developed across the output port,
is clamped to zero, which corresponds to the short circuited output port depicted in the linearized
system of Figure (1.6a),
2
2
1
11
1
V 0
2
21
1
V 0
I
y
V
.
I
y
V
=
=
=
=
(1-8)

- 17 -
Linear Model
Of Electronic
Network
1
2
V = 0
2
3
4
I = y V
2 21 1
(a).
V
1
S
h
o
r
t
C
i
r
c
u
i
t
S
h
o
r
t
C
i
r
c
u
i
t
1
2
V
2
3
4
I = y V
2 22 2
(b).
V = 0
1
I
d
e
a
l

T
e
s
t
V
o
l
t
a
g
e

S
o
u
r
c
e
I
d
e
a
l

T
e
s
t
V
o
l
t
a
g
e

S
o
u
r
c
e
I = y V
1 11 1
I = y V
1 12 2
Linear Model
Of Electronic
Network

Figure (1.6). (a). Measurement of the short circuit admittance parameters, y
11
and y
21
.
(b). Measurement of the short circuit admittance parameters, y
22
and y
12
.
It follows that y
11
is the short circuit (meaning that the output port is a short circuit) input admit-
tance of the two-port undergoing examination, while y
21
designates the forward short circuit
transadmittance. Thus, y
11
is a particular value of the network input admittance that corresponds
to the special case of a short circuited termination imposed on the network output port. On the
other hand, y
21
, which is commonly called the short circuit forward transadmittance of a linear
two-port network, is a measure of the forward gain of the network. It stipulates a value for the
output port current corresponding to a given input port voltage. In view of the fact that a short
circuited load termination is conducive to maximal output port current, y
21
can be viewed as
defining the maximum forward transadmittance. Because the short circuit output current is
y
21
V
1
, parameter y
21
can also be referred to as the Norton I/O transadmittance.
Before proceeding further, it is crucial that we appreciate the implication of the fore-
going short circuit nomenclature. In particular, an output short circuit in the present context
implies only a null output signal; that is, v
os
(t) = 0. From (1-1), this constraint means that the
output voltage in the actual network (as opposed to the linearized model of the network) is, in
general, nonzero and held fixed at its quiescent level, V
oQ
. A simple way of establishing such a
fixed voltage is to connect a capacitor directly across the output port. If this capacitor is suffi-
ciently large to approximate a short circuit for the signal frequency associated with the test signal
source applied at the network input port, it charges to the constant voltage, V
oQ
, thereby sustain-
ing v
os
(t) = 0. In the steady state, the appended capacitor sustains the requisite constant output
voltage without drawing steady state biasing current from the network under test, thereby allow-
ing for a y-parameter characterization under true quiescent operating conditions.
With V
1
= 0, which reflects the short circuited input port diagrammed in Figure (1.6b),
(1-6) yields
1
1
2
22
2
V 0
1
12
2
V 0
I
y
V
.
I
y
V
=
=
=
=
(1-9)
As in the case of the output port, the short circuit signal requirement, V
1
= 0, corresponds only to

- 18 -
the condition, v
is
(t) = 0, in (1-2) or equivalently, v
i
(t) = V
iQ
. Parameter y
22
is the short circuit
(meaning that the input port is short circuited) output admittance of the considered network. It is
the actual output admittance observed under the special case of a short circuit imposed at the in-
put port. On the other hand, the parameter, y
12
, is termed the reverse transadmittance, or the y-
parameter feedback factor, of a two-port network. It is literally the maximum possible, or
Norton, reverse transadmittance since the condition, V
1
= 0, maximizes current flow around the
input port.
A two-port network, and particularly an active two-port network, is naturally thought of
as a system capable of delivering very large y
21
so that maximal output signal is generated in re-
sponse to input port excitation. But an electrical or electronic network generally returns, or feeds
back, a portion of the output response to the input port. Feedback can also be manifested by the
electrical nature of the package in which the electronic circuit is embedded. Feedback can be an
undesirable phenomenon, as in the case of packaging anomalies and relevant capacitances asso-
ciated with bipolar and MOS technology transistors that operate at high signal frequencies. It
can also be a specific design objective, as when feedback paths are appended around active
subcircuits to condition overall circuit response. Regardless of the source of network feedback,
parameter y
12
is its measure in a y-parameter assessment of the I/O performance of a linear net-
work.
An alternative interpretation of y
12
is that of an isolation factor between output and in-
put ports. To this end, y
12
= 0 reflects perfect isolation, which implies that the voltages and cur-
rents at the input port are not affected by electrical phenomena occurring at the output port. On
the other hand, large y
12
infers poor isolation, or significant internal feedback, from the output
port to the input port. In an attempt to clarify these assertions, return to (1-6) to solve for the ra-
tio, I
1
/V
1
, which is literally the driving point (driving point means an actual load incident with
the network output port) input admittance of the subject network. In particular,
1 2
11 12
1 1
I V
y y .
V V
| |
= +
|
\ .
(1-10)
In this expression, the ratio, V
2
/V
1
, of independent network variables is the forward voltage trans-
fer ratio, or voltage gain, between the input port and the output port of the circuit at hand. For a
given input voltage V
1
, this gain is certainly influenced by the load termination, across which the
output signal voltage, V
2
, is established. For example, a short circuited load necessarily renders
V
2
= 0, whereby (1-10) confirms a driving point input admittance that is identical to y
11
, which is
dependent on only an internal network model parameter. Moreover, the V
2
= 0 value of admit-
tance I
1
/V
1
is assuredly independent of output port electrical variables. But we garner the same
admittance result, namely I
1
/V
1
= y
11
, when y
12
= 0. Evidently, y
12
= 0 decouples, or isolates, the
output and input ports. Such decoupling or isolation of the network input port means the input
port signal voltage and current do not respond to any output port signal voltage changes that may
be induced by load impedance fluctuations, spurious signal coupling, or other undesirable elec-
trical phenomena.
In an electronic system, it is generally desirable to achieve |y
21
| >> |y
12
|; that is, the
magnitude of the maximum possible forward transadmittance is much larger than the magnitude
of the maximum reverse transadmittance. This design objective is clearly satisfied when the I/O
ports are perfectly isolated, in which case the subject two-port becomes known as a unilateral
network. The term, unilateral, refers to an ability of a network to propagate signal between I/O
ports in only one direction; in this case, from the input port to the output port. A passive net-
work, on the other hand, has y
21
= y
12
. Any linear network for which y
21
= y
12
is said to be bila-

- 19 -
teral, which means that signal can be propagated from input to output ports just as easily as it can
be transmitted in the reverse direction. All passive linear networks, which are structures whose
topologies are electrical interconnections of only linear resistors, linear capacitors, and/or linear
inductors, are bilateral constructions. But the electrical behavior of certain types of electronic
configurations closely approximates that of a unilateral circuit.
1.2.1.1. Alternative y-Parameter Model
An alternative to the y-parameter equivalent circuit of Figure (1.5) can be constructed.
This alternative is interesting in that it underscores the significance of parameter y
12
as a feed-
back metric for the frequently encountered situation in which a common terminal prevails be-
tween the input and output ports. The subject three terminal two-port is the system diagrammed
in Figure (1.7a). The alternate model for this structure derives from writing (1-6) in the algebrai-
cally equivalent form,
( ) ( )
( ) ( ) ( )
1 11 1 12 2 11 12 1 12 1 2
2 21 1 22 2 21 12 1 22 12 2 12 2 1
I y V y V y y V y V V
.
I y V y V y y V y y V y V V
= + = +
= + = + +
(1-11)
Linear Model
Of Electronic
Network
I
1
I
1
1
1
2
2
V
2
V
2
3
3
4
4
I
2
I
2
1/y
i
1/y
r
V
1
V
1
y V
f 1
1/y
o
(b).
(a).
I
1
1
2
V
2
3
4
I
2
V
1
(c).
1/y
i
1/y
o
1/y
o
1/y
r

Figure (1.7). (a). Three terminal linear two-port network for which nodes 2 and 4 are common to one another.
(b). Alternative -type form of a y-parameter equivalent circuit for a three terminal, linear two-port
network. (c). The model of (b) for the special case of a bilateral, three terminal linear network.
Upon introduction of the ancillary admittances,
i 11 12 f 21 12
r 12 o 22 12
y y y y y y
,
y y y y y
+
+

(1-12)
(1-11) becomes expressible as
( )
( )
1 i 1 r 1 2
2 f 1 o 2 r 2 1
I y V y V V
.
I y V y V y V V
= +
= + +
(1-13)
These relationships are the equilibrium port equations for the -type topological structure in Fig-
ure (1.7b). Note therein that parameter y
r
, which is little more than the negative of y-parameter
y
12
, appears as a feedback element that connects the output port to the input port. Of course, the
model element, y
r
, is also capable of transmitting signal from the input port to the output port.
This capability is the reason underlying an effective forward transadmittance, y
f
, which is the

- 20 -
original forward transadmittance, y
21
, modified algebraically by an amount, (y
12
= y
r
). To the
extent that |y
21
| >> |y
12
|, the forward transmission through the circuit feedback element pales in
comparison to the forward transmission effected by the controlled generator, y
f
V
1
.
For the special case of a bilateral network for which y
21
= y
12
, y
f
in (1-12) is zero. For
this case, we can collapse the model in Figure (1.5b) to the passive configuration offered in Fig-
ure (1.7c).
EXAMPLE #1.2:
Determine the short circuit admittance parameters, y
ij
, and the t-model admit-
tance parameters, y
i
, y
o
, y
r
, and y
f
, for the linear, bilateral circuit given in Figure
(1.8).
I
1
1
2
V
2
3
4
I
2
Z
c
Z
a
V
1
Z
b

Figure (1.8). The bilateral two-port network addressed in Example (1.2).
SOLUTION #1.2:
(1). The determination of the admittance parameters, y
11
and y
21
, requires that a short circuit be
imposed across the output port of the subject network, as diagrammed in Figure (1.9a).
Recalling (1-8), an inspection of Figure (1.9a) reveals
(a).
I
1
1
2
V
2
3
4
I
2
Z
c
Z
a
V
1
Z
b
S
h
o
r
t
C
i
r
c
u
i
t
(b).
I
1
1
2
3
4
I
2
Z
c
Z
a
Z
b
S
h
o
r
t
C
i
r
c
u
i
t V
=

0
2
V

=

0
1

Figure (1.9). (a). Equivalent circuit pertinent to the evaluation of the admittance parameters, y
11
and y
21
, for
the network in Figure (1.6). (b). Equivalent circuit pertinent to the evaluation of the admit-
tance parameters, y
22
and y
12
, for the network in Figure (1.8).
2
1
11
1 a b c
V 0
I 1
y ,
V Z Z Z
=
= =
+
(E2-1)
while
2 2
c 2 2 1
21
1 1 1 b c a b c
V 0 V 0
c
a b a c b c
Z I I I 1
y
V I V Z Z Z Z Z
Z
.
Z Z Z Z Z Z
= =
| | | |
= = =
| |
|
+ +
\ .\ .
=
+ +
(E2-2)
(2). Parameters y
22
and y
12
require a short circuit at the input port. Figure (1.9b) is the applicable
model and by (1-9),

- 21 -
1
2
22
2 b a c
V 0
I 1
y ,
V Z Z Z
=
= =
+
(E2-3)
and
1 1
c 1 1 2
12
2 2 2 a c b a c
V 0 V 0
c
a b a c b c
Z I I I 1
y
V I V Z Z Z Z Z
Z
.
Z Z Z Z Z Z
= =
| | | |
= = =
| |
|
+ +
\ .\ .
=
+ +
(E2-4)
(3). Appealing to (1-12), we find that the subsidiary admittance parameters are
( ) ( )
( ) ( )
b b
i 11 12
a b a c b c b c a b c
c
r 12
a b a c b c
f 21 12
a a
o 22 12
a b a c b c a c b a c
Z Z
y y y
Z Z Z Z Z Z Z Z Z Z Z
Z
y y
Z Z Z Z Z Z
.
y y y 0
Z Z
y y y
Z Z Z Z Z Z Z Z Z Z Z
= + = =
+ + + +
= =
+ +
= =
= + = =
+ + + +
(E2-5)
The network addressed in this example is passive and therefore bilateral structure. It is
consequently hardly surprising that parameters y
12
and y
21
are identical, whence an effective
forward transadmittance, y
f
, of zero is realized.
An inspection of the network in Figure (1.8) suggests immediately that impedance Z
c
func-
tions as the feedback vehicle for coupling the volt-ampere characteristics of the output port to
those of the input port. For example, if Z
c
= 0, voltage V
1
is simply Z
a
I
1
, which is indepen-
dent of output variables V
2
and I
2
. Similarly, with Z
c
= 0, V
2
= Z
b
I
2
, which is independent of
input port variables. Thus, the no feedback condition arising from a short circuited imped-
ance, Z
c
, serves to isolate the input and output ports of the network. we observe that among
the four short circuit admittance parameters, only parameter y
12
vanishes when Z
c
= 0.
Accordingly, and as we might have expected, Z
c
= 0 achieves the zero feedback condition
typified by null y
12
, and hence, null y
r
.
EXAMPLE #1.3:
Two-port models and parameters are most utilitarian when they are applied to li-
near models of such active networks as amplifiers. To this end, consider the cir-
cuit in Figure (1.10), which diagrams an approximate linear model of an am-
plifier realized in MOSFET technology. Determine the short circuit admittance
parameters of this model, the alternative admittance parameters, and the model
implied by the alternative admittance metrics.

- 22 -
C
1
C
2
+

V g V
m
R
g V sC V
m 1
+
I
2
V
2
V
1

Figure (1.10). The non-bilateral, active two-port network ad-
dressed in Example (1.3).
SOLUTION #1.3:
C
1
C
x
C
2
C
2
+

V g V
m
R
R
g V sC V
m 1
+
I
2
I
2
V = 0
2
V
2
V
1
V
1
S
h
o
r
t
C
i
r
c
u
i
t
(a).
(c).
C
1
C
2
+

V g V
m
g V
x 1
R
g V sC V
m 1
+
I
2
V
2
S
h
o
r
t
C
i
r
c
u
i
t
(b).
V = 0
1
1 + sRC
x
C
1
C
2
+

V g V
m
R
I
2
V
2
V
1
1
x
m
m
x
m
C
C
1 g R
g
g
1 g R
=
+
=
+

Figure (1.11). (a). Equivalent circuit pertinent to the evaluation of the admittance parameters, y
11
and y
21
, for the
network in Figure (1.8). (b). Equivalent circuit pertinent to the evaluation of the admittance
parameters, y
22
and y
12
, for the network in Figure (1.8). (c). Alternative two-port equivalent circuit
for the original network in Figure (1.8).
(1). Figure (1.11a) depicts the network of Figure (1.10) under the condition of a short circuited
output port. In view of the fact that resistance R must conduct a current of (g
m
+ sC
1
)V, as is
indicated in the diagram, the input port voltage, V
1
, is necessarily related to voltage V. In
turn, voltage V functions as the controlling variable for the controlled current source, g
m
V.
From Figure (1.11a),
( )
1 m 1
V V V g sC R , = + + (E3-1)
whence

- 23 -
( ) ( )
1
m x
V
V ,
1 g R 1 sRC
=
+ +
(E3-2)
with the understanding that the effective capacitance, C
x
, is the degenerated capacitance given
by
1
x
m
C
C .
1 g R
=
+
(E3-3)
(2). In order to compute the short circuit admittance parameters, y
11
and y
21
, a short circuit must
be imposed across the network output port, as is diagrammed in Figure (1.11a). Since the in-
put port current, I
1
, satisfies
1 1 2
I sC V sC V , = + (E3-4)
the use of (E3-2) results in
2
x 1
11 2
1 x
V 0
sC I
y sC .
V 1 sRC
=
= = +
+
(E3-5)
On the other hand, the output port current, I
2
, is
2 m 2
I g V sC V , = (E3-6)
whence (E3-2) delivers
2
x 2
21 2
1 x
V 0
g I
y sC ,
V 1 sRC
=
= =
+
(E3-7)
where the effective forward transconductance at low signal frequencies is
m
x
m
g
g .
1 g R
=
+
(E3-8)
(3). Admittance parameters y
22
and y
12
derive from an analysis of the model offered in Figure
(1.11b), which is the original network of Figure (1.10) with the requisite short circuit im-
posed across the network input port. Since (E3-2) is a general relationship applicable for any
input or output port termination, V
1
= 0 remands control voltage V to zero. Accordingly, the
short circuit value of the output port current is simply I
2
= sC
2
V
2
, thereby implying a purely
capacitive short circuit output admittance of
1
2
22 2
2
V 0
I
y sC .
V
=
= =
(E3-9)
Moreover, the input port current, I
1
, with V
1
, and therefore V, equal to zero is I
1
= sC
2
V
2
,
whence a purely capacitive feedback transadmittance of
1
1
12 2
2
V 0
I
y sC .
V
=
= =
(E3-10)
(4). Appealing to (1-12),
x
i 11 12
x x
r 12 2
x
f 21 12
x
o 22 12
sC 1
y y y
1 sRC R 1 sC
y y sC
.
g
y y y
1 sRC
y y y 0
= + = =
+ +
= =
= =
+
= + =
(E3-11)
Referring to the generalized y-parameter circuit model shown in Figure (1.5a), the last result

- 24 -
postures Figure (1.11c) as a valid equivalent circuit for the network of Figure (1.8).
It should be noted that the controlled source in the original network is directly proportional to
the intrinsic branch voltage, V, which has no immediate analytical significance. In contrast,
the controlled source at the output port of the equivalent circuit deduced in Figure (1.11c) is
directly proportional to the input port voltage, V
1
, whose value is intimately related to the ap-
plied input signal.
Apart from its analytical convenience, the subject transformation of the controlled output port
generator reveals at least two interesting network characteristics that are not immediately re-
flected by the original network. First, observe that the effective forward transconductance at
low frequencies is g
x
, which is reduced, or degenerated, from the original value of g
m
by the
potentially significant factor, (1+g
m
R). In other words, the effective forward transconduc-
tance, which is a measure of the achievable input port to output port gain of the amplifier
modeled by the architecture in Figure (1.8), is substantively attenuated by the presence of
resistance R. Second, note that the magnitude of the effective transconductance is reduced
further at high signal frequencies owing to the time constant, RC
x
. Fortunately, capacitance
C
x
is smaller than the original input port capacitance, C
1
, by a factor of (1 + g
m
R), but
nonetheless, the magnitude of effective forward transconductance is unavoidably reduced for
very high frequencies. In effect, the ability of the original network to supply gain over a
broad frequency passband is compromised by intrinsic network capacitance and specifically,
by the time constant established by this capacitance.
While the reduction in forward transconductance witnessed in (E3-8) comprises the achieva-
ble gain of the network, it does advance a potentially important performance attribute. In
particular, the forward gain becomes dependent on transconductance g
x
, as opposed to for-
ward transconductance g
m
. Typically, g
m
is the transconductance of a transistor. As a result,
it is invariably sensitive to transistor biasing currents and several semiconductor parameters
whose precise numerical values are neither known precisely nor controlled satisfactorily.
Thus, if R = 0, the gain of the amplifier is vulnerable to the same parametric uncertainties that
plague g
m
. But with R 0, transconductance g
x
, to which the gain becomes dependent, is not
directly dependent on g
m
. The gain therefore boasts reduced sensitivity to the physical
parameters and circuit variables that render parameter g
m
vagarious. For example, in the
extreme case of g
m
R >> 1, g
x
1/R, which is independent of g
m
.
1.2.1.2. Ideal Transconductor
The t-model of a linear network that we show in Figure (1.7b) facilitates a simple
definition of an ideal transconductance amplifier, or transconductor. In particular, an ideal
transconductor is an electronic network whose relevant admittance parameters are y
i
= y
r
= y
o
=
0, and y
f
= G
m
, where G
m
is a frequency invariant constant that is known as the effective forward
transconductance of the amplifier. We see that for all signal frequencies and source and load
terminations, an ideal transconductor provides an infinitely large input impedance to an applied
signal source and an infinitely large output impedance to an arbitrary load termination. Because
no intrinsic feedback is manifested in the ideal structure, the output port of an ideal transconduc-
tor is isolated from the input port, which is to say that load impedances exert no effect on the in-
put impedance. We further understand that an ideal transconductance amplifier delivers an out-
put port current that is directly proportional to the input port voltage via a frequency invariant,
conductance proportionality, which we reference as G
m
. In short, an ideal transconductor be-
haves as the voltage controlled current source that you likely thought was a useless academic
nuisance in your first circuits course.

- 25 -
Figure (1.12a) gives the circuit schematic symbol of an ideal transconductor, together
with its electrical equivalent circuit. In that figure that the input port voltage is applied to the
non-inverting transconductor input terminal, which is symbolized by the + sign adjacent to the
terminal. Transconductors can be designed with negative forward transconductance, which
means that the output port current flows from the network output port, as opposed to into the out-
put port. Rather than deal with the awkwardness of negative transconductance, we assign a new
symbolic schematic designation to a phase inverted transconductor, as we portray in Figure
(1.12b). In this revised designation, the input port voltage is now incident with the inverting in-
put terminal (denoted by ).
+
G
m
V
1
V
1
I
1
I
1
I
2
I
2
G V
m 1
(a).
+
G
m
V
1
V
1
I
1
I
1
I
2
I
2
G V
m 1
(b).

Figure (1.12). (a). Schematic symbol and equivalent circuit for an ideal transconductor. Note
that the input port voltage is applied to the non-inverting input terminal, which is
denoted by the indicated + sign. (b). Schematic symbol and equivalent circuit
for a phase inverting ideal transconductor. The input port voltage is now applied
to the inverting input terminal, which is denoted by the indicated sign. In
both cases, the signal current, I
2
, at the output port is I
2
= G
m
V
1
.
Idealized electrical elements of any type are little more than mathematical artifacts.
The transconductor is no exception to this philosophical tidbit. Practical transconductors are bur-
dened with finite, and generally capacitive, input impedance, finite shunt output resistance and
nonzero shunt output port capacitance. In addition, practical transconductance amplifiers project
frequency variance in their forward transconductances, as opposed to a frequency invariant, con-
stant transconductance. They also can manifest internal feedback. We shall learn that the
performance ramifications of most of these annoying second order effects can often be abridged
in specific transconductor applications. Because the impact of these and related other second
order effects can usually be minimized, the idealized form of a transconductor offers a conve-
nient tool for conducting a meaningful first order performance assessment of many electronic
systems.
An especially useful attribute of most practical transconductors is that they can be de-
signed to offer a so-called tunable transconductance wherein the transconductance value is an
adjustable, monotonic function of a static voltage or current applied to a suitable control port.
This control voltage or current, which is separate and apart from the biasing required for accepta-
ble I/O linearity, allows for fine tuning integrated circuit responses in the face of processing
vagaries, device modeling uncertainties, system manufacturing tolerances, and the effects of
parasitics forged by circuit layout. As an example of the utility of a voltage controlled

- 26 -
transconductance, consider the simple circuit of Figure (1.13a), which depicts a non-inverting
transconductor whose input and output terminals are connected together. While biasing is not
explicitly depicted in this diagram, a static voltage, V
c
, is shown as applied to an available con-
trol port to allow for transconductance adjustment. We can determine the resistance, say R,
established from the transconductor output terminal to ground by exploiting a symbolic,
mathematical ohmmeter to squirt a small current I
x
, into the output port of the network. This
current manifests the indicated terminal voltage, V
x
, so that the desired resistance, R, is simply
the voltage to current ratio, V
x
/I
x
, which keeps George Ohm off our backs Since voltage V
x
is
simultaneously applied to the transconductor input port, the current, I
2
conducted by the network
output port is necessarily G
m
V
x
. It follows that the ohmmeter current, I
x
, must be I
x
= G
m
V
x
,
thereby implying a net resistance, R, of R = V
x
/I
x
= 1/G
m
, as Figure (1.13b) infers. Since control
voltage V
c
is used to adjust the numerical value of transconductance G
m
, we have effectively rea-
lized a variable resistance or equivalently, an electronic potentiometer.
+
G
m
V
x
V
x
V
x
0
I
x
G V
m x
(a).
I
x
G
m
1
V
c
(b).

Figure (1.13). (a). Ideal transconductor interconnected to function as a two terminal li-
near resistance. (b). The equivalent circuit of the structure in (a). The
resistance presented by the transconductor architecture is 1/G
m
, where
transconductance G
m
, and thus the realized resistance, is controllable by
the applied static voltage, V
c
.
At this stage of our travels, we may not have been able to rely exclusively on engineer-
ing intuition to foretell the value of resistance put forth by the architecture in Figure (1.13a). But
we should have been able to assert definitively that the subject structure ideally yields a linear
resistance. In particular, the architecture at hand is effectively a two terminal topology. One of
these two terminals is the interconnection of the transconductor input and output terminals, while
the second terminal is the circuit ground. Moreover, since the control voltage, V
c
, is a constant,
the control port is returned to circuit ground for signal purposes. Since we are modeling the
transconductor by a linear equivalent circuit (in this case, a simple voltage controlled current
source boasting constant transconductance), we clearly have a linear two terminal network be-
fore us. We learned in our basic circuits course that a linear two terminal network defines, at
least at relatively low signal frequencies, a resistance that satisfies a prescribed analytical
relationship between the current conducted by the branch that connects the two terminals to-
gether and the voltage observed across the branch. This prescribed expression is Ohms law.
The two terminal network in Figure (1.13a) appears to confirm our suspicion that if something is
a linear structure and if that something looks, feels, and smells like a resistance, it is indeed
probably a resistance.
EXAMPLE #1.4:
Simple amplifiers can be realized with transconductors without resorting to the

- 27 -
use of passive resistances in the signal path of the circuit. In most MOSFET
technology processes, avoiding passive resistances affords design advantages
that we shall address later. To this end, consider the network in Figure (1.14a),
which utilizes two transconductor elements for which the transconductances of
each are controlled by separate static voltages, V
c1
and V
c2
. A capacitance, C is
appended across the output port of the amplifier. This capacitance absorbs the
output and input port capacitances of a practical realization of the second
transconductor, as well as the output port capacitance of the first transconductor.
Develop expressions for the voltage gain function, A
v
(s) = V
o
/V
s
, the zero fre-
quency value, A
v
(0), of this gain, and the 3-dB bandwidth, B, afforded by the net-
work. Discuss the performance ramifications and engineering attributes of con-
trol voltages V
c1
and V
c2
.
SOLUTION #1.4:
(1). We can tackle this problem in at least two different ways. The first way, which we delineate
in Figure (1.14b), entails the identification of the branch currents supported by the architec-
ture. To this end, we note that the current flowing into the output port of the first
transconductor (G
1
) is G
1
V
s
. Since the output voltage, V
o
, is simultaneously incident with the
input port of the second transconductor (G
2
), a current of G
2
V
o
must flow into the output port
of this unit. Because the input port currents of ideal transconductor amplifiers are zero, the
indicated current, G
1
V
s
, must be supplied by the short circuit that connects the output port to
the input port of the second transconductor. Consequently, we deduce that the current flow-
ing through capacitance C is the sum, (G
1
V
s
+ G
2
V
o
). If Kirchhoff is to be kept content, the
resultant signal output voltage is
1 s 2 o
o
G V G V
V .
sC
+
= (E4-1)
Upon solving this expression for voltage V
o
, the voltage gain, A
v
(s), evolves as
1
o 2
v
s
2
G
V G
A (s) .
sC
V
1
G
= =
+
(E4-2)
(2). The alternative solution strategy relies on our ability to recognize that the interconnection of
the second transconductor realizes a two terminal resistance of value 1/G
2
, which terminates
the output port to ground. Accordingly, the original network in Figure (1.14a) collapses to
the topology appearing in Figure (1.14c). An inspection of the latter circuit diagram leads to

- 28 -
+
G
1
V
o
V
s
(a).
G
2
1
V
c1
+
G
2
V
c2
C
C
+
G
1
V
o
V
s
0
G V
1 s
G V
1 s
(b).
V
c1
+
G
2
0
G V
2 o
V
c2
G V + G V
1 s 2 o
C
+
G
1
V
o
V
s
0
G V
1 s
(c).
V
c1

Figure (1.14). (a). An amplifier formed of two transconductors. Capacitance C
represents the sum of the load, second transconductor input port
and output port, and first transconductor output port capacitances.
(b). The circuit of (a) with key branch currents expressly deli-
neated. (c). The circuit of (a) with the second transconductor sup-
planted by the resistance, 1/G
2
, which it establishes across the
output port of the amplifier.
1
s
1 s 2
o
2
2
G
V
G V G
V ,
sC
G sC
1
G
= =
+
+
(E4-3)
which obviously produces the gain result in (E4-2).
(3). The gain of an amplifier as a function of signal frequency is literally the transfer function of
the considered network. It is extracted from steady state observations of the amplifier output
port response to an applied sinusoidal input signal; that is, voltage V
s
is a fixed amplitude
sinusoid whose frequency is varied over the amplifier passband. For this steady state sinu-
soidal excitation, the Laplace variable, s, is supplanted by j, where we understand that
represents the radial signal frequency of the applied input signal. It follows that in the sinu-
soidal steady state, (E4-2) becomes

- 29 -
1
2
v
2
G
G
A (j) .
jC
1
G
=
+
(E4-4)
Clearly, the gain at zero frequency ( = 0, which is equivalent to s = j0 = 0) is
1
v
2
G
A (0) .
G
=
(E4-5)
On the other hand, the 3-dB bandwidth, B, (in units of radians -per- second) is the value of
signal frequency , such that the gain magnitude is a factor of root two smaller than the
magnitude of the zero frequency gain. It should be noted that the decibel value of root two is
10
Decibel Value Of 2 20 2 3.01, log = = (E4-6)
which for government work, is close enough to 3. Thus, a factor of root two below the
magnitude of the zero frequency voltage gain is a gain that is very nearly 3 decibels smaller
than the decibel value of the zero frequency gain magnitude. From (E4-4),
1 1 1 1
2 2 2 2
v
2
2
2
2
G G G G
G G G G
A (jB ) .
jBC
2 jBC
1
BC 1
1 G
G
G
= = = =
+ | |
+
+
|
\ .
(E4-7)
An inspection of the last result reveals a 3-dB bandwidth of
2
G
B .
C
=
(E4-8)
We note that (E4-8) and (E4-5) enable writing (E4-2) in the generalized form
1
o v 2
v
s
2
G
V A (0) G
A (s) .
sC s
V
1 1
G B
= = =
+ +
(E4-9)
Note that the network characteristic polynomial, which is the denominator polynomial of the
network transfer relationship, is written in monic form; that is, the s
0
term is one. The
characteristic polynomial at hand is a first order function, which means, that the network
undergoing investigation is a nice and simple first order topology. Accordingly, (E4-9)
suggests that the inverse of the coefficient of the s-term in a monic representation of the
characteristic polynomial for a first order circuit is indeed the 3-dB bandwidth of the network.
Although forthcoming chapters provide far more definitive information about the frequency
response of linear networks, this example serves to introduce a few of the important metrics
used to assess circuit performance in the frequency domain. First, we observe that the zero
frequency gain is the gain that would be obtained if capacitance C were zero. We confirm
this contention by multiplying both sides of (E4-1) by (sC), followed by setting C = 0, which
we recognize as an equivalence to an open circuited load capacitance. Second, we observe
that the quoted zero frequency gain cannot be sustained from DC to daylight because the
capacitance, which shunts the amplifier output port, behaves progressively as a branch short
circuit as the signal frequency is increased. This short circuit behavior mirrors the well-
known fact that voltages across capacitances cannot change instantaneously in response to ra-
pidly changing (high frequency) signals. At the 3-dB bandwidth, which is the frequency at
which the impedance of the capacitance matches the resistance said capacitance effectively
faces in the network at hand, the voltage gain is a factor of root two below the gain magnitude

- 30 -
observed at zero frequency. Equivalently, the 3-dB bandwidth is the signal frequency at
which the signal power gain, which is related to the square of voltage gain, is one-half the
power gain achieved at zero, or at least at very low frequencies.
The transconductor realization of the amplifier addressed herewith is sufficiently robust to al-
low gain and bandwidth to be controlled independently. For example, a change in
transconductance G
1
through an appropriate change in control voltage V
c1
alters the zero fre-
quency gain without affecting the 3-dB bandwidth. On the other hand and for the manually
dexterous, a change in G
2
, coupled with an identical change in G
1
, via the application of
suitable control voltages, V
c1
and V
c2
, perturbs the 3-dB bandwidth without influencing the
low frequency gain.
1.2.2. OPEN CIRCUIT z-PARAMETERS
The fallout of an arbitrary selection of input port voltage V
1
and output port voltage V
2

as the independent variables of a linear two-port system is the y-parameter network model we
formulated as Figure (1.5). Numerous choices are available for independent variable selection,
and each such selection breeds different modeling architectures, This assertion synergizes with
an earlier contention as to the non-uniqueness of electronic circuit models. For example, con-
sider the use of the input port current, I
1
, and the output port current, I
2
, as independent electrical
variables in the system of Figure (1.2). The upshot of this selection is the defining volt-ampere
matrix relationship,
1 11 12 1
2 21 22 2
V z z I
,
V z z I
( ( (
=
( ( (

(1-14)
Linear Model
Of Electronic
Network
I
1
I
1
1
1
2
2
V
2
V
2
3
3
4
4
I
2
I
2
z
22
V
1
V
1
z I
21 1
z I
12 2

z
11

Figure (1.15). The open circuit impedance, or z-parameter, equivalent cir-
cuit of a linear two-port network. All of the impedance
parameters, z
ij
, are in units of ohms.
where the z
ij
are the open circuit impedance parameters, or zparameters of the network. The
equivalent circuit implied by (1-14) is given in Figure (1.15). In contrast to the Norton port
representations implicit to the y-parameter model, the z-parameter model exploits Thvenins
theorem at the input and output ports of the considered linear network.
The designation of the zparameters as open circuit impedances follows from the
parametric measurement strategy that we deduce from (1-14). In particular,

- 31 -
2
2
1
11
1
I 0
2
21
1
I 0
V
z
I
,
V
z
I
=
=
=
=
(1-15)
whence z
11
is the open circuit (meaning an open circuited output port) input impedance of the
linear two-port network, while z
21
is seen as the open circuit transimpedance of the two-port sys-
tem. Thus, parameter z
11
is the driving point input impedance of a linear two-port network under
the special case of an open circuited load termination at the output port. Moreover, z
21
represents
the maximum possible forward transimpedance in that the model voltage source, z
21
I
1
, associated
with this parameter drives an open circuited load. Analogously,
1
1
1
12
2
I 0
2
22
2
I 0
V
z
I
.
V
z
I
=
=
=
=
(1-16)
We conclude that z
12
is the feedback transimpedance under the condition of an open circuited
input port, and z
22
is the driving point output impedance measured under the same open circuited
input port constraint.
Recall that if the individual ports of a linear two-port network share a common ter-
minal, the basic y-parameter model can be collapsed to a -type network architecture. Analo-
gously, the conventional z-parameter model of the common terminal two-port network shown in
Figure (1.16a) can be reduced to the tee-type topology we depict in Figure (1.16b). The subsidi-
ary impedance parameters, z
i
, z
f
, z
r
, and z
o
, in the tee model derive from (1-14), which we can
couch as
Linear Model
Of Electronic
Network
I
1
I
1
1
1
2
2
V
2
V
2
3
3
4
4
I
2
I
2
z
i
V
1
V
1
z I
f 1
z
r
(b).
(a).
z
o

I
1
1
2
V
2
3
4
I
2
z
i
V
1
z
r
z
o
(c).

Figure (1.16). (a). Three terminal linear two-port network. Observe that nodes 2 and 4 are common to
one another. (b). Alternative tee-type form of a z-parameter equivalent circuit for a three
terminal, linear two-port network. (c). The model of (b) for the special case of a bilateral,
three terminal linear network.

- 32 -
( ) ( )
( ) ( ) ( )
1 11 12 1 12 1 2
2 21 12 1 22 12 2 12 1 2
V z z I z I I
.
V z z I z z I z I I
= + +
= + + +
(1-17)
Letting
i 11 12
f 21 12
r 12
o 22 12
z z z
z z z
,
z z
z z z
=
=
=
=
(1-18)
(1-17) becomes
( )
( )
1 i 1 r 1 2
2 f 1 o 2 r 1 2
V z I z I I
,
V z I z I z I I
= + +
= + + +
(1-19)
which dispatches the model in Figure (1.16b). For the case of a bilateral network for which open
circuit feedforward signal transmission is equal to open circuit feedback transmission, z
21
= z
12
,
whence z
f
= 0. The tee-type model for the bilateral network becomes the circuit in Figure
(1.15c).
1.2.2.1. Ideal Transresistor
An ideal transconductor delivers an output port signal current that is directly propor-
tional to input port voltage, regardless of source or load terminations. In contrast, an ideal
transresistance amplifier, or transresistor, delivers an output port voltage that is directly propor-
tional to its input port current, independent of source and load terminations. If we return to the
model in Figure (1.16b), we can postulate that an ideal transresistor has z
i
= z
r
= z
o
= 0, while
sustaining a forward transimpedance, z
f
, that equals a real number, say R
m
, which is independent
of signal frequency. Figure (1.17) symbolically portrays this ideal transresistor, in which no
feedback is incurred from its output port to its input port. Additionally, it postures a short cir-
cuited input port (zero input impedance) that renders input port current I
1
independent of the sig-
nal source impedance. The resultant output voltage, V
2
, is rendered directly proportional to the
input port current, I
1
. Because the controlled source at the output port of an ideal transistor is
itself ideal (no series resistance), this output port voltage is independent of the nature of load
terminations.
I
1
I
2
I
2
V
2
V
1
R I
m 1
+
R
m
V
1
I
1
V
2

Figure (1.17). Schematic symbol and equivalent circuit for an ideal transresistance amplifier.
EXAMPLE #1.5:
Figure (1.18a) displays the approximate low frequency, linear equivalent circuit
of a transresistance amplifier realized in bipolar junction transistor (BJT)
technology. Use this model to evaluate the open circuit impedance parameters,

- 33 -
as well as the tee-equivalent impedance parameters. Draw the tee-type model
for the special case of very large , where is the indicated gain of the con-
trolled current source within the model.
(a).
R
1
R
f
R
2
V
1
V
2
I
1
I
2
I
I
(b).
(c).
R
1
R
1
R
f
R
f
R
2
R
2
V
1
V
1
V
2
V
2
I
1
0
I
I I
2
0
I
I
I
I
I
2
(d).
R
1
V
1
V
2
I=I
1
RI
f 1
I
2
I
1

Figure (1.18). (a). Linear equivalent circuit of a transresistance amplifier. (b). The circuit of (a) with the output
port open circuited. (c). The circuit of (a) with the input port open circuited. (d). Tee-equivalent
model of the equivalent circuit in (a) under the special case of very large |.
SOLUTION #1.5:
(1). In Figure (1.17b), we depict the model of Figure (1.17a) for the special case of an open cir-
cuited output port (I
2
= 0). Pertinent branch currents are indicated in the latter structure. In
particular, observe that the control current, I, for the current controlled current source, |I, is I
= I
1
|I, whence
1
I
I .
1
=
+
(E5-1)
Thus, the input port voltage, V
1
, is
1
1 1 1 2 1 1 2
I
V R I R I R I R ,
1
| |
= + = +
|
+
\ .
(E5-2)
from which we obtain the open circuit input impedance,
2
1 2
11 1
1
I 0
V R
z R .
I 1
=
= = +
+
(E5-3)
Similarly, the output port voltage, V
2
, satisfies
( )
1
2 f 2 f 2
I
V R I R I R R ,
1
= + =
+
(E5-4)
which produces a forward transimpedance of
2
2 2
21 f
1
I 0
V R
z R .
I 1 1
=
| |
= = +
|
+ +
\ .
(E5-5)

- 34 -
In bipolar technology and particularly in state of the art silicon-germanium (SiGe)
heterostructure bipolar junction transistors, current gain parameter is very large (of the or-
der of at least a few hundred). When this technology is exploited in the present transresis-
tance application, large reduces z
11
to roughly R
1
, while z
21
R
f
.
(2). The applicable circuit diagram and key branch currents pertinent to an open circuited input
port (I
1
= 0) is the topology of Figure (1.17c). We note now that control current I is given by
I = I
2
|I, which yields
2
I
I .
1
=
+
(E5-6)
The corresponding output port voltage, V
2
, is, using (E5-6),
( )
f 2
2 f 2 2 2
R R
V R I I R I I .
1
+
| |
= + =
|
+
\ .
(E5-7)
Clearly, the open circuit output impedance is
1
f 2
2
22
2
I 0
R R
V
z .
I 1
=
+
= =
+
(E5-8)
Since
( )
2 2
1 1 2
R I
V R 0 R I ,
1
= + =
+
(E5-9)
the feedback transimpedance is
1
1 2
12
2
I 0
V R
z .
I 1
=
= =
+
(E5-10)
If the transresistance amplifier is realized in SiGe BJT technology, impedance z
22
is invaria-
bly very small owing it its inverse dependence on ( + 1). The feedback transimpedance
parameter, z
12
, is very small for much the same reason.
(3). The subsidiary impedance parameters for the tee-equivalent model derive from the preceding
results and (1-18). In particular,
i 11 12 1
f 21 12 f
2
r 12
f
o 22 12
z z z R
z z z R
1
.
R
z z
1
R
z z z
1
= =
| |
= =
|
+
\ .
= =
+
= =
+
(E5-11)
For very large |, the preceding results become
i 11 12 1
f 21 12 f
r 12
o 22 12
z z z R
z z z R
,
z z 0
z z z 0
= =
= ~
= ~
= ~
(E5-12)
Equation (E5-12) gives rise to the simplified equivalent circuit in Figure (1.17d).
Aside from demonstrating the analytical techniques underlying the computation of the open

- 35 -
circuit impedance parameters, this example highlights the utility of the z-parameters in circuit
design ventures. Specifically, the z-parameters and their subsidiary tee-type impedance
counterparts render transparent the fact that the circuit model in Figure (1.18a) emulates ideal
transresistance action only if parameter | is suitably large. To be sure, large | does not re-
duce parameter z
i
to its desirable null value, but because z
i
is an element that is in series with
the input port, it can presumably be absorbed into the Thvenin impedance of the ultimately
applied signal source.
1.2.2.2. z-Parameter Relationship To y-Parameters
Two models for a linear two-port network have now been formulated. The short circuit
admittance parameters model both ports of a two port system by Norton equivalent circuits that
feature current sources controlled by input and output port voltages. On the other hand, the open
circuit impedance parameters exploit Thvenin equivalent input and output port circuits whose
voltage sources are controlled by independent port currents. Obviously, analytical chaos ensues
if the y-parameter and z-parameter models of the same linear network do not deliver identical
input and output port responses to the same input signal excitations. We can avoid such chaos
only if the y-parameters and the z-parameters of the same network are unambiguously related to
one another in a manner that is consistent with the equilibrium volt-ampere relationships prevail-
ing at both network ports. In short, for given source excitation at the input port and load termina-
tion at the output port of a linear network, the y-parameter model and the z-parameter model of
the subject network must deliver identical port voltage and port current responses to the same
signal excitations.
In a linear network, such as the one abstracted in Figure (1.2), the port equilibrium
relationships expressed in terms of z-parameters are stipulated by (1-14). On the other hand, (1-
7) defines these unique relationships in terms of the y-parameters of the network. But the latter
relationship implies
1
1 11 12 1
2 21 22 2
V y y I
,
V y y I
( ( (
=
( ( (

(1-20)
which is precisely the form of (1-14). In other words, the matrix of z-parameters is little more
than the inverse of the matrix of corresponding y-parameters. Specifically,
22
11
12 21
y
11
22
11
22
12 21
y
22
11
12 12
12
y 11 22 12 21
21 21
21
y 11 22 12 21
y 1
z
y y
y
y
y 1
z
y y
y
,
y
y y
z
y y y y
y y
z
y y y y
= =
= =
= =
= =
(1-21)
where the determinant, Ay, of the y-parameter matrix is
11 22 12 21
y y y y y . = (1-22)
Similarly, the matrix of y-parameters is the inverse of the corresponding matrix of z-parameters.

- 36 -
If two different models yield identical response results to identical input signals, we can
naturally question the logic underlying the use of different two-port network models. In other
words, why must are brains be burdened with two models when, in fact, each of the two models
produces identical I/O port responses? One answer to this query is that depending on the
architecture undergoing investigation, one set of parameters may be more easily evaluated or
meaningfully interpreted than another set. But a clue as to the dominant reason for adopting
multiple model representations is provided by (1-21). In particular, if the determinant, A
y
, of the
matrix of short circuit admittance parameters is zero, the matrix is said to be singular, and the
open circuit impedance parameters, z
ij
, cannot be determined. In other words, the z-parameters
of a network whose matrix of y-parameters is singular do not exist, thereby leaving us little
choice but to adopt a y-parameter analytical strategy. Conversely, if the z-parameter matrix of a
linear two-port network is singular, the y-parameters do not exist, thereby forcing us to exploit a
z-parameter representation of the network before us.
Paradoxically, matrix singularity in the course of circuit analysis is commonly the
byproduct of approximations invoked to simplify the network at hand. For example, consider the
idealized transresistor model of Figure (1.17). The matric relationship of this idealized two-port
structure is
1 1
m 2 2
0 0 V I
,
R 0 V I
( ( (
=
( ( (

(1-23)
for which the determinant, A
z
, of the square matrix on the right hand side is zero. Thus, the y-
parameters of the ideal transresistance amplifier cannot be determined. The disbelievers of the
singularity dilemma are hereby challenged to determine the y-parameters of the model in Figure
(1.17). They are additionally reminded that the Thvenin equivalent circuit of an ideal (infinitely
large shunt resistance) current source does not exist, nor does the Norton equivalent circuit of an
ideal (zero series resistance) voltage source.
1.2.3. HYBRID h-PARAMETERS
If we arbitrarily select the input port current, I
1
, and the output port voltage, V
2
, as the
independent variables of a linear network, an h-parameter representation abiding by the genera-
lized volt-ampere relationships,
1 11 12 1
2 21 22 2
V h h I
,
I h h V
( ( (
=
( ( (

(1-24)
results. The parameters, h
ij
, are referred to as hybrid h-parameters, or simply h-parameters. The
adjective, hybrid, underscores the fact that the individual h
ij
do not have the same physical
units. Specifically,
2
1
11
1
V =0
V
h
I
= (1-25)
is in units of ohms in that it is the impedance established at the network input port under the
condition of a short circuited output port. In contrast,
1
2
22
2
I =0
I
h
V
= (1-26)
is dimensioned in mhos as it symbolizes the admittance prevailing at the network output port un-
der the condition of an open circuited input port. In contrast to h
11
and h
22
, both h
21
and h
12
are

- 37 -
dimensionless parameters. Equation (1-24) confirms this contention by projecting
2
2
21
1
V =0
I
h
I
= (1-27)
as the short circuit, and therefore maximum, current gain of the network, while
1
1
12
2
I =0
V
h
V
= (1-28)
monitors internal network feedback as a reverse open circuit voltage transfer function. The
equivalent circuit inferred by (1-24), which we submit as Figure (1.19), evokes a hybrid architec-
tural structure as it is seen to utilize Thvenins theorem at the input port and Nortons theorem
at the output port.
Linear Model
Of Electronic
Network
I
1
I
1
1
1
2
2
V
2
V
2
3
3
4
4
I
2
I
2
1/h
22
V
1
V
1
h I
21 1
h V
12 2
h
11

Figure (1.19). The hybrid h-parameter equivalent circuit of a linear two-
port network. Parameter h
11
is in units of ohms, h
22
has
dimensional units of siemens, and both h
12
and h
21
are
dimensionless parameters.
The h-parameter equivalent circuit is the third modeling option available for linear cir-
cuit analysis. Just as the y- and z-parameters of a linear network are necessarily interrelated, the
h-parameters are tied analytically to both the y- and z-parameters. In the case of the y-parame-
ters introduced in (1-6),
2
1
11
1 11
V =0
V 1
h .
I y
= = (1-29)
This relationship is hardly astonishing news in light of our understanding that y
11
is the short cir-
cuit input admittance, while h
11
designates the short circuit input impedance. For parameter h
21
,
2
2 21
21
1 11
V =0
I y
h ,
I y
= = (1-30)
which confirms that the measure of forward gain, h
21
, is directly proportional to the counterpart
y-parameter gain measure, y
21
. Indeed, we may assert that hybrid parameter h
21
is simply y-
parameter y
21
normalized to y-parameter y
11
. This alternative interpretation serves to confirm the
dimensionless nature of h
21
. Returning to (1-6),
1
y
2 12 21
22 22
2 11 11
I =0
I y y
h y ,
V y y
= = = (1-31)

- 38 -
and finally,
1
1 12
12
2 11
I =0
V y
h .
V y
= = (1-32)
Recalling that an implicit property of a bilateral network is y
21
= y
12
, we observe from (1-30) and
(1-32) that a bilateral network requires forward and reverse transmission hybrid h-parameters
satisfying h
21
= h
12
.
The h-parameter model allows for a convenient definition of an ideal current amplifier,
whose circuit schematic symbol and electrical model are given in Figure (1.20). In particular, an
ideal current amplifier has h
11
= 0 and h
12
= 0, which combine to imply a short circuited input
port for all load terminations. Moreover h
22
= 0 in an ideal current amplifier. In concert with h
12

= 0, h
22
= 0 fashions an infinitely large output impedance that is independent of input port
dynamics. Finally, h
21
= o
m
, where o
m
, a real number that we can identify as the current gain of
the amplifier, is independent of signal frequency. In summary and with reference to Figure
(1.20), the terminal volt-ampere characteristics of an ideal current amplifier are given by
I
1
I
2
I
2
V
2
V
1

m 1
I
+
m
V
1
I
1
V
2

Figure (1.20). Schematic symbol and equivalent circuit for an ideal current amplifier.
1 1
m 2 2
0 0 V I
.
0 I V
( ( (
=
( ( (

(1-33)
The current amplifier in either its idealized or non-ideal forms is commonly exploited
in circuit applications as a current buffer, which is more commonly referred to as a cascode. We
shall find that current buffering is advantageous when a high impedance signal source is coupled
to a load of comparably large impedance. As an illustration of the utility of current buffering,
consider Figure (1.21a), which depicts a signal current source, I
s
, whose shunt resistance is R
s
,
directly coupled to a load resistance of R
l
. The resultant signal transmitted to the load is the cur-
rent I
2
, which derives from the current divider,
s 2
s s l
R I
.
I R R
=
+
(1-34)
Note that R
l
<< R
s
, projects an efficient source to load coupling in the sense that the signal cur-
rent response, I
2
, is a minimally attenuated factor of the applied signal current, I
s
. But if R
l
is
comparable to, or even greater than, R
s
, a significant percentage of the signal current is lost in the
process of its source to load transmission. In the latter event, a current buffer inserted between
the source and load, as diagrammed in Figure (1.21b) proves effective. We observe that the sig-
nal is applied to the inverting input terminal of the current amplifier. Resultantly, the pertinent
equivalent circuit is the model in Figure (1.20c) for which I
1
= I
s
, and I
2
= o
m
I
1
= o
m
I
s
. It
follows that the resultant I/O current gain is I
2
/I
s
= o
m
. The idealized nature of the current am-
plifier in this example renders the current transfer function, I
2
/I
s
, unlike the form of (1-34),
independent of both source and load resistances. Moreover, if the amplifier delivers a current
gain, o
m
, of one, the signal source current is effectively coupled directly to the load termination

- 39 -
at the output port of the current amplifier.
I
1
I
2
I
2
I
2
m 1
I
m
I
1
I
s
I
s
I
s
R
s
R
s
R
s
R
l
R
l
R
l
(a). (b).
(c).

Figure (1.21). (a). A signal current, I
s
, whose Thvenin resistance is R
s
, is coupled to a resistive load of value
R
l
. (b). The circuit of (a) modified by the insertion of a current buffer between the signal source
and the load termination. (c). The equivalent circuit of the system in (b), assuming that the cur-
rent buffer approximates the electrical characteristics of an ideal current amplifier.
1.2.4. HYBRID g-PARAMETERS
The independent and dependent electrical variable sets used to define the hybrid g-
parameters are the converse of those used in conjunction with the hybrid h-parameters. Specifi-
cally, the independent variables for g-parameter modeling are the input port voltage, V
1
, and the
output port current, I
2
, thereby establishing the input port current, I
1
, and the output port voltage,
V
2
, dependent electrical quantities. Accordingly, the port equilibrium relationships assume the
form
1 11 12 1
2 21 22 2
I g g V
,
V g g I
( ( (
=
( ( (

(1-35)
and by comparison with (1-24),
1
11 12 11 12
21 22 21 22
g g h h
.
g g h h
( (
=
( (

(1-36)
Like the hybrid h-parameters, the g-parameters have mixed dimensions. In particular, g
11
has
units of admittance, g
22
is an impedance, and g
21
and g
12
, which respectively measure feedfor-
ward and feedback within the subject network, are dimensionless metrics. Figure (1.22) is the
electrical equivalent circuit implied by (1-35). In further analogy to h-parameters, a bilateral net-
work has g
12
= g
21
, just as it has h
12
= h
21
if h-parameters are adopted as the modeling ve-
hicle.

- 40 -
Linear Model
Of Electronic
Network
I
1
I
1
1
1
2
2
V
2
V
2
3
3
4
4
I
2
I
2
1/g
11
V
1
V
1
g I
12 2
g V
21 1
g
22

Figure (1.22). The hybrid g-parameter equivalent circuit of a linear two-port
network. Parameter g
11
is in units of siemens, g
22
has units of
ohms, and both g
12
and g
21
are dimensionless parameters.
Although the g-parameters are used less often than are the h-, y-, and z-parameters
when arbitrary linear two-port networks are modeled for circuit analysis purposes, they are suita-
ble for the modeling of an ideal voltage amplifier. Formally, an ideal voltage amplifier, which is
illustrated symbolically in Figure (1.23), delivers null g
11
and g
12
. These constraints dictate an
infinitely input impedance that is independent of load terminations imposed at the output port.
Additionally, g
22
= 0, which along with g
12
= 0, guarantees a zero output impedance that is
independent of source impedance. Finally, g
21
=
m
, where parameter
m
, which is termed the
open circuit voltage gain of the subject amplifier, is a constant that is independent of signal fre-
quency. The operational amplifier, which to first order emulates an ideal voltage amplifier takes
the concept of an ideal voltage amplifier a step further. In particular, assigns an infinitely large
value to the open circuit voltage gain; that is,
m
= .
I
1
I
2
I
2
V
2
V
1

m 1
V
+
m
V
1
I
1
V
2

Figure (1.23). Schematic symbol and equivalent circuit of an ideal voltage amplifier.
EXAMPLE #1.6:
Figure (1.24a) diagrams a low frequency, small signal equivalent circuit of a vol-
tage amplifier that exploits feedback via the resistance, R
2
. Let R
1
= 22 KO, and
R
2
= 3 KO. Assume an amplifier output resistance, r
o
, of 300 O, and an am-
plifier open circuit voltage gain, A
o
, of 250. Derive general expressions for, and
numerically evaluate, the four g-parameters, g
ij
, of the feedback amplifier.
SOLUTION #1.6:
(1). Figure (1.24b) is the original circuit in Figure (1.24a) but with an open circuit delineated at
the output port. Because of this open circuit, we see that the only current conducted by resis-

- 41 -
tance R
2
is the input port current, I
1
. It follows that
I
1
V
2
I
2
A V
o
R
1
R
2
V
1
(a).
I
1
V
2
I = 0
2
A V
o
R
1
R
2
V
1
(b).
I
1
V
2
I
2
A V
o
R
1
R
2
V

=

0
1
(c).

Figure (1.24). (a). Linear equivalent circuit of the amplifier studied in Example #1.6. (b). The circuit of (a) with an
open circuit imposed at the output port to allow for the computation of g-parameters g
11
and g
21
. (c).
The circuit of (a) with a short circuit imposed at the input port to calculate parameters g
22
and g
12
.
2
1
11
1 1 2
I 0
I 1
g 40 S .
V R R
=
= = =
+
(E6-1)
Since I
2
= 0 delivers V
1
= (R
1
+ R
2
)I
1
and V
2
= A
o
V + R
2
I
1
= (A
o
R
1
R
2
)I
1
,
2 2
o 1 2
2 2 1
21
1 1 1 1 2
I 0 I 0
A R R
V V I
g 219.88 volts/volt .
V I V R R
= =
(
= = = =
(
+

(E6-2)
(2). The circuit for computing g-parameters g
12
and g
22
is given in Figure (1.23c), which is the
structure of Figure (1.23a) with a short circuit imposed at its input port. With V
1
= 0,
1 2 1 2 2
0 ( R R )I R I , = + + (E6-3)
which leads to
1
1 2
12
2 1 2
V 0
I R
g 120 mA/amp .
I R R
=
= = =
+
(E6-4)
Continuing with V
1
= 0,
2 o 2 o 2 1 2 o 2 2 o 1 2 1
V r I A V R ( I I ) ( r R )I ( A R R )I . = + + = + (E6-5)
With the help of (E6-4), we find that

- 42 -
1
2
22 o o 1 2
2
V 0
V
g r ( A 1)( R R ) 662.94 K .
I
=
= = + + =
(E6-6)
In the heat of a detailed analysis, it is only human to incur mathematical errors. But engi-
neers who customarily commit them while assuming the responsibility for the design of relia-
ble and reproducible circuits destined for fabrication in inordinately expensive fabrication
processes are banished to deserted islands divorced of electronic components. It is therefore
prudent to check and re-check analyses and calculations and even to adopt simple validation
procedures that test the propriety of relevant results. For example, if A
o
were zero in Figure
(1.24b), the resistance seen looking into the output port under the condition of a short cir-
cuited input port is obviously
o 1 2
r ( R R ) + . (While A
o
= 0 is pragmatically unrealistic, one
of the kudos of engineering academe is that nothing hinders the mathematical stipulation of a
null gain). Referring to (E6-6), note that g
22
, which is the short circuit output resistance of
the considered amplifier model, collapses to the quoted result if A
o
= 0. This affirmation
does not guarantee the correctness (E6-6), but a result that differs from reasonable expecta-
tions suggests analytical errors. At a minimum, a disparity between expectation and reality
certainly warrants a reconsideration of the solution tack adopted. An additional check is af-
forded by the observation that A
o
= 0 reduces the network at hand to a passive, and therefore
bilateral, architecture. From (E6-2) and (E6-4), observe that A
o
= 0 gives rise to g
12
= g
21
,
as we expect.
1.2.5. MODEL SELECTION
The preceding subsections propounds that we can deploy as many as four types of
equivalent circuits to model the terminal volt-ampere characteristics of an electronic network.
Of course, these two port models insist that the network undergoing examination is biased to en-
sure nominally linear processing of an applied input signal. The number of choices may be less
than four if one or more of the parametric matrices is singular. For example, if the z-parameter
matrix is singular, y-parameters do not exist, while similarly, a singular g-parameter matrix prec-
ludes our using hybrid h-parameters. But if all four parameter sets subsist, questions naturally
arise as to which of the four models should be utilized in a particular application. The cavalier
answer is that the choice is immaterial because the interrelationship of all four sets of two-port
parameters guarantees analytical consistency. From a practical perspective, however, a prudent
modeling choice can forestall a profane description of an apparently challenging analysis prob-
lem.
The y-parameter and g-parameter equivalent circuits represent the input port of a linear
network by Norton equivalent circuits. Accordingly, y-parameters and g-parameters work well
on networks whose input ports are driven by a signal current source, which is otherwise referred
to as a high impedance source. Moreover, y-parameters complement a study of transimpedance
amplifiers, which feature a low output impedance to facilitate the delivery of an output voltage
response that is nominally independent of the load termination. The requisite low output imped-
ance of a transimpedance unit is supported by the admittance, y
22
, which shunts the output port of
a y-parameter model and therefore reduces the achievable output impedance. On the other hand,
g-parameters work famously in current amplifiers. These amplifiers offer high output impedance
so that the output current, which is proportional to input current, can be delivered efficiently to a
load termination. The presence of series impedance g
22
at the output port of a g-parameter model
for a current amplifier hints at the possibility of realizing large output impedance.

- 43 -
The h-parameter and z-parameter models feature Thvenin equivalent circuits at their
input ports. They therefore nicely accommodate linear networks whose input ports are driven by
low impedance voltage sources. Voltage amplifiers, whose output ports are designed to offer
low impedances so that their voltage responses can be transferred efficiently to a load termina-
tion, are best modeled by h-parameters. As in the case of y
22
, h
22
shunts the output port of an h-
parameter model to reduce the observable output impedance of a linear network. If for no other
reason, the process of elimination suggests the utility of z-parameter models in transadmittance
applications. Like g
22
, the series impedance presence of z
22
at the output port of a z-parameter
model bolsters the network output impedance. Of course, high output impedance in a
transadmittance amplifier facilitates a current response that is nominally invariant with the load
termination.
1.2.6. FEEDBACK ARCHITECTURES
We shall ultimately learn that many practical amplifiers exploit feedback around their
active devices and their subcircuits to ensure that target performance specifications are achieved
predictably and reproducibly. This applied feedback supplements the internal feedback (as
measured by y
12
, z
12
, h
12
, or g
12
) established internally in subcircuits the considered two-port net-
work. In these cases, the decision as to which of the four basic models should be adopted is of-
ten made in terms of the feedback circuit architecture, independent of the nature of the source
signal. Just as there are four basic two-port network models on which we can predicate an elec-
tronic circuit analysis, there are four fundamental feedback topologies.
1.2.6.1. Shunt-Shunt Feedback
When the input port of a feedback subcircuit appended to an amplifier is connected in
shunt with the input port of the amplifier and when the output port of the same feedback subcir-
cuit is in parallel with the output port of this base, or open loop, unit, the resultant circuit
architecture is cleverly referred to as shunt-shunt feedback. The feedback is also referenced as
global in nature since the implemented feedback returns a portion of the output port signal all the
way back to the input port. The shunting nature of the feedback subcircuit at both network ports
gives rise to low input and output impedances. Since a low input impedance allows for an effi-
cient processing of an applied current signal and a low output impedance facilitates the delivery
of a voltage response to a load, the shunt-shunt feedback amplifier functions optimally as a
transimpedance amplifier (or transresistance amplifier if only low signal frequencies are ad-
dressed). This is to say that shunt-shunt feedback supports transimpedance signal processing in
the sense that the low input and output impedances render the achieved transimpedance approx-
imately independent of the source and load impedances.
The shunt-shunt feedback architecture in question is abstracted in Figure (1.25a), where
the basic amplifier, which may or may not possess significant internal feedback, is labeled as the
a network. The appended feedback subcircuit is the b network in the subject diagram. In
practice, terminals 2 and 4 can be common with one another and even grounded, but in the inter-
est of generality, we shall sustain electrical independence of these two terminals. Because of the
shunt-shunt interconnection of the feedback subcircuit with the two network ports, the I/O ports
of both subcircuits support the same signal input port voltage, V
1
, and the same output port re-
sponse, V
2
. But the net signal input port current, I
1
, which must be supplied by the signal source
comprised of Thvenin voltage V
s
and Thvenin impedance Z
s
, is the sum of the currents, I
1a
and
I
1b
. Observe that currents I
1a
and I
1b
flow respectively flow into the input ports of the base am-

- 44 -
plifier and the feedback structure. Similarly, the net output port current conducted by load
impedance Z
l
is the sum of the indicated output port currents, I
2a
and I
2b
. This preliminary
assessment of the overall amplifier exploits nothing more than the classic Kirchhoff laws. We
state this fact because when encountering an unfamiliar circuit architecture, it is best to initiate
analysis by putting away the pencil and paper in favor of relying only on our eyes and brain to
digest the electrical essence of the network.
Linear Model
Of Feedback
Network
-Circuit (b)-
I
1b
I
2b
Z
l
Z
l
Z
s
Z
s
V
1
Linear Model
Of Base
Amplifier
-Circuit (a)-
I
1a
I
1
I
2a
+
V
s
V
s
V
2
V
2
I
2
V
1
I
1
y V
12b 2
1
2
2
V
2
3
3
4
4
I
2
V
1
y V
21a 1
(a).
y
11b
1
y
11a
1
y
22a
1
y
22b
1
1
(b).

Figure (1.25). (a). System level abstraction of a shunt-shunt feedback amplifier. The base amplifier has y-
parameters y
ija
, while the feedback circuit is characterized by admittance parameters of y
ijb
. The
entire network has y-parameters, y
ij
= y
ija
+ y
ijb
. (b). Approximate equivalent circuit of the feed-
back architecture in (a). The model ignores feedback in the base amplifier and feedforward in the
feedback network.
Since the input ports of both the base amplifier and the feedback network support the
same signal voltage, V
1
, and the respective output ports share an identical signal voltage, V
2
, y-
parameter models, which invoke input and output port voltages as independent circuit variables,
are expedient for studying shunt-shunt feedback architectures. This contention stems from the
following straightforward analytical argument, which we begin by writing for the base amplifier,
1a 11a 12a 1
2a 21a 22a 2
I y y V
,
I y y V
( ( (
=
( ( (

(1-37)
while for the feedback subcircuit,
1b 11b 12b 1
2b 21b 22b 2
I y y V
,
I y y V
( ( (
=
( ( (

(1-38)
where the appended subscripts, a and b, obviously refer to the base amplifier and feedback
structures, respectively. In view of KCL,

- 45 -
1a 1b 1a 1b 1
2a 2b 2a 2b 2
I I I I I
.
I I I I I
+ ( ( ( (
= + =
( ( ( (
+

(1-39)
It follows that the two-port equilibrium equations for the entire feedback interconnection are
( ) ( )
( ) ( )
11a 11b 12a 12b 1 1 11 12 1
21a 21b 22a 22b 2 2 21 22 2
y y y y I V y y V
,
y y y y I V y y V
+ + (
( ( ( (
=
(
( ( ( (
+ +

(1-40)
which highlights the mathematical simplicity of the overall y-parameter modeling strategy. It is
important to understand that such simplicity is enabled solely because voltage V
1
is common to
both base and feedback input ports, while voltage V
2
is common to both output ports. We can
conclude, therefore, that the short circuit admittance parameters, y
ij
, of the overall shunt-shunt
feedback system are little more than sums of the corresponding parameters, y
ija
and y
ijb
, for the
a and b structures.
In typical shunt-shunt feedback realizations, the magnitude of the feedforward
transadmittance, y
21a
, of the base amplifier is much larger than is the magnitude of the feedfor-
ward transadmittance, y
21b
, of the feedback component. Since the 21 two-port parameter is a
measure of forward gain, y
21a
>> y
21b
simply affirms the presumption that most of the I/O gain is
(and should be) supplied by the base amplifier. Such an operating circumstance is particularly
true if the feedback structure is formed of a passive, bilateral network for which no forward gain
is impossible. With the possible exception of the very high signal frequencies that challenge the
performance capabilities of the base amplifier, feedback in the base amplifier, as monitored by
|y
12a
|, is commonly much smaller than |y
12b
| if for no other reason than the b network is ex-
pressly deployed to ensure substantial feedback over the frequency passband of the entire am-
plifier. The last two statements articulate the fundamental goal of appending the indicated b
network expressly for feedback with hopefully minimal feedforward signal transmission.
Despite the foregoing reasonable simplifications, the incorporated feedback incurs
potentially significant loading of the input and output ports of the amplifier. Therefore, no
conclusions can be drawn about the relative values of |y
11a
| and |y
11b
| and |y
22a
| and |y
22b
|. As a
result of these observations, (1-40) can be approximated as
( )
( )
11a 11b 12b 1 1
21a 22a 22b 2 2
y y y I V
.
y y y I V
+ (
( (
~
(
( (
+

(1-41)
The immediate implication of (1-41) is the equivalent circuit offered in Figure (1.25b).
The interesting features of this model include the additional impedance, 1/y
11b
, imposed across
the input port of the base amplifier and the impedance, 1/y
22b
, appended in shunt with the output
port. These two modeling features account for the aforementioned loading effects of the feed-
back subcircuit. To the extent that feedback intrinsic to the base amplifier can be tacitly ignored,
y
12b
, which derives exclusively from the characteristics of the feedback subcircuit, appears as the
feedback factor for the entire amplifier. And if feedforward through the feedback subcircuit is
negligible in comparison to the feedforward afforded by the base amplifier, y
21a
, which derives
exclusively from the base amplifier, is the feedforward parameter of the entire structure.
1.2.6.2. Series-Series Feedback
A series connection of both the input and output ports of an open loop base amplifier
and an external feedback subcircuit, as we depict in Figure (1.26a), comprises a series-series
feedback amplifier. As we noted in the shunt-shunt architecture, terminals 2 and 4 can be electri-

- 46 -
cally connected together. The indicated topological structure encourages high input and output
impedances, which makes the series-series architecture most suitable for transadmittance
amplification. A hint that these I/O impedances are large follows from the fact that the input and
output port voltages, V
1
and V
2
, of the overall configuration are respectively the sum of the input
and output port voltages of the amplifier and feedback unit; that is, and with reference to the sub-
ject figure,
Linear Model
Of Feedback
Network
-Circuit (b)-
I
1b
I
2b
Z
l
Z
l
Z
s
Z
s
V
1a
Linear Model
Of Base
Amplifier
-Circuit (a)-
k I
i 1
k I
o 2
I
1
+
V
s
V
s
V
2a
I
2
V
1b
V
2b
V
1
V
2
I
1
1
2
2
3
4
4
I
2
z
22a
V
1
z I
21a 1
k z I
o 12b 2

z
11a
k z
i 11b
k z
o 22b
(a).
V
2
(b).
1 3

Figure (1.26). (a). System level abstraction of a series-series feedback amplifier. The base amplifier has z-
parameters z
ija
, while the feedback circuit is characterized by open circuit impedance parameters
of z
ijb
. (b). Approximate equivalent circuit of the feedback architecture in (a). The model ignores
feedback within the base amplifier and feedforward incurred by the feedback network.
1a 1b 1a 1b 1
2a 2b 2a 2b 2
V V V V V
.
V V V V V
+
( ( ( (
= + =
( ( ( (
+

(1-42)
On the other hand, the net input port current, I
1
, which the signal source supplies, routes through
the input ports of both the amplifier and the feedback structure. But in some two-port networks,
and particularly in two-port, three terminal models of active devices and amplifiers, the input
port current may not straightforwardly circulate around the loop formed by the two terminals of
the port. Instead, some of this current may be diverted to the output port. For this reason, the
diagram in Figure (1.26a) depicts an amplifier input port current of I
1
and a return input port cur-
rent of k
i
I
1
, which flows as current I
1b
into the input port of the feedback circuit. The same logic
allows a return current of k
o
I
2
at the amplifier output terminal, where it is noted that I
2b
= k
o
I
2
.
Thus,

- 47 -
1b i 1
2b o 2
I k I
I k I
=
=
(1-43)
and to keep Kirchhoff happy, k
i
and k
o
are factors (possibly frequency variant factors) that satisfy
( ) ( )
i 1 o 2
1 k I 1 k I 0 . + = (1-44)
Strictly speaking, (1-43) implies that the respective input and output ports are no longer in series
with one another. Nonetheless, the architecture is unwaveringly referred to as a series-series
feedback configuration.
The Thvenin nature, and thus series electrical temperament, of the input and output
ports in a z-parameter equivalent circuit is a clue that z-parameters, which adopt port currents as
independent variables, might be profitably exploited to model series-series feedback architec-
tures. To this end, we write
1a 11a 12a 1
2a 21a 22a 2
V z z I
,
V z z I
( ( (
=
( ( (

(1-45)
for the base amplifier, and
1b 11b 12b 1b i 11b o 12b 1
2b 21b 22b 2b i 21b o 22b 2
V z z I k z k z I
,
V z z I k z k z I
( ( ( ( (
= =
( ( ( ( (

(1-46)
for the feedback subcircuit, where we have incorporated (1-43). The substitution of the last two
results into (1-42) readily delivers
( ) ( )
( ) ( )
11a i 11b 12a o 12b 1 1
21a i 21b 22a o 22b 2 2
z k z z k z V I
,
z k z z k z V I
+ + (
( (
=
(
( (
+ +

(1-47)
which suggests immediately that the entire structure in Figure (1.26a) can be represented by a z-
parameter model whose open circuit impedances subscribe to
( ) ( )
( ) ( )
11a i 11b 12a o 12b 11 12
21a i 21b 22a o 22b 21 22
z k z z k z z z
.
z k z z k z z z
+ + (
(
=
(
(
+ +

(1-48)
As indicated in conjunction with the shunt-shunt feedback architecture, the feedback
associated with the entire structure is likely to be dominated by the feedback implicit to the feed-
back subcircuit; that is, |z
12a
| << |k
o
z
12b
|. Moreover, overall feedforward, on which the net for-
ward gain is dependent, is largely determined by the base amplifier so that |z
21a
| >> |k
i
z
21b
|. Un-
der these circumstances, (1-48) implies the ability to model the linear characteristics of the se-
ries-series feedback architecture by the equivalent circuit we provide in Figure (1.26b). Observe
the branch impedance, k
i
z
11b
, in the loop associated with the input port of the amplifier and the
appearance of branch impedance k
o
z
22b
in series with the output port loop. These elements sug-
gest that series-series feedback is likely to increase both the input and output impedances of the
base amplifier. Since high impedance input ports accept voltage signals with minimal attenua-
tion and high output port impedances efficiently transfer current responses to load terminations,
the series-series feedback amplifier is best suited for transadmittance (or transconductance) sig-
nal processing.
1.2.6.3. Series-Shunt Feedback
The third type of feedback system is the global series-shunt architecture depicted in
Figure (1.27a). The input ports of the base amplifier and the feedback topology of this system
are electrically connected in series with one another, thereby encouraging high input impedance.

- 48 -
But the output ports of these two networks are connected in parallel with one another, which fos-
ters low output impedance. Accordingly, the series-shunt feedback architecture is well suited for
voltage amplifier applications.
Linear Model
Of Feedback
Network
-Circuit (b)-
I
1b
Z
s
V
1a
Linear Model
Of Base
Amplifier
-Circuit (a)-
k I
i 1
I
1
+
V
s
V
1b
V
1
I
2a
Z
l
I
2b
V
2
I
2
V
2
I
2
h I
21 a 1
Z
s
+
V
s
I
1
1
2
2
V
1
h V
12b 2
h
11a
k h
i 11b
h
22a
1
h
22b
1
(a).
3
4
V
2
Z
l
(b).
4
1 3

Figure (1.27). (a). System level abstraction of a series-shunt feedback amplifier. The base amplifier has
h-parameters h
ija
, while the feedback circuit is characterized by hybrid h-parameters of h
ijb
.
(b). Approximate equivalent circuit of the feedback architecture in (a). The model ignores
feedback within the base amplifier and feedforward incurred by the feedback network.
In Figure (1.27a), the net input port current, I
1
, supplied by the signal source flows
through the input port of the base amplifier and thence into the input port of the feedback struc-
ture. As is the case with the input port of the base amplifier deployed in series-series feedback,
the input port current returned by the present base amplifier is k
i
I
1
. Accordingly, (1-43) remains
applicable for current I
1b
, which is conducted by the input port of the feedback subcircuit. The
overall output port situation is simpler in that the overall voltage response, V
2
, developed across
the load termination is sustained across the output ports of both the base amplifier and feedback
structures.
The currents flowing in the input ports of both the base amplifier and the feedback
structure are proportional to the net input current, I
1
, while the respective output port voltages are
identical to signal voltage, V
2
. These facts are a clue that h-parameter modeling, which invokes
net input port current and net output port voltage as independent electrical variables, is optimal
for the series-shunt feedback architecture. Specifically, the h-parameter equivalent circuit
projects a Thvenin type (series) input port representation and a Norton type (shunt) output port

- 49 -
description. From Figure (1.27),
1a 1b 1a 1b 1
2a 2b 2a 2b 2
V V V V V
.
I I I I I
+
( ( ( (
= + =
( ( ( (
+

(1-49)
Moreover,
1a 11a 12a 1
2a 21a 22a 2
V h h I
,
I h h V
( ( (
=
( ( (

(1-50)
for the base amplifier, and for the feedback unit,
1b i 11b 12b 1
2b i 21b 22b 2
V k h h I
.
I k h h V
( ( (
=
( ( (

(1-51)
It follows that
( ) ( )
( ) ( )
11a i 11b 12a 12b 1 1
21a i 21b 22a 22b 2 2
h k h h h V I
,
h k h h h I V
+ + (
( (
=
(
( (
+ +

(1-52)
where it is understood that the effective matrix of h-parameters for the series-shunt feedback am-
plifier is
( ) ( )
( ) ( )
11a i 11b 12a 12b 11 12
21a i 21b 22a 22b 21 22
h k h h h h h
.
h k h h h h h
+ + (
(
=
(
(
+ +

(1-53)
If, as is typically the case, feedforward through the base amplifier prevails over the
feedforward properties of the feedback subcircuit and if intrinsic feedback within the base am-
plifier is negligible, (1-53) gives rise to the approximate equivalent circuit shown in Figure
(1.27b). The appearance of the element, k
i
h
11b
, as a branch impedance in series with the input
port of the series-series interconnection conflates with the high input impedance predilection.
On the other hand, the shunting action of the impedance, 1/h
22b
, across the output port diminishes
the achievable output impedance. It follows that the series-series feedback amplifier enjoys util-
ity in applications for which a specified voltage gain is targeted to be nominally independent of
source and load terminations.
1.2.6.4. Shunt-Series Feedback
It is hardly rocket science to surmise now that the final feedback architecture warrant-
ing consideration is the global shunt-series feedback amplifier, whose topology appears in Figure
(1.28a). In this topology, the input ports of the base amplifier and feedback unit are electrically
in parallel, while their output ports are connected in series. Consequently, low input and high
output impedances are forged by this interconnection, which is therefore tailored for current
amplification. As in the case of series-series feedback, the amplifier return current at the output
port is adjusted by a factor of k
o
.
The hybrid g-parameters are best suited for modeling the feedback system at hand. The
analysis proceeds along lines analogous to those invoked on the series-shunt structure. The
reader is encouraged to confirm that the hybrid g-parameter volt-ampere relationships of the
overall shunt-series network derive from
( ) ( )
( ) ( )
11a 11b 12a o 12b 1 1
21a 21b 22a o 22b 2 2
g g g k g I V
.
g g g k g V I
+ + (
( (
=
(
( (
+ +

(1-54)

- 50 -
Linear Model
Of Feedback
Network
-Circuit (b)-
I
2b
Z
l
Linear Model
Of Base
Amplifier
-Circuit (a)-
k I
o 2
V
2a
I
2
V
2b
V
2
I
1a
Z
s
V
1
I
1b
I
1
+
V
s
V
1
k g I
o 12 b 2
Z
s
+
V
s
I
1
1
2
V
1
g
11b
1
g
11a
1
(b).
(a).
Z
l
3
4
I
2
g
22a
g V
21a 1
k g
o 22b
V
2
2
1
4
3

Figure (1.28). (a). A shunt-series feedback amplifier. The base amplifier has g-parameters g
ija
, while the
corresponding feedback circuit parameters are g
ijb
. (b). Approximate equivalent circuit of
the feedback architecture in (a). The model presumes negligible feedback in the base am-
plifier and negligible feedforward through the feedback network.
The corresponding approximate equivalent circuit is given as Figure (1.28b). This model, like its
predecessors, is premised on the presumptions of negligible feedback internal to the base ampli-
fier and negligible feedforward through the feedback subcircuit.
1.3.0. ANALYSIS OF LINEARIZED ACTIVE NETWORKS
The four two-port models allow for convenient and systematic transfer function and I/O
impedance characterizations of any linear two-port network in terms of parameters extracted
from voltage and current responses observed at only the extrinsic ports of a network. These
models are the fundamental tools that expedite a computationally efficient and even insightful
analysis of electronic systems. They are especially germane to those electronic systems whose
base amplifier topologies are either unknown or otherwise too intricate for straightforward circuit
analyses predicated on the traditional Kirchhoff laws.
1.3.1. ANALYSIS VIA y-PARAMETERS
Recalling Figure (1.2a), the y-parameter equivalent circuit corresponding to a given
quiescent operating point imposed on the electronic system of Figure (1.1a) is the topology given

- 51 -
in Figure (1.29). Because y-parameter equivalent circuits exploit a Norton topology for their
input port, it is convenient to represent the signal source as a Norton structure. In this Norton
representation, the short circuit signal current is I
s
, and the presumably large shunt impedance
associated with this signal source is Z
s
. An inspection of the subject model reveals
21 1
2
22 l
y V
V
y Y
=
+
(1-55)
and
( )
s 11 s 1 12 2
I y Y V y V , = + + (1-56)
where Y
l
= 1/Z
l
and Y
s
= 1/Z
s
symbolize the admittances of the load and source impedances,
respectively. If we insert (1-55) into (1-56), we obtain
( )
12 21 1
s 11 s 1
22 l
y y V
I y Y V .
y Y
= +
+
(1-57)
Linear Model
Of Electronic
Network
I
1
I
s
I
s
1
2
V
2
3
4
I
2
Z
l
Z
l
Z
s
Z
s
V
1
I
1
y V
12 2
1
2
1/y
11 V
1
Y
out
Y
in
V
2
3
4
I
2
y V
21 1
1/y
22

Figure (1.29). The y-parameter equivalent circuit for a linear model of an electronic network. The
electronic network is designed to provide transimpedance signal processing. The
applied input signal is represented as an independent current source because of the
Norton nature of the y-parameter input port model.
The last expression suggests that in the absence of feedback, which is typified by the condition,
y
12
= 0, load admittance Y
l
imposes no load on the current that must be supplied by the signal
source, I
s
, to sustain an input port voltage of V
1
. But for nonzero feedback, an appreciable load is
manifested by Y
l
on the signal source and more generally, on the amplifier input port. We
prognosticate an appreciable load, because in (1-57), feedback parameter y
12
multiplies
feedforward parameter y
21
, which (1-55) postures as a measure of the achievable I/O voltage gain
of the network. If we adopt large gain as a design target, parameter y
21
must be suitably large,
which, by (1-57), gives rise to possibly significant input port loading sensitivity to the load
termination.
The combination of (1-57) and (1-55) delivers a system transimpedance, Z
fs
= V
2
/I
s
, of
( )( )
( )( )
2
s
21
11 s 22 l
fs
12 21
11 s 22 l
y
V
y Y y Y
Z .
y y
I
1
y Y y Y
+ +
=
+ +
(1-58)
If I/O transimpedance is not the fundamental design target, we can convert this transimpedance,
to a transadmittance, voltage gain, or current gain. Such conversion relies on recognizing that

- 52 -
output current I2 is I
2
= Y
l
V
2
and that the Norton source current is related to its Thvenin
source voltage, say V
s
, by I
s
= Y
s
V
s
.
1.3.1.1. Transfer Function And Gain Metrics
The algebraic sloppiness of the gain expression in (1-58) hardly fosters the proverbial
warm feelings in the tummy in that it does not lend itself toward forging design insights about
the behavior of the system undergoing investigation. But a more constructive format emerges if
we exploit the substitution,
( )( )
21
fo
11 s 22 l
y
Z ,
y Y y Y
=
+ +
(1-59)
whereupon (1-58) becomes the manageable relationship,
2
s
fo
fs
12 fo
V Z
Z .
I 1 y Z
=
+
(1-60)
An initial inspection of this transimpedance formulation indicates that Z
fo
represents the I/O
transimpedance gain under the condition of zero net feedback factor. Note we have not claimed
that Z
fo
is the I/O transimpedance with the feedback subcircuit removed; we infer only that Z
fs
=
Z
fo
when net feedback factor is null; that is, y
12
= 0. The reason for this critically important
disclaimer is that Z
fo
in (1-59) is directly proportional to y
21
, which, recalling (1-40), includes
feedforward effects through the feedback subcircuit, along with the dominant feedforward
transmission manifested by the base amplifier. Moreover, Z
fo
is a function of parameters y
11
and
y
22
, which again by (1-40), respectively include the effects of input port loading and output port
loading incurred by the feedback subcircuit.
Equation (1-60) implies the algebraic relationship,
( )
2 fo s 12 2
V Z I y V , = (1-61)
Z
fo
y
12
I
s
V
2
y V
12 2
I y V
s 12 2

Figure (1.30). Signal flow representation of the I/O transfer characteristics for
the circuit in Figure (1.24). The diagram highlights the feedback,
as manifested by parameter y
12
, inherent to the subject circuit.
which maps into the system level block diagram provided in Figure (1.30). The block diagram is
a conceptually useful design-oriented tool in that it enables ascribing an engineering perspective
to the various model parameters introduced in (1-60). For example, the y-parameter, y
12
, is
clearly portrayed in Figure (1.30) as a global feedback metric in that a current, y
12
V
2
, which is
obviously proportional to the output response, V
2
, is returned all the way back to the input port
(hence, the adjective, global) where it is algebraically summed with the signal source current.
The summing action derives from KCL applied to the input port node. We note that the resultant
current difference signal, (I
s
y
12
V
2
), which is commonly referred to as the error signal in a
feedback network, must have a magnitude that is smaller than that of the prevailing signal

- 53 -
current, I
s
, for otherwise, V
2
is unbounded. This latter contention is intimately related to the
problem of ensuring electronic network stability, about which far more is discussed later. When
the magnitude of the error signal is smaller than the magnitude of the applied input signal source
(current I
s
in this case), we say that negative feedback prevails in the subject feedback network.
Observe, for example, that if negative feedback is to prevail at low frequencies where y
12
is
invariably frequency invariant, the current, y
12
V
2
must be positive. This means, for example, that
if phase inversion prevails between signal source I
s
and voltage response V
2
, V
2
is negative for
positive I
s
, whence y
12
must be negative to achieve negative (stable) feedback.
A further study of the block diagram at hand divulges that a closed loop path from the
input port to the output port and back to the input port is established by the blocks labeled Z
fo
and
y
12
. This closed loop encourages referencing the transimpedance, Z
fs
, in (1-60) as the closed loop
transimpedance of the electronic network. In other words, the closed loop gain is the actual
transimpedance observed when the effects of all model elements in the system, including those
of the feedback subcircuit, are embraced by circuit analysis. The loop is broken, or opened,
when the feedback factor is set to zero, whence the transimpedance reduces to Z
fs
= Z
fo
. Since
y
12
= 0 effectively breaks the closed loop we have introduced, Z
fo
is known as the open loop
transimpedance of the network undergoing investigation. In effect, the open loop gain of an
electronic network is the ratio of the output port response to the error signal. Moreover, Z
fo

happens to be the effective overall gain of the network for the special case of zero feedback
transadmittance, which effectively breaks the aforementioned closed loop. Of course, the loop
can be opened by setting Z
fo
to zero. But such action wins you clown of the month honors in that
Z
fo
= 0 severs the signal path from input to output ports and therefore precludes the possibility of
any nonzero I/O gain.
The aforementioned closed loop path forged by the open loop gain block and the feed-
back factor block manifests a net loop gain, T
y
(Y
s
, Y
l
), given by
( )
( )( )
12 21
y s l 12 fo
11 s 22 l
y y
T Y ,Y y Z ,
y Y y Y
= =
+ +
(1-62)
where subscript y reminds us that we have adopted y-parameters for the analysis. Moreover,
the functional dependence on the source admittance, Y
s
, and load admittance, Y
l
, incorporated
into the loop gain notation derives from the dependence of the open loop gain on these admit-
tance terminations. The loop gain, T
y
(Y
s
, Y
l
), is alternatively referred to as the y-parameter return
ratio of the considered network. A related metric, F
y
(Y
s
, Y
l
), which is known as the return differ-
ence of the subject network, is simply the ratio of the open loop gain to the closed loop gain.
Thus, the return difference is the factor by which the open and closed loop gains differ owing to
the dynamics of incorporated feedback. We observe that the loop gain is zero and the return
difference is one when no feedback factor is evidenced in the network. Recalling (1-60),
( ) ( )
2
s
fo fo fo
fs
12 fo y s l y s l
V Z Z Z
Z ,
I 1 y Z 1 T Y , Y F Y , Y
= = =
+ +
(1-63)
where
( ) ( )
fo
y s l y s l
fs
Z
F Y , Y 1 T Y , Y .
Z
+ (1-64)
One attribute of the return difference function is that in principle, it elegantly conveys
the necessary condition underlying system stability. In particular, the return difference is a
function of frequency and thus, the Laplace operator, s, because of the energy storage

- 54 -
elements implicit to the base amplifier and feedback subcircuits. As such, the roots of F
y
(Y
s
, Y
l
),
which are the poles of the I/O closed loop transimpedance, must lie in the left half s-plane; that
is, the real parts of all of these roots must be negative numbers. The assurance of only left half
plane poles guarantees that time domain responses to any type of input signal excitation remain
bounded for all time; that is, the network is unconditionally stable. As interjected earlier,
stability fans are asked to await a forthcoming chapter for relevant design requirements and
details.
Return to (1-63) or (1-60) and consider the case of a stable system in which the magni-
tude of the loop gain is far greater than unity; that is, |T
y
(Y
s
, Y
l
)| = |y
12
Z
fo
| >> 1. Under this
condition, the closed loop transimpedance reduces to the simple result,
2
s
12 fo
fs
12
|y Z | 1
V
1
Z .
I y
>>
= ~ (1-65)
In other words, a very large loop gain in a stable electronic network modeled by y-parameters
produces a closed loop transimpedance that depends on only the feedback factor, y
12
. This result
contrasts sharply with (1-60), which with the help of (1-59), shows a closed loop transimpedance
that is dependent on six parameters. As an engineering rule of thumb, network performance
functions that are simple in the sense of being dependent on a minimum number of circuit va-
riables generally (but not always) give rise to monolithic networks exuding high yield and
excellent reproducibility
1
.
The result advanced by (1-65) is both interesting and insightful from at last four
perspectives. First, the gain in (1-65) is independent of source and load terminations, thereby
rendering the given network suitable for a broad variety of general input port and output port
terminations. Second, the closed loop gain is invariant with the open loop gain in (1-59), which
implies that the y-parameters, y
11
, y
21
, and y
22
, are nominally unimportant with respect to
stipulating the closed loop performance of the amplifier, as long, of course, as the loop gain
remains very large. Processing and manufacturing vagaries, operating temperature changes,
parasitic uncertainties associated with circuit layout and/or device modeling, and other
engineering problems invariably alter the measured values of one or more of these admittance
parameters. But for very large loop gain systems, these resultant parametric shifts have
essentially no impact on the observable closed loop performance predicted by (1-65). To the
extent that parameter y
12
can be rendered independent of the quiescent operating point of the
network, standby voltage or current fluctuations incurred by poorly regulated static supplies, and
temperature variations, we can conclude that the closed loop gain is accurately predictable and
reliably reproducible. Finally, we note that if (1-65) is indicative of the closed loop
transimpedance, the error signal, (I
s
y
12
V
2
), which drives the open loop component of the feed-
back network is zero. In other words, high loop gain in a stable feedback architecture drives the
observable error signal to zero. Thus, in cases for which the loop gain of a network to which
global shunt-shunt feedback is applied is very large, a viable first order estimate of the closed
loop transimpedance is simply the inverse, 1/y
12
, of the net feedback transadmittance.
The elimination, or at least circumvention, of the effects of the foregoing environmental

1
High yield means that a large percentage (80% or more of the circuits fabricated on the processed wafer meet or
exceed all stipulated performance specifications. Reproducibility means that circuits fabricated at one point in time
do not differ substantively from those circuits that are fabricated later. In a word, the Friday circuit is just as good as
the Monday realization.

- 55 -
issues is a fundamental objective of all circuit design endeavors. Such prudent design results in
circuits that can be produced to meet stipulated performance specifications reliably and
reproducibly. The design issue here is transparent. In particular, Z
fs
in (1-65) depends on one
parameter, while the general expression for Z
fs
in (1-60) is a function of six parameters (source
and load admittances included). One parameter can arguably be controlled easier than can six,
especially when that one parameter derives from a ratio of reasonable valued passive compo-
nents. When we find that the performance metric of interest is largely determined by few, as op-
posed to many, network parameters, we applaud the feedback configuration for satisfying its
principle goal. In particular, the incorporated feedback achieves a relative desensitization of
performance with respect to the numerous, generally active, elements and therefore generally
difficult to predict, parameters on which the open loop gain is functionally dependent. It follows
that an electronic circuit whose I/O transfer characteristics abide by (1-65) is robust in the sense
of its relative insensitivity to the deleterious ramifications of design, manufacturing, and both
engineering and environmental uncertainties.
The third interesting perspective fostered by (1-65) is that on the presumption of a
design goal that nurtures a greater than unity magnitude of closed loop gain, the magnitude of the
feedback parameter, y
12
, must be correspondingly smaller than one siemen. But since (1-65)
requires |y
12
Z
fo
| >> 1, this feedback factor limitation implies that the magnitude of the open loop
gain, Z
fo
, must be very large. We note that while Z
fo
is indeed a function of five parameters, the
numerical values of most or all of which may be difficult to predict and control precisely, it is
not necessary that Z
fo
be obligated to a particular numerical value; instead, it simply must mirror
a sufficiently large magnitude that satisfies the inequality, |y
12
Z
fo
| >> 1. Thus, we must ensure
that very large loop gain be achieved for realistic worst case operating circumstances. We
deduce from (1-65) that |y
12
Z
fo
| >> 1 must therefore be satisfied for the smallest estimated
magnitude of the forward gain metric, y
21
, and the largest anticipated magnitudes of the
admittances, y
11
, y
22
, Y
s
, and Y
l
.
1.3.1.2. Circuit Interpretation of the Loop Gain
The loop gain, is a critically important circuit metric in that it effectively brackets the
quality of a feedback system in at least the senses of closed loop network stability and the
desensitization of the closed loop gain with respect to open loop parametric uncertainties. As is
demonstrated in the following subsection, the loop gain is even critically important to the
problems of determining the input and output impedances of a feedback network. Accordingly, a
clear understanding of the manner in which a given circuit establishes its loop gain is vital for
innovative and creative circuit design. In order to examine this loop gain from an engineering
perspective, we return to the block diagram of Figure (1.30) and consider the case of zero input
signal; in this case, I
s
= 0. The output voltage response, V
2
, obviously vanishes in the absence of
source excitation. A non-vanishing response in the face of zero input signal is indicative of
either an unstable system (at least one closed loop pole lies in the right half plane) or a system
whose designer is a viable candidate for Nobel distinction in that said system produces output
signal energy despite the absence of applied input energy. With I
s
sustained at zero, let the loop
be broken between the output port and the feedback network input port. The input port to the
feedback subcircuit normally accepts a voltage input as per Figure (1.30) but in this broken loop
case, allow an independent and phase-inverted test voltage signal, say V
test
, to be applied to the
feedback subcircuit, as indicated in Figure (1.31a). The resultant response of the feedback block
is y
12
V
test
, and with I
s
= 0, the error signal applied to the open loop component of the system is
merely +y
12
V
test
. It follows that this input excitation manifests an output voltage, V
2
, of

- 56 -
+y
12
Z
fo
V
test
, whence we conclude that the gain, V
2
/V
test
, around the entire modified network loop
is seen to be y
12
Z
fo
. From (1-62), this voltage gain is precisely the loop gain of the original
feedback network. It is important to comprehend the product, y
12
Z
fo
, as signifying the gain
around the entire network loop, for the response evaluated under the special test condition is ex-
tracted at the same node to which the phase-inverted test signal is applied.
Z
fo
y
12
I
= 0
s
V
= y Z V
2
12 fo test
y V
12 test
+y V
12 test
(b).
(a).
Z
l
Z
s
I
1
y V
12 test
1
2
1/y
11 V
1
V
2
3
4
I
2
y V
21 1
1/y
22
V
test
( )( )
2 12 21
y s l
test 11 s 22 l
V y y
T (Y , Y )
V y Y y Y
=
+ +

Figure (1.31). (a). The block diagram of Figure (1.30) with the feedback loop broken and a test
voltage signal, V
test
, inserted at the input port of the feedback subcircuit. (b). The
y-parameter equivalent circuit of the system captured in (a). Note that the
feedback controlled source is reversed to reflect the test condition of an input
signal, V
test
, applied to the input port of the feedback unit.
With I
s
= 0 and with an input signal, V
test
, applied to the input port of the feedback
unit, the y-parameter equivalent circuit drawn in Figure (1.29) becomes the network shown In
Figure (1.31b). In this representation, we reverse the polarity of the original feedback current,
y
12
V
2
, to account for the test condition input, V
test
, applied to the feedback subcircuit. Note
further that the revised model reflects no feedback presence and that an effective input signal,
y
12
V
test
, is applied to the amplifier input port in a fashion that mirrors the application of the origi-
nal signal source, I
s
. But since no feedback prevails herewith, the input of y
12
V
test
is effectively
applied to the input port of the open loop component of the feedback architecture. A straightfor-
ward circuit analysis predicated on the subject model reveals a voltage ratio, V
2
/V
test
, that is iden-
tical to the loop gain function appearing on the far right hand side of (1-62). It is important to
remember that the y-parameters, y
ij
, embedded in this test model are the net admittance
parameters of the entire feedback circuit and not just the parameters of the base amplifier.
1.3.1.3. Input and Output Admittances
In addition to quantifying the transfer function of a linear network, the loop gain intro-
duced in the preceding subsection plays a pivotal role in the determination of the driving point
input and output admittances of the network. The driving point input admittance is the input
admittance seen by the entire signal source (inclusive of the source admittance) with the output

- 57 -
port terminated in the actual load impedance. Similarly, the driving point output admittance is
the admittance effectively shunting the terminating load impedance, with the signal source sup-
planted by its internal impedance. The model pertinent to an evaluation of the input admittance
is shown in Figure (1.32a), while its output admittance counterpart appears in Figure (1.32b). In
the former case, the signal source comprised of the shunt interconnection of current I
s
and admit-
tance Y
s
is replaced by an ideal independent current source, I
x
. This independent current estab-
lishes a terminal voltage, V
x
, in disassociated reference polarity to I
x
, so that the desired input
admittance is the current to voltage ratio, I
x
/V
x
. In effect, we have inserted a mathematical
ohmmeter in shunt with the input port and in the process, we have removed the signal source.
An analogous ohmmeter replaces the load admittance, Y
l
in Figure (1.32b), where we note that
the signal source is represented by its original shunting impedance, Z
s
.
I
x
Z
l
Z
s
I
1
y V
12 2
1
2
1/y
11 V
1
Y
in
V
2
3
4
I
2
y V
21 1
1/y
22
V
x
(a).
I
x
I
1
y V
12 2
1
2
1/y
11 V
1
Y
out
V
2
3
4
I
2
y V
21 1
1/y
22
V
x
(b).

Figure (1.32). (a). The y-parameter model pertinent to computing the driving point input admittance of the
electronic network in Figure (1.25). (b). The y-parameter model for computing the driving
point output admittance of the electronic network in Figure (1.25).
The driving point input admittance has all but been determined by (1-57). Comparing
Figure (1.32a) with Figure (1.29), the only differences are (1) the source admittance is set to zero
(equivalent to infinitely large source impedance Z
s
), (2) current I
s
is replaced by the ohmmeter
current, I
x
, and (3) voltages V
1
and V
x
both represent potentials developed across the input port.
Thus, the driving point input admittance, Y
in
, is
( )
s
x s 12 21 12 21
in 11 11
x s 22 l 11 22 l
Y 0
I I y y y y
Y y y 1 .
V V y Y y y Y
=
(
= = = =
(
+ +

(1-66)
While authors, and especially authors who are university professors, never commit errors, it is
nonetheless prudent to validate (1-66) for at least one special case. In particular, observe as ex-
pected that Y
in
collapses to y
11
(the short circuit input admittance) if the load admittance, Y
l
, is
infinitely large, which indeed represents a short circuited load impedance.
An especially useful form of (1-66) evolves from the use of (1-62). To wit,
( )
x
in 11 y l
x
I
Y y 1 T 0,Y ,
V
( = = +

(1-67)
where T
y
(0, Y
l
) is the originally computed loop gain, T
y
(Y
s
, Y
l
), evaluated under the condition of
Y
s
= 0. This result reveals several interesting properties of the transimpedance amplifier. First,
parameter y
11
, in addition to symbolizing the short circuit input admittance of the amplifier, can

- 58 -
be viewed as the open loop input admittance for with y
12
= 0, which produces T
y
(0, Y
l
) = 0, Y
in

y
11
. We therefore reasonably interpret the driving point input admittance predicted by (1-67) as
the closed loop input admittance, which is to say that (1-67) represents the input admittance
when the loop gain is nonzero. Second, the driving point input admittance of a stable
transimpedance feedback amplifier is likely to be bolstered by feedback. This admittance
enhancement is especially pronounced if the amplifier is designed to deliver an I/O
transimpedance that approximates the inverse of the feedback parameter, y
12
. In such a case, a
very large loop gain is mandated and since |T
y
(0, Y
l
)| is larger than |T
y
(Y
s
, Y
l
)| owing to the
inverse dependence of the loop gain on source admittance, Y
in
is potentially significantly larger
than is its open loop counterpart. This situation is good news for in a transimpedance amplifier,
low and even ideally zero, driving point input impedance is desired to promote an input port
signal current that is virtually identical to the applied signal source current.
Returning to Figure (1.32) KCL applied to the output port of the model in Figure
(1.31b) gives
x 22 x 21 1
I y V y V , = + (1-68)
where
12 x
1
11 s
y V
V
y Y
=
+
(1-69)
and we have made use of the fact that the output port voltage, V
2
, is identical to the ohmmeter
voltage, V
x
. Subsequent to substituting (1-69) into (1-68), we find that the driving point, or
closed loop, output admittance, Y
out
, is
( )
x 12 21 12 21
out 22 22
x 11 s 22 11 s
I y y y y
Y y y 1 .
V y Y y y Y
(
= = =
(
+ +

(1-70)
Appealing to (1-62) once again,
( )
x
out 22 y s
x
I
Y y 1 T Y ,0 ,
V
( = = +

(1-71)
where T
y
(Y
s
, 0) is the loop gain, T
y
(Y
s
, Y
l
), evaluated for Y
l
= 0. The similarity between this last
result and (1-67) for the input admittance is indisputable. It is therefore only reasonable that the
commentary offered with respect to the input admittance function applies to the output admit-
tance as well. In brief, y
22
represents the open loop output admittance, which is likely to be
appreciably enhanced in a transimpedance unit by the feedback embedded therein.
EXAMPLE #1.7:
Figure (1.33) is an approximate low frequency model of a single stage BJT am-
plifier that incorporates a feedback resistance identified as R
f
. Although the am-
plifier is fundamentally a transimpedance unit, the closed loop transfer function
of interest herewith is the voltage gain, V
2
/V
s
. To this end, derive general
expressions for the open loop voltage gain, loop gain, and closed loop voltage
gain. Also, give general expressions for the open loop and closed loop input and
output driving point resistances, R
in
and R
out
, respectively, of the amplifier.
Numerically evaluate all of the foregoing metrics for R
s
= 300 , r
i
= 4 K, R
f

= 2.7 K, r
o
= 40 K, R
l
= 5 K and finally, | = 150 amps/amp.
SOLUTION #1.7:

- 59 -
(1). Figure (1.34a) redraws the schematic diagram of Figure (1.33) to highlight the connection of
resistance R
f
as a feedback branch that is in shunt with both of the I/O ports of the base am-
plifier. Although R
f
is merely a conventional two terminal resistance, it can nonetheless be
viewed as a two-port network in that its incidence with the input and output ports of the base
amplifier shares the ground node of said amplifier. If we adopt the notation advanced by (1-
38), it is readily apparent that for the resistive feedback circuit,
+
V
s
R
s
r
i
R
f
I
I
1
V
1
I
r
o
R
l
V
2
I
2
R
in
R
out

Figure (1.33). Linearized low frequency model of the transimpedance amplifier
considered in Example #1.7. Feedback is implemented in the form
of the resistance, R
f
.
2 1
1b 2b
11b 22b
1 f 2
V 0 V 0
I I 1
y y
V R V
= =
= = = (E7-1)
and
1 2
1b 2b
12b 21b
2 f 1
V 0 V 0
I I 1
y y .
V R V
= =
= = = (E7-2)
Obviously, y
12b
y
21b
because of the passive nature of the feedback element.
(2). The base amplifier in Figure (1.34a) delivers
2
1a
11a
1 i
V 0
I 1
y ,
V r
=
= = (E7-3)
and recognizing that with V
2
= 0, I
2
= |I = |V
1
/r
i
,
2
2a
21a
1 i
V 0
I
y .
V r
=
= = (E7-4)
Continuing, while noting that the controlling current, I, for the dependent generator, |I, is
identical to the input port current, I
1a
, of the base amplifier,
1
2a
22a
2 o
V 0
I 1
y ,
V r
=
= = (E7-5)
and
1
1a
12a
2
V 0
I
y 0 .
V
=
= = (E7-6)
The last result underscores a base amplifier boasting no internal feedback.
Before proceeding further with the solution to this problem, a few sidebars may prove to be
instructive. In particular, (E7-1) through (E7-6) can be substituted into (1-40), and the resul-
tant equations can be written out, albeit on scratch paper. An inspection of these port equili-
brium relationships suggests that the original circuit is electrically identical to the network

- 60 -
offered in Figure (1.34b). Although the latter circuit is not especially inviting from a sheer
circuit analysis undertaking, it does underscore clearly the input port loading, output port
loading, feedback, and feedforward that are implicit to attaching resistive feedback in shunt-
shunt connection to a base amplifier.
+
V
s
R
s
r
i
R
f
I
I
1
V
1
I
r
o
R
l
V
2
I
2
I
1a
I
2a
I
2b
I
1b
(a).
+
V
s
R
s
r
i
I
I
1
V
1
I
r
o
R
l
V
2
I
2
(b).
R
f
R
f
V
2
R
f
V
1
R
f
R
in
R
out

Figure (1.34). (a). The amplifier model of Figure (1.32) with resistance R
f
relocated to confirm its function
as shunt-shunt feedback with the base amplifier. (b). Alternative model to the structure in (a),
which expressly delineates the effects that feedback resistance R
f
exerts on the base amplifier.
(a). Observe that resistance R
f
appears in shunt with both the input and output ports of the
base amplifier, thereby suggesting that the appended feedback resistor increases the
impedance loading imposed on these ports. Clearly, too small of a resistance causes
diminished voltage gain because both ports ultimately resemble a short circuit in the ex-
treme limit of very small R
f
.
(b). Note that a controlled current source of value V
1
/R
f
is manifested directly across the con-
trolled source, I, at the output port of the overall system. The I source models feedfor-
ward through the base amplifier from its input port to its output port. On the other hand,
the source, V
1
/R
f
, accounts for feedforward through the resistive feedback element. In
other words, the potential difference, (V
1
V
2
), developed across R
f
encourages a portion
of the base amplifier input port current to bleed to the output port through R
f
. This
bleeding is in a direction to incur a clockwise current flow through the load resistance,
which is the reason that the polarity of the subject feedforward controlled source is
opposite to that of I. Once again, too small of a resistance value, R
f
, is undesirable, this
time from the viewpoint of incurring significant parasitic signal feedforward. If
comparable to the feedforward current in the base amplifier (which indeed reflects an ex-
treme condition), this undesirable feedforward through the feedback element substan-
tively attenuates the overall gain of the network.
(c). The fundamental purpose of installing R
f
is to provide feedback from the amplifier out-

- 61 -
put port to its input port. To this end, the generator, V
2
/R
f
, which is intimate with the
y
12
V
2
controlled source in a y-parameter model, appears across the amplifier input port as
a current proportional to the output port voltage. The subject current source flows north,
as opposed to the conventional downward flow of y
12
V
2
because y
12b
, which in this case
is identical to y
12
, is the negative of 1/R
f
.
(d). The final sidebar statement may be perceived by the reader as academic chicanery and
indeed repetitive in light of previous discourse. But it does reflect a lesson that must be
learned now! In particular, and despite the clearly feedback nature of resistance R
f
and
even a small body of literature to the contrary, the evaluation or computation of open
loop metrics for the amplifier at hand does not mean that R
f
is to be physically removed.
To remove R
f
is to neglect the effects of its I/O port loading, as well as its parasitic
feedforward. Open loop computations herewith mean only that the feedback factor, y
12
,
in the y
12
V
2
generator is set to zero. Specifically, the generator, V
2
/R
f
, and only that
generator, is set to zero in the course of open loop circuit evaluations. In other words,
open loop allows for the removal of only the output port to input port feedback factor,
and assuredly not the other aforementioned ramifications of feedback. Of course, it can
be argued that for suitably large R
f
, loading and parasitic feedforward are negligible. In
this case, and only in this special case, open loop circumstances can be adequately
approximated by disconnecting the feedback resistance.
(3). Continuing now with the problem at hand, the results of the first two steps of the solution
tack combine with (1-40) to deliver the short circuit admittance parameters of the overall net-
work. Specifically,
11 11a 11b
i f i f
1 1 1
y y y ,
r R r R
= + = + = (E7-7)
12 11a 11b
f
1
y y y ,
R
= + = (E7-8)
i
21 21a 21b
i f i f
r 1
y y y 1 ,
r R r R
| |
= + = = |
|
\ .
(E7-9)
and
22 22a 22b
o f o f
1 1 1
y y y .
r R r R
= + = + = (E7-10)
(4). Using (1-59) and the preceding disclosures, the open loop transimpedance is
( )
f s
i
fo o f l
f
f s i
R R
r
Z 1 r R R ,
R
R R r
| |
| |
|
= |
|
|
+
\ .
\ .
(E7-11)
which is clearly and correctly a function, albeit a relatively weak function, of the feedback
resistance. In fact, the first parenthesized term on the right hand side of (E7-11) accounts for
feedforward through the feedback resistance. The second parenthesized term in the subject
relationship incorporates the effect of input port loading by the feedback element. Finally,
the last parenthesized term incorporates feedback resistance loading of the amplifier output
port. The open loop transimpedance in (E7-11) represents the zero feedback factor value of
the ratio of the output port voltage, V
2
, to the Norton equivalent signal source current, which
is V
s
/R
s
. Accordingly, the open loop voltage gain, say A
vo
, is

- 62 -
12
12 12
2 s
y 0 fo
2 2
vo
s s s s s
y 0 y 0
o f l f
i
f f i i f s
V I
Z
V V
A
V I R R R
r R R R
r
1 52.58 volts/volt .
R R r r R R
=
= =
= = = =
| |
| | | |
|
= = | |
| |
+ + |
\ . \ .
\ .
(E7-12)
(5). From (1-62) and (E7-11), the loop gain evaluated in terms of admittance parameters is
o f l
i s
y s l 12 fo
f s i i s f
r R R
r R
T ( G ,G ) y Z 1 5.84 ,
R R r r R R
| |
| |
| |
|
= = = |
|
|
| + +
\ .
\ .
\ .
(E7-13)
which is hardly large by most feedback network standards. For future use, the zero source
conductance and zero load conductance values of the loop gain are computed here as
o f l
i
y l
f i s f
r R R
r
T ( 0,G ) 1 83.74 ,
R r R R
| |
| |
|
= = |
|
| +
\ .
\ .
(E7-14)
and
o f
i s
y s
f s i i s f
r R
r R
T ( G ,0 ) 1 8.80 .
R R r r R R
| | | |
| |
= = | |
|
| |
+ +
\ .
\ . \ .
(E7-15)
(6). Equation (1-63) stipulates the closed loop transimpedance of the shunt-shunt feedback am-
plifier. It therefore follows that the closed loop voltage gain, A
v
, is
fo s
vo
v
y s l y s l
Z R
A
A 7.68 volts/volt ,
1 T ( G , G ) 1 T ( G , G )
= = =
+ +
(E7-16)
where Z
fo
is given by (E7-11) and the loop gain, T
y
(G
s
, G
l
), is the expression in (E7-13).
(7). The open loop input admittance (conductance) is simply y
11
. Thus, the corresponding open
loop input resistance, say R
ino
, is
ino i f
11
1
R r R 1.61 K .
y
= = = (E7-17)
Equation (1-67) defines the closed loop driving point input admittance (conductance), the in-
verse of which is the closed loop driving point input resistance, R
in
. Consequently and with
the help of the preceding result and (E7-14),
ino
in
y l
R
R 19.02 .
1 T ( 0, G )
= =
+
(E7-18)
The open loop output conductance is y
22
, whence an open loop output resistance, say R
outo
, of
outo o f
22
1
R r R 2.53 K .
y
= = = (E7-19)
This result, (E7-15), and (1-71), leads to a closed loop driving point output resistance, R
out
, of
outo
out
y s
R
R 258.16 .
1 T ( G , 0 )
= =
+
(E7-20)
Although we can argue that the circuit in Figure (1.33) is not so complicated that the gain and
impedance levels could not be deduced by conventional Kirchhoff methods, applying the
feedback concepts introduced in Section (1.2.6.1) has several advantages. First, the partition-

- 63 -
ing of the feedback subcircuit, which in this case is a simple two-terminal resistance, from the
base amplifier facilitates the evaluation of the short circuit admittance parameters for the
overall network. Second, the identification of such feedback circuit metrics as open loop
gain, loop gain, and so forth renders the fruits of analytical endeavors more understandable.
For example, the loop gain in (E7-13) is not very large, which immediately teaches that the
overall gain of the network is not optimally desensitized to changes in the various network
element values that pervade the open loop transimpedance. The subject expression also
shows that larger loop gains can be obtained for larger load resistance, R
l
, larger source resis-
tance, R
s
, and so forth.
It should be interjected that if the loop gain were to be made very large, (E7-13) and (E7-16)
verify an approximate closed loop gain, A
v
, of R
f
/R
s
, which is reminiscent of stereotypical
operational amplifier cells with a feedback resistance appended globally between its output
and inverting input terminals. If this large loop gain assumption is invoked a priori, the
closed loop gain estimate is 9 volts/volt, whose magnitude differs from the true gain magni-
tude computed in (E7-16) by slightly more than 17%.
The example computations suggest that the amplifier at hand is a far better transimpedance
unit than it is a voltage amplifier, which functions best when its input impedance is large and
its output impedance is small. To wit, a driving point input resistance of about 19 ohms
means that the net input current is essentially the Norton source current for most high imped-
ance sources. But for typical voltage sources, a low input resistance spawns significant
attenuation, dependent on the signal source resistance, of the applied voltage signal at the am-
plifier input port. The output resistance of slightly less than 260 ohms does not imply a great
output voltage port, but it can reasonably drive load terminations whose resistances are at
least a few thousand ohms.
1.3.2. ANALYSIS VIA z-PARAMETERS
For a particular quiescent operating point, the z-parameter equivalent circuit of the elec-
tronic system of Figure (1.1a) is the topology submitted as Figure (1.35a). Because z-parameter
equivalent circuits exploit a Thvenin input port topology, the signal source is represented in
Thvenin format. An inspection of Figure (1.35a) produces the output port relationship,
21 1
2
22 l
z I
I ,
z Z
=
+
(1-72)
as well as the input port expression,
( )
s s 11 1 12 2
V Z z I z I . = + + (1-73)
The combination of (1-72) and (1-73) generates
( ) ( )
( )( )
12 21 1 12 21
s s 11 1 s 11 1
22 l s 11 22 l
z z I z z
V Z z I Z z 1 I .
z Z Z z z Z
(
= + = +
(
+ + +
(

(1-74)
Substituting the solution for current I
1
in (1-74) into (1-72) gives an I/O transadmittance, say Y
fs
,
which is indeed the closed loop transadmittance of the active network, of
( )( )
( )( )
21
11 s 22 l
2
fs
12 21
s
11 s 22 l
z
z Z z Z
I
Y .
z z
V
1
z Z z Z
+ +
= =
+ +
(1-75)
Under open loop circumstances, for which z
12
= 0, the transadmittance in (1-75) is the
open loop transadmittance, Y
fo
; namely,

- 64 -
+
I
1
1
2
V
2
3
4
I
2
z
22
V
1
z I
21 1
z I
12 2

z
11
Linear Model
Of Electronic
Network
I
1
V
s
V
s
1
2
V
2
3
4
I
2
Z
l
Z
l
Z
s
Z
s
V
1
Z
out
Z
in
(a).
I
1
1
2
V
2
3
4
I
2
z
22
V
1
z I
21 1
z I
12 test

z
11
Z
l
Z
s
(b).

Figure (1.35). (a). The z-parameter linear model of an electronic network. The electronic network is de-
signed to provide transadmittance signal processing. The applied input signal is represented
as an independent voltage source because of the Thvenin nature of the z-parameter input port
model. (b). The equivalent circuit pertinent to the computation of the z-parameter loop gain,
T
z
(Z
s
, Z
l
) = I
2
/I
test
.
( )( ) 12
21
fo fs
z 0
11 s 22 l
z
Y Y .
z Z z Z
=
= =
+ +
(1-76)
It follows that (1-75) is elegantly expressible as
fo
2
fs
s 12 fo
Y
I
Y .
V 1 z Y
= =
+
(1-77)
The mathematical form of this closed loop transadmittance is identical to that of the transimped-
ance expression in (1-60). Indeed, replacing all z-parameters by their corresponding y-parame-
ters and further replacing source and load impedances by their respective admittances renders (1-
76) identical to (1-59) and (1-75) the same as (1-58). This similarity of expressions applies
equally well to the loop gain metric, T
z
(Z
s
, Z
l
), which for z-parameters is
( )
( )( )
12 21
z s l 12 fo
11 s 22 l
z z
T Z , Z z Y .
z Z z Z
= =
+ +
(1-78)
The performance metric, T
z
(Z
s
, Z
l
), is commonly called the z-parameter return ratio of the linear
network undergoing study. Thus,
( )
fo fo
2
fs
s 12 fo z s l
Y Y
I
Y .
V 1 z Y 1 T Z , Z
= = =
+ +
(1-79)
For large loop gain, or return ratio, which requires the satisfaction of the inequality, |z
12
Y
fo
| >> 1,

- 65 -
12 fo
fs
z Y 1
12
1
Y .
z
>>
~ (1-80)
As in the case of the transimpedance amplifier, the loop gain in (1-78) can be computed
directly from the equivalent circuit. In the case of open circuit impedance parameters, the re-
sponse is taken as the output current, I
2
. With the input signal V
s
, set to zero, a test signal cur-
rent, I
test
, is conceptually applied to the feedback subcircuit, with the result that the applicable
equivalent circuit is the structure in Figure (1.35b). An inspection of this circuit confirms
( )( )
2 1 2 12 21
test test 1 11 s 22 l
I I I z z
,
I I I z Z z Z
= =
+ +
(1-81)
which is indeed the loop gain stipulated in (1-78).
We can enlist the assistance of Figure (1.36) to derive expressions for the driving point
input and output impedances, Z
in
and Z
out
, respectively. Each of these two impedances is com-
puted as the ohmmeter voltage -to- current ratio, V
x
/I
x
. In the case of Figure (1.36a), the driv-
ing point input impedance, Z
in
, derives directly from (1-74) upon recognizing that V
x
/I
x
in Figure
(1.36a) is identical to V
s
/I
s
in (1-74), provided that Z
s
is set to zero. In particular,
I
1
I
1
1
1
2
2
V
2
V
2
3
3
4
4
I
2
I
2
z
22
z
22
V
1
V
1
z I
21 1
z I
21 1
z I
12 2
z I
12 2
z
11
z
11
Z
l
Z
s
Z
out
I
x
Z
in
V
x
(a).
I
x
V
x
(b).

Figure (1.36). (a). The z-parameter model for computing the driving point input admittance of the
transimpedance amplifier in Figure (1.34). (b). The z-parameter equivalent circuit pertinent to
computing the driving point output admittance of the subject electronic network.
( )
( )
x 12 21
in 11 11 z l
x 11 22 l
V z z
Z z 1 z 1 T 0, Z ,
I z z Z
(
= = = + (
(

+

(1-82)
where (1-78) is invoked. Just as admittance parameter y
11
represents the open loop input admit-
tance of a transimpedance amplifier, we can view z
11
as the open loop driving point input imped-
ance of a transadmittance amplifier. If the transadmittance configuration is designed to achieve
the large loop gain required to desensitize the closed loop transadmittance with respect to
parameter and/or source and load impedance uncertainties, the resultant driving point input
impedance is potentially very large because the modified loop gain, T
z
(0, Z
l
), is even larger than
the actual loop gain. This large input impedance is a laudable attribute for an input port that is
earmarked to accept an applied voltage signal
In Figure (1.36b),
x 22 x 21 1
V z I z I , = + (1-83)

- 66 -
where
12 x
1
11 s
z I
I .
z Z
=
+
(1-84)
Upon inserting (1-84) into (1-83), the closed loop driving point output impedance is found to be
( )
( )
x 12 21
out 22 22 z s
x 22 11 s
V z z
Z z 1 z 1 T Z , 0 ,
I z z Z
(
= = = + (
(

+

(1-85)
where z
22
symbolizes the open loop driving point output impedance. Like Z
in
, Z
out
can be very
large, which is advantageous from the standpoint of delivering an output current response of a
transadmittance amplifier to an arbitrary external load termination.
1.3.3. ANALYSIS VIA h-PARAMETERS
A voltage amplifier requires high input impedance and low output impedance to estab-
lish a voltage gain that is nominally independent of source and load terminations. In other
words, the high input and low output impedances effectively produce a general purpose voltage
amplifier that is capable of driving a wide range of load impedances while accepting a
correspondingly wide range of signal source impedances. The h-parameters work well for
modeling the linear characteristics of such amplifiers and to this end, we submit Figure (1.37a).
The analysis underpinning the definition of voltage gain and I/O impedances mirrors the ana-
lyses undertaken with respect to short circuit admittance and open circuit impedance parameters.
Moreover, the relevant results emulate the mathematical forms encountered in preceding subsec-
tions. The reader is encouraged to obviate boredom by confirming that the closed loop voltage
gain, say A
vs
, is of the form
( )
vo vo 2
vs
s 12 fo h s l
A A V
A ,
V 1 h A 1 T Z ,Y
= = =
+ +
(1-86)
where A
vo
, the open loop voltage gain, is
( )( )
12
21
vo vs
h 0
11 s 22 l
h
A A ,
h Z h Y
=
= =
+ +
(1-87)
and the loop gain, or h-parameter return ratio, T
h
(Z
s
, Y
l
), is
( )
( )( )
12 21
h s l 12 vo
11 s 22 l
h h
T Z , Y h A .
h Z h Y
= =
+ +
(1-88)
It is worthwhile pointing out that admittance is used herewith to represent the load impedance
terminating the output port because of the Norton topological nature of the output port in the h-
parameter model. Thus, the load admittance, Y
l
, merely sums with the open circuit output admit-
tance, h
22
, as (1-87) and (1-88) imply.
Like y-parameter representations of the electrical properties of feedback networks, the
output voltage, V
2
, drives the feedback subcircuit in an h-parameter model of a network. Accor-
dingly, a test voltage signal, V
test
, is applied to the feedback unit. With the signal drive, V
s
, set
to zero, the resultant model pertinent to a circuit level examination of the h-parameter loop gain
is the structure appearing in Figure (1.37b). A worthwhile exercise for the reader is to confirm
that the loop gain defined by (1-87) is simply the ratio, V
2
/V
test
, in the latter model.
The determination of the driving point input impedance and driving point output admit-
tance mimics the impedance and admittance analyses undertaken in conjunction with the
transimpedance and transadmittance amplifiers. In the present voltage amplifier case, h
11
repre-

- 67 -
sents the open loop input impedance, while h
22
is the open loop output admittance. The asso-
ciated closed loop input impedance, Z
in
, and closed loop output admittance, Y
out
, results are
I
1
1
2
V
2
3
4
I
2
1/h
22
V
1
h I
21 1
h V
12 2
h
11
+
Linear Model
Of Electronic
Network
I
1
V
s
V
s
1
2
V
2
3
4
I
2
Z
l
Z
l
Z
s
Z
s
V
1
Y
out
Z
in
(a).
I
1
1
2
V
2
3
4
I
2
1/h
22
V
1
h I
21 1
h V
12 test
h
11
Z
l
Z
s
(b).

Figure (1.37). (a). The h-parameter equivalent circuit for a linear model of an electronic network designed
to provide voltage gain signal processing. The applied input signal is represented as an
independent voltage source because of the Thvenin nature of the h-parameter input port
model. (b). Equivalent circuit used to compute the h-parameter return ratio, T
h
(Z
s
, Y
l
), as the
voltage ratio, V
2
/V
test
.
( )
in 11 z l
Z h 1 T 0, Y , = + (

(1-89)
and
( )
out 22 z s
Y h 1 T Z , 0 . = + (

(1-90)
We note that in a voltage amplifier, feedback enhances the driving point input impedance while
diminishing the driving point output impedance. The potentially large input impedance allows a
voltage signal to be coupled efficiently to the amplifier input port, while low output impedance
enables the efficient delivery of the voltage response to the load termination.
EXAMPLE #1.8:
Figure (1.38) diagrams a two-stage amplifier utilizing two identical active de-
vices that are biased at the same quiescent operating points. The parameters, r
i

and g
m
, in the circuit are model elements associated with the active devices,
which are biased for nominally linear operation. Feedback in the form of the R
1
-
R
2
divider is connected around the amplifier as shown. In the interest of clarity,
the input and output port currents, I
1b
and I
2b
, respectively, are delineated for the
feedback subcircuit, as are the net input and output port currents, I
1
and I
2
, for

- 68 -
the entire feedback amplifier. Derive expressions for the feedback factor, open
loop voltage gain, closed loop voltage gain, and closed loop driving point input
and output resistances. Numerically evaluate these performance metrics for R
s
=
300 O, r
i
= 2.5 KO, g
m
= 60 mS, R
a
= 10 KO, R
1
= 120 O, R
2
= 1 KO, and R
l
=
5 KO.
SOLUTION #1.8:
(1). The output ports of both the base amplifier and the feedback subcircuit are connected in
parallel with one another. Specifically, these ports sustain the same voltage, V
2
, which we
observe as the net output voltage of the entire interconnection. On the other hand, the input
port voltage, V
1b
, of the feedback unit algebraically adds to the voltage, V
a
, which happens to
be the input port voltage of the base amplifier, to establish the input port voltage, V
1
for the
entire feedback network. Insofar as terminal voltages are concerned, the feedback subcircuit
is interconnected in series-shunt with the base amplifier. This observation suggests using h-
parameters to model the I/O volt-ampere characteristics of the amplifier because the h-
parameter model adopts a series input port and a shunt output port. From Figure (1.38),
2
1b
11b 1 2
1b
V 0
V
h R R ,
I
=
= = (E8-1)
+
r
i
r
i
R
a
R
1
R
2
R
l
R
s
V
s
g V
m a
g V
m b
V
a
V
1b
V
b
V
2
I
1b
I
2b
I
2
I
1
V
1
R
in
R
out
Feedback Subcircuit

Figure (1.38). Schematic diagram of the two stage feedback amplifier studied in Example #1.8.
2
2b 1
21b
1b 1 2
V 0
I R
h ,
I R R
=
= =
+
(E8-2)
1b
1b 1
12b
2b 1 2
I 0
V R
h ,
V R R
=
= =
+
(E8-3)
and
1b
2b
22b
2b 1 2
I 0
I 1
h .
V R R
=
= =
+
(E8-4)
Recalling the characteristic h-parameter equations, the foregoing results imply

- 69 -
( )
1
1b 1 2 1b 2
1 2
1 2
2b 1b
1 2 1 2
R
V R R I V
R R
,
R V
I I
R R R R
| |
= +
|
+
\ .
| | | |
= +
| |
+ +
\ . \ .
(E8-5)
which in turn suggests depicting the circuit in Figure (1.38) as the architecture we offer in
Figure (1.39a). In the latter diagram, the symbol, k
f
, denotes the feedback factor, which is the
voltage divider,
1
f
1 2
R
k .
R R +
(E8-6)
(2). Now, we can determine the hybrid h-parameters of the base amplifier in accordance with Fig-
ure (1.39a). Subsequent to this determination, we can combine the matrix of these parame-
ters with the matrix of the h-parameters for the feedback subcircuit to produce the effective
hybrid h-parameters for the complete network. However, the relative simplicity of the circuit
at hand renders this computational step unnecessary (although certainly valid). Instead, we
set the k
f
V
2
feedback generator in Figure (1.39a) to zero to arrive at the open loop version of
the circuit drawn in Figure (1.39b). In the latter (open loop) diagram, the current, I
1b
, flowing
into the input port of the feedback subcircuit is
( )
a a
1b m a m i
i i
V V
I g V 1 g r .
r r
= + = + (E8-7)
It follows that the feedforward current, k
f
I
1b
, produced by the feedback structure is
( ) ( )
f a
a 1
f 1b m i m i
i i 1 2
k V
V R
k I 1 g r 1 g r .
r r R R
| |
= + = +
|
+
\ .
(E8-8)
It should also be noted that the conduction of current I
1b
by the parallel combination of resis-
tances R
1
and R
2
produces a voltage across this shunt combination that is equivalent to the
voltage established by the flow of the input port current, V
a
/r
i
, through an effective resistance
of value, (1 + g
m
r
i
)(R
1
||R
2
).
Continuing with our analysis, we witness the interstage potential, V
b
, as
( )
b m a i a
V g R r V , = (E8-9)
whence a feedforward base amplifier current of
( )
2
m b m a i a
g V g R r V . = (E8-10)
The design goal of achieving an amplifier feedforward current that is much larger than the
feedforward current evidenced by the feedback subcircuit requires that the magnitude of the
current in (E8-10) be significantly larger than the current defined by (E8-8). Since g
m
r
i
in
this example is 150 and therefore much larger than one, this design objective essentially
translates into the requirement,
i
m i f
a
r
g r 1 k .
R
| |
>> +
|
\ .
(E8-11)
The foregoing observations, and specifically (E8-7), (E8-8), and (E8-10), allow us to recast
the model in Figure (1.39b) into the topological structure shown in Figure (1.39c). Of
course, we understand that this revised topology remains applicable only for open loop opera-
tion of the original amplifier modeled in Figure (1.39a).
(3). Figure (1.39c) makes it clear that the open loop input resistance, R
ino
, is
( ) ( )
ino i m i 1 2
R r 1 g r R R 18.68 K , = + + = (E8-12)
while the open loop output resistance, R
outo
, is seen to be

- 70 -
+
r
i
r
i
R
a
R +R
1 2
R ||R
1 2
R
l
R
s
V
s
g V
m a
g V
m b
k I
f 1b
V
a
V
b
V
2
I
1b
I
2b
I
2
I
1
V
1
R
in
R
out
+
k V
f 2
V
1b
(a).
+
r
i
r
i
R
a
R +R
1 2
R ||R
1 2
R
l
R
s
V
s
g V
m a
g V
m b
k I
f 1b
V
a
V
b
V
2
I
1b
V /r
a i
I
2b
I
2
I
1
V
1
R
ino
R
outo
(b).
+
r
i
R +R
1 2
(1+g r )(R ||R )
m i 1 2
R
l
R
s
V
s
g (R ||r )V
m a i a
2
V
a
V
2
I
2
I
1
V
1
R
ino
R
outo
(c).
k (1+g r )V
f m i a
r
i
Model of
Feedback Subcircuit

Figure (1.39). (a). The circuit model of Figure (1.38) with the feedback subcircuit supplanted by its h-parameter
equivalent circuit. (b). The circuit model of (a) under open loop operating conditions. By
comparison with the network in (a), note that only the controlled feedback subcircuit source, k
f
V
2
,
is set to zero. The resultant open loop input resistance is symbolized as R
ino
, while its counterpart
output resistance is R
outo
. (c). Simplified version of the model in (b).
outo 1 2
R R R 1.12 K . = + = (E8-13)
The figure at hand also confirms an open loop voltage gain, A
vo
, of

- 71 -
( ) ( )
( ) { }
f 2 f 2
a 2 2
vo
s s a
k V 0 k V 0
i
eff 1 2 l
s i m i 1 2
V V V
A
V V V
r
G R R R ,
R r 1 g r R R
= =
= =
(
= + ( (

+ + +
(

(E8-14)
where G
eff
, which represents an effective forward transconductance of the open loop
configuration, is
( )
( )
f m i
2
eff m a i
i
k 1 g r
G g R r 7.21 S .
r
+
= + = (E8-15)
This result and (E8-14) give an open loop voltage gain of A
vo
= 868.63 volts/volt. Moreover,
the loop gain computes as
( )
h s l f vo
T R , G k A 93.07 . = =
(E8-16)
where G
l
represents the conductance corresponding to the stipulated load resistance, R
l
. With
R
s
= 0, T
h
(0, G
l
) = 94.56, while for the case of infinitely large load resistance, T
h
(R
s
, 0) =
113.91. These last two loop gain special cases are, of course, germane to the computation of
the driving point input and output resistances.
(4). Recalling (1-86), the closed loop voltage gain, A
vs
, is
( )
vo 2
vs
s h s l
A V
A 9.23 volts/volt .
V 1 T R , G
= = =
+
(E8-17)
In view of the fact that the loop gain computed in (E8-16) is very large, this gain closely
approximates the inverse of the feedback factor, k
f
. From (E8-6),
2
vs
f 1
1 R
A 1 9.33 volts/volt ,
k R
~ = + = (E8-18)
which exceeds the true voltage gain predicted in (E8-17) by only 1.07%.
(5). From (1-88), the driving point input resistance, R
in
, is
( )
in ino h l
R R 1 T 0, G 1.78 Meg , = + = (

(E8-19)
while (1-89) provides a driving point output resistance, R
out
, of
( )
outo
out
h s
R
R 9.75 .
1 T R , 0
= =
+
(E8-20)
The amplifier tackled in this example is an excellent voltage amplifier for at least three rea-
sons. First, its very large loop gain aggressively desensitizes its I/O gain characteristics with
respect to source resistance, load resistance, and the routinely vagarious active element
parameters. Indeed and as is suggested by (E8-18), its forward gain is fundamentally set by
the resistance ratio, R
2
/R
1
. This resistance ratio conclusion is a circuit attribute, for while
individual resistances synthesized in integrated circuits are subject to tolerances of at least
20%, ratios of geometrically similar resistances can be controlled to tolerances of less than
5%. Second, the driving point input resistance is exceedingly large, thereby allowing a wide
range of source resistances to be utilized without significantly affecting the voltage gain. For
example, the source resistance in the considered amplifier can be increased to as much as 90
KO without incurring a gain degradation of larger than 5%. Finally, the very low driving
point output resistance allows for the incorporation of a wide range of load terminations. To
wit, the load resistance, R
l
, can be decreased to as little as 175 O without altering the voltage
gain by more than 5%.

- 72 -
A valuable lesson learned herewith, albeit subliminally, is that two-port parameters can be a
powerful tool underlying a streamlined, insightful analysis of many feedback circuits. In this
example, the two-port parameters for the feedback circuit are computed and thence exploited
from a circuit perspective to allow for a straightforward analysis without leaning on the two-
port parameters for the entire configuration. In particular, the open loop gain is obtained al-
most by mere inspection, as are the corresponding loop gain and closed loop gain metrics.
1.3.4. ANALYSIS VIA g-PARAMETERS
In contrast to the voltage amplifier addressed in the preceding subsection, a current am-
plifier requires low input impedance and high output impedance in order to deliver a current gain
that is nominally invariant with source and load impedances. The g-parameters, which extol
Norton input port and Thvenin output port topologies, are best suited for the current amplifier,
as we suggest in Figure (1.40a).
As in the case of all previous two-port network analyses, an analytical study premised
on g-parameters is a case of dj vu all over again. Thus, without explicit derivation, the closed
loop current gain, say A
is
, is expressible as
I
1
1
2
V
2
3
4
I
2
1/g
11
V
1
g I
12 2
g V
21 1
g
22
Linear Model
Of Electronic
Network
I
1
I
s
I
s
1
2
V
2
3
4
I
2
Z
l
Z
l
Z
s
Z
s
V
1
Z
out
Y
in
(a).
I
1
1
2
V
2
3
4
I
2
1/g
11
V
1
g I
12 test
g V
21 1
g
22
Z
l
Z
s
(b).

Figure (1.40). (a). The g-parameter equivalent circuit for a linear model of an electronic network designed to
provide current gain signal processing. The applied input signal is represented as an independent
current source because of the Norton nature of the g-parameter input port model. (b). Equivalent
circuit used to evaluate the g-parameter return ratio, T
g
(Y
s
, Z
l
), as the current ratio, I
2
/I
test
.
( )
io io 2
is
s 12 io g s l
A A I
A ,
I 1 g A 1 T Y , Z
= = =
+ +
(1-91)
where the open loop current gain, A
io
, is given by

- 73 -
( )( )
12
21
io is
g 0
11 s 22 l
g
A A ,
g Y g Z
=
= =
+ +
(1-92)
and the loop gain, T
g
(Y
s
, Z
l
), is
( )
( )( )
12 21
g s l 12 io
11 s 22 l
g g
T Y , Z g A .
g Y g Z
= =
+ +
(1-93)
This loop gain computes as the current ratio, I
2
/I
test
, in the model of Figure (1.40b). Finally, the
closed loop input admittance, Y
in
, can be shown to be
( )
in 11 g l
Y g 1 T 0, Z , ( = +

(1-94)
while the closed loop output impedance, Z
out
, is
( )
out 22 g s
Z g 1 T Y , 0 . ( = +

(1-95)
EXAMPLE #1.9:
The linear amplifier studied in Example #1.8 is reconfigured for current gain sig-
nal processing in accord with the equivalent circuit of the feedback amplifier
drawn in Figure (1.41). The device model parameters, r
i
and g
m
, have the values
stipulated in the preceding example; namely, r
i
= 2.5 KO and g
m
= 60 mS. Feed-
back in the form of the R
1
-R
2
divider is connected in shunt with the amplifier in-
put port and in series with the amplifier output port. In the interest of clarity, the
input and output port currents, I
1b
and I
2b
, respectively, are delineated for the
feedback subcircuit, as are the net input and output port currents, I
1
and I
2
, for
the entire feedback amplifier. Derive expressions for the feedback factor, loop
gain, open loop current gain, closed loop current gain, and closed loop driving
point input and output resistances. Numerically evaluate these performance in-
dices for R
s
= 20 K, R
a
= 500 , R
1
= 120 , R
2
= 1 K, and R
l
= 300 .
r
i
r
i
R
a
R
1
R
2
R
l
R
s
g V
m a
g V
m b
V
a
V
2b
V
b
V
2
I
1b
I
2b
I
2
I
1
V
1
R
in
R
out
Feedback Subcircuit
I
s

Figure (1.41). The current amplifier addressed in Example #1.9. The input signal is the current, I
s
, whose
shunt Thvenin resistance is R
s
. The output response is taken as the current, I
2
, conducted by
the terminating load resistance, R
l
.


- 74 -
SOLUTION #1.9:
(1). As noted in the problem statement, the feedback subcircuit highlighted in Figure (1.41) is
connected in shunt with the input port of the amplifier and in series with its output port. This
shunt-series topology encourages modeling the feedback unit with a g-parameter equivalent
circuit. The logic underpinning this assertion is that a hybrid g-parameter model advances a
Norton (shunt) input port and a Thvenin (series) output port architecture. To this end,
2b
1b
11b 1 2
1
I 0
I
g R R ,
V
=
= = + (E9-1)
2b
2b 1
21b
1 1 2
I 0
V R
g ,
V R R
=
= =
+
(E9-2)
1
1b 1
12b
2b 1 2
V 0
I R
g ,
I R R
=
= =
+
(E9-3)
and
1
2b
22b 1 2
2b
V 0
V
g R R .
I
=
= = (E9-4)
From (1-35) and the foregoing disclosures, it follows that
( )
1
1b g 2b
1 2
2b g 1 1 2 2b
V
I k I
R R
,
V k V R R I
=
+
= +
(E9-5)
where
1
g
1 2
R
k 0.107
R R
=
+
(E9-6)
is literally the feedback factor of the entire amplifier. As the feedback factor, k
g
represents
the magnitude of the reverse current gain established by the feedback subcircuit.
(2). Equation (E9-5) forges the alternative circuit model offered in Figure (1.42a). In this
embodiment, observe that the feedback generator, k
g
I
2b
, is, in accordance with g-parameter
modeling, a dependent current generator controlled by the current, I
2b
, which flows into the
output port of the feedback subcircuit. The polarity of this controlled source accounts for the
fact that the feedback transconductance, g
12b
in (E9-3), is a negative number. From the
perspective of loop gain computation, it is desirable to cast this feedback current as a function
that is linearly dependent on the actual output current response, I
2
, which is, of course, an
independent variable in the g-parameter model formulation. To this end, Figure (1.42a) con-
firms
( )
b b m i
2b m b m i 2
i i m i
V V 1 g r
I g V 1 g r I ,
r r g r
| | +
= + = + =
|
\ .
(E9-7)
whence
m i
g 2b g 2 f 2
m i
1 g r
k I k I k I ,
g r
| | +
=
|
\ .
(E9-8)
where
m i m i 1
f g
m i 1 2 m i
1 g r 1 g r R
k k 0.108
g r R R g r
| | | | | | + +
= = =
| | |
+
\ . \ . \ .
(E9-9)
represents the feedback factor of the entire amplifier. Note that in the likely circumstance

- 75 -
that g
m
r
i
>> 1, parameters k
g
and k
f
are almost identical. Nevertheless, parameter k
f
quanti-
fies, as a direct proportion to the output current response, the amount of current fed back to
the input port of the base amplifier. We have incorporated the circuit implications of the
foregoing disclosures into the modified equivalent circuit of Figure (1.42b).
r
i
r
i
R
a
R +R
1 2
R ||R
1 2
R
l
R
s
g V
m a
k I
g 2b
g V
m b
V
a
V
b
V
2
I
1b
I
2b
I
2
I
1
V
1
R
in
R
out
I
s
+
k
V
g
1
(a).
r
i
r
i
R
a
R +R
1 2
R ||R
1 2
R
l
R
s
g V
m a
g V
m b
V
a
V
b
V
2
V
2b
I
1b
I
2b
I
2
I
1
V
1
R
in
R
out
I
s
+
k
V
g
1
(b).
k I
f 2
Model of
Feedback Subcircuit
V
2b
Alternative Model of
Feedback Subcircuit

Figure (1.42). (a). The current amplifier in Figure (1.41) with the feedback subcircuit replaced by its g-parameter
equivalent circuit. (b). An alternative form of the model in (a), wherein the feedback current
source is cast as an explicit function of the output current response, I
2
. The feedback factor, k
f
, is
defined by (E9-9).
(3). The direct way to compute the loop gain of the amplifier at hand is to exploit (1-93).
Unfortunately, this solution tack requires an identification of the g-parameters for the entire
feedback amplifier, which in turn requires an evaluation of the g-parameters for the base am-
plifier. The latter requirement entails analytical tedium owing to the reasonably cumbersome
nature of the base amplifier topology. A computationally more efficient determination of the
loop gain, T
g
(G
s
, R
l
), derives from injecting a test current, I
test
, into the output port of the
feedback subcircuit (which is driven by the amplifier output port) and then computing the
resultant current transfer ratio, I
2
/I
test
, under the condition of zero input signal current, I
s
= 0.
The pertinent circuit model appears in Figure (1.43), which advances

- 76 -
r
i
r
i
R
a
R +R
1 2
R ||R
1 2
R
l
R
s
g V
m a
g V
m b
V
a
V
b
V
2
I
2
V
1
+
k
V
g
1
k I
f test
V
b
V
b
r
i
r
i
g V +
m a
(1 + g r )
m i

Figure (1.43). Circuit model used to evaluate the loop gain of the network in Figure (1.41b). Observe that
the input current signal is set to zero, while the direction of the original feedback current
generator, k
f
I
2
, is reversed and set to k
f
I
test
to reflect the conceptual injection of the test
current, I
test
, into the output port of the feedback subcircuit.
( )
a
f s 1 2 i
test
V
k R R R r .
I
( = +

(E9-10)
Moreover,
( ) ( )
b b
a m a b 1 2 m i g a
i i
V V
R g V V R R 1 g r k V 0 ,
r r
| | | |
+ + + + + =
| |
\ . \ .
(E9-11)
where we exploit the fact that the input port voltage, V
1
, is identical to the indicated control
voltage, V
a
. After enduring a bit of algebraic grief, we find that the last relationship delivers
( )
( ) ( )
b i
m a g
a a m i 1 2
V r
g R k .
V R 1 g r R R
(
= +
(
+ +
(

(E9-12)
Recognizing that the output port current, I
2
, is little more than g
m
V
b
, (E9-12) and (E9-10)
combine to produce a network loop gain of
( )
( ) ( )
( )
m i
g s l f m a g s 1 2 i
a m i 1 2
g r
T ( G , R ) k g R k R R R r
R 1 g r R R
21.75 amps/amp .
(
(
= + + (

+ +
(

=
(E9-13)
(4). The open loop current gain, A
io
= I
2
/I
s
, can be evaluated by analyzing the circuit in Figure
(1.42b) under the condition of zero feedback; that is, k
f
I
2
= 0. But we can obviate this
analytical procedure in favor of observing that the resultant open loop circuit is topologically
identical to the structure in Figure (1.43), which precipitates the loop gain expression as (E9-
13). In effect, the latter circuit collapses to the former if the current source, k
f
I
test
, in the latter
diagram is supplanted by I
s
. Consequently,
s
2 test g s l g s l
f
I
I I T ( G , R ) T ( G , R ) ,
k
| |
= = |
|
\ .
(E9-14)
whence an open loop current gain (without further circuit analysis) of
f 2
g s l
2
io
s f
k I 0
T ( G , R )
I
A 201.64 amps/amp .
I k
=
= = =
(E9-15)
The corresponding closed loop current gain, A
is
, is

- 77 -
io 2
is
s g s l
A I
A 8.86 amps/amp .
I 1 T ( G , R )
= = =
+
(E9-15)
(5). Under open loop circumstances, we see that the input resistance, say R
ino
, at the amplifier in-
put port is
( )
ino 1 2 i
R R R r 773.48 . = + = (E9-16)
With the source conductance, G
s
, set to zero, which is equivalent to remanding the source
resistance, R
s
, to an infinitely large value, (E9-13) yields
( )
( ) ( )
( )
f m i
g l m a g 1 2 i
a m i 1 2
k g r
T ( 0, R ) g R k R R r
R 1 g r R R
22.59 amps/amp .
(
= + + ( (

+ +
(

=
(E9-17)
Accordingly, the closed loop driving point input resistance, R
in
, follows from (1-94) as
ino
in
g l
R
R 32.79 .
1 T ( 0, R )
= =
+
(E9-18)
(6). The open loop output resistance, R
outo
, is calculated by setting k
f
I
2
= 0 and the independent
signal source, I
s
, to zero. The immediate ramification of this due diligence is V
a
= 0 and V
b
=
0, whence g
m
V
b
at the amplifier output port is zero. But g
m
V
b
= 0 is tantamount to an open
circuited output port, whence an infinitely large open loop, and therefore closed loop,
driving point output resistance.
Because of the reasonably large loop gain computed in (E9-13), the amplifier studied in this
example delivers a current gain that is essentially invariant with model parameter uncertain-
ties and source impedance fluctuations. In particular, the closed loop current gain is very
nearly, 1/k
f
= 9.27, whose magnitude differs from that of the actual current gain by only
4.60%. This approximation entails neglecting unity in the [1 + T
g
(G
s
, R
l
)] denominator of the
closed loop gain expression in (E9-15). Such neglect is tantamount to a percentage error of
100%/T
g
(G
s
, R
l
), which is shockingly 4.60%.
Although two-port network theory is the theoretic basis of all computations required of this
problem, it is interesting that two-port parameter methods requiring the evaluation of the g-
parameters for the overall network, are forsaken. Instead, the circuit analyses we have
undertaken take advantage of the insights and pragmatic implications spawned by classic
two-port theory to advance a computationally efficient and illuminating evaluation of am-
plifier performance. For example, it is interesting that the loop gain and open loop gain de-
rive from effectively one set of circuit equations. In the process, an initial assessment of the
relative quality of the amplifier is almost immediate in that the magnitude of the open loop
gain becomes transparent from the circuit manipulations undertaken to arrive at the loop gain
of the network.
1.4.0. REFERENCES
[1]. J. Choma and W-K Chen, Feedback Networks: Theory and Circuit Applications. Singapore:
World Scientific Press, Inc., 2007, chap. 3.


- 78 -
EXERCI SES
PROBLEM #1.1
Derive general expressions for the short circuit admittance parameters of the passive network de-
picted in Figure (P1.1). As usual, the input port voltage and current variables are delineated as V
1

and I
1
respectively, while V
2
and I
2
denote the corresponding variables at the output port. Evaluate
these parameters for the special case of R
1
R
2
= R
3
R
4
, and comment on the engineering significance
of this resistive constraint.
R
1
R
3
R
4
R
2
+
V
1
+ V
2

Figure (P1.1)
PROBLEM #1.2
The circuit in Figure (P1.2) is a simplified, linearized model of a voltage buffer realized in
MOSFET technology. If terminal (1) and ground comprise the input port of the buffer and terminal
(2) and ground form the output port, derive expressions for the short circuit admittance parameters
and the alternative -model parameters for the subject circuit.
C
1
C
2
+

V g V
m
r
o
R
V
2
V
1
I
2
I
1
(1)
(2)
Z (j )
in

Figure (P1.2)
(a). Do you expect capacitance C
1
to be a significant bandwidth deterrent? Explain why or why
not in simple engineering terms.
(b). Is there an operating constraint for which the real part of the steady state driving point input
impedance, Z
in
(j), is negative? What is a potentially serious dilemma of negative real part
impedance?
PROBLEM #1.3
The circuit in Figure (P1.3) is a simplified, linearized model of a voltage amplifier realized in bipo-
lar technology. If terminal (1) and ground comprise the input port of the amplifier and terminal (2)
and ground form its output port, derive expressions for the short circuit admittance parameters and
the alternative t-model parameters for the subject circuit.

- 79 -
C
1
C
2
I
r
o
R
V
2
V
1
I
2
I
1
I
(1) (2)
r
t

Figure (P1.3)
PROBLEM #1.4
The twin tee structure shown in Figure (P1.4) is commonly used as a notch filter; that is, it ideally
affords zero transmission between its input and output ports at a single frequency, say
n
, which is
known as the notch frequency, in units of radians -per- second. Without evaluating the actual vol-
tage transfer function, V
o
/V
i
, from the network input port to the network output port, use y-parame-
ter concepts to determine an expression for the notch frequency,
n
, in terms of resistance R and
capacitance C.
2R
C
2R
C
2C R
V
i
V
o

Figure (P1.4)
PROBLEM #1.5
The circuit given in Figure (P1.5) is capable of realizing a negative resistance between terminals (1)
and (2). Derive an expression for this negative resistance, assuming ideal transconductors.
+
G
m
+
G
m
(1) (2)

Figure (P1.5)
PROBLEM #1.6
The terminal volt-ampere characteristics of the linear network depicted in Figure (P1.6a) subscribe
to the matric,
1 1
2 2
3 3
I 1 1 2 V
I 1 1 2 V ,
I 3 0 3 V
( ( (
( ( (
=
( ( (
( ( (


- 80 -
Linear
Network
I
1
V
1
1
4
V
2
2
3
I
2
(a).
V
3
I
3
Linear
Network
I
1
V
1
1
4
2
3
I
2
(b).
V
3
I
3
V
4
I
4
2 O

Figure (P1.6)
where all elements in the 3x3 coefficient matrix are in units of siemens, and terminal voltages V
1
, V
2
,
and V
3
are measured with respect to network terminal #4. Find the short circuit admittance matrix,
Y, of the modified architecture offered in Figure (P1.6b), such that
1 1
3 3
4 4
I V
I V ,
I V
( (
( (
=
( (
( (

Y
with the understanding that terminal voltages V
1
, V
3
, and V
4
are measured with respect to network
terminal #2, which is presently grounded.
PROBLEM #1.7
A three terminal, two-port, bilateral circuit is terminated at its output port in a resistance, R
L
. The
circuit is known to have short circuit admittance parameters, y
ij
and is symmetrical in the sense that
y
11
= y
22
. Show that if the driving point input resistance of the circuit is to identical to R
L
, resistance
R
L
must be given by
L
2 2
11 12
1
R .
y y
=

We should interject that when the driving point input impedance of a linear network is identical to
its terminating load impedance, that load impedance is called the characteristic impedance of the
network.
PROBLEM #1.8
Figure (P1.8) depicts the linear model of a MOSFET amplifier formed of three nominally identical
transistors biased at roughly identical quiescent operating points. The input port is associated with
voltage V
1
and current I
1
, while the output port is associated with voltage V
2
and current I
2
. Deter-
mine the short circuit admittance parameters of this amplifier, and draw the corresponding y-
parameter equivalent circuit for the case of g
m
r
o
>> 1.
I
1
V
1
I
2
V
2
g V
m b
r
o
g V
m a
r
o
g V
m c
r
o
+
V
b
+
V
c
+ V
a

Figure (P1.8)
PROBLEM #1.9
Derive expressions for the open circuit impedance parameters of the network given in Problem #1.1.

- 81 -
PROBLEM #1.10
PROBLEM #1.11
PROBLEM #1.12
Derive relationships for the hybrid h-parameters in terms of the open circuit impedance, or z-
parameters.
PROBLEM #1.13
Derive expressions for the hybrid h-parameters of the network given in Problem #1.1.
PROBLEM #1.14
Derive expressions for the hybrid h-parameters of the network given in Problem #1.3.
PROBLEM #1.15
Derive expressions for the hybrid h-parameters of the linear equivalent circuit in Figure (P1.15).
Discuss the engineering ramifications of a very large resistance, r
o
.
g V
m
r
o
R
1
R
2
V
2
V
1
I
2
I
1
V

Figure (P1.15)
PROBLEM #1.16
Derive expressions for the hybrid g-parameters in terms of the short circuit admittance parameters of
a linear two-port network.
PROBLEM #1.17
Figure (P1.17) is a low frequency, small signal equivalent circuit of a bipolar junction transistor
amplifier. The amplifier utilizes an emitter degeneration resistance, R
e
, to achieve a forward gain
that is nominally independent of the transistor current gain parameter, |. Let the amplifier input
resistance, r
i
, be 2.7 K, the transistor output resistance, r
o
, be 40 K, = 300, and R
e
= 120 .
Derive general expressions for, and numerically evaluate, the four g-parameters, g
ij
, of the emitter
degenerated configuration.
I
1
I
2
I
1
R
e
r
o
r
i
V
1
V
2

Figure (P1.17)

- 82 -
PROBLEM #1.18
Figure (P1.18) is an approximate small signal model of a metal-oxide-semiconductor field-effect
transistor (MOSFET) configured to operate as a common source amplifier. Terminal 1 represents
the gate of the transistor, terminal 2 is the transistor drain terminal, and terminal 3 is the source
terminal of the device. In this model, C
gs
represents the gate -to- source capacitance of the
transistor, C
gd
is the gate -to- drain capacitance, C
bd
is the bulk substrate -to- drain capacitance, r
o

designates the drain-source channel resistance, and g
m
is the forward transconductance of the device.
g V
m 1
r
o
C
bd
C
gs
C
gd
V
1
V
2
I
1
I
2
1

(
G
a
t
e
)
2

(
D
r
a
i
n
)
3 (Source)

Figure (P1.18)
(a). Find general expressions for each of the four common source y-parameters, y
ij
. Use these y-
parameters to give general expressions for the h-parameters of the equivalent circuit.
(b). Use the appropriate hybrid h-parameter to give a general expression for the short circuit
(meaning the drain terminal is short circuited to the source terminal) current gain, I
2
/I
1
.
(c). Use the preceding result to evaluate the frequency (in units of hertz) at which the magnitude of
the short circuit current gain degrades to unity. If g
m
= 10 mS, r
o
= 10 K, C
gs
= 20 fF, C
gd
=
4 fF, and C
bd
= 15 fF, numerically evaluate this unity gain frequency, which is commonly
symbolized as f
T
.
PROBLEM #1.19
The circuit in Figure (1.33) is modified through the incorporation of resistive degeneration, R, as
depicted in Figure (P1.19). Resistance R is 20 , and all other circuit parameters remain as
stipulated in Example #1.7; namely, R
s
= 300 , r
i
= 4 K, R
f
= 2.7 K, r
o
= 40 K, R
l
= 5 K,
and | = 150 amps/amp.
+
V
s
R
s
r
i
R
f
I
I
1
V
1
I
r
o
R
l
R
V
2
I
2
R
in
R
out

Figure (P1.19)
(a). Derive expressions for and numerically compute the open loop voltage gain, A
vo
, the loop gain,
T
y
(G
s
, G
l
), and the closed loop voltage gain, A
v
.
(b). Derive expressions for and numerically compute the open loop and closed loop driving point
input impedances, R
ino
and R
in
, respectively, as well as the open loop and closed loop driving
point output resistances, R
outo
and R
out
, respectively.

- 83 -
(c). Compare the results of parts (a) and (b) with those generated in Example #1.6. Comment on
any differences observed, particularly with regard to the suitability of the present amplifier as
either a voltage amplifier or a transimpedance processor.
(d). Are there conditions by which the closed loop, driving point input and output resistances are
identical to one another? If so, stipulate these conditions.
PROBLEM #1.20
The circuit in Figure (1.33) is modified through the incorporation of a capacitance, C
f
, in shunt with
the feedback resistance, R
f
, as depicted in Figure (P1.20). While R
f
retains its original 2.7 K value,
the other circuit and model parameters have been suitably modified to ensure that the loading by
resistance R
f
on both the input and output ports of the base amplifier are negligible, as is the effect of
R
f
on the forward transconductance of the base amplifier.
+
V
s
R
s
r
i
R
f
I
I
1
V
1
I
r
o
R
l
V
2
I
2
C
f

Figure (P1.20)
(a). Use the feedback theory and methods exploited in Example #1.7 to deduce a general
expression, in terms of the open loop transimpedance, for the time constant, say t
f
, associated
with C
f
. Be aware that the numerical value of the open loop transimpedance in this exercise
differs from that computed in Example #1.7 because of the aforementioned parametric
modifications.
(b). Assuming a revised value, Z
fo
, of the open loop transimpedance of 20 K, what value of
capacitance C
f
delivers a voltage gain 3-dB bandwidth of at least 500 MHz?
PROBLEM #1.21
The passive two-port network in Figure (P1.21) is to be modeled by open circuit impedance parame-
ters, z
ij
. Observe that the input and output ports are electrically connected together so that the entire
two-port network functions as an impedance established between the indicated terminals, 1 and 2.
In terms of the z-parameters of the network, derive a general expression for this two-terminal imped-
ance.
Passive
Linear
Network
I
1
V
2
I
2
V
1
1
2
Figure (P1.21)

- 84 -
PROBLEM #1.22
Confirm the expressions given in Section (1.3.4) for the closed loop current gain, the open loop cur-
rent gain, the loop gain, the driving point input admittance, and the driving point output impedance
of a current amplifier.
PROBLEM #1.23
Show that the loop gain, T
h
(Z
s
, Y
l
), computed in terms of the hybrid h-parameters for a linear two-
port network, is related to the loop gain, T
y
(Y
s
, Y
l
), computed as a function of the short circuit admit-
tance parameters, by the relationship,
( )
( )
s y s l
h s l
in
Y T Y , Y
T Y , Z ,
Y
=
where Y
s
is the admittance of the signal source applied to the network, Z
l
= 1/Y
l
is the load imped-
ance terminating the output port of the network, and Y
in
is the driving point input admittance of the
linear network.
PROBLEM #1.24
The loop gain, computed in terms of the open circuit impedance parameters of a linear two-port net-
work, is T
z
(Z
s
, Z
l
), while the loop gain, computed as a function of the short circuit admittance
parameters, is T
y
(Y
s
, Y
l
). Let the impedance, Z
s
, of the signal source that drives the network be iden-
tical to the inverse of the network driving point input admittance. Moreover, let the load impedance,
Z
l
, which terminates the network output port be equal to the inverse of the network driving point
output admittance. For these two conditions, show that the two loop gains are identical.
PROBLEM #1.25
In the amplifier studied in Example #1.9, a capacitance, C
a
, is appended in shunt with resistance R
a

as depicted in Figure (P1.25). Assume that the parameters in this circuit satisfy the inequalities,

1
m a
1 2
a
m i
1 2
R
g R
R R
.
R
1 g r
R R
>>
+
+ >>

r
i
r
i
R
a
R
1
R
2
R
l
R
s
g V
m a
g V
m b
V
a
V
b
V
2
I
2
I
1
V
1
I
s
C
a

Figure (P1.25)
(a). Derive an expression for the closed loop time constant, say t
a
, associated with capacitance C
a

and use this time constant relationship to deduce the closed loop 3-dB bandwidth. Express this
bandwidth in terms of the low frequency loop gain, T
g
(G
s
, R
l
).
(b). Give engineering design arguments that support an increase in the closed loop bandwidth.
(c). What major disadvantage accrues if attempts are made to set the closed loop 3-dB bandwidth
by connecting capacitance C
a
directly across the input port of the amplifier, as opposed to the

- 85 -
indicated shunt incidence with resistance R
a
?
(d). As is verified in Example #1.9, the driving point closed loop output resistance of the feedback
amplifier is infinitely large. This attribute allows the amplifier to deliver a prescribed closed
loop current gain for broad ranges of load resistance. In light of this observation, is there an
engineering disadvantage to setting the bandwidth by placing capacitance C
a
in shunt with the
load termination, R
l
?
PROBLEM #1.26
A three-stage transadmittance amplifier has the linear equivalent circuit given in Figure (P1.26).
The response to the applied voltage signal, V
s
, is the indicated current, I
2
.
+
g V
m a
R
a
V
a
+
g V
m b
R
b
V
b
+
g V
m c
R
c
R
1
R
s
R
1
R
R
2
V
c
+
I
2
V
s
R
in
R
out

Figure (P1.26)
(a). Identify the feedback network and indicate the type of feedback (series-series, series-shunt,
etc.) applied to the three-stage base amplifier.
(b). In light of the topological feedback form deduced in Part (a), determine the appropriate set of
two-port parameters for the feedback subcircuit.
(c). Use the results of Part (b) to provide an alternate linear equivalent circuit that explicitly identi-
fies the feedback factor, as well as the amount of feedforward.
(d). Exploit the results of Part (c) to determine expressions for the loop gain, open loop transadmit-
tance, closed loop transadmittance, and closed loop driving point input and output resistances,
R
in
, and R
out
, respectively.
(e). What conditions must be satisfied if a high loop gain is to be achieved?
(f). If the loop gain is indeed very large, what is the approximate closed loop transadmittance?
PROBLEM #1.27
The feedback subcircuit in the three-stage transadmittance amplifier studied in Problem #1.26 is
modified in accordance with the schematic diagram in Figure (P1.27). In terms of resistances R
1
and
R
2
in the preceding problem, what relationships must be satisfied by resistances R
x
and R
y
if the two
networks are to deliver identical closed loop performance?

- 86 -
+
g V
m a
R
a
V
a
+
g V
m b
R
b
V
b
+
g V
m c
R
c
R
x
R
s
R
x
R
R
y
V
c
+
I
2
V
s
R
in
R
out

Figure (P1.27)
PROBLEM #1.28
The two-port network in Figure (P1.28) is fundamentally a voltage amplifier that utilizes a feedback
capacitance, C
f
, to establish a low frequency network pole.
+
r
o
r
a
A V
o
R
l
V
2
r
b
+
V
V
1
C
f

Figure (P1.28)
(a). Determine the short circuit admittance parameters and corresponding y-parameter equivalent
circuit of the feedback subcircuit. Use this y-parameter model to construct an alternative am-
plifier equivalent circuit that clearly identifies the feedback and feedforward factors associated
with the closed loop voltage gain, V
2
/V
1
.
(b). Use the alternative model developed in Part (a) to derive an expression for the loop gain of the
overall network.
(c). Give an expression for the open loop voltage gain, V
2
/V
1
.
(d). Give an expression for the closed loop voltage gain, V
2
/V
1
.
(e). Derive expressions for the frequencies of the closed loop pole and closed loop zero established
by the feedback capacitance, C
f
.
PROBLEM #1.29
Figure (P1.29) depicts the schematic diagram of a model for a current amplifier commonly used in
MOS technology architectures. Find the hybrid g-parameters of the model and draw the correspond-
ing g-parameter equivalent circuit.

- 87 -
g V
m b
g V
m a
+
V
b
+
V
c
r
o
r
o
g V
m c
r
o
+ V
a
V
1
V
2
I
1
I
2

Figure (P1.29)
PROBLEM #1.30
For the two RC networks appearing in Figure (P1.30), use the appropriate two-port parameters to
evaluate the frequencies associated with the pole and zero of the forward transadmittance function.
V
2
I
2
R
C
V
1
I
1
V
2
I
2
R R
C
V
1
I
1
(a). (b).

Figure (P1.30)

Chapter 1 - Analog Integrated Circuit Design by John Choma

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