6.

3 LINEAR AND DIGITAL IC APPLICATIONS

6.3.1 COURSE OBJECTIVE:
This subject develops the student ability to design practical circuits using op-amps. It
enables the student to have firm grip of basic principles of many of the common operational
amplifier and linear IC configurations so that the student is able to adapt to configurations
and changing technology as new devices appear on the market. This subject also enhances
the knowledge on digital circuits using ICs.
Its focus is on fundamentals of operational amplifier, linear and non-linear applications such
as comparators and waveform generators, different types of active filters & oscillators using
op-amp. unctional !lock "iagrams and #pplications of $$$ timer IC, %&& 'phase-locked-
loop( and IC version of $)$. It gives e*posure on different types of analog to digital and
digital to analog converters and their parameters. It also focuses on various logic families
like TT&, C+,- etc. different circuit configurations using these logic families, digital
circuits like code converters, decoders, multiple*ers and demultiple*ers design using TT&-
./00 & C+,- /100 series, operation and applications of flip flops, registers and counters
JNTU SYLLABUS:
PART 1 : LINEAR INTEGRATED CIRCUITS
UNIT-I: INTEGRATED CIRCUITS
Classification chip si2e and circuit comple*ity, basic information of op-amp, ideal and
practical op-amp, internal circuits, op-amp characteristics, "C and #C characteristics, ./3
op-amp and its features, modes of operation-inverting, non-inverting, differential
UNIT II: OP-AMP APPLICATIONS
!asic application of op-amp, instrumentation amplifier, ac amplifier, 4 to I and I to 4
converters5 sample and hold circuits, multipliers and dividers, "ifferentiators and
integrators, Comparators, -chmitt trigger, +ulti-vibrators, introduction to voltage
regulators, features of .67
UNIT III: ACTIVE FILTERS & OSCILLATORS
Introduction, 3st order &%, 8% filters. !and pass, !and reject and all pass filters.
,scillator types and principle of operation 9 :C, ;ien and <uadrature type, waveform
generators 9 triangular, sawtooth, s<uare wave
UNIT IV: TIMERS & PHASE LOCKED LOOPS
Introduction to $$$ timer, functional diagram, monostable and astable operations and
applications, -chmitt Trigger. %&& 9 introduction, block schematic, principles and
description of individual blocks of $)$ and 4C,..
PART : DATA CONVERTER INTEGRATED CIRCUITS
UNIT V: D-A AND A-D CONVERTERS
Introduction, basic "#C techni<ues, weighted resistor "#C, :-6: ladder "#C, inverted :-
6: "#C, and IC 3/1= "#C, different types of #"Cs 9 parallel comparator type #"C,
counter type #"C, successive appro*imation #"C and dual slope #"C, "#C and #"C
specifications.
PART 3 : DIGITAL INTEGRATED CIRCUITS
UNIT VI: LOGIC FAMILIES
Classification of integrated circuits, comparison of various logic families, standard TT&
>#>" ?ate-#nalysis and characteristics, TT& open collector ,@%s, Tristate TT&, +,- &
C+,- open drain and tristate outputs, C+,- transmission gate, IC interfacing TT& driving
C+,- & C+,- driving TT&.
UNIT VII: COMBINATIONAL CIRCUITS
"esign using TT&-./00 & C+,- /100 series code converters, decoders, "emultiple*ers,
decoders and drives for &A" & &C" display. Ancoder, priority Ancoder, multiple*ers and
their applications, priority generators@checker circuits. "igital arithmetic circuits-parallel
binary adder@subtractor circuit using 6Bs Complement system, "igital comparator circuits.
UNIT VIII: SE!UENTIAL CIRCUITS
lip-flops and their conversions. "esign of synchronous counters. "ecade counter, shift
registers and applications, familiarities with commonly available ./00 & C+,- /100
series of IC counters.
6.3.3 SUGGESTED BOOKS :
TE"T BOOKS :
T1 : ".:oy Chowdary, CLinear Integrated Circuits , >ew #ge International' p( &td, 6nd
Ad.,
6117.
T : :amakanth ?ayakward, COP-amps and linear integrated circuitsD, %8I, 3E=..
T3 : loyd and Fain, CDigital Fundamentals, %earson Aducation, =th Adition, 611$.
T# : :.%. Fain, CModern Digital Electronics by 7rd Adition.
T$ : Fames +.iore, COp-Amps and Linear Integrated Circuits 9 Concepts and
#pplications
Cengage@Faico, 6@e, 611E.
REFERENCE BOOKS :
R1 : Couglin & redrick ."riscoll, COperational Amplifiers & Linear Integrated
CircuitsD-
:. %8I, 3E...
R : "enton F. "aibey, COperational Amplifiers & Linear Integrated CircuitsD, T+8.
R3 : -ergio ranco, CDesign wit operational amplifiers and Analog Integrated CircuitsD,
+c?raw 8ill, 7rd Ad., 6116.
R# : G. &al Gishore - COperational Amplifiers & Linear Integrated CircuitsD, %earson,
611=.
R$: ;illiam ".-tanley - COperational Amplifiers & Linear Integrated CircuitsD, %earson
Aducation India, 611E
SESSION PLANNER
T%&'() '* +,(- .*'/ ,) &+0 JNTU
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T+6/ B%%7)8 R+5+0+*(+
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P0%90,: O./(%:+)
,//,'*+48C%.0)+
D+2';+01 M+/-%4)
U)+4.
UNIT I
Introduction 3 ,verview of Integrated circuits,&inear and
digital
T3H3H3
%,sHa,b,c,i
C"+sH &C" %rojector,
!lackboard, ,.8.%
-lides
Classification chip si2e and circuit
comple*ity
6 Introduction to IC,types of IC, "evelopment
of IC,IC package types pin identification and
temperature ranges
T3H3.6,3.73.$
:6H6.E,6.31
%,sHa,b,h
C"+sH &C" %rojector,
,.8.% -lides
Introduction to ,perational amplifier,
#nalysis of typical op-amp e<uivalent
circuits, schematic symbol, e<uivalent
circuit of opamp
T3H6.3,6.6
:6H7./
%,sHa,b,c,h
C"+sH &C" %rojector,
!lackboard, ,.8.%
-lides
Ideal and %ractical ,p-#mp 7 Concepts of Ideal op- amp ,op- amp block
diagram, "etails of different blocks
T3H6.7,6./
:6H6.7,7.7
%,sH a,b,c,h
C"+sH
!lackboard, ,.8.%
-lides
/ Internal circuit-Transistor based differential
amplifier concepts, transfer
characteristics,low fre<uency small signal
analysis of differential amplifier,"efinition of
C+::,circuits for improving C+::, input
resistance,active load, level translator, output
stage
T3H6./.3-6./.=
:6H3.3-3.3/
%,sHa,b,e,
C"+sH !lackboard,
,.8.% -lides
$ Tutorial
,p-amp characteristics-"C and #C
Characteristics
) >ecessity of "C,#C characteristics,"C
characteristicsH Input bias current,input offset
current,Input offset voltage,Thermal "rift
T3H7.6
:6H$.3-$.33
%,sHa,b,
C"+sH &C" %rojector,
!lackboard, ,.8.%
-lides
. #C characteristicsHre<uency
response,-tability of an op amp, re<uency
compensation,-lew rate
T3H7.7
:6H).3-)..
%,sHb,c
C"+sH &C" %rojector,
!lackboard, ,.8.%
-lides
./3 ,p-#mp and its eatures = "etail description of ./3 op-
amp,characteristics of ./3 op-amp
T3H6.$.3,7,/
:6H7.6
%,sHb,c,e
C"+sH &C" %rojector,
!lackboard, ,.8.%
-lides
+odes of operation-inverting, non-
inverting, differential.
E Configurations, open loop
configurations5eedback -4oltage series and
voltage shunt-inverting,non
inverting5"ifferential amplifier
T3H6.7
:6H/.6-/.$
%,sHb,c
C"+sH !lackboard,
,.8.% -lides
31 Tutorial
UNIT-II
!asic #pplications of ,p-#mp,
Instrumentation #mplifier,
33 ,verview of applications of op amp in real
time environment,Introduction to arithmetic
operations performed by opamp-
-umming,-caling and averaging amplifier,
instrumentation amplifier
T3H/.6,/.7
:6H..$,..)
%,sHb,c,e
C"+sH &C" %rojector,
#C #mplifier, 4 to I and I to 4
Converters, ,
36 #mplifiersH#C and "C amplifiers
ConvertersH4oltage to current converter with
floating load,with grounded load,Current to
voltage converter
T3H/./,,/.$
:6H..6,,..=-..31
%,sHb,e
C"+sH &C" %rojector,
!lackboard, ,.8.%
-lides
-ample & 8old
Circuits.
,verview of sampling theorem,-ample and
hold circuit
T3H/..
:6HE.3$
%,sHb,c,e
C"+sH !lackboard,
,.8.% -lides
"ifferentiators and Integrators. 37-3/ ,verview of differentiator and integrator
using transistor,disadvantages and replace
transistor with ,pamp,%ractical
T3H/.31,/.33
:6H..36,..37
%,sHb,c,e
"ifferentiators and Integrators C"+sH
!lackboard, ,.8.%
-lides
3$ Tutorial
Comparators. -chmitt Trigger. 3) Introduction to comparators and its
applications-2ero crossing
detector,:egenerative comparator
T3H$.3,$.6,$.7
:6HE.6-E.E
%,sHb,c,e
C"+sH &C" %rojector,
!lackboard, ,.8.%
-lides
+ultivibrators 3. ,verview of multivibrators using
transistor,disadvantages and replace transistor
with ,pamp, #stable and monostable
multivibrators
T3H$./,$.$
%,sHb,c,d
C"+sH !lackboard,
,.8.% -lides
Introduction to 4oltage
:egulators eatures of .67 :egulators.
3= >eed for regulators,IC forms and .67 IC
features
T3H).7,)./
:6H31..'introduction(
%,sHb,c,d,j,k
C"+sH
!lackboard, ,.8.%
-lides
UNIT-III
Introduction. irst. ,rder and -econd
,rder &ow %ass
3E ilters introduction and classification-
"erivation of cut off fre<uency of low pass
3st and 6nd order
T3H..3,..6'introduction
(,..6.3,..6.6
:6H=.3-=./
%,Hb,c,e,i,j,k
C"+sH !lackboard,
,.8.% -lides
irst. ,rder and -econd ,rder 8igh %ass
..
61 "erivation of cut off fre<uency of high pass
3st and 6nd order
T3H..6./
:6H=.$,=.)
%,sHb,c,e,i,j,k
C"+sH &C" %rojector,
!lackboard, ,.8.%
-lides
63 Tutorial
irst. ,rder and -econd ,rder !and %ass
ilters.
66 >arrow band pass and wide band pass filters T3H..6.$
:6H=.=
%,sHb,c,e,j,k,i
C"+sH !lackboard,
,.8.% -lides
#ctive !and :eject and #ll 67 >arrow and wide band reject filters and need
for all pass filter and its circuit
T3H..6.)
:6H=.E,=.31
%ass ilters. %,sHb,c,e,j,k,i
C"+sH !lackboard,
,.8.% -lides
%rinciple of ,peration and Types of
,scillators - :C, ;ien !ridge and
<uadrature type
6/ ,scillator principle,oscillator types and
fre<uency stability
reuency e*pression derivation for all types
of oscillators
:6H=.33-=.3/
%,sHb,c,e,i,j,k
C"+sH
&C" %rojector,
!lackboard, ,.8.%
-lides
;aveform ?enerators -
Triangular. -aw Tooth, -<uare ;ave
6$ ?eneration of waveforms using opamp-
Triangular,sawtooth and s<uare and
derivation of time period for all the waves
:6H=.3$-=.3.
%,sH b,c,e,i,j,k
C"+sH !lackboard,
,.8.% -lides
6) tutorial
UNIT-IV
Introduction to $.$$ Timer, unctional
"iagram
6. Ise of $$$ timer,A*planation of functional
diagram
T3H=.3,=.6
:6H31./'introduction(
%,sHb,c,e,k
C"+sH !lackboard,
,.8.% -lides
+onostable and #stable ,perations and
#pplications, -chmitt Trigger
6= ,verview of multivibrators of
./3,+onostable multivibrators operation and
its application
T3H=.7
:6H31./.3,31./.6
%,sHa,b,c,e,k
C"+sH !lackboard,
,.8.% -lides
6E #stable multivibrators operation and its
application
T3H=./
:6H31./.7,31././
%,sHb,c,e,k
C"+sH !lackboard,
,.8.% -lides
71 -chmitt trigger operation T3H=.$
%,sHb,c,e,k
C"+sH!lackboard,
,.8.% -lides
73 Tutorial
%&&- Introduction, !lock -chematic,
%rinciples and "escription of individual
!locks of $)$
76 "efinition of %&&,!lock diagram and
description of pin diagram
T3HE.3
:6H31.$.3
%,sHj,h
C"+s!lackboard,
,.8.% -lides
77 %rinciple and applications of %&& IC $)$ T3HE.6-E..
:6H31.$.6
%,sHj,h
C"+s!lackboard,
,.8.% -lides
4C, 7/ "efinition of 4C,,!lock diagram of
4C,,working principle
T3HE./
:6H=.3=
%,sHb,c,e,k
C"+sH &C" %rojector,
!lackboard, ,.8.%
-lides
7$ Tutorial
UNIT V: D-A AND A- D CONVERTERS
Introduction, !asic "#C Techni<ues -
;eighted :esistor Type. :-6: &adder
Type, inverted :-6: Type.
7) >eed for "@# and #@" converters,Types f
"@# coverters -;eighted :esistor Type.
T3H31.3,31.6.3
:6HE.33.3'a(
:3H31.6.3
%,sHc,d
C"+sH !lackboard,
,.8.% -lides
7. :-6: &adder Type, inverted :-6: Type.
#dvantages and disadvantages
T3H31.6.6,31.6.7
:6HE.33.3'b(
:3H31.6.6
%,sHc,d
C"+sH !lackboard,
,.8.% -lides
"@# IC3/1= introduction T3H31.6.$
:6HE.33.3'c(
%,sHc,d
C"+s!lackboard,
,.8.% -lides
7= Tutorial
"ifferent
types of #"Cs - %arallel Comparator
Type. Counter Type. -uccessive
#ppro*imation :egister Type and "ual
-lope
7E ,peration of parallel comparator type #"C T3H31.7.3
:3H31./.3
%,sHc,d
C"+sH &C" %rojector,
!lackboard, ,.8.%
-lides
Type
,peration of counter type #"C T3H31.7.6
:3H31./.7
%,sHc,d
C"+sH &C" %rojector,
!lackboard, ,.8.%
-lides
/1 ,peration of servo type and successive
appro*imation #"C
T3H31.7.7,31.7./
:6HE.33.6'a(
:3H31./.6
%,sHc,e,j,k
C"+sH !lackboard,
,.8.% -lides
/3 Integrating type #"C-,peration of "ual
slope #"C
T3H31.7.)
:3H31././
%,sHc,e,j,k
C"+sH !lackboard,
,.8.% -lides
"#C and #"C specification /6 -pecifications of #"C and "#C to be
considered in practical applications
T3H31./
:3H31.6.7,31./..
%,sHd,c,h,i,j,k
C"+sH !lackboard,
,.8.% -lides
/7 Tutorial
UNIT VI
Classification of Integrated Circuits // Classification of "igital IC, characteristics of
"igital IC,Introduction to logic families
:3H/.3,/.6
%,sHa,b,e
C"+sH !lackboard,
,.8.% -lides
-tandard TT& >#>" ?ate-#nalysis &
Characteristics, TT& ,pen Collector
,utputs. Tristate TT&
/$ Concepts of TT&,operation of TT& nand
gate,active pull up,wired #>"
T6H33./,33.$
:3H/.=
%,sHa,b,e
C"+sH
, !lackboard, ,.8.%
-lides
/) open collector output,unconnected
inputs,clamping diodes
+,- & C+,- open drain and tristate
outputs
/. >+,- logic,+,-AT >#>" and >,:
gate,an in,an out,%ropagation delay,power
dissipation,unconnected inputs
T6H33.$
:3H/.36
%,sHa,b,e
C"+sH &C" %rojector,
!lackboard, ,.8.%
-lides
/= C+,- advantages over +,-,C+,-
inverter,>#>" and >,: gate,transmission
gate,noise margin,unconnected inputs,wired
logic,open drain outputs
T6H33.$
:3H/.37
%,sHa,b,e
C"+sH &C" %rojector,
!lackboard, ,.8.%
-lides
Comparison of 4arious &ogic amilies Comparison all the logic families :3H%gH361,363
%,sHa,b,e
C"+sH
!lackboard, ,.8.%
-lides
IC interfacing- TT& driving C+,- /E Interfacing C+,- and TT&,TT& driving
C+,--Current and voltage relations
:3H/.3/
%,sHa,b,e
C"+sH
!lackboard, ,.8.%
-lides
C+,- driving TT& C+,- driving TT& -Current and voltage
relations
$1 Tutorial
UNIT VII
Ise of TT&-./00 -eries & C+,-
/100 -eries ICs, TT& ICs - Code
Converters,

$3 Introduction to IC forms of TT& and C+,-
logic families-Code converters,!C" to
binary,binary to !C" converters
T6H)..
:3H).E
J %,sHj,h,e
C"+sH !lackboard,
,.8.% -lides
"ecoders, "emultiple*ers, $6 "ecoders@"emultiple*ers IC forms and
designing with them
T6H).$,).E
:3H).7
%,sHb,e,k
C"+sH !lackboard,
,.8.% -lides
Ancoders,%riority Ancoders, multiple*ers
& their applications.
$7 Ancoder,priority encoders,+ultiple*er IC
form and design of digital circuits using them
T6H).),).=
:3H).31
%,sHb,e,k
C"+sH !lackboard,
,.8.% -lides
%arity ?enerators, $/ %arity generators and checkers using ICs T6H).31
:3H).=
%,sHb,e,k
C"+sH !lackboard,
,.8.% -lides
#rithmetic Circuit ICs-%arallel !inary #dders and subtractors IC forms T6H).7
#dder@-ubtractor Ising 6Ks Complement
-ystem
:3H)./
%,sHb,e,k
C"+sH
!lackboard, ,.8.%
-lides
+agnitude Comparator Circuits. Comparator IC form T6H)./
:3H)..
%,sHb,e,k
C"+sH
!lackboard, ,.8.%
-lides
$$ Tutorial
UNIT VIII
Commonly #vailable ./00 & C+,-
/100 -eries ICs - :-, FG.FG +aster-
-lave. " and T Type lip-lops & their
Conversions
$) Introduction to se<uential circuits,lip flop
ICs
T6H..3-..$
:3H..3-..)
%,sH b,c,e,k
C"+sH !lackboard,
,.8.% -lides
$. conversion from one flip flop to other
$= Tutorial
-ynchronous and asynchronous
counters,"ecade counters.
$E "esign of asynchronous up@down counters. T6HE.3-E.=
:3H=./-=.)
%,sHb,c,e,k
C"+sH !lackboard,
,.8.% -lides
)1 "esign of synchronous up@down counters
)3 "ecade counters
-hift :egisters & applications. )6 -hift register type -I%,,-I-,,%I%,,%I-, T6H=.3-=..
:3H=.6,=.7
%,sHb,c,e,k
C"+sH !lackboard,
,.8.% -lides
)7 5ring counter, twisted ring counters
)/ Tutorial
6.3.$ BOOKS REFERRED TO BY FACULTY :
T1 : ".:oy Chowdary, CLinear Integrated Circuits , >ew #ge International' p( &td, 6nd
Ad.,
6117.
T : :amakanth ?ayakward, COP-amps and linear integrated circuitsD, %8I, 3E=..
T# : :.%. Fain, CModern Digital Electronics by 7rd Adition.
ouglin & redrick ."riscoll, COperational Amplifiers & Linear Integrated CircuitsD-:.
...
6.3.6 <EBSITES :
3. www.fau.edu
lorida #tlantic Iniversity, lorida, >#
&ibraries you find the information regarding both electronically and in paper.
6. www.iitb.ac.in
Indian Institute of Technology, !ombay
The links contains list of journal titles arranged alphabetically in %" format.
Alectronic Fournals on subscription at the IIT !ombay are listed separately.
7. httpH@@www.library.iisc.ernet.in@
Indian Institute of -cience, !angalore
The links contains &ibrary Collections, Alectronic :esources, I>"A-T- #ICTA A-
:esource ,: -I!FACT A0%,-I:A 'I> T8I- ;A!-ITA- L,I ;I&& I>" -,+A
%:,FACT- !#-A" ,> ./3, $$$, $))(
3. httpH@@www.electrokits.com@pojects@circuits-using-ic-./3
6. httpH@@www.uoguelph.ca@Mantoon@gadgets@./3@./3.html
7. httpH@@$$$-timer.clarkson-uk.com@
/. httpH@@www.elecfree.com@electronic@generating-a-delayed-pulse-using-the-$$$-timer@
$. httpH@@www.elecfree.com@electronic@tag@$))@
). httpH@@www.ee.surrey.ac.uk@%rojects@&abview@gatesfunc@inde*.html
.. httpH@@www.synthdiy.com@show@NidO3161
6.3.= JOURNALS :
3 IAAA transactions on 4&-I systems
6 IAAA Transactions on Industrial Alectronics.
7 IAAA Transactions on Circuits and -ystems-I
/ IAAA Transactions on Circuits and -ystems-II
$ Alectronics for you maga2ine 'monthly (
) IATA technical review
6.3.> STUDENT SEMINAR TOPICS :
3. >e*t generation IC technology for analog@digital 4&-I, -wanson, A.
-olid--tate Circuits Conference. "igest of Technical %apers. 3E=. IAAA International,
4olume
000, Issue , eb 3E=. %age's(H 366 9 367, "igital ,bject Identifier
6. ,p amps and analog circuits overall discussion of analog computer circuits and op
amp behavior
httpH@@www.play-hookey.com@analog@
7. Integrated "C &ogarithmic #mplifiers
httpH@@www.ma*im-ic.com@appnotes.cfm@anPpk@7)33
/. #nalog Integrated Circuits
httpH@@openbookproject.net@@electricCircuits@A*per@A0%P).html
$. #udio "esigns ;ith ,p-#mp
httpH@@sound.westhost.com@dwopa.htm
). #nalog-to-"igital Conversion
httpH@@www.mwit.ac.th@Mphysicslab@hbase@electronic@adc.html
.. #nalog to "igital Converter & "igital to #nalog Converter - ,verview
httpH@@dev.emcelettronica.com@analog-to-digital-converter-digital-to-analog-converter-
overview
=. &ogic amily 4oltage Translation
httpH@@www.interfacebus.com@"esignPTranslation.html
E. "esigning Combinational Circuits
httpH@@www.spsu.edu@cs@faculty@bbrown@webPlectures@sumprod@
31. "esign of -e<uential Circuits
httpH@@www.eelab.usyd.edu.au@digitalPtutorial@part7@design.htm
6.3.? ASSIGNMENT !UESTIONS:
UNIT I
3. A*plain briefly the difference between digital and linear ICBs.
6. ;hat is the difference between monolithic and hybrid ICBsN
7. ;hat is the major difference between --I, +-I, &-I, 4&-I, I&-I & ?-IN
/. ;hat is the major difference between the power supply re<uirements of linear and
digital ICBsN
$. ;hat information is contained in the typical op-amp data sheetN
). A*plain why proper interpretation of op-amp data sheet is important.
.. &ist the parameters that should be considered for ac and dc applications
=. ;hat are the three factors that effect the electrical parameters of an op ampN
E. A*plain the difference between constant current bias and current mirror.
31. ;hy AT opamps are better than !FT op-ampsN
33. ;hat is the major functional block of an op-amp.
36. "ifferentiate the inverting, non inverting modes of an op-amp
37. ;rite a short note on stability of an op-amp
3/. ;rite short notes on slew rate of an op-amp
3$. ;rite short notes on fre<uency response of an op-amp
UNIT II
3. ;hat are the major advantages and disadvantage of a single supply ac amplifierN
6. A*plain briefly the advantages of the differential input and output amplifier.
7. If a ./3ic is configured as an i 9 v converter. ;hat is the lowest$ value of current
that may bemeasuredN
/. A*plain the difference between ac and dc voltage follower
$. A*plain the difference between integrator and differentiator and give one application
of each
). ;hat is the difference between basic comparator and -chmitt triggerN
.. ;hat is sample and hold and why is it neededN
=. A*plain briefly why integration is proffered over differentiation in analog computers
E. Indicate how two analog voltages are multiplied using log and anti log amplifiers
31. ;hat are the limitations of ordinary op-amp differentiatorN
33. write short notes on instrumentation amplifier
36. "ifferentiate between I-4 and 4-I converters.
37. "ifferentiate between multipliers and dividers.
3/. ;rite short notes on 2ero crossing detector
3$. &ist out the features of .67
UNIT III
3. "efine a filter and how are filters classifiedN
6. write short notes on active filters
7. write short notes on passive filters
/. differentiate analog and digital filters
$. differentiate audio and radio fre<uency filters
). write short notes on band pass filters
.. &ist the commonly used filtersN
=. ;hat is a passband and a stopband for a filterN
E. ;hat are the advantages of active filters over passive onesN
31. ;hat is all pass filterN ;here and why is it neededN
33. ;hat is the difference between the sawtooth wave and the triangular waveN
36. ;hat is 4C,N ?ive two applications of a 4C,N
37. ;hat are the important of band pass filterN
3/. 8ow to get a notch filter from a band pass filterN
3$. &ist out the advantages and disadvantages of active and passive filters
UNIT-IV
3. &ist out the important features of $$$ timer
6. ;hat are the two basic modes in which the $$$ timer operates.
7. ;hat must the relationship be between the pulsewidth tp and the time period t of the
input trigger signal if the $$$ is to be used as a divider by / net works
/. briefly e*plain the internal structure of $$$ timer
$. why $$$ timer is called as $$$IC
). e*plain the operation of comparators used in $$$.
.. what is the role of transistors in $$$ IC.
=. &ist one application each in which the $$$ can be used as a monostable and astable
multivibrator
E. &ist the basic building blocks of the discrete %&&.
31. what is the use of 4C, in %&&.
33. ;hat is the major difference between digital and analog pllsN
36. ;hat is the major difference between small signal and power amplifiersN
37. ;hat is voltage regulator and list out the different voltage regulators.
3/. ;hat are the advantages of adjustable voltage regulator over fi*ed voltage
regulatorN
3$. ;hat is voltage refrence and why is it neededN
UNIT V
3. Classify "#C- on the basis of their outputs
6. >ame the essential parts of a "#C
7. "escribe the various types of electronic switches used in "@# converter
/. 8ow many resistors are re<uired in 36-bit weighted resistor "#CN
$. ;hy is an inverted :-6: ladder network "#C better than :-6: ladder "#C.
). &ist the various #@" conversions techni<ues
.. ;hich is fastest #"C and whyN
=. A*plain how dual slope #"C provides noise rejection
E. A*plain the important specifications of "@# and #@" converters
31. ?ive the conversion time for different types of #"C converters
33. ;hat is the need of #"C converters
36. ;hat is the need of "#C converters
37. "ifferentiate #"C and "#C converters
3/. A*plain the operation of #"C and "#C in computers
3$. or the input to a processor which type of converter is used and whyN
UNIT VI
3.. A*plain the following terms with reference to ttl gateN
i. &ogic levels.
ii. "c noise margin.
iii. &ow-state unit load. Iv. 8igh-state fan out.
6. &ist out ttl families and compare them with reference to propagation delay, power
consumption, speedpower
product and low level input currentN
7. &ist out standard ttl characteristics and e*plain them briefly with necessary
diagrams.
/. "esign cmos transistor circuit for 6-input and gateN ;ith the help of function table
e*plain the circuitN
$. ;hat is meant by tri-state logic N "raw the circuit of tri-state ttl logic and e*plain its
functions.
). Compare different logic families and mention their advantages and disadvantagesN
.. &ist out ttl families and compare them with reference to propagation delay, power
consumption, speedpower product and low level input currentN
=. &ist out standard ttl characteristics and e*plain them briefly with necessary
diagrams.
E. "esign cmos transistor circuit for 6-input and gateN ;ith the help of function table
e*plain the circuitN
31. "esign a /-input cmos or-and-invert gateN A*plain the circuit with the help of logic
diagram and function tableN
33. Compare various logic families
36. ;rite short notes on TT&
37. ;rite short notes on +,- technologies
3/. ;rite short notes on AC&
3$. "ifferentiate between AC& and TT&
UNIT VII
3. "esign a 76H3 multiple*er using two 3)H3 multiple*er icBs
6. "esign a full adder using =H3 mu* ics. Compare the ic package count with the nand-
nand reali2ation
7. "esing a /-bit adder@subtractor circuit with add@sub control line
/. "esign a parity generator circuit to check odd or even parity
$. "escribe encoding and give an e*ample
). "escribe decoding and give an e*ample.
.. "iscuss the basic structure of parallel binary adder. -how how two ./ls=7a can be
connected to form an =-bit parallel adder.
=. "iscuss the basic structure of parallel binary adder. Ise ./ls6=7 adders to
implement a 36 bitparallel adder.
E. ;hat does a comparator do. Ise ./hc=$ comparators to compare the magnitudes of
two =-bit numbers. -how the comparators with proper connections.
31. ;hat is the basic function of decoder. "etermine the logic re<uired to decode the
binary number 3133 by producing a high level on the output.
33. ;rite short notes on mu*
36. ;rite short notes on demu*
37. &ist out the different types of encoders
3/. &ist out the different types of decoders
3$. ;hat is code converter. &ist different types of code converters.
UNIT VIII
3. "esign a 3)*6 cam using two =*6 cam chips
6. A*plain linear selection addressing and coincident selection addressing
7. It is desired to find the ma*. 4alued number stored in a cam of si2e 3)*=. -uggest a
suitable method
/. -uggest a suitable arrangement for e*panding the bit capacity of ccdBs
$. -uggest a suitable arrangement for e*panding the word length of ccdBs
). It is desired to design a memory system for storing information which is not already
stored in it. this type of memory is known as learning memory. ;ill you prefer to use ram
or cam
.. "iscuss and compare the s-r, d and j-k flip flop.
=. A*plain the operation of edge triggered d flip flop and draw its output waveforms.
E. 8ow does a j-k flip flop differ from an s-r flip flop in its basic operationN
31. "iscuss about the flip flop operating characteristics.
33. ;rite short notes on counters
36. ;hat do you mean decade counters.
37. ;rite short notes on registers. ;hat is the need of shift register.
3/. ;rite down the application of counters
3$. Compare flip-flops with registers.
6.3.1@ !UESTION BANK :
UNIT I
3. 'a( &ist the reasons for differences inideal & practicle inverting op-amp amplifier
'b("erive the e*pressions for i@p o@p impedances of practicle non-inverting op-amp
amplifier
'c("iscuss how a voltage follower is built using an op-amp'JNTU NOV8DEC 1A
2. (a) Discuss about stability of an OP-Amp.
(b) Draw high frequency model of an OP-Amp and eplain its wor!ing.
(J.N.T.U MAY/JUNE 2012)
7. 'a( ;hat is a level translator circuitN ;hy it is used with the cascaded differential
amplifierN
'b( ;hat is a cascode amplifierN &ist the characteristics of the cascode amplifier.
BC*/. 4+( @11A
/. 'a( A*plain the various techni<ues used to compensate for thermal drift in ,p-
#mps.
'b( A*plain the effects of time on input-,ffset voltage and input-offset current.
BC*/. 4+( @11A
$. 'a( A*plain the role of negative feedback in operational amplifiers.
'b( 8ow does negative feedback affect, the performance of an inverting amplifiersN
;hat are the three operating temperature ranges of the ICN
BC*/. 4+( @11(
). 'a( CalculateH
i. ma*imum output offset voltage caused by the input offset voltage 4ios
ii. ma*imum output offset voltage caused by the input bias current I! . or
an inverting amplifier with :3 O 311 kQ & :f O 31 kQ. 8ere ./3 ,%-#mp
is used with 4ios O ) m4 I! O $11 n#.
'b( "raw and e*plain the practical circuit for offset voltage measurement of ,%
-#mps.
BC*/. 4+( @11A
.. Consider the circuit shown in figure $.
'a( Calculate the output voltages of the circuit.
'b( A*plain the effect of CB on stability of the ,%-#mp connection.

BC*/. 4+( @11A
=. 'a( A*plain why open loop configurations are not used in linear applicationsN
'b( or an op-#mp, %-::O.1d!'min(, C+::O31$ , differential mode gain #d O31$ ,
The output voltage changes by 61v in / R seconds. Calculate
i. >umerical value of %-::
ii. C+::
-lew rate.
E. 'a( A*plain the concept of current mirror circuit by drawing the circuit.
'b( ;hat is an integrated circuit chipN ;hat it consist of N
31. 'a( ;ith help of a block diagram e*plain the basic building blocks of an ,p-amp.
'b( ;hat does the term Sbalanced outputB mean in an ,p-ampN
'c( &ist the parameters that should be considered for #C and "C application.
BJNTU A&08M,1 @@?A
33. 'a( "erive closed loop voltage gain, input resistance, output resistance and band-
width for inverting amplifier with feedback arrangement.
'b( A*plain any one of the fre<uency compensation techni<ue in connection with
,p-amp.
BJNTU A&08M,1 @@?A
36. 'a( "efine slew rate and derive the e*pression for it. &ist causes of the slew rate and
e*plain its significance in applications.
'b( A*plain the difference between slew rate and transient response. BJNTU
A&08M,1 @@?A
37. 'a( ;hat are the three factors that affect the electrical parameters of an ,p-amp.
'b( "erive the e*pression for C+:: for the first stage differential amplifier.
BJNTU A&08M,1 @@?A
3/. 'a( ?ive the design procedure of a compensating network for an ,%-#+% which
uses T314
supply voltages. #ssume necessary data.
'b( In the circuit of figure3b below, :3O311, :O/..G C+::OE1 db. If the amplitude of
the induced )1-82 noise at the output is $mv 'rms(, calculate the amplitude of the common-
mode input voltage 4cm.. BJNTU M,1 @>A
3$. i. "efine the terms H-4::,C+::,input bias offset volteage ,?ain !andwidth
product.
ii. ;hat are the differences between the inverting and non inverting terminalsN ;hat do you
mean by the term Cvirtual groundDN BJNTU M,1 @>D F+3 @>D S+&/ @6D M,1 @$A
3). 'a( ;hat is cross over distortions and how it is eliminated in differential amplifierN
'b( A*plain different methods of e*ternal fre<uency compensation in an ,p-amp.
'c( "esign an amplifier with a gain of U$ using one ,p-amp 'make necessary
assumptions(.
BJNTU M,1 @>A
3.. 'a( &ist out the ideal characteristics of an ,p-amp.
'b( ;ith neat block diagram e*plain the function of various building blocks of an
,p-amp.
'c( "raw the e<uivalent circuit of an ,p-amp. BJNTU M,1 @>D F+3 @>A
3=. 'a( "esign a unity gain summing amplifier to add three dc input voltages -1.$4,
1.34 and 1..$4 in inverting configuration. If the saturation voltages of the ,%- #+% are
U3=4, and -3=4, find the possible ma*imum gain of the amplifier.
'b( "esign a subtractor circuit whose output is e<ual to the difference between the two
inputs. Ise a differential ,%-#+% configuration BJNTU F+3 @>A
3E. 'a( "erive the e*pression of the output voltage of an antilog amplifier using ,%
#+%
'b( ;hat is a summerN "esign a summer to add / "efine the terms H -4::,C+:: input
voltages in inverting configuration BJNTU F+3 @>A
61. i. "efine input offset voltage and C+:: as applied to ,p-amp ICs.
ii. A*plain how the above parameters can be measuredN BJNTU A.9 @=D M,1
@3A
63. i. "efine slew rate and derive the e*pression for it. &ist causes of the slew rate and
e*plain its significance in applications.
ii. A*plain the difference between slew rate and transient response BJNTU A.9D
A&0 @=D M,1 @3A
66. i. A*plain the open loop and closed loop operations of an ,p-amp.
ii. A*plain different methods to increase the input resistance of an ,p-amp.
BJNTU A.9D A&0 @=A
67. i. ;hat are the three differential amplifier configurationsN Compare and contrast
these
configurations.
ii. ;hat is a level translator circuitN ;hy is it used with the cascaded differential amplifier
used in ,p-ampsN
iii. A*plain the termD-lew :ateD and how it affects the fre<uency response of an ,p-
ampN
BJNTU A.9 @=A
6/. i. ?ive the pin diagram of IC./3 and give its specifications.
ii. "iscuss the differences between the differential amplifiers used in the first two stages of
,p-amp. BJNTU M,1 @>D A&0 @=A
6$. i. #n op-amp has a slew rate of 64@Rs. ;hat is the ma*imum fre<uency of an output
sinusoid of peak value $4 at which the distortion sets in due to the slew rate limitation.
"erive the formulae used.
ii. If the sinusoid of 314 peak is specified, what is the full power band widthN
iii. &ist out the non ideal "c characteristics of an ,p-ampN BJNTU A&0 @=A
6). i. ;hy is emitter resistor :A replaced by a constant current bias circuit in
differential amplifier stage of an ,%-#+%N
ii. A*plain why open loop configurations are not used in linear applications
iii. or an ,%-#+%, %-::O.1d!'min(,C+::O31$,differential mode gain#dO31$. the
output voltage changes by 614 in / microseconds. Calculate i(numericalvalue of %-::
'ii(Common mode gain iii( -lew rate of the ,%-#+%. BJNTU M,1 @6D@$A
6.. i. "erive the e*pression for C+:: for the first stage differential amplifier
ii. A*plain about any two linear and nonlinear applications of ,%-#+% BJNTU
M,1 @6D@$A
6=. A*plain in detail all the dc and ac characteristics of an ideal ,%-#+% with relevant
e*pressions. BJNTU M,1 @$A
6E. i. "raw a circuit using ,%-#+% ,which can work as adder ' inverting and
noninverting( and e*plain how it works.
ii. ;hat is an ,%-#+%N ;hy it is called soN BJNTU S+&/ @6D M,1 @$A
71. "raw and e*plain the three open loop ,%-#+% configurations with neat circuit
diagram.
BJNTU D+( @#A
73. ;hat is a summerN "esign a summer to add / input voltages in inverting
configuration.
BJNTU M,1 @$D @#A
76. "raw the circuit diagram of a two input non inverting type summing amplifier and
derive the e*pression for output voltage. !riefly e*plain why negative feedback is desirable
in amplifier applications 8ow does negative feedback affect the performance of an inverting
amplifierN
BJNTU F+3 @>D M,1 @$D @#A
77. "iscuss the electrical characteristics of an ,%-#+% in detail BJNTU F+3 @>D
M,1 @#A
"raw an ideal voltage transfer curve of an ,%-#+% what are the features of IC ./3N
7/. i &ist and e*plain the two special cases of inverting amplifiers.
ii. ;hat is a voltage followerN ;hat are its features and applicationsN
iii. "erive the e*pression for the output voltage of a non inverting amplifier.
BJNTU M,1 @>D M,1 @#A
7$. i. A*plain the precautions that can be taken to minimi2e the effect of noise on an ,%-
#+%
circuit.
ii. Calculate the effect of variation in power supply voltages on the output offset voltage for
an inverting amplifier circuit. BJNTU D+( @#A
7). "efine the following electrical parameters of an op-amp input offset current, input
bias current. "ifferential input resistance, input capacitance, offset voltage adjustment range
and C+::. BJNTU J,* @3A
7.. "etermine the output voltage in each of the following cases for the open loop
differential amplifier shown in figure.
Case 'i( 4in3 O $Rv dc, 4in6 O -Rv dc
Case 'ii(4in3 O 31mvrms, 4in6 O 61 mvrms
The op-amp has the following specification # O 611111, :i O 6+V, :o O .$V, 4cc O
U3$4, 4AA O -3$4 and output swing O T3/4. BJNTU J,* @3A
7=. "erive closed loop voltage gain, input resistance, output resistance and bandwidth
for inverting amplifier with feedback arrangement. A*plain any one of the fre<uency
compensation techni<ue in connection with ,p-amp. BJNTU M,1 @>D J,* @3A
7E. "efine the following electrical parameters of an op-amp Input offset voltage, Input
resistance, C+::, output voltage swing. -lew rate, -upply voltage rejection ratio and ?ain
bandwidth %roduct. BJNTU J,* @3A
/1. "etermine the output voltage for the Inverting amplifier shown in figureH
Case 'i( 4in O 61 mv"C
Case 'ii( 4in -$1Rv peak sine wave
?ain O 611,111 'for both cases( BJNTU J,* @3A
/3. "erive closed loop voltage gain, input resistance, output resistance and !andwidth
for non inverting amplifier with feedback arrangement. BJNTU J,* @3A
/6. i. ;ith the help of a block diagram e*plain the basic building blocks of an op-amp.
ii. ;hat does the term Sbalanced outputB mean in an op-amp. BJNTU J,* @3A
/7. i. &ist the parameters that should be considered for #C and "C application.
ii. ;hat are the three factors that affect the electrical parameters of an op-amp.
BJNTU J,* @3A
//. i. "efine input offset voltage and C+:: as applied to op-amp ICs.
ii. A*plain how the above parameters can be measuredN BJNTU M,1 @3A
/$. i. "efine slew rate and derive the e*pression for it. &ist causes of the slew rate and
e*plain its significance in applications.
ii. A*plain the difference between slew rate and transient response. BJNTU M,1 @3A
/). i. ;hy is it necessary to use an e*ternal offset voltage compensating network with
practical opamp circuitsN
ii Compare and contrast an ideal op-amp and practical op-amp.
iii. A*plain the precautions that can be taken to minimi2e the effect of noise on an
,%-#+%
circuit.
iv. Calculate the effect of variation in power supply voltages on the output offset voltage for
an inverting amplifier circuit. BJNTU M,1 @>D M,1 @3A
/.. i. A*plain the precautions that can be taken to minimi2e the effect of noise on an op-
amp circuit.
ii. Calculate the effect of variation in power supply voltages on the output offset
voltage for an inverting amplifier circuit. BJNTU M,1 @3A
/=. "esign a subtractor circuit whose output is e<ual to the difference between two
inputs. Ise a basic differential ,p-#mp configuration. BJNTU N%; @3A
/E. i. "raw the open loop configuration of inverting amplifier and non inverting
amplifier. -tate why open loop configurations are not used in linear application.
ii. ;hat are the characteristics of an ideal opam5
iii. ;hat is meant by voltage transfer curve in an opampN
iv. A*plain with block diagram the different feedback configuration in an opamp.
BJNTU J,* @3A
$1. i. !riefly e*plain the characteristics of an ideal opamp.
ii. ;hat do you mean by input offset voltage and input offset current of an opampN A*plain
and give the e*perimental setup to measure these parameters. BJNTU M,1 @3A
$3. ind the output voltage of the following circuit, assuming ideal op-amp behavior.
BJNTU GATE ?#A
$6. -ketch the output as a function of the input voltage 'for negative values( for circuit
shown in ig. -how all the ,%-#+%, and forward drop of the diode "3O1. BJNTU
GATE ?$A
$7. #ssuming ideal op-amps, show that the circuit shown in ig. simulates an inductor,
i.e. show that 4i's(@Ii's( is inductive and write the e*pression for the effective inductance
BJNTU GATE ?6A
$/. Consider the circuit given in ig., using an ideal operational amplifier BJNTU
GATE ?=A
$$. In the circuit shown in ig., assume that the operational amplifier is ideal and that
4oO14 initially. The switch is connected first to S#B charging C3 to the voltage 4. It is then
connected to the point S!B. This process is repeated f times per second BJNTU GATE
?=A
$). "evelop the voltage transfer function 4o@4s for the amplifier shown BJNTU
GATE ?$A
$.. "etermine the input impedance of the circuit of ig. #nd investigate if it can be
inductive
BJNTU GATE ?>A
$=. The differential input operational amplifier shown below consists of a base amplifier
of infinite gain. "erive an e*pression for its output voltage, 41 BJNTU GATE ?>A
$E. ;hat is the output voltage 4o of the circuit shown in figure. The input voltages are
43 O 6.$4 and 46 O 34. BJNTU GATE @@A
)1. or the circuit shown below, what is the magnitude of transfer function 4o @ 4i.
BJNTU GATE @@A
)3. igure given below shows an op-amp amplifier. ;hat is the output voltage in steady
state condition, where
i. -witch S-B is open ii. -witch S-B is closed BJNTU GATE @@A
)6. or the figure shown below, 4o's(@4i's( will be BJNTU GATE @@A
UNIT II

3( 'a( what is the operation performed by an inverting op-amp amplifier if iers if its
feedback resistance is replaced by a capacitanceNe*plain the function of such a circuit.what
are the practical difficulties associated with this circuitN
'b( what is the purpose of an n-channel +,-AT in a typical op-amp based sample &hold
circuit NA*plian through circuit operation & relevant waveform.
c(A*plain the operation of an op-amp astable multivibrator used as s<uare wave generator
suggest a method to resist its o@p swing to predetermined valuesN'F>TI >,4@"AC 36(
6( 'a( A*plain the operation of limiters using ,p-#mp.
'b( A*plain the characteristics of comparator and draw the circuit for comparator
using ,p-#mp.'jntu may 6136(
3. Consider the circuit shown in figure 3H
"etermine the following when, 43 O 34 & 46 O 64
'a( I*
'b( 4#
'c( 4!
A*pression for 4# & 4! in terms of 43 & 46 .

'jntu dec 6133(
7. 'a( A*plain what the circuit does as shown in figure 6 and e*plain its working.
'b( ;hat is the ma*imum value for 4in when the potentiometer is set to its
ma*imum resistanceN

'jntu dec 6133(
/. 'a( A*plain how & 7E= can be used as sample and hold circuitN
'b( "raw the wave forms of inverting and non-inverting comparator.
'jntu dec 6133(
$. 'a( ;hat is a clipperN ;ith circuit diagram, e*plain the operation of positive and
negative clippers.
'b( "escribe the principle of operation of a precision half wave rectifier with wave forms.
BJNTU A&08M,1 @@?A
BJNTU A&08M,1 @@?A
). 'a( A*plain the operation of Wero crossing detector.
'b( !riefly mention the disadvantages of using Wero crossing detector and how it is
overcome in -chmitt TriggerN
'c( "raw a circuit using ,p-amp which can work as adder 'inverted and non-inverted( and
e*plain how it works. BJNTU A&08M,1 @@?A
BJNTU A&08M,1 @@?A
.. 'a( ;hat is ?yrator circuitN A*plain its operation with a neat circuit diagram.
'b( ;hat is a sample and hold circuitN ;hy is it neededN ;ith neat circuit diagram, describe
the operation of an ,p-amp based sample and hold circuit. BJNTU A&08M,1 @@?A
. 'a( -ketch the circuit of a logarithmic amplifier using one ,p-amp and e*plain its
operation. -tate its application.
'b( ;hat is a sample and hold circuitN ;hy is it neededN "raw a sample and hold circuit
and e*plain its operation. BJNTU A&08M,1 @@?A
=. 'a( A*plain how ,p-amp used as a integrator and differentiator.
'b( ;ith the help of a neat circuit diagram, e*plain the operation of instrumentation
amplifier of obtain the e*pression for its o@p voltage 4,. BJNTU M,1 @>A
E. 'a( "raw the circuit and e*plain the working ofH
i. voltage to current converter
ii. current to voltage converter.
'b( "raw a circuit using ,p-#mp, which can work as adder 'inverting and non-inverting(
and e*plain how it works. BJNTU M,1 @>A
31. 'a( "erive the closed loop voltage gain, input resistance, output resistance and
bandwidth for an inverting amplifier with feedback arrangement.
'b( !riefly e*plain why negative feedback is desirable in amplifier applications. 8ow does
negative feedback affect the performance of an inverting amplifierN BJNTU M,1 @>A
33. 'a( ;hat is a clipperN ;ith circuit diagram, e*plain the operation of positive and
negative clippers.
'b( "escribe the principle of operation of a precision half wave rectifier with wave
forms.
BJNTU M,1 @>A
36. 'a( A*plain the operation of Wero crossing detector.
'b( !riefly mention the disadvantages of using Wero crossing detector and how it is
overcome in -chmitt TriggerN
'c( "raw a circuit using ,p-amp which can work as adder 'inverted and non-inverted( and
e*plain how it works. BJNTU M,1 @>A
37. 'a( "iscuss the operation of a log amplifier and derive the e*pression for output
voltage
'b( "esign a current to voltage converter using ,%-#+% and e*plain how it can be
used to
measure the output of a photocell. BJNTU F+3 @>A
3/. i. "iscuss important characteristics of a comparator and the limitations of ,pamps as
comparators.
ii. A*plain the operation of -chmitt trigger circuit. BJNTU A.9 @=A
3$. i. "raw the circuit diagram of a two input non inverting type summing amplifier and
derive the e*pression for output voltage.
ii. !riefly e*plain why negative feedback is desirable in amplifier applications.
iii. 8ow does negative feedback affect the performance of an inverting amplifierN
BJNTU A.9 @=A
3). i. A*plain with a neat circuit diagram the working of voltage to current converter
with floating load and grounded.
ii. "esign a circuit to convert a / m# to 61m# input current to 14 to 314 output voltage.
The circuit is powered from T3$4 regulated supplies. '#ssume necessary data(
BJNTU A.9 @=A
3.. i. A*plain 8;: using inverting and non-inverting configuration.
ii. A*plain the operation of astable multivibrator using ,p-amp. BJNTU A.9 @=A
3=. i. In the circuit 'figure 6b( it can be shown in that 4o O a343 U a646 U a747. ind
the values of a3, a6, a7. #lso find the value of 4o if
:/ is shorted circuited. ii. :/ is removed. iii. :3 is shorted circuited.
ii. "esign anaveraging circuit for/ "CinputBs. BJNTU A&0 @=A
3E. i. "iscuss the functioning of a practical integrator and derive the necessary
e*pressions.
ii. "esign a practical integrator circuit to properly process input sinusoidal wave
forms up
to 3 G82. The input amplitude is 31m4 BJNTU A&0 @=A
61. i. A*plain the non-linear application of ,p-amp as logarithmic and anti loga rithmic
amplifier.
ii. "esign a Integrator to integrate an I@% signal that varies in fre<uency from 3 G82
to 31 G82 and plot the ,@% wave forms if the I@% is a sine wave of 34 peakat3G82.
iii. In some measurements it is necessary to sense current from a transducer and convert it
into voltage. or a three ,p-amp reali2ation of a current input instrumentation amplifier,
derive the e*pression for 4o. BJNTU A&0 @=A
63. "esign a practical intergrator circuit to properly process input sinusoidal wave forms
upto 3G82. The input amplitude is 31mv. BJNTU A&0 @=D M,1 @3A
66. "raw a sample and hold circuit and e*plain its operation with necessary input and
output waveforms and indicate its uses. BJNTU M,1 @6D @$A
67. i. "raw the circuit and e*plain the working of voltage to current converter
ii. Current to voltage converter. BJNTU M,1 @$A
6/. ;ith reference to sample and hold circuit define the following termsH
i. #perture time ii. 8old mode. BJNTU M,1 @6D @$A
6$. ;hat do you mean by samplingN A*plain the basic circuit for sample and hold
circuit.
BJNTU M,1 @>D M,1 @$A
6). ;hat is a switching regulatorN "raw the block diagram of a typical switching
regulator and e*plain its operation. BJNTU S+&/ @6D M,1 @$A
6.. ;hat are the four types of voltage regulatorsN Compare the performance of these
regulators. A*plain the principle of operation of IC.67 general purpose regulator with neat
block diagram. BJNTU D+( @#A
6=. ;hat is 4C,N 8ow can you design a 4C, using ,%-#+%N A*plain the role of
4C, in a phase locked loop. BJNTU D+( @#A
6E. "esign a differentiator to differentiate an input signal that varies in fre<uency from
3182 to about 3G82 .draw its output waveform if sin 6n * 3111t signal is applied.
BJNTU D+( @#A
71. ;hat are the advantages of instrumentation amplifierN "erive an e*pression for the
transfer function of an instrumentation amplifier. BJNTU S+&/ @6D N%; @#A
73. A*plain the use of reference terminal provided in an integrated circuit
instrumentation amplifiers. BJNTU N%; @#A
76. ;hy do you need -@8 circuit in data loggers. A*plain the operation of -@8 circuit
employing AT as input ,%-#mp. BJNTU N%; @#A
77. i. ;ith neat block diagram, e*plain the operation of a fi*ed voltage regulator
describe the operation of an IC based negative voltage regulator. ?ive few applications.
BJNTU M,1 @#A
7/. i. ;hat are the advantages of adjustable voltage regulator over the fi*ed regulatorN
ii. A*plain the importance of voltage references and voltage inverters. BJNTU
M,1 @#A
7$. i. "esign a saw tooth wave form generator using ,%-#+% and plot the waveforms
for the given specifications fre<uencyH $G82, 4satO T 3$4. '#ssume necessary data(
ii. ;hat is the difference between a basic comparator and the -chmitt triggerN
Construct a
-chmitt trigger circuit using ,%-#+% and derive the threshold voltages. BJNTU
M,1 @#A
7). "raw an integrator circuit and e*plain its operation. "iscuss the fre<uency response
for a
practical integrator. BJNTU J,* @3A
7.. "erive the voltage gain and input resistance for an Instrumentation amplifier.
BJNTU J,* @3A
7=. ;ith the help of block diagram e*plain Instrumentation #mplifier in detail.
BJNTU N%; @3A
7E. A*plain the application of three terminal adjustable voltage regulator. BJNTU
N%; @3A
/1. ;ith the help block diagram e*plain &7E= sample and hold IC along with
waveforms.
BJNTU N%; @3A
/3. "raw any one multivibrator circuit using op-amp and e*plain its operation.
BJNTU J,* @3A
/6. "raw the circuit of a s<uare wave generator and e*plain itBs operation BJNTU
J,* @3A
/7. "esign a practical intergrator circuit to properly process input sinusoidal wave forms
upto 3G82. The input amplitude is 31mv. BJNTU M,1 @3A
//. "esign a differentiator that will differentiate an input signal with fma* O 31182.
BJNTU M,1 @3A
/$. "esign a differentiator using ,p-amp to differentiate an input signal that varies in
fre<uency from 3G82 to 31G82. BJNTU M,1 @3A
/). ind the output voltage, 41 in the following circuit, assuming that the op-amps are
ideal
BJNTU GATE ?3A
i. -how that the system shown in ig., is a double integrator. In other words, prove that the
transfer gain is given by X4o's(@4s's(Y O X3@'C:s(6Y, assume ideal ,%-#+% BJNTU
GATE ?$A
UNIT III
3( 'a( &ist out the merits &demerits of active filter over passive filter
'b(A*plain the functioning of any one :C type oscillators based on suitable circuit
diagramNwhat are the typical fre<uencies of oscillationN'F>TI >,4@"AC 6136(
2) (a) Di"erentiate between the feedbac! networ!s of #$ phase shift
oscillator and
%ein &ridge Oscillator.
(b) 'ist out the applications of %ein &irdge Oscillator.((ntu 2)*2 may)
7. 'a( "esign a fourth order !utter worth low pass filter having upper cut off fre-
<uency 3 G82 and pass band gain of 31.
'b( ;rite about fre<uency transformation in active filter.

'jntu dec 6133(
/. 'a( ;ith a neat diagram e*plain about triangular wave generator.
'b( ;ith a neat diagram, A*plain about -awtooth. ;ave form generator.
'jntu dec 6133(
$. 'a( "efine the conditions on the feed back circuit of an amplifier to convert it into
an oscillator.
'b( ;hat is 4C,N ?ive two applications of it.
"esign a )1 82 #ctive &%.

'jntu dec 6133(
). "esign and -econd ,rder I?+ band pass filter with the following specifications.
f, O $11 82, gain at resonance O -$ and band width O $1 82. Ise the circuit
shown in figure / assume necessary data.

'jntu dec 6133(
.. 'a( "esign a irst order 8% at a cut off fre<uency of 7k82.
'b( "raw the fre<uency response of the above filter.
=. 'a( "esign a first -order low pass filter so that it has a cut off fre<uency of 6k82
and pass !and gain of B3B
'b( Convert the 6k82 low pass filter to a cut off fre<uency of 7k82 in part 'a(
E. 'a( "esign a second order high pass filter at a cut off fre<uency of 3k82.
'b( "raw the fre<uency response of the network in part 'a(.
31. or a second order butter worth filter given C6 O C7 O 1.1/.R 5
:6 O :7 O 7.7kQ, :3 O 6.kQ, and : O 3$.=kQ
'a( "etermine the lower cutoff fre<uency f& of the filter.
'b( "raw the fre<uency response plot of the above filter.
33. 'a( "erive the e*pression for fre<uency of oscillation of a :C phase shift oscillator
and e*plain the operation of the circuit. B
'b( "esign a second order low pass filter at a high cut off fre<uency of 3 G82. "erive the
transfer function of the above filter. BJNTU A&08M,1 @@?A
36. 'a( Classify the filters and e*plain the characteristics of each one of them.
'b( "raw the first order low-pass !utterworth filter and analy2e the same by deriving the
gain and phase angle e<uation. BJNTU A&08M,1 @@?A
37. 'a( "erive the e*pression for fre<uency of oscillation of a :C phase shift oscillator
and e*plain the operation of the circuit.
'b( "esign a second order low pass filter at a high cut off fre<uency of 3 G82. "erive the
transfer function of the above filter. BJNTU A&08M,1 @@?A
3/. 'a( "erive the transfer function, gain and phase angle for second order high pass
active filter.
'b( A*plain how Z, upper cutoff fre<uency and lower cutoff fre<uency is determined in
!and pass filter. BJNTU A&08M,1 @@?A
3$. 'a( "efine a >otch filter. ?ive its application.
'b( "etermine the order of the !utterworth low-pass filter so that at [ O 3.$[7d!, the
magnitude response is down by at least 71 d!.
'c( "esign a notch filter for fo O= k82 and <uality factor ZO31. Choose CO$11pf
and assume
necessary data BJNTU M,1 @>A
3). 'a( !riefly describe three uses of an analog multiplier. BJNTU M,1 @>A
'b( ;hat do you mean by samplingN A*plain the basic circuit for sample and hold
circuit
BJNTU M,1 @>A
3.. 'a( !riefly describe three uses of an analog multiplier.
'b( ;hat do you mean by samplingN A*plain the basic circuit for sample and hold
circuit.
BJNTU M,1 @>A
3=. 'a( "iscuss the functioning of a practical integrator and derive the necessary
e*pressions.
'b( "esign a practical integrator circuit to properly process input sinusoidal
waveforms upto 3
G82. The input amplitude is 31m4. BJNTU M,1 @>A
3E. 'a( "erive the e*pression for fre<uency of oscillation of a :C phase shift oscillator
and e*plain the operation of the circuit.
'b( "esign a second order low pass filter at a high cut off fre<uency of 3 G82.
"erive the
transfer function of the above filter. BJNTU M,1 @>A
61. 'a( "esign a II order !utterworth &ow-pass filter for a cut off fre<uency of 3G82
and for a given normali2ed polynomial of -6U3./3/-U3. #ssume necessary data.
'b( In the above circuit given 'figure 7'b(ii( if the integrator components are :3O361 G and
C3 O1.13\,:7O ).= G :6O 3.6G, determine %eak-to-peak triangular output amplitude. The
fre<uency of triangular wave BJNTU M,1 @>A
63. 'a( The cutoff fre<uency of a certain first order low pass filter is 6 G82. Convert this
low pass
filter to have a cutoff fre<uency of 7 G82 by using the fre<uency scaling techni<ue.
'b( 8ow do we get a >otch filter from a band pass filter.
'c( ;hat are the advantages of active filters over passive filters BJNTU M,1 @>A
66. 'a( A*plain the function of a typical adjustable voltage regulator. 8ow can you
increase the current driving capacity of the regulatorN
'b( "escribe the principle of working of a balanced modulator using ,%-#+%. #lso
give the
applications of it. BJNTU F+3 @>A
67. 'a( ;hat feedback is preferred for oscillators and whyN ;hat is the effect of
negative feedbackN
'b( "esign an ,%-#+% based rela*ation oscillator and derive the fre<uency of
oscillation.
BJNTU F+3 @>A
6/. 'a( ;hat feedback is preferred for oscillators and whyN ;hat is the effect of
negative feedbackN
'b( "esign an ,%-#+% based rela*ation oscillator and derive the fre<uency of
oscillation
BJNTU F+3 @>A
6$. i. "raw the circuit diagram of a low-pass sallen key filter and determine itBs gain.
ii. "raw the block diagram of a band rejection filter and e*plain itBs operation.
BJNTU A.9 @=A
6). i. ;hat are the advantages of active filtersN A*plain wideband band pass filter
together with itN samplitude response.
ii. ;hat is phase shifterN ;ith respect to schematic e*plain the operation. BJNTU
A.9 @=A
6.. i. "erive the transfer function for a general second order sallen-key filter with
suitable circuit
diagram.
ii. ;ith suitable circuit diagram e*plain the operation of a triangular wave generator
using a
comparator and an integrator. BJNTU M,1 @>D F+3 @>D A.9 @=A
6=. ;rite short notes on the operation of any twoH
i. Zuadrature oscillator.
ii. :C phase shift oscillator.
iii. ;ien- bridge oscillator. BJNTU A.9 @=A
6E. i. "efine the conditions on the feedback circuit of an amplifier to convert it in to an
oscillator.
ii. "esign an :C phase shift oscillator for 7118W fre<uency using IC R# ./3 and
T3$4 power
supplies. #ssume necessary component values. -uggest a method to reduce the output
voltage swing to I T ).$ 4olts. BJNTU A&0 @=A, BJNTU A.9 @=A
71. i. &ist the conditions for oscillation in all the three types of oscillators, namely, :C
phase shift,
wien- bridge and <uadrature oscillators.
ii A*plain the difference between a signal generator and a function generator.
iii. Fustify the name for <uadrature oscillator. BJNTU A&0 @=A
73. i. A*plain the operation of a delay e<uali2er circuit with neat sketches. "erive an
e*pression
relating input and output voltages of the e<uali2er.
ii. or the all pass filter, determine the phase shift between input and output at fO6
G82.
iii. ?ive the condition for oscillationsN BJNTU M,1 @>D F+3 @>D A&0 @=A
76. i. "raw the schematic diagram of ;ien !ridge ,scillator and derive the e*pres-sion
for fre<uency of oscillation.
ii. ;hat are the conditions to be satisfied by a circuit to produce oscillationsN
BJNTU F+3 @>D A&0 @=A
77. "esign a notch filter for fo O=k82 and <uality factor ZO31. Choose CO$11 pf and
assume necessary data. BJNTU M,1 @6D @$A
7/. i. "esign the band pass filter with fc O 3G82, ZO7 and # O31.
ii. "raw the fre<uency response and also change the center fre<uency to 3.$ G82
keeping #
and band-width constant. BJNTU M,1 @$A
7$. "esign and obtain the fre<uency response of a band pass filter with f&O /1182, f8 O
3G82 and the pass band gain O3. BJNTU M,1 @6D @$A
7). "raw the band pass filter circuit with its fre<uency response curve. A*plainits
working. BJNTU M,1 @$A
7.. i. ;hat are the advantages of active filters over passive once
ii. "esign a second order low pass butter worth filter for a cutoff fre<uency of 6 G82
assume
necessary data. BJNTU M,1 @$A
7=. # certain narrow band pass filter has been designed to meet the following
specificationsH fc O
6kh2, ZO 61 and #p O 31. what modifications are necessary in the filter circuit to change
the center fre<uency SfcB to 3kh2, keeping the gain and bandwidth constantN BJNTU
S+&/ @6D M,1 @$A
7E. i. "efine !essel, !utterworth and Chebyshev filters ,and compare their fre<uency
response.
ii. -ketch the circuit diagram of band elimination filter and design a wide band reject
having
fhO61182 and flO3k82. #ssume nessary data. BJNTU M,1 @$A
/1. "esign a !utterworth filter for a given normali2ed polynomial of =6U 3./3/=U 3.
#ssume
necessary data. BJNTU D+( @#A
/3. i. "erive an e*pression for the <uality factor SZB of a twin- T notch filter. ?ive the
suitable
circuit diagram.
ii. Identify the given circuit and derive an e*pression for !andwidth of the same
circuit.
BJNTU D+( @#A
/6. A*plain the term Cre<uency -ealingD with suitable e*ample. BJNTU D+( @#A
/7. i. "efine a >otch filter. ?ive its application.
ii. "etermine the order of the !utterworth low-pass filter so that at wO3.$ w7d!, the
magnitude response is down by at least 71 d!.
iii. "esign a notch filter for fo O=k82 and <uality factor ZO31. Choose CO$11 pf
and assume
necessary data. BJNTU F+3 @>D M,1 @#A
//. A*plain the operation of a delay e<uali2er circuit with neat sketches. "erive an
e*pression relating input and output voltages of the e<uali2er. BJNTU S+&/ @6D M,1
@#A
/$. or the all pass filter, determine the phase shift between input and output at fO6 k82.
To obtain a positive phase shift, what modifications are necessary in the circuitN BJNTU
M,1 @#A
/). -ketch the circuit diagram of band elimination filter and design a wide band-reject
having f8O611 82 and f&O3k82. #ssume necessary data. BJNTU M,1 @#A
/.. "esign a wide band pass filter with f& O 61182 , f8 E 3 G82 and a pass band gain O /
i. "raw the fre<uency response plot of this filter.
ii. Calculate the value of Z for the filter. BJNTU M,1 @#A
/=. "esign a band pass filter with I?+ config. by selecting fC O3G82 ,Z O 7,# O31.
Change the center fre<uency to 3.$ G82 , keeping # and band width constant.
BJNTU M,1 @#A
/E. "esign a narrow band pass filter so that fC O 6G82 , ZO 61 and # O 31. BJNTU
M,1 @#A
$1. "esign a first order high pass filter at a cutoff fre<uency of /1182 and a pass band
gain of 3.
BJNTU N%; @#A
$3. i. or the all-pass filter, determine the phase shift f between the input and output at f
O 6G82. To obtain a positive phase shift f, what modifications are necessary in the circuitN
ii. ;hat is a pass band and a stop band for a filterN 8ow are filters classifiedN
BJNTU N%; @#A
$6. A*plain how Z, upper cutoff fre<uency and low cutoff fre<uency is determined in
!andpass filter. BJNTU J,* @3A
$7. i. "raw the circuit diagram of a low-pass sallen key high pass filter and determine
itBs gain.
ii. "raw the block diagram of a band rejection filter and e*plain itBs operation.
BJNTU J,* @3A
$/. "erive the transfer function, gain and phase angle for first order low pass active
filter. BJNTU J,* @3A
$$. i. ;hat is meant by all pass filter. -tate itBs application.
ii. "raw a block diagram of a broad-band bandpass filter and e*plain itBs operation.
BJNTU J,* @3A
$). i. "raw a bandpass filter circuit and show how upper and lower cutoff fre<uency is
determined
by selecting Z. "erive the transfer function and gain for the band pass filter.
ii. "raw a circuit diagram of a universal bi<uard filter and show how low pass, band
pass and
high pass output can be achieved simultaneously. BJNTU J,* @3A
$.. i. "raw the second order high pass butterworth filter circuit and itBs fre<uency
response.
ii or the above circuit C6 O C7 O 1.1/.R, :6 O 7.7 kilo ohm, :3 O 6. kilo ohm and :f O
3$.= kilo ohm. "etermine the lower cutoff fre<uency of the filter.
$=. i. ;hat is all pass filterN A*plain.
ii. "esign a narrow band pass filter using one op-amp. The resonant fre<uency is
36=82 and Z
O 3.$. -elect C O 1.3R. BJNTU M,1 @3A
$E. i. "esign suitable component values for a low pass filter to achieve a corner
fre<uency of 3
G82. ;ith a dc gain of 61d! and an input impedance of at leat 31 kilo ohms.
ii. Calculate the fre<uency at which gain drops of unity. BJNTU M,1 @3A
)1. i. "esign a wide band reject filter using first order high pass and low pass filter
having f& O 6
G82 and f8 O /11 h2 respectively.
ii. "raw an appro*imate fre<uency response plot for the above filter. BJNTU
M,1 @3A
)3. !riefly e*plain the steps involved in constructing phase plots of filters. BJNTU
M,1 @3A
)6. "efine by means of a diagram the pass band , stop band, transition band and
passband
ripple. sketch the ideal fre<uency 9response characteristics of low pass ,high passand band
reject system BJNTU J,* @3A
)7. i. "esign suitable component values to achieve a bandpass response with a gain of
61d! over
the audio range.
ii. -ketch the fre<uency response of this filter in the fre<uency range 1-3+82.
BJNTU M,1 @3A
)/. i. "esign a multiple feedback narrow bandpass filter for fcO3G82 , ZO7 and #fO31.
ii. Change the center fre<uency to 3.$G82 keeping #f and the bandwidth constant for the
above filter. BJNTU M,1 @3A
)$. i. The cutoff fre<uency of a certain first order low pass filter is 6G82 cover this low
pass filter
to have a cutoff fre<uency of 7G82 by using the fre<uency scaling techni<ue.
ii. ;hat is the butter worth responseN BJNTU M,1 @3A
)). ?ive the classification of filters e*plain the fre<uency response of all filters.
BJNTU N%; @3A
BJNTU GATE ?#A
).. or the circuit shown find the damping factor and the cut-off fre<uencyH BJNTU
IES @3A
)=. ind the value of :B in the circuit of ig. or generating sinusoidal oscillations. ind
the fre<uency of oscillations. BJNTU GATE ?>A
)E. "etermine the fre<uency of oscillation of the circuit shown in figure, assume op-
amp is ideal.
BJNTU GATE @@A
.1. The circuit given in the figure will work as an oscillator at f O 3@'6]:C(, if :3@:6 is
BJNTU GATE @@A
.3. The input voltage 4I in the circuit shown in the figure is a 3 G82 sine wave of 34
amplitude.
#ssume ideal operational #mplifier with T3$4 "C supply
ind the peak value of 43
ii. ind the average value of 41 BJNTU GATE @@A
UNIT-IV
3. 'a( "iscuss how a $$$ Timer can be used for -G modulation,missing pulse detection
,pulse width &pulse position modulation state the mode of operation $$$ in each caseN
'b(what is the role played by phase detector in a operation of %&&Ne*plain its block
diagram Ndifine the lock and capture range of %&&N'jntu nov@dec 36(
6. 'a( ;rite the speciPcations of >A$$$ timer IC.
'b( "esign a $$$ timer circuit whose output fre<uency is 6 G82 when the
Trigger input signal fre<uency is / G82.
'c( In the $$$ monostable multivibrator circuit if :# O 31 k determine the value
of C for output pulse duration of 3 m sec.'jntu 6136 may(
7. 'a( "escribe the application of $$$ timer as pulsing bu22er.
'b( ;hat are the functions of threshold and control voltage pins in $$$ timer ICN
'jntu dec 6133(
/. 'a( 8ow an symmetrical wave form generator can be constructed using $$$ timerN
'b( If :# O ).= kQ, :! O 7.7 kQ, c O 1.3 R in $$$ astable multivibrator.
CalculateH
i.thigh
ii.tlow
iii.ree running fre<uency
iv."uty cycle.
'jntu dec 6133(
$. 'a( ;rite about voltage controlled fre<uency shifter using $$$ timer.
'b( or the fre<uency shifter calculateH
i. The charge current I for input A O ,4
ii. The centre fre<uency when A O ,4
The fre<uency shift fout for A O T 34.

'jntu dec 6133(
). ;hat are passive loop filters in %&& consider the %&& shown in figure 7N
'jntu dec 6133(
.. 'a( A*plain the importance of $$$ timer in designing a monostable multivibrator
'b( "esign a monostable multivibrator using $$$ timer to produce a pulse width
of 311msec.
=. A*plain the basic principles used in %&&. ;hat does the feed back system consist.
A*plain.
E. 'a( ?ive the block diagram of >A $)$ %&& and e*plain the role of each block. +ake
circuit connections to track the incoming signal and e*plain its operations. BJNTU
A&08M,1 @@?A
'b( ;ith neat sketches, e*plain the following termsH
i. &ock-in-range.
ii. Capture range
iii. %ull-in time.
31. 'a( "escribe the $$$ time +onostable multivibrator applications in BJNTU
A&08M,1 @@?A
i. re<uency +odulation.
ii. %ulse ;idth +odulation.
'b( "escribe
i. %ulse %osition +odulation '%%+( and
ii. -G generator using $$$ timer astable multivibrator.
33. 'a( &ist the application of IC $)$%&& and briefly describe the role of the %&&
in any of that application.
'b( :eferring to the circuit shown in figure /b determine the free running output, lock range
and the capture range BJNTU A&08M,1 @@?A
36. 'a( "raw and e*plain the functional diagram of a $$$ Timer.
'b( A*plain the function of SresetB pin. BJNTU M,1 @>A
37. 'a( "escribe the operation of an analog phase detector.
'b( #naly2e the behavior of an analog phase detector through necessary circuit diagram,
waveforms, mathematical e*pressions and characteristic curves BJNTU M,1 @>A
3/. 'b( "esign a s<uare waveform generator of fre<uency 3k82 and duty cycle of .$^
using $$$
timer BJNTU F+3 @>A
3$. "escribe any two applications of $$$ timer in
i. #stable multivibrator configuration.
ii. +onostable multivibrator configuration BJNTU A.9 @=A
3). i. ?ive the functional block diagram of >A $)$ %&& and for the given component
values. C3 O
7E1%, C6 O )=1% and R1 = 31k,4cc O T )4. ind
i. The free running fre<uency.
ii. The lock range and capture range.
;here C1 is the capacitor connected between pin number E and - 4CC, C6 is the
capacitor
connected between U 4CC and output pin ., and R1 is connected between pin
number = and
U 4CC.
ii. ?ive the functional block diagram of 4C, >A$)) and e*plain its working and
necessary
e*pression for free running or center fre<uency BJNTU A.9D A&0 @=. S+& @6D
M,1 @$A
3.. i. A*plain the operation of #stable multivibrator using $$$ timer.
ii. "esign a +onostable multivibrator using $$$ timer to produce a pulse width of
611 ms.
BJNTU F+3 @>D A.9 @=A
3=. i. "raw the block diagram of $)$ %&& and e*plain about each block. +ake circuit
connections
to track the input signal and e*plain its operation.
ii. ;rite short notes on H
i. %&& as fre<uency multiplier.
ii. %&&asfre<uency translator. BJNTU A.9 @=A
3E. i. "esign a $$$ #stable multivibrator to operate at 31 G82 with /1^ duty cycle.
ii. "raw the circuit of %&& as fre<uency multiplier and e*plain its working.
BJNTU M,1 @>D A&0 @=D M,1 @3A
61. i. ;hat is the phase-&ocked loopN !riefly e*plain the roles of &ow-pass filter and
4C, in %&&.
ii. A*plain an application in which the $$$ timer can be used as #stable
multivibrator. BJNTU A&0 @=A
63. i. ;ith necessary e*ternal components to a 4C, IC >A$$), A*plain the generation
of a triangular wave.
ii. # %&& has a free running fre<uency of $11 G82, the bandwidth of the &%O3 G82. ;ill
the %&& lock in if fi O)1 G82N ;hat is the fre<uency of the 4C, outputsN BJNTU A&0 @=A
66. i. "raw the circuit of -chmitt trigger using $$$ timer and e*plain its operation.
ii. 8ow is an #stable multivibrator using $$$ timer connected in to a pulse position
modulatorN BJNTU M,1D F+3 @>D M,1 @$A
67. i. ?ive the functional block diagram of >A$)$ %&& '"I%( and for the given
component values. C3 O7E1%, C6 O )=1% and :3O31G, 4cc O U)4 find
i. the free running fre<uency
ii. the lock range and capture range
where C3 is the capacitor connected between pin number E and 94cc , C6 is the
capacitor
connected between U4cc and output pin ., and :3 is connected between pin number
= and
U4cc.
ii. ?ive the functional block diagram of 4C, >A$)) and e*plain its working and
necessary
e*pression for free running or center fre<uency. BJNTU S+&/ @6D M,1 @$A
6/. "iscuss, with relevant circuits and waveforms, the working of monostable
multivibrator using $$$ timer. BJNTU M,1 @6D @$A
6$. "esign a $$$ #stable multibrator to operate at 31k82 BJNTU M,1 @6D @$A
6). "raw a circuit and e*plain in detail the two operating modes of the $$$ timer with
timing
diagram. BJNTU J,* @3A
6.. i. ?ive the pin configuration of $$$ times and list itBs important features.
ii !riefly e*plain the difference between the two operating modes of $$$ timer. A*plain any
one of the modes in detail. BJNTU J,* @3A
6=. i. A*plain the operation of +onostable multivibrator using $$$ timer. "erive the
e*pression of
time delay of a +onostable multivibrator using $$$ timer.
ii. "esign a +onostable multivibrator using $$$ timer to produce a pulse width of
311m sec.
BJNTU F+3 @>D M,1 @3A
6E. i. A*plain the role of the basic building blocks of %&&.
ii. "etermine the "C control voltage 4c at lock if signal fre<uency fsO31 G82, 4C,
free
running fre<uency is 31.)) G82 and the voltage to fre<uency transfer co-efficient of
4C, is
))11 82@v. BJNTU F+3 @>D M,1 @3A
71. A*plain the operation of a phase detector. BJNTU M,1 @#D@3A
73. i. ;hat are the two basic modes in which the $$$ timer operatesN !riefly e*plain the
differences between the two operating modes of the $$$ timer. BJNTU F+3 @>D M,1
@3A
ii. "esign a ramp generator using $$$ timer having an output fre<uency of appro*imately $
G82.
76. "esign an astable multivibrator having an output fre<uency of 31 G82 with a duty
cycle of $1^ using $$$ timer. BJNTU N%; @3A
77. i. A*plain %&& using block diagram.
ii. A*plain pin configuration of $$$ timer. BJNTU N%; @3A
7/. A*plain in detail one application each in which the $$$ can be used as a monostable
multivibrator and astable multivibrator. BJNTU J,* @3A
7$. i. A*plain the significance of each of comparators and operation of $$$ timer.
ii. A*plain the application of $$$ timer as &inear ramp generator. BJNTU M,1 @>D
M,1 @$A
7). i. ?ive the block diagram of $)$ %&& '"I%( and e*plain about each block and
BJNTU M,1 @$A
for the given component values find the free running fre<uency fo, lock-range
and capture range C3O/.1%5 C6O3111%, :3O31k and 4CCO T )4
C3 connected between pin E and -4CC
C6 connected between pin . and U4CC.
ii. ?ive any two applications of %&& and e*plain about each one on detail.
7.. i. Calculate the fre<uency of oscillation of a $)) 4C, IC for the e*ternal component
values :T O ).=G and CT O /.1%. #ssume other component valuesif necessary.
ii. "raw the pin diagram of $)) 4C, IC and list important specifications of
$))4C, IC.
BJNTU M,1 @6D @$A
7=. i. "raw the dc voltage versus phase difference characteristic of balanced modulator
phase
detector of a %&& indicating all important regions.
ii. "raw the dc out put voltage of 4C, versus fre<uency characteristic of a %&&
indicating the
capture and lock range clearly.
iii. -tate the relationship between lock range and capture range through a mathematical
e*pression. BJNTU M,1 @$A
7E. i. "escribe the $$$ time monostable multivibrator applications in
i. pulse stretching ii. re<uency iii. %ulse ;idth +odulation
ii. "escribe %ulse %osition +odulation '%%+( using $$$ timer astable multivibrator.
BJNTU M,1 @6D @$A
/1. i. ;ith a suitable circuit diagram using >A $)$ %&& IC, e*plain implementation of a
-G
demodulation.
ii. ;hat are the standard fre<uencies used for mark and space to originate and
answer in -G
teletypewriter signal transmission. BJNTU M,1 @$A
/3. i. ?ive the functional block diagram of >A $)$ %&& '"I%( and for the given
component values. C3 O 7E1%, C6 O )=1% and :3 O 31k, 4cc O T)4 ind
ii. The free running fre<uency BJNTU M,1 @>D S+&/ @6D M,1 @$A
/6. i. A*plain the terms &ock range, Capture range and %ull-in time a %&&. 8ow are
&ock :ange and Capture range determinedN BJNTU S+&/ @6D M,1 @$A
ii. "esign a %&& circuit using IC $)$ to get
i. ree-running fre<uency O /.$ G82
ii. &ock range of 6 G82 and
iii. Capture range O 311 82.
#ssume a supply voltage of U or - 314. -how the circuit diagram with all
component values.
/7. "esign a ramp generator using $$$ timer having an output fre<uency of
appro*imately $G82.
BJNTU M,1 @$A
//. i. A*plain the role of the basic building blocks of %&&.
ii. "etermine the "C control voltage vc at lock if signal fre<uency fs O 31 G82,
4C, free
running fre<uency is 31.)) G82 and the voltage to fre<uency transfer co-efficient of
4C, is
))11 82 @ v. BJNTU M,1 @$A
/$. A*plain the use of $$$ timer as free running ramp generator and draw the output
waveforms
BJNTU D+( @#A
/). i. ;hat is the role of the following blocks in the operations of %&&. ?ive the circuit
diagrams
and e*plain in detail
i. %hase Comparator ii. &ow pass filter iii. 4C,.
ii. ?ive any two applications of %&&. A*plain in detail. BJNTU D+( @#A
/.. "iscuss, with relevant circuits and waveforms, the working of +onostable multi
vibrator using $$$ timer. BJNTU D+( @#A
/=. i. ?ive the function block diagram of >A $)$ %&& and make circuit connections to
track the
input signal and e*plain its working principle. BJNTU D+( @#A
ii. 8ow %&& is used as + demodulatorN A*plain its operation with neat circuit
diagram.
/E. i ?ive the block diagram of>A $)$ %&& and e*plain the role of each block. +ake
circuit
connections to track the incoming signal and e*plain its operations.
ii. ;ith neat sketches, e*plain the following termsH
'i( &ock-in-range 'ii( Capture range 'iii( %ull-in time.
iii. -ketch the capture transient and e*plain why it is generated before lockingN
BJNTU D+( @#A
$1. A*plain one application in which the $$$ can be used as a +onostable multivibrator.
BJNTU M,1 @#A
$3. i. ?ive the block diagram of %&& and e*plain about each block in detail.
ii. "efine the following terms with reference to %&& BJNTU M,1 @>D M,1
@#A
i. &ock range ii. Capture range iii. %ull-in-time
$6. ?ive the basic block diagram of %&& and e*plain about each block. BJNTU
M,1 @#A
$7. "esign a $$$ #stable multivibrator to operate at 31 G82 with /1^ duty cycle
BJNTU M,1 @#A
$/. "raw the circuit of %&& as fre<uency multiplier and e*plain its working. BJNTU
M,1 @#A
$$. "efine supply voltage sensitivity. ;hat is meant by poorly regulated power supplyN
BJNTU M,1 @#A
$). A*plain how %&& is used as a fre<uency translator, #+ demodulator. BJNTU
N%; @#A
$.. i. A*plain in detail the following terms with reference to %&&
'i( &ock range 'ii( Capture range 'iii( Capture transient 'F>TI iv( %ull-in-time.
ii. 'i( "raw the internal functional diagram of >A $)) 4C, and derive e*pression
for free
running fre<uency.
'ii( rom the given component values find the free running fre<uency
Control voltage 4CO31.E4, 4CCO364, :3O/..k and C3O3.3n. BJNTU N%; @#A
$=. ;hat is 4C,N 8ow can you design a 4C, using ,%-#+%N A*plain the role of
4C, in a phase locked loop. BJNTU M,1 @#A
$E. "efine the terms &ock range and Capture range, # %&& has a free running fre<uency
of $11 G82, the bandwidth of the &% O 31 G82. ;ill the %&& lock in if fi O )1 G82N
;hat is the fre<uency of the 4C, outputN BJNTU M,1 @#A
)1. "istinguish between a timer and counterN 8ow a $$$ timer can be used as fre<uency
decider.
BJNTU N%; @#A
)3. "efine &ock range and Capture range. ;hy &ock range is usually greater than the
capture rangeN BJNTU M,1 @#A
)6. i. "raw the circuit of a %&& #+ detector and e*plain its operation.
ii. ;hat is the major difference between digital and analog %&&sN BJNTU M,1 @>D
M,1 @#A
)7. #n IC $$$ chip has been used to construct a pulse-?enerator. Typical pin
connections with
components is shown in ig., or such as application. 8owever it is desired to generate a
s<uare pulse of 31k82. Avaluate values of :# and :! if the capacitor C has the value of
1.13 m for the configuration chosen. If necessary you can suggest modification in the
e*ternal circuit configuration BJNTU GATE ?=A
)/. ig. -hows the block diagram of phase-locked-loop '%&&( in the locked condition
The output voltage of the phase detector is given by 4%OGd 'fI - f1(, ;here fi is phase of
the input signal, and f1 is the phase of the output 4oltage Controlled ,scillator '4C,(. The
value of Gd is 3 4olt@ radian, the fre<uency deviation of the 4C, output is " fo O Gf 4C,
;here 4C is input voltage of the 4C,, and kf O 3$E.3$ 82@volt. The amplifier # is a buffer
with a voltage gain of unity. BJNTU GATE ?=A
i. "erive the transfer function f1 's(@ fI 's(.
ii. &et the loop to be locked for time t_1 and 1 't( for t`1
)$. Implement a mono-stable multivibrator using the timer circuit shown in ig. #lso
determine an e*pression for ,> time T of the output pulse BJNTU GATE ?>A
)). "raw the internal block diagram of an IC %&& >A$)$ or e<uivalent. A*plain how
you will reali2e a fre<uency multiplier to multiply an input fre<uency by a factor of 36 by
using this %&&BJNTU GATE @@A
UNIT-V
3. 'a(&ist specifications & the draw the pin diagram of IC 3/1= "#CN
'b(what is the specifications of ClinearityD and Cconversion timeD in #"C
'C( e*plain the operation of the weighted resistors "#CN'F>TI "AC@>,4 36(
6. 'a( Compare :-6: and weighted resistor types of "#Cs.
'b( ;rite short notes on #@" converters.
'c( "ePne the following terms as related to "#CH
i. &inearity
ii. :esolution.'jntu 6136 may(
7. 'a( A*plain the difference between #nalog to "igital converter and "igital to
#nalog converters through underlying e<uations.
'b( Illustrate one application each of #nalog to "igital and "igital to #nalog
converters.
'jntu dec 6133(
/. 'a( ;rite a note on multiplying "#Cs.
'b( Compare and contrast :-6: ladder type and weighted resistor type "#Cs.
&ist the specifications of a "igital-to-#nalog converter IC, 3/1=.
$. 'a( A*plain the operation of parallel comparator type #"C with the help of a
neat diagram.
'b( The &-! of a )-bit "@# converter represents 1.34. ;hat voltage value will
be represented by the following binary wordsN
i. 313131
ii. 331331

'jntu dec 6133(
). 'a( A*plain the operation of a -uccessive #ppro*imation type analog to digital
converter.
'b( Calculate the number of bits re<uired to represent a full scale voltage of 314
with a resolution of $m4 appro*imately.
'jntu dec 6133(
.. 'a( A*plain the effect of floating inputs on C+,- gate.
'b( A*plain how a C+,- device is destroyed.
'c( ;hat is the difference between transmission time and propagation delayN A*-
plain these two parameters with reference to C+,- logic.
'jntu dec 6133(
=. A*plain with neat block diagram a typical application in which #@" and "@#
conversions are employedN
E. 'a( 8ow many bits are re<uired to design a "#C, that has a resolution of $mvN
The ladder has U=4 full scale.
'b( 8ow many resistors are re<uired for an =-bit weighted resistor "#CN ;hat
are the resistance values, assuming the smallest resistance is :N
31. 'a( ;hat are the sources of analog errors in an #"CN
'b( ;hat is meant by differential linearity an #"CN
33. 'a( ;hat are the advantages of :-6: adder type "@# converter over weighted
resister typeN
'b( In an inverted :-6: ladder, :O:f O66kohms and 4: O364. Calculate the
total current delivered to the op-amp and the output voltage when the binary
is 331
36. 'a( "ifferentiate between "-# and #- " C,>4A:TA:-.
'b( A*plain "@# converter with : and 6: resistors. BJNTU A&08M,1 @@?A
37. 'a( The basic step of a 3)-bit "#C is 31.7 m4. If 1111111133333333 represents 14,
what output is produced if the input is 3333333333133133N
'b( Calculate the values of the &-!, +-! and full scale output for an 76bit "#C for the 1 to
614. BJNTU A&08M,1 @@?A
3/. 'a( Compare different #@" converters for their merits and demerits.
'b( ?ive the schematic circuit diagram of a successive appro*imation type #@" converter
and e*plain the operations of this system. BJNTU A&08M,1 @@?A
3$. A*plain different types #@" and "@# converters. BJNTU A&08M,1 @@?A
3). i. ;ith an e*ample e*plain the functional diagram of successive appro*imation
#"C.
ii. "raw the schematic circuit diagram of a -ervo #@" converter and e*plain the
operations of
this system.
iii. Compare -ervo #@" with other types of #@" converters. BJNTU F+3 @>D
A.9D A&0 @=A
3.. i. -ketch and e*plain the transfer characteristic of a "#C with necessary e<uations.
ii. &-! of a E-bit "#C is represented by 3E.) m 4olts. If an input of E 2ero bits is
represented by 1 volts.
i. ind the output of the "#C for an input, 31331 3313 and 13313 3133.
ii. ;hat is the ull scale :eading '-:( of this "#CN BJNTU M,1 @>D A.9
@=A
3=. i. A*plain the operation of a multiplying "#C and mention its applications.
ii. # 36-bit " to # converter has a full-scale range of 3$ volts. Its ma*imum
differential linearity error is T 3@6 &-!.
i. ;hat is the percentage resolutionN
ii. ;hat are the minimum and ma*imum possible values of the increment in its output
voltageN BJNTU A.9 @=A
3E. ;rite short notes onH
i. Counter type #"C devices.
ii. Inverted :-6: "igital to #nalog converter. BJNTU A&0 @=A
61. i. A*plain the operation of a dual slope type #nalog to "igital converter.
ii. # dual slope #nalog to "igital converter uses a 3)-bit counter and operates at /
+82 clock
rate. The ma*imum input voltage is U=volts. ind the value of integrator resistor S:B
if the
ma*imum output voltage of the integrator is -)4 after 6n counts for an integrator
capacitor of
1.3R. BJNTU A&0 @=D @$A
63. i. "raw the circuit of ;eighted :esistor "#C and derive e*pression for output
analog voltage
4o.
ii. ?ive the schematic circuit of an #@" converter widely used in digital volt-meters and
e*plain its operation. "erive e*pression for output voltage. BJNTU A&0 @=A
66. i. ;hy successive appro*imation #@"converters faster than dual-slope #@"
converterN A*plain.
ii. "raw the complete schmatic circuit of successive appro*imations #@" converter and
e*plain operations of this system. BJNTU M,1 @6A
67. i. &ist out various types of "@# converter and #@" converters and compare their
merits and
demerits.
ii ?ive the schmetaic circuits of successive appro*imations #@" converter and
e*plain its
operations. BJNTU M,1 @6D @$A
6/. i. &ist out different types of #@" converters.
ii. "raw the schmatic circuit diagram of dual-slope #@" converter and e*plain its
operation.
"erive e*pression for output voltage.
iii. Compare dual-slope #@" conerter with successive appro*imation #@" converter.
BJNTU M,1 @>D S+&/ @6D M,1 @$A
6$. i. "raw the circuit of a ;eighted :esistor "#C and obtain e*pression for n-bits.
ii. -ketch the #nalog output voltage for the given digital input code.
iii. ;hat are the major disadvantages in this typeN BJNTU M,1 @>D S+&/ @6D M,1
@$A
6). i. ;ith a neat circuit diagram e*plain the functioning of an inverted :-6: ladder
type "igital to analog converter.
ii. The &-! of a 31-bit "#C is 61 m volts.
i. ;hat is its percentage resolutionN BJNTU M,1 @6D @$A
ii. ;hat is its full-scale rangeN
iii. ;hat is the output voltage for an input, 31331 13313N
6.. i. -ketch and e*plain the transfer characteristic of a "#C with necessary e<uations.
ii. &-! of a E-bit "#C is represented by 3E.) m 4olts. If an input of E 2ero bits is
represented by 1 volts.
i. ind the output of the "#C for an input, 31331 3313 and 13313 3133
ii. ;hat is the ull scale :eading '-:( of this "#CN BJNTU M,1 @$A
6=. i. A*plain the operation of a counter type of #nalog to "igital converter.
ii. -pecify the modifications necessary in the circuit for a time varying analog input
voltage.
iii. Calculate the conversion time for a full scale input incase of a 36-bit counter type
#nalog to "igital converter driven by 6+82 clock. BJNTU M,1 @$A
6E. i. "efine the following terms as related to "#C
i. #ccuracy ii. :esolution.
ii. "efine the following terms as related to #"C
ii. Conversion time ii. %ercentage resolution.
iii. ;hich type of "#C is more preferableN "raw the circuit diagram and obtain e*pression
for output voltage for / bits. BJNTU M,1 @$A
71. A*plain the operation of the fastest analog to digital converter. ;hat is the main
draw back of this converterN Compare this converter with other types. BJNTU F+3 @>D
M,1 @$A
73. i. "raw the complete !lock -chematic circuit including gating circuit, level
amplifiers of :-6: / bit "@# converter and e*plain its operations. "erive e*pression for its
output voltage 41.
ii. "raw the block-schematic circuit of the fastest #@" converter and e*plain its
operation.
;hat are the disadvantages of this type of converter. BJNTU M,1 @#A
76. i. &ist out different types of #@" converters and compare their merits and demerits.
ii. ?ive the schematic circuit of an #@" converter widely used in digital voltmeters and
e*plain its operation. "erive e*pression for output voltage. BJNTU S+&/ @6D D+( @#A
77. i. "raw the schematic circuit diagram of a -ervo #@" converter and e*plain the
operations of
this system.
ii. Compare -ervo #@" with other types of #@" converters. BJNTU D+( @#A
7/. "esign a /-bit weighted resistor "#C whose full-scale output voltage is 9314olts.
#ssume :f O 31 k; logic S3B level as U $volts and logic S1B level as 1 volts. ;hat is the
output voltage when the input is 3133. BJNTU N%; @#A
7$. "efine the terms, S:esolutionB, S&inearityB and SConversion timeB of an #nalog to
"igital converter. BJNTU N%; @#A
7). "raw the circuit of ;eighted :esistor "#C and derive e*pression for output analog
voltage 4o. BJNTU M,1 @$A
7.. ?ive the working principle of #nalog-+ultiple*er. ?ive block diagram of a input
analog
+ultiple*er using C+,- gates and e*plain how it works. BJNTU S+&/ @6D N%;
@#A
7=. i. Compare this #@" converter with parallel comparator type #@" converter.
ii. ?ive the working principle of analog multiple*er. BJNTU N%; @#A
7E. "raw the complete !lock -chematic circuit including gating circuit, level amplifiers
of :-6: / bit "@# converter and e*plain its operations. "erive e*pression for its output
voltage 41.
BJNTU M,1 @6D @#A
/1. Compare weighted resistor "@# converter and :-6: "@# converter BJNTU
M,1 @6D @#A
/3. "raw a schematic diagram of a "@# converter. Ise resistance values whose ratios
are multiples of 6.A*plain the operation of the converter. BJNTU M,1 @#A
/6. i. A*plain the operation of a multiplying "#C and mention its applications.
ii. # 36-bit " to # converter has a full-scale range of 3$ volts. Its ma*imum differential
linearity error is U 3@6 &-!. BJNTU N%; @#A
i. ;hat is the percentage resolutionN
ii. ;hat are the minimum and ma*imum possible values of the increment in
its output a
voltageN
/7. i. "efine the terms S#perture timeB and S"roop rateB of a sample and hold circuit.
ii. Indicate one monolithic sample and hold IC of any manufacturer. BJNTU
N%; @#A
//. i. A*plain how the deficiencies of weighted resister type "#C can be overcome
through an :-
6: ladder type network. A*plain the conversion procedure in :-6: ladder type "#C
ii. The logic levels used in an =-bit :-6: ladder type "#C are logic S3BOU$ volts and logic
S1BO1 volts. ind the output voltage for an input of 31331331. BJNTU N%; @#A
/$. i. A*plain the basic techni<ue utili2ed in "igital to #nalog conversion using suitable
mathematical e*pressions.
ii. In an inverted :-6: ladder type "igital to #nalog Converter :O 31k; 4:A O U
61 volts.
ind the current in each 61 k; resister and the ma*imum current passing into the
feedback
resistor of the op-amp. BJNTU N%; @#A
/). i. "efine the terms S:esolutionB, SConversion timeB and S&inearityB of an #nalog to
"igital
converter.
ii. Indicate the fastest #nalog to "igital converter specifying its conversion time
with a
representative e*ample.
iii. ;hat is the resolution of a 33 bit #nalog to "igital converter for a full scale input
voltage of 31.6/ voltsN BJNTU N%; @#A
/.. "raw the block diagram of the $$$ timer. -how how $$$ can be used as an astable
multivibrator. "escribe the circuit operation with the help of waveforms and derive an
e*pression for the fre<uency of oscillations BJNTU J,* @3A
/=. i. "escribe in detail about !inary weighted resistance "@# converter. BJNTU
J,* @3A
ii. A*plain the principle of operation of single and dual slope analog to digital
converter.
/E. i. "raw the block diagram for a ladder network whose resistance has one of two
values : or
6:. A*plain the operation of the converter.
ii. ;hat limits the ac<uisition time in a sample and hold circuit. BJNTU J,* @3A
$1. i. "raw the block diagram for a 6-bit parallel-comparator #@" converter and e*plain
the operation of the system. BJNTU M,1 @>D J,* @3A
ii. "raw a schematic diagram of a ladder network "@# converter. A*plain the
operation of the
converter.
$3. i. "raw and compare the conversion times for tracking and successive
appro*imation #"C
devices.
ii. # dual slope #"C uses a 36 bit counter and a = +82 clock rate. The ma* input
voltage is
U314. The ma* integrator output voltage should be -=4, when the counter has
cycled through
6n counts. The capacitor used in the integrator is 1.3 micro farad. ind the value of
the
resistor of the integrator. BJNTU M,1 @>D M,1 @3A
$6. i. # counting type #"C uses a = bit "#C. The +-! of "#C output voltage is U$4
i. If the analog input voltage is U).=$v, what will be the :-6: ladder output voltage
when
the clock stopsN
ii. ;hat is the number of clock pulses that occur between the release of reset and stopping
of the clockN
ii. Calculate the values of the &-!, +-! ad full scale output for an = bit "#C for
the 1 to 314
range. BJNTU M,1 @3A
$7. ;rite short notes on the followingH BJNTU M,1 @3A
i. +ultiplying #"C
ii. -emi tracking #@" converters.
$/. i. A*plain in detail the following characteristics of #nalog to "igital converter.
i. :esolution ii. Zuanti2ation error BJNTU M,1 @3A
ii. #n = bit #"C is capable of accepting an input unipolar 'positive values
only( voltage 1 to 314.
i. ;hat is the minimum value of 3 &-!
ii. ;hat is the digital output code if the applied input voltage is $./4N
$$. A*plain in detail the succession appro*imation type #"CN BJNTU N%; @3A
$). ;rite short notes on -uccessive appro*imation #"C. BJNTU N%; @3A
$.. A*plain #"C and "#Cs. BJNTU N%; @3A
$=. # dual slope #"C uses a 3) bit counter and a / +82 clock rate. The ma* input
voltage is
31volts. The ma* integrator output voltage should be 9=4 when the counter has cycled
through 6n counts. The capacitor used in the integrator is 1.3m . ind the value of the
resistor : of the integrator. BJNTU N%; @3A
$E. i. A*plain the operation of the successive appro*imation #@" converter, with a block
diagram
and timing diagram. ?ive itBs advantages. BJNTU J,* @3A
ii. ;ith help of a block diagram and timing diagram e*plain the operation of ramp
type #@"
converter.
)1. i. ;hat is the difference between #@" and "@# converter. ?ive an application for
#@" and "@
# converter.
ii. "efine the following terms of "@# converter resolution, settling time and
conversion time.
iii. ;hat is a sample and hold circuit N why is it needed. "raw a sample and hold
circuit and
e*plain itBs operation. BJNTU J,* @3A
)3. A*plain the following terms pertaining to the logic families. Tphl, 4ol, 4ih, "C
noise margin,
#.C noise margin.
)6. "raw the block diagram for a counting #@" converter and e*plain itBs operation.
BJNTU J,* @3A
)7. i. "raw the block diagram of integration type #@" converter and e*plain its
operation. ?ive its
advantages and disadvantages.
ii. ;ith help of a block diagram e*plain in detail about parallel type #@" converter.
BJNTU J,* @3A
)/. i Compare weighted resistor "@# converter and :-6: "@# converter.
ii ;hy successive appro*imation "@# converter is preferable than parallel
comparator #@"
converter. A*plain.
iii. "raw the schematic block diagram of "ual-slope #@" converter and e*plain its
operation.
"erive e*pression for its output voltage 41. BJNTU M,1 @3A
)$. # monochrome video signal that ranges from 1 to =4, is digiti2ed using an =-bit
#"C.
i. "etermine the resolution of the #"C in 4@bit
ii. Calculate the mean s<uared <uanti2ation error
iii. -uppose the #"C is counter controlled. The counter is upcount and positive edge
triggered
with clock fre<uency 3+82. ;hat is the time taken in second to get a digital
e<uivalent of
3.$E 4N BJNTU GATE @1A
)). "raw a neat schematic to show the functional blocks of a successive appro*imation
#@" converter.A*plain its operation using timing diagrams. Comment on its conversion
speed with respect to the speeds of parallel #@" converter and dual slope #@" converter.
BJNTU IES @3A
).. Compare the ma*imum conversion time of an =-bit digital ramp #"C with that of a
successive appro*imation #"C both using a clock of 311 k82. 8ow do these compare with
that of a flash type #"CN BJNTU IES @3A
)=. "escribe the operation of a 7-bit flash type #"C with the help of a suitable diagram
and a table. BJNTU IES @3A
UNIT VI
3. a(;hy are the tri stated outputs &open collector outputs used in TT& ICN &ist
advantages of both type outputs
b(list different between various logic family ICs under TT& &ogic like ./series ,./
series ,./#&- series &./#- series of ICN'F>TI "AC@>,4 36(
6. 'a( "esign a C+,- transistor circuit that has the functional behavior f 'W(
O#.'!UC(
'b( "esign a /-input C+,- #>"-,:-I>4A:T gate. "raw the logic diagram
and function table. 'jntu may 6136(
7. 'a( "esign a C+,- transistor circuit with the functional behavior
f '0( O # U ! C U "
'b( "istinguish between static and dynamic power dissipation of a C+,- circuitN
"erive the e*pression for dynamic power dissipationN

'jntu dec 6133(
/. 'a( ;hat are the parameters that are necessary to define the electrical charac-
teristics of C+,- circuitsN +ention the typical values of a C+,- >#>"
gate.
'b( "esign a C+,- /-input #>"-,:-I>4A:T gate. "raw the logic diagram and
function table.
'jntu dec 6133(
$. 'a( "raw the circuits of >#>" and >,: gates using C+,- logic and e*plain
their operation with truth tables.
'b( Compare the performance of various logic families with reference to power
dissipation, propagation time delay, an in and an out.
'jntu dec 6133(
). 'a( "raw the C+,- circuit diagram of tri-state buffer. A*plain the circuit with
the help of logic diagram and function table.
'b( "esign a C+,- transistor circuit that reali2es the following !oolean function.
f 'a( O % U Z . 'Z U :( #lso e*plain its functional operations.
'jntu dec 6133(
A*plain the features of the TT& logic family.
.. A*plain the +,- and C+,- logic families and give different C+,- characteristics.
=. ;ith the help of a neat circuit diagram e*plain how e*tremely low propagation in
AC& logic can be achieved.
E. Compare the various &ogic amilies.
31. 'a( "efine logic family and e*plain
'b( -ketch TT& ,: ?ate and e*plain its working
'c( -ketch TT& #>" ?ate and e*plain its working. BJNTU A&08M,1 @@?A
33. # ./&- TT& gate drives four ./8C C+,- gates. +inimum 4cc is /..$ 4.
"etermine the minimum value of pull-up resistor for interfacing these devices.
'4,&'ma*(O1./4 I,&O=m# and II&O-3micro#
'a( A*plain TT& inverter with open collector output.
'b( Compare various logic families
'c( "ifferentiate bipolar IC and +,- IC. BJNTU A&08M,1 @@?A
36. 'a( A*plain the classification of integrated circuits
'b( -ketch TT& >#>" ?ate and e*plain its working
'c( -ketch TT& >,: ?ate and e*plain its working. BJNTU A&08M,1 @@?A
37. -pecify the following parameters for ./8 C+,-H BJNTU A&08M,1 @@?A
3/. 'a( "raw the schematic circuits of C+,- >#>" and C+,- >,: gates and
e*plain their functions with the help of Truth-Table.
'b( ;hat are the advantages and disadvantages of C+,- over TT& gateN
'c( ;hich is the fastest saturated logic gateN and ;hyN BJNTU M,1 @>A
3$. 'a( A*plain the term C4-4- configurationD. "esign a 4C4- low-pass !utter worth
second order filter with a cutoff fre<uency of / k82. #ssume necessary data in the design
process.
'b( "esign a second order I?+ band-pass filter with the following specifications H foO$11
825 ?ain at resonanceO-$ and band-widthO$182. Ise the circuit shown below 'figure )(.
#ssume necessary data. BJNTU M,1 @>A
3). 'a( A*plain the term SBre<uency -ealingSB with suitable e*ample.
'b( "esign a wide band-pass filter with f&O61182. 8O3G82 and a pass-band gainO/.
"raw the fre<uency response and calculate SZB factor for the filter. BJNTU M,1 @>A
3.. &ist out advantages, disadvantages & applications of +,- logic. BJNTU M,1 @>A
'a( A*plain the operation of open drain output of C+,-N
'b( A*plain the behavioral difference between simple transistor logic inverter and -chottky
logic inverterN BJNTU M,1 @>A
3=. 'a( A*plain the term Cre<uency -calingD with suitable e*ample.
'b( "esign a wide band-pass filter with f&O61182. 8O3G82 and a pass-band ainO/. "raw
the fre<uency response and calculate SZB factor for the filter. BJNTU F+3 @>A
3E. 'a( ;hat are the important blocks of %&&. ;hat is the role of each blockN A*plain in
detail.
'b( ?ive any two applications of %&& and e*plain about each applications in detail.
BJNTU M,1 @>A
61. A*plain the use +C 3/E) as #+ modulator with necessary circuit diagram.
BJNTU F+3 @>A
63. A*plain block schematic of %&&. &ist the application of %&&. BJNTU F+3 @>A
66. 'a( !riefly e*plain the role of phase comparator, low-pass filter and 4C, in %&&.
'b( ?ive any two applications of %&&. A*plain about each application in detail.
BJNTU F+3 @>A
67. i. ;hat is meant by Tri-state logic N "raw the circuit of Tri-state TT& logic and
e*plain its
functions.
ii. "raw the schematic circuit of TT& active pull-up >#>" gate and e*plain its
operation with
the helpof Truth-Table. BJNTU F+3 @>D A.9 @=A
6/. i. Compare different logic families and mention their advantages and disadvantagesN
ii. ;hich is the fastest non-saturated logic gateN "raw the circuit and e*plain its
functions.
BJNTU A.9 @=A
6$. i. A*plain the following terms with reference to TT& gateN
i. &ogic levels.
ii. "C >oise margin.
iii. &ow-state unit load. iv. 8igh-state fan out.
ii. &ist out TT& families and compare them with reference to propagation delay, power
consumption, speed-power product and low level input currentN BJNTU M,1 @>D A.9
@=A
6). &ist out standard TT& Characteristics and e*plain them briefly with necessary
diagrams.
BJNTU A&0 @=A
i. "esign C+,- transistor circuit for 6-input #>" gateN ;ith the help of function
table
e*plain the circuitN
ii. "raw the resistive model of a C+,- inverter and e*plain its behavior for &,;
and 8I?8
outputsN BJNTU A&0 @=A
6.. i. "esign a /-input C+,- ,:-#>"-I>4A:T gateN A*plain the circuit with the
help of logic
diagram and function tableN
ii. A*plain the following terms with reference to C+,- logicN
i. &ogic &evels.
ii. "C >oise margin.
iii. %ower supply rails.
iv. %ropagation delay. BJNTU A&0 @=A
6=. i. "raw the logic diagram e<uivalent to the internal structure of an =-input C+,-
>#>" gateN -how the transistor circuit for this gate and e*plain the operation with the help
of function tableN
ii. "raw the circuit diagram of basic C+,- gate and e*plain the operationN
BJNTU A&0 @=A
6E. or the given circuit shown below BJNTU M,1 @>D M,1 @6A
i. A*plain the operations of the circuit with the help of Truth-Table.
ii. If hA of Z3 is 71, find hAmin of Z6
iii. If hA of Z6 is 71, what is an-,utN
iv. ind >oise-+argin.
71. i. "efine the terms 'i( %ositive &ogic 'ii( >egative &ogic BJNTU M,1 @6D @$A
ii. -how that %ositive logic A0-,: operation is e<uivalent to negative logic A0->,:
operation.
73. "raw the circuit 7 input ".T.&. >#>" gate and e*plain its operation with the help
of truth-table. 8ow can you improve the an-out of the circuit. A*plain with the help of
modified circuit. BJNTU M,1 @6D @$A
76. i. "efine
i. %ositive logic ii. >egative logic iii. %ulse logic.
ii. ;hat is meant by #,I logic. A*plain with help of an e*ample. BJNTU
M,1 @>D M,1 @$A
77. i. :eali2e the given e*pression y O #! U C" using >-+os logic and verify it. ;hat
is the name of the given function and what is its advantageN
ii. Compare the relative merits of >+,-, C+,-, TT& and AC& logic families.
BJNTU S+&/ @6D M,1 @$A
7/. i. Compare different logic families and mention their advantages and disadvantagesN
ii. ;hich is the fastest non-saturated logic gateN "raw the circuit and e*plain its
functions. BJNTU M,1 @$A
7$. "raw the circuit of AC& logic ,:@>,: gate and e*plain its functions. BJNTU
S+&/ @6D M,1 @$A
7). or the given circuit e*plain its operation with the help of Truth Table. ind
hAmin, an-out if hAO71, and >oise-+argin for the given circuit shown below. '#ssume
all the active devices are made of silicon(.
7.. i. ;hat is meant by Tri-static logicN "raw the circuit of Tri-state TT& logic and
e*plain its functions.
ii. "raw the circuit of AC& logic ,:I>,: gate and e*plain its functions. BJNTU
D+( @#A
7=. A*plain the following with suitable circuit diagramsH
i. Totem-pole TT& gate
ii. AC& gate #re they called universal gatesN justify your answer. BJNTU
D+( @#A
7E. i. &ist out the advantages of C+,- logic.
ii. "raw the circuit of C+,- >,: gate and verify the !oolean function.
iii. ?ive the working principle of 36 & logic with neat circuit diagram. BJNTU
D+( @#A
/1. i. ;hen do we prefer 8.T.&. '8igh-Threshold &ogic( gateN #nd e*plain whyN
ii. "raw the Integrated circuit of 8.T.&. 7-input >#>" gate, and e*plain its
operation with the
help of Truth Table.
iii. ind out the average power dissipation of the gate. BJNTU F+3 @>D D+( @#A
/3. or the circuit shown belowH BJNTU N%; @#A
i. A*plain the operations and the circuit with the help of Truth-Table.
ii. If hA of Z3 is 71, find hAmin of Z6.
iii. If hA of Z6 is 71, what is an-,utN
iv. ind >oise +argins.
/6. i. ;hat is meant by ;ired-logic. A*plain with the help of an e*ample.
ii. ;hy TT& passive pull-up circuit is not suitable for capacitive loadsN A*plain.
BJNTU M,1 @#A
/7. "raw the circuit of an improved version of ".T.&. 7-input >and gate, and e*plain its
operations with the help of Truth Table. If hA of each transistor is /1, find #>-,IT of
the circuit. BJNTU M,1 @#A
//. i. "raw the circuit of a Totem-pole TT& >#>" gate N ;hat is the purpose of using
a diode at
the output stage N A*plain its operation and verify the truth table.
ii. ;hen do we use open-collector TT& gateN
iii. ;hich is the fastest logic gate and why N BJNTU F+3 @>D M,1 @#A
/$. i. ;hat are the desirable features of C+,- gatesN
ii. -ketch the circuit of C+,- >#>" gate and verify that it satisfies the !oolean >#>"
e<uation.
iii. "efine the following terms H
i. an-in,
ii. an-out,
iii. -tandard load,
iv. Current sink,
v. Current source BJNTU M,1 @#A
/). A*plain the following with suitable circuit diagramsH BJNTU M,1 @#A
i. Totem-pole TT& gate
ii. AC& gate #re they called universal gates N Fustify your answer.
/.. i. &ist in tabular form the fan out, power dissipation, propagation delay and noise
margin for the following digital IC logic families. TT& and AC&.
ii. A*plain with logic diagram and timing relationship of a master-slave flip flop and edge
triggered flip flop. BJNTU J,* @3A
/=. i. "efine the terms with respect to logic families fan out, power dissipation,
propagation delay
and noise margin. BJNTU J,* @3A
ii. A*plain open-collector output, totem pole output and tristate output with respect to TT&
logic.
/E. Compare the relative merits of TT& and AC& logic families. BJNTU J,* @3A
$1. i. ;ith the help of neat circuit diagram e*plain the operation of a "T& >#>" gate.
ii. &ist out the important properties of "T& circuit. BJNTU M,1 @3A
$3. i. &ist out the advantages, disadvantages and application of AC& logic.
ii. -how how the TT& and +,- gates can be interfaced with AC& gates BJNTU
M,1 @3A
$6. i. ;ith a neat sketch e*plain the operation of TT& >#>" gate.
ii. # two input >#>" gate has 4cc O U$4 and 3 G ohm load connected to its output.
Calculate the output voltage
i. ;hen both inputs are low
ii. ;hen both inputs are high BJNTU M,1 @3A
$7. i. "efine edge trigged flip flops
ii. "raw the circuit of edge traigged -: flip flop made up of by basic gates and e*plain the
operation. -ketch the waveform. BJNTU M,1 @3A
$/. i. ;hat are the draw backs of TT& gateN A*plain how they are overcome using
schottky
clampN
ii. Compare the various parameters of all TT& series >#>" gates. BJNTU M,1 @3A
$$. i. A*plain with an e*ample why asynchronous input are re<uired in flip flops.
ii. A*plain the operation of edge triggered T flip-flop. BJNTU M,1 @3A
$). ;hat do you understand by the team C:ace aroundD in FG flip flopN A*plain how
this is removed in a master-slave flip flop with the circuit diagram. BJNTU M,1 @3A
$.. "raw the cross section of a II& inverter and e*plain its function. BJNTU J,* @3A
$=. -how the interconnection diagram for a bistable latch in II&. BJNTU J,* @3A
$E. i. -ketch a 6 input ,: AC& gate what parameter determine the noise margin e*plain
why
power line spikes are virtually non e*istent. BJNTU J,* @3A
ii. &ist and discuss atleast four advantages and four disadvantages of the AC& gates.
)1. i. ;ith neat circuit e*plain the operation of TT& inverter.
ii. !riefly e*plain the different types of TT& gates. BJNTU M,1 @3A
)3. i. "efine the following terms H
'i( an-in 'ii( an-out 'iii( -tandard load ' iv( >oise-+argin.
ii. "raw the circuit of AC& ,:@>,: gate and e*plain its operations with the help of
Truth
Table.
iii. ;hat are the principal advantages of AC& logic '&ist out at least $ advantages(
BJNTU M,1 @3A
)6. ;rite short notes on the following gates H BJNTU M,1 @3A
i. TT&
ii. I6&
iii. AC&.
)7. # typical C+,- interval has the transfer characteristics '4TC( '41-4in(, as shown
in the fig.
!elow. Avaluate the value of the Inverter threshold, 4in*, which is the value of the input t
which 4o falls abruptly by "41O4Tn U Tp.
?iven bn O mnCo* ';@&(n O bp O mpCo* ';@&( p
4TnO34, 4TpO-34 and 4""O$4 BJNTU GATE ?#A
)/. ?iven an >+,- circuit as shown in ig. The specifications of the circuit areH
4""O3145 b O GOmnCo*';@&( O 31-/ #mp@ 46
4TO34 and I"- O 1.$ m#.
Avaluate 4"- and :" for the circuit. >eglect body 9 effect for 4T. BJNTU
GATE ?=A
)$. or the TT& circuit shown in ig. find the current through the collector of transistor
Z/ and 41 O 1.64. #ssume 4CA'sat(O1.6 4, b O 311 and 4!A'sat(O1..4. The a of Z3 in
its inverse active mode is 1.13 BJNTU GATE ?>A
)). or the C+,- monostable multivibrator of ig., :O$1 k;, CO1.13 m, 4""O$4,
and the C+,- >,: gates have a threshold voltage '4T( of 3.$ 4. vin is a trigger pulse
'tp__:C( as shown in the figure.
i. %lot v13 and v: as function of time.
ii. ;rite the e<uation for v:'t(, for t`1.
iii. ind the time period of the output pulse BJNTU GATE @@A
).. ;hat is wired logicN ;hat are the applications of open collector TT& gatesN or the
circuit shown, find e*pression of L. ;hat logical function is performed by the circuitN
BJNTU IES ?>A
)=. i. "raw the circuit diagram of a two input TT& >#>" gate and label component and
write
function table.
ii. "raw a typical input-output transfer characteristic of a TT& inverting gate.
iii. "efine fan out. ;hich factor is responsible for the limit of fan out in TT& circuits
iv. C&oading an output with more than its rated fan out has several effectsD. ;rite at
least five
effects BJNTU IES ?>A
UNIT-VII
3. a("raw the pin diagram of ./ series decoder IC and e*plain its functioning how the
boolean functions can be generated using decoders using e*ample
b(&ist out ./ series IC no. for code converters to translate !C" to seven segmented
display and !C" to ?ray scale ."raw the pin diagrams
6. 'a( "esign a 76 to 3 multiple*er using four ./P3$3 multiple*ers and ./P37E
decoder.
'b( :eali2e the following e*pression using ./P3$3 IC
f'L ( O #! U !C U #C 'jntu may 6136(
7 'a( ;ith the help of logic diagram e*plain ./b3$. multiple*er.
'b( "esign a full subtractor with logic gatesN
Ising the above subtractor design a =-bit ripple subtractor.
'jntu dec 6133(
/. 'a( Ising two ./b37= decoders design a / to 3) decoderN
'b( :eali2e the following e*pression using ./b3$3 ICN
f '0( O #!C U #!C U #! C

'jntu dec 6133(
$. 'a( ?ive the logic diagram of ./b37EN A*plain with the help of truth tableN
Ising this device design a 7 to = decoder and provide the truth tableN
'b( "esign a 3)-bit comparator using ./b=$ ICsN
'jntu dec 6133(
). 'a( ;hat is the need for a parity checkerN
'b( "esign an odd parity generator, for an = bit binary words .
.. Implement the following functions using a multiple*er.
'a( '#,!,C( O
m'3,7,$,)(
'b( '#,!,C( O
m'1,3,7,/,=,E,3$(
=. 'a( A*plain parity generator and parity checkerN
'b( "esign a digital comparator for 6-bit numbersN
E. ;ith the help of logic circuits e*plain a +ultiple*er and a "emultiple*er also give
their circuit symbols and give their applicationsN
31. "esign = - bit adder using ./=6 . BJNTU A&08M,1 @@?A
33. "esign and e*plain the following BJNTU A&08M,1 @@?A
'a( !asic comparator operation
'b( &ogic diagram for comparison of 6- bit binary numbers.
36. A*plain "ecimal - to - !C" priority Ancoder. BJNTU A&08M,1 @@?A
37. 'a( A*plain "ecimal to !C" Ancoder BJNTU A&08M,1 @@?A
'b( A*plain application of an encoder using a keyboard encoder
3/. 'a( ;rite short notes on n- !it parallel adder.
'b( "esign a driver circuit for &C" display. BJNTU M,1 @>A
3$. 'a( "esign the combinational circuit for common cathode . segment display@driverN
'b( ;rite short notes on gray code to !inary converter BJNTU M,1 @>A
3). i. "esign a serial binary adderN
ii. "esignafull subtractor with logic gatesN BJNTU A.9 @=A
3.. i. ;hat is multiple*erN "raw the logic diagram of / to 3 line multiple*erN
ii. "esign half adder using >#>" gates onlyN BJNTU M,1 @>D A.9 @=A
3=. i. ;hat is the necessity of tri state bufferN
ii. "esign a 3)-bit comparator using ./b=$ ICsN BJNTU A.9 @=A
3E. i. "raw the circuit for 7 to = decoder and e*plainN
ii. ;rite short notesonhalf adderN BJNTU A&0 @=A
61. i. "esign 3H= "emultiple*er using two 3H/ "emultiple*erN
ii. :eali2e the followinge*pression using ./* 3$3 ICs and./* 37E IC
F( Z) = ABCD U ABCD U ABCD U ABDE U ACDE U ABCE U ABCD BJNTU
M,1 @>D A&0 @=A
63. i. "esign a 7 input $-bit multiple*erN ;rite the truth table and draw the logic
diagram.
ii. ;rite short notesonfull subtractor. BJNTU A&0 @=A
UNIT-VIII
3. "esign 7-bit synchronous counter using FG lip lop'JNTU NOV8DEC 1A
2. (a) Design a modulo-+ binary counter and decoder with glitch-free
outputs. ,-
plain the operation.
(b) Design a modulo-*)) counter using two -."*/0 binary counters.((ntu
may *2)
7. 'a( "esign a conversion circuit to convert a T flip-flop to F-G flip-flopN
'b( ;rite short notes onH
i. Adge triggered flip-flop
+aster slave flip flop.
'jntu dec 6133(
/. 'a( "esign a /-bit binary synchronous counter using ./b./.
'b( "esign a modulo-)1 counter using ./b3)7 ICs.
'jntu dec 6133(
$. 'a( "esign a 7-bit &-: counter using ./b3E/N &ist out the se<uence assuming
that the initial state is 31.
'b( "esign a +odulo-36 ripple counter using ./b./.
'jntu dec 6133(
). 'a( "raw the " flip flop and T flip flop and e*plain the operation with truth table.
'b( "raw the F-G flip-flop and e*plain its operation with truth table.
'jntu dec 6133(
.. 'a( ;rite short notes on the followingH
'i( &evel triggering.
'ii( Adge triggering.
'iii( %ulse triggering .
'b( A*plain the functioning of :- flip-flop using >#>" gates.
=. 'a( ;ith neat circuit diagram e*plain a master-slave lip-flop and also draw the
timing diagram
'b( A*plain about asynchronous lip lops.
E. 'a( ;hat is the major difference between digital and analog %&&sN
'b( A*plain the fre<uency multiplier using IC %&&. BJNTU A&08M,1 @@?A
31. A*plain ./3E/ four bit bidirectional universal shift register with block diagram and
timing diagram. . BJNTU A&08M,1 @@?A
33. A*pand 76G 0 3 :#+s to form 76G 0 / :#+ . BJNTU A&08M,1 @@?A
36. 'a( ind a modulo-) gray code using k-+ap & design the corresponding counter.
'b( Compare synchronous & #synchronous. BJNTU A&08M,1 @@?A
37. 'a( A*plain with an e*ample why asynchronous inputs are re<uired in flip flops.
'b( A*plain the operation of edge triggered T flip- flop BJNTU M,1 @>A
3/. 'a( "raw the schematic circuit diagram of / bits -uccessive #ppro*imations #@"
converter and e*plain its operation.
'b( Compare this #@" converter with parallel comparator type #@" converter.
'c( ?ive the working principle of analog multiple*er. BJNTU M,1 @>D F+3
@>A
3$. 'a( Compare different #@" converters for their merits and demerits.
'b( ?ive the schematic circuit diagram of a successive appro*imation type #@"
converter and
e*plain the operations of this system. BJNTU M,1 @>A
3). 'a( "istinguish between Combinational circuits and se<uential circuits.
'b( ;rite short notes on Clocked -: flip flop. BJNTU M,1 @>A
3.. 'a( A*plain with the help of neat diagram the simple structure of +,- :,+.
'b( "esign +," $ synchronous counter. BJNTU M,1 @>A
3=. 'a( ;hat is a sample-and-hold circuitN "raw the circuit diagram and e*plain its
actionN
'b( ;ith reference to sample and hold circuit define the following terms
i. #perture time
ii. 8old mode.
'c( "raw the circuit of ;eighted :esistor "#C and derive e*pression for output analog
voltage 4o. BJNTU F+3 @>A
3E. 'a( "efine the following terms as related to "#C
i. #ccuracy
ii. :esolution.
'b( "efine the following terms as related to #"C
i. Conversion time
ii. %ercentage resolution.
'c( ;hich type of "#C is more preferableN "raw the circuit diagram and obtain e*pression
for output voltage for / bits BJNTU F+3 @>A
61. i. "istinguish between combinational and se<uential circuit.
ii. "efine the following terms as applied to flip flops.
i. -et up time.
ii. 8old time.
iii. %ropagation delay.
iv. +a*imum clock fre<uency.
v. %ower dissipation. BJNTU M,1 @>D.A.9 @=A
63. i. ;rite a note on applications, advantages and disadvantages of -:#+.
ii. "esign +,")synchronous counter. BJNTU A.9 @=A
66. i. A*plain / bit serial in parallel out register.
ii. "raw the circuit of edge trigged -: flip flop made up of by basic gates & e*plain the
operation. -ketch the wave form. BJNTU A.9 @=A
67. i. ;rite short notes on synchronous up counter.
ii. A*plain the operation of -ynchronous -:#+ with the help of its internal
#rchitecture. BJNTU A.9 @=A
6/. i. "esign a conversion circuit to convert a " flip-flop to F-G flip-flopN
ii. "esign a /-bit binary synchronous counter using ./b./N BJNTU A&0 @=A
6$. i. "iscuss in detail :,+ access mechanism with the help of timing waveformsN
ii. ;rite short noteson Clocked Tflipflop. BJNTU A&0 @=A
6). i. ;rite short notes on serial in parallel out shift register.
ii. "esign a conversion circuit to convert a " flip-flop to T flip-flopN BJNTU
A&0 @=A

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