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Synchronization, islanding detection and power flow control

1. Background
After converting the input voltage from the bike generator in to AC voltage, the
inverter should maintain some requirements so that it can supply power to the utility grid. The
requirements are:
1. The amplitude of the output voltage of the inverter should be the same as the
amplitude of the grid voltage.
2. The frequency of the inverter should be the same as the grid frequency.
3. The phase of the inverter should match the phase of the grid.
If the above requirements are full filled the inverter is said to be synchronized with the system.
The other important thing is to control the power flow from the inverter to the grid. The best
way to control a power flow is by adjusting the phase difference between the inverter
waveform and the grid waveform. In order to understand this concept an equivalent circuit of
inverter-grid transmission line model is given as follow:






and

are the output voltage of the inverter and the grid respectively. Z is the total
impedance of the power line between the inverter and the grid. The phasor diagram of the line
power model is shown in figure x. The apparent, active and the reactive power injected to the
grid power exported from the inverter to the grid are given as follow:

=

sin ()

cos ()


The above equations show that the active power flow can be controlled by adjusting the phase
angle between the inverter and the grid voltage. Since power line is purely inductive (X >>R),
the resistance can be neglected. The maximum power flow occurs when =90 but in practice
a small angle is used to keep the system stable from transient and dynamic oscillation. During
synchronization process this phase angle can be adjusted to supply the required amount of
power.
Z
Inverter side Grid side




The other important requirement is islanding detection. Islanding refers to a condition in
which a grid tie inverter continues to power a location even though electrical power from the
utility grid is no longer present. Islanding condition is not desirable since it can feed power
back to utility location and this can cause personal and equipments damage. Hence the grid
tie inverter must detect islanding condition with in specific period of time and perform the
necessary tasks. According to the report done by IEA (international energy agency), the IEA
countries have their own standards towards islanding. The following table shows the limit of
detection of islanding operation in IEA countries:






According to the above table the voltage and the frequency range in Netherland are 215-240V
and 48-52Hz respectively. If the grid voltage is out of this range the inverter must be
disconnected from the grid within 0.2 second. The inverter also must be disconnected from
the grid within 2 second if the grid frequency is out of the specified range.
In order to fulfill these requirements, the amplitude, frequency and phase of the grid voltage
must be measured continuously. In the following sub section the proposed method to achieve
this goal will be discussed.
2. Proposed method:
The following block diagram shows the proposed method in order to extract the grid
parameters (amplitude, frequency and phase) and perform synchronization as well as islanding
detection.










Country Voltage range Frequency range Disconnect within
Australia 200V-270V 48-52Hz -
Austria 230V,+10%,-15% 50Hz0.2 0.2s/ 0.2s
Denmark 230V,+10%,-15% 48-51Hz 1.5s/ 0.5s
Germany 230V,+10%,-15% 50Hz0.2 0.2s/ 0.2s
Italy 230V,+20%,-20% 50Hz1.0 0.1s/ 0.1s
Netherland 230V,+6%,-20% 50Hz2 0.1s/ 2s
Switzerland 230V,+10%,-10% 50Hz1.0 -
The UK 230V,+10%,-10% 44-51Hz 0.5s/ 0.5s
T
r
a
n
s
f
o
r
m
e
r

ISR

ZCD
r
Sine wave
table
SPLL
Algorithm
The 230VAC of the grid is stepped down in to 5VAC using a transformer. The output of the
transformer is fed to both the zero crossing detector. The zero crossing detector is used to
detect when grid voltage cross a zero voltage. Its output is a square wave. This information is
used to measure both the frequency and phase of the grid voltage. The rising edge of this
square wave trigs an interrupt service routine in the microcontroller. When this interrupt
occurs the SPLL (software phase locked loop) algorithm will be executed. Depending on the
output of the SPLL algorithm the sine wave table is adjusted. Based on the sine wave table a
PWM is generated in order to control the inverter.
3. Software phase locked loop (SPLL)
A phase locked loop is an efficient way of synchronizing the inverter output with grid. In this
project a software based PLL is used. The following block diagram shows the basic elements of
SPLL.







As shown in the figure the SPLL is a closed loop system. It consists of phase detector, a PI
controller and an integrator. The phase detector detects the phase difference between the
grid (

) and the inveter (

) and produces a phase error (). The PI controller receive


the phase error from the phase detector and produces a frequency changes (). If the
inverter signal is lagging behind the grid signal become positive value and the PI controller
produces positive . This will be added to the center frequency (

) to speed up the
frequency of the inverter. If the inverter signal is leading the grid signal become negative
value and the PI controller produces negative . This will be added to the frequency (

) to
slow down the frequency of the inverter. If the inverter signal is in phase with the grid the
will be zero and the SPLL remain locked. The frequency of the inveter is feed to the integrator
to extract the phase angel. The following table summarize the concept:
Condition



Grid is lagging >0

+

Grid is leading <0



Grid is in phase =0



N:B

Phase
detector
PI
controller


Implementation of the SPLL in the microcontroller.
In SPLL implementing the phase detector and the PI controller is challenging. In order to measure
the phase difference between the grid and the inverter both the phase of the grid and the inverter
must be measured. The sine wave look up table generated in the microcontroller and the zero cross
detector plays an important role in detecting the phase difference. The following block diagram
shows how the SPLL is implemented in the microcontroller.









The output of the zero cross detector is connected with external interrupt pin of a microcontroller.
Whenever a rising edge of the zero cross detector is detected an interrupt service routine will be
executed. The interrupt service routine consists of the phase detector algorithm and PI controller
algorithm. When the interrupt occurs the phase detector algorithm extract the phase of the inverter
from the sine wave lookup table. The interrupt occurs when the phase of the grid is zero. Hence the
phase of the grid is all the time zero. So the phase difference is the current value from the look up
table minus zero. This value is then feed to the PI controller algorithm.
The PI controller
Depending on the phase error the PI controller determines the change in frequency to be added or
subtracted from the center frequency (50HZ). The P term of the controller decreases the rising time
of the system. This allows the output to follow the input (the reference) faster. The integral term of
the controller is used to reduce a steady state error. In order to determine the parameters of the PI
controller, it is necessary to see the mathematical model of the system.
Mathematical model of SPLL






ZCD
External
interrupt
Pin
Microcontroller
Algorithm
Phase detector
Algorithm
PI algorithm
Sine wave look up
table
ISR
+

( +


-
The functional diagram of the SPLL is shown in the figure x. The transfer function of the closed loop
is given as follow:
H(s) =

()

()
=
K
p
(1 +
1

)
1
s
1 +K
p
(1 +
1

)
1
s

H(s) =
K
p
s +
K
p

2
+ K
p
s +
K
p



Comparing the closed loop transfer function of the SPLL with general second ordered transfer
function, the natural frequency and the damping ratio of the system are given as follow

=
K
p

4 =

K
p

4
5
One way of estimating the parameters (K
p
and

) of the PI controller is by estimating the overshoot


percentage () and the settling time (t
s
) of the system. The sampling time of the system is 20ms. Therefore
the settling time must be smaller than the sampling time. Let say out the system settles after 10ms with 5%
overshoot.

(2%) =
4

6
=

1
2
100 7
From equation 7
=
ln (D%/100)

2
+ ln
2
%/100)

=
ln (5%/100)

2
+ ln
2
5%/100)
= 0.69 0.7
From equation 6

=
4

(2%)
=
4
0.7 10
= 571
From equation 5

=
4
2
K
p
=
1.96
K
p
8
From equation 4
K
p
=

8
K
p
=
1.96
K
p

2

K
p
2
= 1.96

2

K
p
= 1.96

2
= 1.96(571)
2
= 799

=
1.96
799
= 0.00245
H(s) =

2
+ 2

s +

2


Where:

(2%) is the time required for the transient damped oscillation to reach and
stay within 2% of the steady-state value.

Where: D is the overshoot in percentage


Modeling in MATLAB
After calculating the parameters of the PI controller mathematically, it is necessary to see how the system
responds to different value of K
p
and Ti using a MATLAB Simulink. The following figure shows the closed loop
of the SPLL in MATLAB Simulink.






In order to see how the proportional and the integral gain influence the system five cases are
selected as shown in the table.
Case Condition K
p


Case 1 Normal 799 0.00245
Case 2 Only

increased 799 0.0024+30%


Case 3 Only

decreased 799 0.0024-30%


Case 4 Only K
p
increased 799+30% 0.0024
Case 5 Only K
p
decreased 799-30% 0.0024

To see the effect of the integral part, only Ti is increased and decreased by 30% from the normal
value. The same thing is done to see the effect of the proportional term K
p
. The result of the Simulink
is shown in figure x. A closer look at the figure shows that increasing both the value of K
p
and Ti
decreases the overshoot. Increasing Ti or decreasing K
p
. Causes the settling time to increase.
Decreasing the value of Ti increases the overshoot. In general keeping the value of Ti at 0.0024 and
increasing the value of K
p
will lead us to a good stability. We can see for example the system is more
stable at Ti =0.0024 and K
p
=799+30%.









P

I

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