vii)

Course Code:
ECE301
Title: VLSI SYSTEM DESIGN L T P C
3 0 0 3
Version No. 1.1
Course
Prerequisites
Digital Logic Design, Electron Devices and Circuits
Objectives
To illustrate the basic concepts of modern VLSI circuit design.
Describe the fundamental principles underlying digital design using CMOS logic
and analyze the performance characteristics of these digital circuits.
Discuss the basic concepts of Verilog HDL and use it to describe combinational
and sequential circuits HDL at different abstraction levels.
Design the synthesizable digital sub-system components using Verilog HDL.
Verify that a design meets its functionality, timing constraints, both manually and
through the use of computer-aided design tools.
Develop problem-solving skills in order to be able to successfully approach a
digital design project of medium to high complexity in the final semester.

Expected
Outcome
The students shall be able to:
apply knowledge of mathematics, science, and engineering in the design, and
analysis and modeling of digital integrated circuits.
design and analyze the performance (Speed, Power) of CMOS digital integrated
circuits for different design specifications.
identify and interpret the design towards realizing digital IC design.
describe digital design using a hardware description language.
design and conduct experiments in digital design using Verilog HDL and able to
illustrate the outcome of the design.
use modern EDA tools to simulate and synthesize the digital designs.

Unit No. Unit Title Number of
hours (per
Unit)
Unit 1
CMOS LOGIC DESIGN
Introduction to VLSI Design. MOS Transistor Theory: nMOS,
pMOS Enhancement Transistor, ideal I-V characteristics, C-V
characteristics, Non-ideal I-V effects. CMOS logic: Basic gates,
Complex Gates, Multiplexer and Flip-flop.

10
Unit 2 CIRCUIT CHARACTERIZATION AND PERFORMANCE
ESTIMATION
DC transfer Characteristics of CMOS inverter, Circuit
characterization and performance estimation: Delay estimation,
Logical effort and Transistor Sizing. Power Dissipation: Static &
Dynamic Power Dissipation.

10
Proceedings of the Standing Committee of the Academic Council of VIT [7.8.2010]
Unit 3 VERILOG HDL BASICS
Overview of Digital Design with Verilog HDL. Hierarchical Modeling
Concepts. Basic Concepts of Verilog HDL: Lexical conventions, data
types. Modules and Ports. Gate level Modeling. Dataflow Modeling:
Continuous Assignment, Delays, Operators. Behavioral Modeling:
Procedural Assignments, Conditional Statements. Writing a test bench
for the design.

10
Unit 4 DIGITAL SYSTEM DESIGN USING VERILOG HDL
Design of Combinational and Sequential Circuits using Verilog HDL.
Logic Synthesis with Verilog HDL. ALU sub-system components
design: Adders, Multipliers, Shift registers, and Memory units.

10
Unit 5 INTRODUCTION TO TIMING ANALYSIS
Introduction to Static timing analysis. Setup Time, Hold Time.
Calculation of critical path, slack, setup and hold time violations.

5
Text Books
1. Neil H Weste, Harris, A Banerjee, CMOS VLSI Design, 3/e, Pearson Education,
Singapore, 2006.
2. Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, PHI, Second
Edition,2003.

Reference
Books
1. Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, Digital Integrated Circuits: A
Design Perspective, Prentice Hall India, 2nd Ed, 2002.
2. S. Ramachandran, Digital VLSI Systems Design, Springer, 2007
3. John P.Uyemura, CMOS Logic Circuit Design , Springer International Edition.2005

Mode of
Evaluation
CAT- I & II , Quiz, Lab based Assignments/Mini-project, Term End Examination
Recommended
by the Board of
Studies on
02/08/2010
Date of
approval by the
Academic
Council











Proceedings of the Standing Committee of the Academic Council of VIT [7.8.2010]