Paul Rajani Lassen E2DSD 19-05-2014

Exercises 5-8
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Contents
Contents ........................................................................................................................................................ 1
Exercise 5 ........................................................................................................................................................... 2
Process Statements ....................................................................................................................................... 2
Question 1 ................................................................................................................................................. 2
Question 2 ................................................................................................................................................. 2
Question 3 ................................................................................................................................................. 3
Question 4 ................................................................................................................................................. 4
Binary to 7-segment hexadecimal with case statement. ........................................................................... 5
Question 1 ................................................................................................................................................. 5
Question 2 ................................................................................................................................................. 6
Guess a Hex Number Game. .......................................................................................................................... 6
Question 1 ................................................................................................................................................. 6
Question 2 ................................................................................................................................................. 8
Question 3 ................................................................................................................................................. 9
8 input NAND using the for loop .............................................................................................................. 11
Question 1 ............................................................................................................................................... 11
Count 1 using the for loop ...................................................................................................................... 11
Question 1 ............................................................................................................................................... 11
Exercise 6 ......................................................................................................................................................... 13
Counter one digit. ..................................................................................................................................... 13
Question 1 ............................................................................................................................................... 13
Watch six digits. ........................................................................................................................................ 14
Question 1 ............................................................................................................................................... 14
Question 2 ............................................................................................................................................... 15
Question 3 ............................................................................................................................................... 16
Alarm Watch ................................................................................................................................................ 17
Question 1 ................................................................................................................................................... 17
Exercise 7 ......................................................................................................................................................... 19
MeeMoo State Machine .............................................................................................................................. 19
Question 1 ............................................................................................................................................... 19

Paul Rajani Lassen E2DSD 19-05-2014
Exercises 5-8
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Exercise 5
Process Statements
Question 1
Write a behavioural style description of the logic circuit below. The description must have a
separate process corresponding to each gate in the logic diagram. Each process must consist
of a single sequential signal assignment statement.


Figure1ThelogiccircuittobecodedinVHDL
One process was used per gate (ag for the and gate and og for the or gate).

Figure2VHDLcodeforthelogiccircuitinFigure1
Question 2
Perform a functional simulation to verify the correctness of the design.
Paul Rajani Lassen E2DSD 19-05-2014
Exercises 5-8
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Figure3FunctionalSimulationofthelogiccircuitfromFigure1
The functional simulation agrees with the logic circuit.
Question 3
Given the truth table below, write a component that accomplishes the function defined by
the truth table below. Use a behavioural style architecture that consists of two processes, one
to assign a value to x and the other to assign a value to y.

Figure4TruthTabletobecodedinVHDL
Paul Rajani Lassen E2DSD 19-05-2014
Exercises 5-8
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Figure5VHDLcodeforthetruthtableinFigure4

Question 4
Perform a functional simulation to verify the correctness of the design.

Figure6TheFunctionalsimulationofthecodefromFigure5mirrorsthetruthtableofFigure4




Paul Rajani Lassen E2DSD 19-05-2014
Exercises 5-8
5
Binary to 7-segment hexadecimal with case statement.
Question 1
Design a Binary to 7-segment hexadecimal converter using the case statement. The bit
pattern for 0-9 is practically the same as in exercise 4 with the exception of the number 6
which should be changed so it does not look like the letter b. Add the A-F letters, of you
own design, to the converter.

Figure7Binaryto7-segmenthexadecimalconverterVHDLcode
Paul Rajani Lassen E2DSD 19-05-2014
Exercises 5-8
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Question 2

With all of the switches set (1111) the 7-segment display displays F
Guess a Hex Number Game.
The guess game is basically a game, where the player should guess a target number. After the
player trys out a guess, the player gets information about if the guess is right or lower/higher than
the target number. Because we have not learned about registers we can not count how many turns
have been used to guess the numbers (next lecture stuff). Furthermore we are still not able to
generate a random number, so we will have to set the target number manually.
Question 1
Design a guess game with the following functionality.
1.) When no key is asserted, the corresponding input number is shown on the 7-segments.
2.) When set is asserted the current input number is stored as the target number to be guessed
3.) When show is asserted the stored target number is shown on the 7 segments
4.) When try is asserted the guess is evaluated and Lo, Hi or is displayed depending
on if the guess is: higher, lower or equal to the target number.
Paul Rajani Lassen E2DSD 19-05-2014
Exercises 5-8
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Figure 8 VHDL code for the guess game

Paul Rajani Lassen E2DSD 19-05-2014
Exercises 5-8
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Question 2
Download and test the design on the DE2 board, are any latches generated in the RTL
viewer? If so - why?


The images above show a user choosing a value (fa) setting it, making sure that it is set (--) and then trying
to check a value higher than fa.
Paul Rajani Lassen E2DSD 19-05-2014
Exercises 5-8
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There are 19 latches. This is due to having many places in the code where information is temporarily stored.

Figure 9 RTL diagram of the Guess game
Question 3
Extend the design to at two-player game with two instances of the GuessGame(meaning
dont change GuessGame) plus some additional behavioural code. Download and test the
design on the DE2 board using SW[17] to switch back and forth between player 1 and
player 2 and display the current player number on HEX3.
Paul Rajani Lassen E2DSD 19-05-2014
Exercises 5-8
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Figure 10 VHDL code for the 2 player guessing game.


In the above image, the 2 on the left indicates that it is player 2 currently playing. The CF indicate the
current state of the switches.
Paul Rajani Lassen E2DSD 19-05-2014
Exercises 5-8
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8 input NAND using the for loop
Question 1
Write a behavioural style component that uses a for loop to describe an eight-input NAND gate,
illustrated below. Perform a functional simulation to verify the correctness of the design.

Figure 11 VHDL code for the NAND gate using a for loop

Figure 12 Functional Simulation of the NAND gate
To do a full functional simulation there would be 256 values for input. Quartas Simulation Waveform
Editor is too messy for that, so 9 rather arbitrary values were chosen, while the last one was deliberately
chosen because it is the one case where the NAND gate is supposed to change its state.
Count 1 using the for loop
Question 1
Write a behavioural style component that uses a for loop to count the number of 1
occurring at the input and display it on the 7-segment output. Download and test the design
on the DE2 board
Paul Rajani Lassen E2DSD 19-05-2014
Exercises 5-8
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Figure 13 VHDL code for the '1' counter

The 8 sensitive switches were set alternating between high and low, 4 up and 4 down.


Paul Rajani Lassen E2DSD 19-05-2014
Exercises 5-8
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Exercise 6
Counter one digit.
Question 1
Design a binary circular counter (returns to zero after reaching maximum value) that
increments every positive edge of the CLK. Display the current counter value on the 7-
segment display. Use the 7-segment decoder component from former exercises.

Figure 14 VHDL code for the counter
Paul Rajani Lassen E2DSD 19-05-2014
Exercises 5-8
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After counting up to the maximum the counter resets and sets COUT high.

After one button press, the counter increments, COUT is set to low and BIN_VAL is set to 0001, which
due to a pin assignment error appears mirrored.
Watch six digits.
Question 1
Design a new component called watch containing a clockGen component that generates a
one clock width pulse. The pulse is generated every second when SPEED is 1 and every 5
milliseconds when SPEED is 0. Connect the CLK_OUT output of the clockGen to the
CLK input of the multiCounter component. CLOCK_50 is found in the pin assignment and
is a 50 MHz 50% duty cycle clock. /RESET must be an active low asynchronous reset.
HI NT: use a variable integer type in the clockGen component for the counter and set
CLK_OUT high every time the counter reaches 50.000.000 - otherwise the CLK_OUT
should be set to low.

Paul Rajani Lassen E2DSD 19-05-2014
Exercises 5-8
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Figure 15 VHDL code for the clockGen component

Figure 16 Architecture of the 'Watch' entity. Note that the CLK_OUT from clockGen goes directly into the CLK of the One digit
counter, via the signal i_clk
Question 2
Download and test the design on the DE2 board
The DE2 board counts once per second, respecting the maximums from the one digit count in all
modes.
Paul Rajani Lassen E2DSD 19-05-2014
Exercises 5-8
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Question 3
Extend the design with 6 cascade coupled instances of the multiCounter component, so it
will end up as a 6 digit 24 hours clock (eg.. ::). Refer to the drawing on the next page
for design inspiration. Use the BI N_VAL, from the hour counters, output to RESET all
counters to :: when they hits . Leave the rest of BI N_VAL unconnected. This can
be done by using the open keyword in the port mapping (eg. BIN_VAL => open).

Figure 17 VHDL Code for the 24 Hour Watch. It is made up of 6 chained One digit counters and a clockGen

This clock ticks once a second and goes from 00:00:00 until 23:59:59 after which the time is reset to
00:00:00
Paul Rajani Lassen E2DSD 19-05-2014
Exercises 5-8
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Alarm Watch
Question 1
Extend the watch component with an alarm feature with a one minute resolution (meaning:
only hours and minutes can be set). Use the BI N_VAL output from the counters to detect an
alarm.

Although these two images look as though they were taken 22 seconds apart, they were in fact taken
only seconds apart. The upper image shows what the alarm was set to, while the lower image shows
the time. Note the red ALARM! light.
Paul Rajani Lassen E2DSD 19-05-2014
Exercises 5-8
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Figure 18 VHDL code for the Alarm Watch
Paul Rajani Lassen E2DSD 19-05-2014
Exercises 5-8
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Exercise 7
MeeMoo State Machine
Question 1
Implement the state-diagram for the MeeMoo state machine illustrated below using the three process
template in the book. The diagram has both Moore and Mealy outputs with conditional and
unconditional transitions. In other words: if you can solve this exercise you will actually be able to
implement VHDL code for both state machine types.

Figure 19 VHDL code for the MeeMoo state machine, utilising the three process template
Paul Rajani Lassen E2DSD 19-05-2014
Exercises 5-8
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Question 2


Figure 20 Functional Simulation of the MeeMoo state machine
Notice that with the exception of an asynchronous reset the Moore output only changes at the positive
edge of the next clock, regardless of changing inputs. The Mealy outputs can change within a clock cycle, if
the input changes before the next clock cycle. This can also be easily demonstrated by getting to the init
state and flipping SW[1] while SW[0] is high. (No pictures were added because there is not much to see on
the DE2 board in this case.

Code Lock
The code lock accepts a sequence of three correct codes, each followed by an enter press, to let the
lock output change from locked (1) to unlocked (0). The code lock remains unlocked until enter
is pressed again. Three wrongly entered codes will lock the code lock permanently until reset is
asserted.
In solving the exercise you must explain in text how the listed SysML terms correspond to
Moore/Mealy terms and explain how they can be implemented in VHDL using snippets from your code:
SysML triggers, guards and effects (no effects in exercise)
SysML do actions
SysML entry actions (err_cnt++ in Wrong Code)
SysML exit action (None in the exercise)

Note that entry- and exit actions are properties of a state, but can also be interpreted as common
effects on the in- and outgoing transitions.

Paul Rajani Lassen E2DSD 19-05-2014
Exercises 5-8
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Paul Rajani Lassen E2DSD 19-05-2014
Exercises 5-8
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Figure 21 VHDL Code for CodeLock
Even though this code resembles a Moore state machine, there are many elements of SysML state
machines. To change from state to state in SysML there need to be triggers, guards and (to a lesser extent
effects). There are triggers and guards in this Moore state machine, just under different names. In this case
Paul Rajani Lassen E2DSD 19-05-2014
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the trigger is a key press. For Mealy and Moore state machines these are simply called inputs. The guards in
SysML are simply achieved here by if and when statements. Although there are no effects in this exercise
they do also occur in Mealy diagrams, as the output. In that case the trigger is usually a change of the
inputs and the effect is an immediate change in the output (and possibly a state change.
Do actions in SysML are what occur within a state. These are simplest in Moore diagrams, where the do
statement is the output, as seen in lines 82-90.
Entry actions in SysML occur as a new state is entered into. Lines 61and 62 are examples of this. As w state
wrongCode is entered into, err_cnt is incrementally increased, but only on entry, not passively while
waiting within wrongCode. That would be a do action.
An exit action is very similar to an entry action, but, as its name suggests, it happens as a state is left.
Exercise 8
A simple procedure and function
Question 1 and 2
Design the component illustrated below and download it on the DE2 board.
Make the procedures and functions visible for all components in the project by
encapsulating the functions and procedures into a package. Download and test the new
design on the DE2 board.


Figure 22 A Package containg an xor function and an and/or procedure
Paul Rajani Lassen E2DSD 19-05-2014
Exercises 5-8
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Figure 23 The "Main" program or top level entity

On the left SW[1] (b) and SW[0](a) are both high on the right SW[1] is high and SW[2] is low.
LEDR0 = a xor b
LEDR1 = a and b
LEDR2 = a or b

The Italian flag on VGA
I was unable to test this due to time constraints and poor management on my part, but I went as far as I
could without a monitor including the reverse engineering and creating the sync generator class.
Question 1
Reverse engineer the template project and make sure you understand how the template
works. Write a brief description in your documentation. You can read about VGA in the
DE2 user manual page 38-39.
Paul Rajani Lassen E2DSD 19-05-2014
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The Template starts by declaring the entity and the incoming and outgoing signals. It goes on to
define many constants which have to do with screen size and synchronization. This is done for both
horizontal and vertical.
It goes on to define one process for halving the clock frequency and two more, one for horizontal
sync and one for vertical sync, before trying to draw out green white and red stripes, vertically
down the screen.
Question 2

Looking at the declarations made at the beginning of the architecture, we can see that most are natural
constants, while syncOut and blankout are outgoing.