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EE241 - Spring 2004

Advanced Digital Integrated Circuits
Borivoje Nikoli
Lecture 21
Timing
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Announcements
Homework #4 due next Tuesday
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Overview
Synchronization Approaches
Synchronous Systems
Timing methodologies
Latching elements
Clock distribution
Clock generation
Asynchronous Systems
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References
Chapter 11 Clocked storage elements, by H. Partovi
High-speed CMOS design styles, Bernstein, et al,
Kluwer 1998.
Unger/Tan IEEE Trans. Comp. 10/86
Harris/Horowitz JSSC 11/97
Messerschmitt JSAC 10/90
Stojanovi/Oklobdija JSSC 4/99
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Issues in Timing
D. Messerschmitt, Oct 1990
Boolean signal - stream of 0s and 1s, generated by saturating
circuits and bistable memory elements
but
finite rise and fall times inter-symbol interference
metastability leads to non-deterministic behavior
signal transitions are crucial
typically defined with respect to slicer/sampler
associated clock with uniformly spaced transitions
0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
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Boolean signal Boolean signal
Isochronous
f + f = constant
Anisochronous
f + f constant
Single Single
Clock signal :
f + f average frequency
d/dt instantaneous frequency deviation
Issues in Timing
equal
not equal
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Issues in Timing
Synchronous
f + f identical
(t) = 0 (or known)
Asynchronous
Mesochronous
(t) variable
(but bounded)
Plesiochronous
Average Frequency
almost the same
Heterochronous
Nominally
Different freq
together
not together
near
middle
different
Two Boolean Signals Two Boolean Signals
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Some Definitions
Signals that can only transition at predetermined times with
respect to a signal clock are called
{syn,meso,plesio}chronous
An asynchronous signal can transition at any arbitrary
time.
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Some Definitions (contd)
Synchronous Signal: exactly the same frequency as local clock, and
fixed phase offset to that clock.
Mesochronous Signal: exactly the same frequency as local clock,
but unknown phase offset.
Plesiochronous Signal: frequency nominally the same as local clock,
but slightly different
Mesochronous and plesiochronous concepts are very useful for the
design of systems with long interconnections, and/or multiple
clock domains
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Mesochronous Interconnect
clock
synchronous
island
Data synchronous
island
Phase Generator
Select
Phase
Detect
Data
R1 R2
Clock
Local Synchronization
samples in certainty
period of signal
(local)
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Mesochronous Communication
R
1
Interconnect
R
2
Clk
A
D
2
Block A
Delay
Block B
Clk
B
D
4
Control
D
1
D3
Variable
Delay Line
Timing Recovery
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Plesiochronous Communication
Originating
Receiving
FIFO
Timing
Clock C
1
Clock C
2
Module
Module
Recovery
C
3
Does only marginally deal with fast variations in data delay
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Anisochronous Interconnect
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Synchronous Pipelined Datapath
In
t
pd,reg
t
pd1
D
R1
Q
CLK
Logic
Block #1
t
pd2
D
R2
Q
Logic
Block #2
t
pd3
D
R3
Q D
R4
Q
Logic
Block #3
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Latch versus Flip-Flop
Lat ch
st or es dat a when
cl ock i s l ow (hi gh)
D
Cl k
Q
D
Cl k
Q
Flip-Flop (or Register)
stores data when
clock rises (falls)
Cl k Cl k
D
D
Q Q
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Latch Parameters
D
Cl k
Q
D
Q
Cl k
T
Clk-Q
T
H
PW
m
T
SU
T
D-Q
Delays can be different for rising and falling data transitions
Unger and Tan
Trans. on Comp.
10/86
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Flip-Flop (Register) Parameters
D
Cl k
Q
D
Q
Cl k
T
Clk-Q
T
H
PW
m
T
SU
Delays can be different for rising and falling data transitions
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Example Clock System
Courtesy of IEEE Press, New York. 2000
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Clock Nonidealities
Clock skew
Spatial variation in temporally equivalent clock edges; deterministic + random,
t
SK
Clock jitter
Temporal variations in consecutive edges of the clock signal; modulation +
random noise
Cycle-to-cycle (short-term) t
JS
Long term t
JL
Variation of the pulse width
for level sensitive clocking
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Clock Skew and Jitter
Both skew and jitter affect the effective cycle time
Only skew affects the race margin
Cl k
Cl k
t
SK
t
JS
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Clock Uncertainties
2
4
3
Power Supply
Interconnect
5 Temperature
6 Capacitive Load
7 Coupling to Adjacent Lines
1 Clock Generation
Devices
Sources of clock uncertainty
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Clock Skew
# of registers
Clk delay
Insertion delay
Max Clk skew
Earliest occurrence
of Clk edge
Nominal /2
Latest occurrence
of Clk edge
Nominal + /2

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Positive and Negative Skew
R1
In
(a) Positive skew
Combinational
Logic
D Q
t
CLK1
CLK
delay
t
CLK2
R2
D Q
Combinational
Logic
t
CLK3
R3

D Q
delay
R1
In
(b) Negative skew
Combinational
Logic
D Q
t
CLK1
delay
t
CLK2
R2
D Q
Combinational
Logic
t
CLK3
R3

D Q
delay CLK
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Positive Skew
CLK1
CLK2
T
CLK

T
CLK
+
+ t
h

2
1
4
3
Launching edge arrives before the receiving edge
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Negative Skew
CLK1
CLK2
T
CLK

T
CLK
+
2
1
4
3
Receiving edge arrives before the launching edge
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Longest Logic Path in
Edge-Triggered Systems
Cl k
P
T
SU
+ T
sk
+ T
JS
T
Clk-Q
T
LM
Latest point
of launching
Earliest arrival
of next cycle
Unger and Tan
Trans. on Comp.
10/86
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Clock Constraints in
Edge-Triggered Systems
JS sk SU LM QM clk
T T T T T P + + + +

LM QM clk SU JS sk
T T T T T P + +

If launching edge is late and receiving edge is early, the data will not be too late if:
Minimum cycle time is determined by the maximum delays through the logic
Double-sided definitions of setup and jitter
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Shortest Path
Cl k
T
Clk-Q
T
Lm
Earliest point
of launching
Data must not arrive
before this time
Cl k
T
H
Nominal
clock edge
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Clock Constraints
in Edge-Triggered Systems
Minimum logic delay
If launching edge is early and receiving edge is late:
H sk Lm Qm clk
T T T T + +

Qm clk H sk Lm
T T T T

+
Jitter does not really play as this concerns the same clock edge
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Clock Constraints
in Edge-Triggered Systems
Courtesy of IEEE Press, New York. 2000
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Flip-Flop Based Timing
Flip
-flop
Logic

= 1
= 0
Flip-flop
delay
Skew
Logic delay
T
SU
T
Clk-Q
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Flip-Flops and Dynamic Logic
= 1
= 0
Logic delay
T
SU
T
Clk-Q
= 1
= 0
Logic delay
T
SU
T
Clk-Q
Precharge
Evaluate
Evaluate
Precharge
Flip-flops are used only with static logic
No way to hide the precharge overhead