June 12, 2002 2

EHCI Specification
and Testing
EHCI Specification
and Testing
John S. Howard
John S. Howard
Engineering Manager
Engineering Manager
Intel Corporation
Intel Corporation
June 12, 2002 3
Agenda
Agenda
!
!
EHCI Development Overview
EHCI Development Overview
!
!
EHCI Architecture/Key Features
EHCI Architecture/Key Features
!
!
Top 10 Developer
Top 10 Developer
FAQs
FAQs
!
!
USB2 Host Controller Compliance Program
USB2 Host Controller Compliance Program
!
!
Top Issues Identified with Compliance Tests
Top Issues Identified with Compliance Tests
!
!
Summary
Summary
June 12, 2002 4
What is The EHCI Spec.?
What is The EHCI Spec.?
!
!
Enhanced Host Controller Specification for USB
Enhanced Host Controller Specification for USB

Defines the architecture for a USB 2.0 capable host

Defines the architecture for a USB 2.0 capable host
controller, and
controller, and

Defines register (hardware/software) interface

Defines register (hardware/software) interface
for a high
for a high
-
-
speed capable host controller
speed capable host controller
!
!
Revision 1.0 Released March 2002
Revision 1.0 Released March 2002
June 12, 2002 5
What Is It
What Is It
!
!
Intel developed specification w/contributions:
Intel developed specification w/contributions:

NEC, Lucent (
NEC, Lucent (
Agere
Agere
), Philips, HP, Compaq
), Philips, HP, Compaq
and Microsoft
and Microsoft

Licensees can also suggest contributions

Licensees can also suggest contributions
to specification
to specification
!
!
License agreement with Intel
License agreement with Intel

Intel provides reciprocal royalty free license to use

Intel provides reciprocal royalty free license to use
the specification to manufacture compliant
the specification to manufacture compliant
USB 2.0 host controllers
USB 2.0 host controllers
" "
both discrete and integrated implementations
both discrete and integrated implementations
Continued
Continued
June 12, 2002 6
Goals & Requirements
Goals & Requirements
!
!
Evolutionary approach
Evolutionary approach
!
!
Use best features from USB 1.1 Controllers
Use best features from USB 1.1 Controllers
!
!
Mix of OHCI and UHCI
Mix of OHCI and UHCI
!
!
Re
Re
-
-
use existing technology where possible
use existing technology where possible
!
!
Learn from USB 1.1 Controller issues
Learn from USB 1.1 Controller issues
!
!
Maintain maximum device support and control
Maintain maximum device support and control
!
!
Support 32 & 64
Support 32 & 64
-
-
bit addressing
bit addressing
!
!
Support PCI Power Management
Support PCI Power Management
!
!
Explicit Mechanism for support of Pre
Explicit Mechanism for support of Pre
-
-
boot SW and OS
boot SW and OS
ownership hand
ownership hand
-
-
off
off
June 12, 2002 7
Agenda
Agenda
!
!
EHCI Development Overview
EHCI Development Overview
!
!
EHCI Architecture/Key Features
EHCI Architecture/Key Features
!
!
Top 10 Developer
Top 10 Developer
FAQs
FAQs
!
!
USB2 Host Controller Compliance Program
USB2 Host Controller Compliance Program
!
!
Top Issues Identified with Compliance Tests
Top Issues Identified with Compliance Tests
!
!
Summary
Summary
June 12, 2002 8
USB 2.0 Host Controller
Architecture
USB 2.0 Host Controller
Architecture
!
!
Companion Controller(s) support FS/LS devices on root ports
Companion Controller(s) support FS/LS devices on root ports
!
!
High
High
-
-
speed Host Controller support HS devices on root ports
speed Host Controller support HS devices on root ports
Simpler design; optimized for high Simpler design; optimized for high- -speed functionality speed functionality
!
!
Reuses USB 1.1 Host Controller Designs (drop
Reuses USB 1.1 Host Controller Designs (drop
-
-
in)
in)
!
!
USB ports
USB ports
work
work
independent of high
independent of high
-
-
speed capable software
speed capable software
USB 2.0 Host Controller (HC) USB 2.0 Host Controller (HC)
Port 1 Port 1
Companion USB HCs for FS/LS Companion USB HCs for FS/LS
Port 1 Port 1 Port 2 Port 2
Port Owner Port Owner
Control(s) Control(s)
Port 1 Port 1 Port Port 2 2
Port Routing Logic Port Routing Logic
Port N Port N
HC Control Logic/Data HC Control Logic/Data
Buffering Buffering
Enhanced HC Control Logic Enhanced HC Control Logic
Enhanced Data Buffering Enhanced Data Buffering
Port 2 Port 2 Port N Port N
Port N Port N
High High- -Speed Speed
(Enhanced Interface) USB HC (Enhanced Interface) USB HC
June 12, 2002 9
EHCI Ext. Caps.
SW Hand-Off
EHCI Ext. Caps. EHCI Ext. Caps.
SW Hand SW Hand- -Off Off
EHCI Interface Architecture
EHCI Interface Architecture
Capability
Registers
Capability Capability
Registers Registers
Operational
Registers
Operational Operational
Registers Registers
Memory-Based
I/O Registers
Memory Memory- -Based Based
I/O Registers I/O Registers
PCI Class
Code, etc.
PCI Class PCI Class
Code, etc. Code, etc.
USB Base
Address
USB Base USB Base
Address Address
PCI Power
Management
Interface
PCI Power PCI Power
Management Management
Interface Interface
PCI Configuration
Register
PCI Configuration PCI Configuration
Register Register
Shared Memory Work Schedules
Shared Memory Work Schedules Shared Memory Work Schedules
Periodic Schedule
Periodic Schedule Periodic Schedule
Asynchronous Schedule
Asynchronous Schedule Asynchronous Schedule
Debug Port
& BAR
Debug Port Debug Port
& BAR & BAR
Debug Port
Registers
Debug Port Debug Port
Registers Registers
June 12, 2002 10
EHCI Registers
EHCI Registers
! ! EHCI Capabilities EHCI Capabilities
Optional Feature Indicators and Optional Feature Indicators and
Parameters Parameters
Structural Parameters Structural Parameters
! ! Operational Space Operational Space
Command/Configuration Command/Configuration
Host Controller Status Host Controller Status
Interrupt Enables Interrupt Enables
Schedule Base References Schedule Base References
" " Periodic Schedule Base Address Periodic Schedule Base Address
" " Next Asynchronous Queue Head Next Asynchronous Queue Head
USB Hub Port Status and Control USB Hub Port Status and Control
! ! Debug Port Register Set ** Debug Port Register Set **
! ! PCI Power Management PCI Power Management
! ! EHCI Extended Capabilities (EECP) EHCI Extended Capabilities (EECP)
OS Handoff Registers ** OS Handoff Registers **
I/O Space
I/O Space
PCI
PCI
Config
Config
. Space
. Space
** Optional ** Optional
June 12, 2002 11
EECP: BIOS/OS Handoff
EECP: BIOS/OS Handoff
!
!
Provides simple, reliable semaphore
Provides simple, reliable semaphore
-
-
based
based
mechanism for exchanging EHCI ownership
mechanism for exchanging EHCI ownership

Semaphores are located in PCI Configuration Space

Semaphores are located in PCI Configuration Space
" "
Located via EHCI
Located via EHCI
-
-
defined EECP pointer
defined EECP pointer
!
!
Semaphores can be Polled or
Semaphores can be Polled or
!
!
Pre
Pre
-
-
Boot Software can enable
Boot Software can enable
SMIs
SMIs
to be notified
to be notified
on ownership semaphore modifications
on ownership semaphore modifications
!
!
See Chapter 5 for details
See Chapter 5 for details
June 12, 2002 12
EHCI Data Structures
EHCI Data Structures
!
!
Small set of data structure primitives
Small set of data structure primitives

Supports all transfer types & speeds

Supports all transfer types & speeds
!
!
Transfer
Transfer
-
-
oriented ( Bulk/Control/Interrupt )
oriented ( Bulk/Control/Interrupt )

Large* buffer per data structure

Large* buffer per data structure

Queue semantics
Queue semantics
!
!
Packet
Packet
-
-
oriented ( Isochronous )
oriented ( Isochronous )

Frame (millisecond) based

Frame (millisecond) based

Exposes per micro

Exposes per micro
-
-
frame programmability
frame programmability
!
!
32
32
-
-
bit and 64
bit and 64
-
-
bit addressing support
bit addressing support
!
!
Simple hardware support for Scatter/Gather
Simple hardware support for Scatter/Gather
!
!
Special Frame Span Traversal Node (FSTN)
Special Frame Span Traversal Node (FSTN)
June 12, 2002 13
3 3
3. 3. When transfer complete, HC writes When transfer complete, HC writes
back source back source qTD qTD with results and with results and
advances state to the next advances state to the next qTD qTD in in
the chain the chain
1 1
1. 1. HC reads HC reads qTD qTD at top of at top of
queue and overlays it onto queue and overlays it onto
qHD qHD if marked Active if marked Active
EHCI Queue Heads
EHCI Queue Heads
!
!
Designed to reduce
Designed to reduce
avgerage
avgerage
memory accesses
memory accesses
!
!
Used for all non
Used for all non
-
-
Isochronous data flows
Isochronous data flows
!
!
Provides FIFO ordering
Provides FIFO ordering
!
!
Execution Steps:
Execution Steps:
qTD qTD
1 1
qTD qTD
0 0
qHD qHD
2 2
2. 2. HC executes bus transactions HC executes bus transactions
from from qHD qHD till transfer is complete till transfer is complete
June 12, 2002 14
EHCI Interface Schedules
EHCI Interface Schedules
!
!
A Periodic Schedule
A Periodic Schedule

Isochronous & Interrupt

Isochronous & Interrupt
!
!
An Asynchronous Schedule
An Asynchronous Schedule

Bulk & Control

Bulk & Control
!
!
Each explicitly enabled via
Each explicitly enabled via
System software
System software
!
!
Execution Rules
Execution Rules

Repeat each micro

Repeat each micro
-
-
frame:
frame:

Periodic schedule first, then

Periodic schedule first, then

Asynchronous schedule
Asynchronous schedule
Shared Memory Work Schedules
Shared Memory Work Schedules Shared Memory Work Schedules
Periodic Schedule
Periodic Schedule Periodic Schedule
Asynchronous Schedule
Asynchronous Schedule Asynchronous Schedule
June 12, 2002 15
Periodic Schedule Overview
Periodic Schedule Overview
! ! Binary Binary- -tree structure tree structure
Traversal from leaf level to root Traversal from leaf level to root
Frame List Frame List is the Leaf level is the Leaf level
Each level in tree is a poll rate Each level in tree is a poll rate
interval interval
! ! Objects linked relative to the Objects linked relative to the Frame Frame
List List, are at correct poll rate , are at correct poll rate
! ! Transfer Types Supported Transfer Types Supported
HS Isochronous ( HS Isochronous (iTD iTD), ),
HS Interrupt ( HS Interrupt (Queue Heads Queue Heads) )
FS/LS Interrupt ( FS/LS Interrupt (Queue Heads Queue Heads), ),
FS Isochronous ( FS Isochronous (siTD siTD) )
! ! Other Support Other Support
Dynamic Rebalancing of FS/LS Dynamic Rebalancing of FS/LS
Frame Frame- -Spanning Split Transactions Spanning Split Transactions
4
4 4
Poll Rate: N Poll Rate: N ! !1 1
Periodic Frame List Periodic Frame List
4
4 4
4
4 4
4
4 4
2
2 2
2
2 2
1
1 1
June 12, 2002 16
Periodic Frame List
Periodic Frame List
!
!
Array of schedule object pointers
Array of schedule object pointers
!
!
Represents a rolling window
Represents a rolling window
of time
of time
Each location is base pointer for Each location is base pointer for
one frames worth of work one frames worth of work
(8 micro (8 micro- -frames) frames)
Frame work for establishing Frame work for establishing
time time- -oriented oriented reachability reachability
!
!
HC builds an offset into the
HC builds an offset into the
Periodic Frame list from:
Periodic Frame list from:
Periodic frame list base address Periodic frame list base address
Frame Index Register [12:3] Frame Index Register [12:3]
" " Increments once each frame (1ms) Increments once each frame (1ms)
Frame List Base Frame List Base
12 12 31 31 13 13 12 12
3 3 0 0
Frame Index Frame Index
31 31 12 12 11 11 2 2
Periodic Frame List Periodic Frame List


To schedule graph To schedule graph
Accesses same offset 8 micro Accesses same offset 8 micro- -
frames before preceding to next frames before preceding to next
location location
Micro-frame select
June 12, 2002 17
High Speed Isochronous
High Speed Isochronous
!
!
Packet
Packet
-
-
oriented Data
oriented Data
Structure
Structure
!
!
8 Transaction Records
8 Transaction Records
per
per
iTD
iTD
(one per Micro
(one per Micro
-
-
Frame)
Frame)
Transaction Record 0 Transaction Record 0
Transaction Record 1 Transaction Record 1
Transaction Record 7 Transaction Record 7
Memory Pointers, addressing, Memory Pointers, addressing,
transfer state, etc. transfer state, etc.
Isochronous Isochronous
Transfer Descriptor Transfer Descriptor
( (iTD iTD) )
13 13 12 12
3 3 0 0
Frame Index Frame Index
Selects Selects
Transaction Transaction
Record Record
Selects Frame List Selects Frame List
Offset Offset
June 12, 2002 18
Periodic Split Transactions
Periodic Split Transactions
!
!
Used to service data streams through TT periodic
Used to service data streams through TT periodic
pipeline(s)
pipeline(s)
!
!
Requirement on Host is to:
Requirement on Host is to:

Execute starts and completes when they need to occur

Execute starts and completes when they need to occur
" " System software must budget execution footprint (starts/complete System software must budget execution footprint (starts/completes) s)
" " Host controller must execute and track progress of split transac Host controller must execute and track progress of split transaction tion
!
!
Each endpoint data structure contains:
Each endpoint data structure contains:

Micro
Micro
-
-
frame masks which encode which micro
frame masks which encode which micro
-
-
frames to
frames to
execute Starts & Complete splits
execute Starts & Complete splits

Micro
Micro
-
-
state to track progress (to detect lost data, etc.)
state to track progress (to detect lost data, etc.)
!
!
Projection of core
Projection of core
-
-
spec bus frame boundaries into the
spec bus frame boundaries into the
host schedule created many scheduling boundary
host schedule created many scheduling boundary
conditions, so
conditions, so
June 12, 2002 19
7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 0 0
CS CS CS CS CS CS CS CS SS SS CS CS CS CS CS CS CS CS
7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2
HS Bus HS Bus
Frames Frames
HC Periodic HC Periodic
Schedule Schedule
Micro Micro - - frames frames
HS/FS/LS Bus HS/FS/LS Bus
Frame Boundaries Frame Boundaries
HC Periodic Schedule HC Periodic Schedule
Frame Boundaries Frame Boundaries
SS SS
B B- -Frame N Frame N B B- - Frame N+1 Frame N+1
Interface Data Interface Data
Structure Structure
H H - - Frame N Frame N
Interface Data Interface Data
Structure Structure
H H - - Frame N+1 Frame N+1
Bus Frame View Vs.
Host Frame View
Bus Frame View Vs.
Host Frame View
! ! In order to simplify host for TT periodic pipeline support we ha In order to simplify host for TT periodic pipeline support we had to offset the d to offset the
Hosts view of frame boundaries by one micro Hosts view of frame boundaries by one micro- -frame from Buss view frame from Buss view
Full/Low-Speed
Transaction
Full/Low-Speed
Transaction
Full/Low-Speed
Transaction
Full/Low-Speed
Transaction
June 12, 2002 20
FS Isochronous IN
Frame-Wrap Example
FS Isochronous IN
Frame-Wrap Example
Start Start- -Mask Mask 08h 08h
Complete Complete- -Mask Mask C3h C3h
siTD
X
siTD
X+1
0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2
H H- -Frame X Frame X
0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1
B B- -Frame Y Frame Y
7 7
SS SS CS CS
0 0
CS CS
1 1
CS CS
2 2
CS CS
3 3
H H- -Frame X+1 Frame X+1
B B- -Frame Y+1 Frame Y+1
Back Pointer Back Pointer
June 12, 2002 21
FS/LS Interrupt IN
Frame-wrap Example
FS/LS Interrupt IN
Frame-wrap Example
Start Start- -Mask Mask 40h 40h
Complete Complete- -Mask Mask 03h 03h
Must be reachable from Must be reachable from
consecutive Frame list locations: consecutive Frame list locations:
0,1, 8,9, 16,17 (poll period of 8) 0,1, 8,9, 16,17 (poll period of 8)
Queue Head Queue Head
0 0 0
1 1 1
2 2 2
3 3 3
4 4 4
5 5 5
6 6 6
7 7 7
0 0 0
1 1 1
2 2 2
H-Frame H H- -Frame Frame
0 0 0
1 1 1
2 2 2
3 3 3
4 4 4
5 5 5
6 6 6
7 7 7
0 0 0
1 1 1
B-Frame B B- -Frame Frame
7 7 7
SS SS SS
CS
0
CS CS
0 0
CS
1
CS CS
1 1
Requires use Requires use
of FSTN of FSTN
June 12, 2002 22
FSTN Example
FSTN Example
FSTNs FSTNs are specific routing data structures to are specific routing data structures to
allow system software to describe alternate allow system software to describe alternate
traversal on necessary frame traversal on necessary frame- -wrap wrap
boundaries boundaries
8A.0 8A.0
8B.0 8B.0
8C.0 8C.0
8D.0 8D.0
8F.0 8F.0
8G.0 8G.0
8H.0 8H.0
8I.0 8I.0
4A.0 4A.0 4A.1 4A.1 4A.2 4A.2
2A.0 2A.0
1A.0 1A.0
4B.0 4B.0 4B.1 4B.1 4B.2 4B.2
4C.0 4C.0 4C.1 4C.1
4D.0 4D.0 4D.1 4D.1
2B.0 2B.0
4 4
4 4
0 0
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
4 4
4 4
4 4
4 4
2 2
2 2
1 1
4 4
4 4
4 4
4 4
N N- -ptr ptr
B B- -ptr ptr
(push) (push)
FSTN FSTN
N N- -ptr ptr
B B- -ptr ptr
(pop) (pop)
FSTN FSTN
Push FSTN, B Push FSTN, B- -ptr ptr is traversed (only in is traversed (only in
Micro Micro- -frame 0, 1). frame 0, 1).
Pop FSTN, HC returns to Push location Pop FSTN, HC returns to Push location
and follows N and follows N- -Ptr Ptr
June 12, 2002 23
FS/LS Interrupt
Rebalance Lockout
FS/LS Interrupt
Rebalance Lockout
!
!
When there are changes in
When there are changes in
active endpoints below a TT
active endpoints below a TT
System software recalculates System software recalculates
TT budget TT budget
Active endpoints may require Active endpoints may require
rebalancing rebalancing
" " New start New start- - and complete and complete- -split split
masks masks
!
!
Queue Head
Queue Head
I
I
-
-
Bit
Bit
Feature makes
Feature makes
rebalancing easy to manage
rebalancing easy to manage
Software sets Software sets I I- -Bit Bit in queue head in queue head
to a one, indicating HC must to a one, indicating HC must
deactivate Queue Head before deactivate Queue Head before
starting another split transaction starting another split transaction
Very easy for system software to Very easy for system software to
detect when data structure is safe detect when data structure is safe
to update, then reactivate to update, then reactivate
Set Active
Set Active
to zero
to zero
Do Complete
Do Complete
Last CS
Last CS
No change
No change
to Active
to Active
Do Complete
Do Complete
Not Last CS
Not Last CS
Sets Active
Sets Active
to zero
to zero
Do Start
Do Start
Queue Head State & Queue Head State &
Transaction Result Transaction Result
Side Effect to Queue Side Effect to Queue
Head Active bit Head Active bit
June 12, 2002 24
Async. Schedule Overview
Async. Schedule Overview
!
!
HS, FS, LS Bulk & Control
HS, FS, LS Bulk & Control

Split transactions for FS/LS

Split transactions for FS/LS
!
!
Simple, circular linked list
Simple, circular linked list

Yields fair service of bus

Yields fair service of bus
transactions via Round
transactions via Round
-
-
Robin
Robin

Nominally, one bus

Nominally, one bus
transaction per list element
transaction per list element
per traversal **
per traversal **
!
!
Only Queue Heads allowed
Only Queue Heads allowed
in schedule
in schedule
!
!
HC stops traversal when
HC stops traversal when
schedule is empty **
schedule is empty **
I/O Register: I/O Register:
Asynchronous List Pointer Asynchronous List Pointer
Current Current qHead qHead Pointer Pointer
H
H H
June 12, 2002 25
Asynch. HS Park-Mode
Asynch. HS Park-Mode
!
!
Nominally, rules are one transaction per active queue head per
Nominally, rules are one transaction per active queue head per
traversal of the Asynchronous schedule
traversal of the Asynchronous schedule
!
!
Traversing data structures is pure overhead
Traversing data structures is pure overhead
Large contributor to inter Large contributor to inter- -transaction times on USB transaction times on USB
Reduces actual number of bus Reduces actual number of bus- -transactions and effective throughput transactions and effective throughput
!
!
Asynchronous Park
Asynchronous Park
-
-
Mode (optional)
Mode (optional)
Allows HC to execute more than one consecutive bus transaction ( Allows HC to execute more than one consecutive bus transaction (max 3) max 3)
from a HS Queue Head before proceeding to next Schedule element from a HS Queue Head before proceeding to next Schedule element
May Improve performance of high May Improve performance of high- -speed Bulk & Control Transfers (depends speed Bulk & Control Transfers (depends
on HC implementation) on HC implementation)
When implemented: default ON (possibly no SW support required) When implemented: default ON (possibly no SW support required)
SW may turn off or set level via the USB Command Register SW may turn off or set level via the USB Command Register
Only available for High Speed Queue Heads in Asynchronous Schedu Only available for High Speed Queue Heads in Asynchronous Schedule le
June 12, 2002 26
Asynch. Split Transactions
Asynch. Split Transactions
!
!
Same execution model as
Same execution model as
HS Queue Head with:
HS Queue Head with:

Micro
Micro
-
-
machine to track split
machine to track split
transaction progress
transaction progress

FS/LS transfer advancement

FS/LS transfer advancement
occurs when entire split
occurs when entire split
transaction is complete
transaction is complete
" " e.g. All start e.g. All start- -split and split and
complete complete- -split bus split bus
transactions transactions
!
!
HC uses split transaction
HC uses split transaction
protocol if Queue Head
protocol if Queue Head
marked LS or FS
marked LS or FS
H H- -Frame X Frame X
2 2
1 1
0 0
7 7
1 1
0 0
SS SS
ACK ACK
CS CS
NYET NYET
CS CS
ACK ACK
CS CS
NYET NYET

Frequency of service depends on number of

active Queue Heads Heads in Async. List
June 12, 2002 27
Agenda
Agenda
!
!
EHCI Development Overview
EHCI Development Overview
!
!
EHCI Architecture/Key Features
EHCI Architecture/Key Features
!
!
Top 10 Developer
Top 10 Developer
FAQs
FAQs
!
!
USB2 Host Controller Compliance Program
USB2 Host Controller Compliance Program
!
!
Top Issues Identified with Compliance Tests
Top Issues Identified with Compliance Tests
!
!
Summary
Summary
June 12, 2002 28
Top 5 SW Developer FAQs
Top 5 SW Developer FAQs
!
!
How do I add
How do I add
qTDs
qTDs
to a
to a
qHD
qHD
without stopping the
without stopping the
qHD
qHD
?
?

See foil
See foil
!
!
How do I map
How do I map
qHD
qHD
state to specific error conditions?
state to specific error conditions?

See foil
See foil
!
!
Getting horrible Bulk throughput, why?
Getting horrible Bulk throughput, why?

Ans(1): trying to do one packet per

Ans(1): trying to do one packet per
qTD
qTD

Ans(2): many inactive

Ans(2): many inactive
qHDs
qHDs
on
on
Asynch
Asynch
Schedule. Cut the fat
Schedule. Cut the fat
!
!
How/when do I use these S
How/when do I use these S
-
-
mask/C
mask/C
-
-
mask
mask
thingys
thingys

Ans
Ans
: use for FS/LS Interrupt. Used to implement budgeted
: use for FS/LS Interrupt. Used to implement budgeted
execution footprint See Budgeting presentation
execution footprint See Budgeting presentation
!
!
The specified operation of the Configured Bit causes
The specified operation of the Configured Bit causes
OSs
OSs
to impose load ordering why did you do this?
to impose load ordering why did you do this?

Long story
Long story
June 12, 2002 29
Adding qTDs to qTD Chain
Adding qTDs to qTD Chain
!
!
Dummy
Dummy
qHD
qHD
Always leave inactive Always leave inactive qTD qTD on on
qTD qTD chain chain
When adding new work, use the When adding new work, use the
existing dummy existing dummy qTD qTD as the first as the first
qTD qTD for next buffer for next buffer
Add additional Add additional qTDs qTDs for for
remaining buffer remaining buffer
Add new dummy Add new dummy qTD qTD
Activate all Activate all qTDs qTDs (except (except
dummy) dummy)
Alt.Next pointers always point Alt.Next pointers always point
to the new dummy to the new dummy qTD qTD
!
!
Manage
Manage
qTDs
qTDs
as a pre
as a pre
-
-
linked
linked
circular list
circular list
Use software head & tail pointers Use software head & tail pointers
Head pointer tells software which Head pointer tells software which
qTD qTD to use next to use next
Tail pointer tells software which Tail pointer tells software which
qTD qTD is next one to reap (transfer is next one to reap (transfer
results) results)
When adding new work must make When adding new work must make
Alt.Next pointers reference new Alt.Next pointers reference new
Head Head qTD qTD
Requirement is to add work to a queue without hitting race condi
Requirement is to add work to a queue without hitting race condi
tions
tions
June 12, 2002 30
qHD State Mapping
qHD State Mapping
0 0
>0 >0
>0 >0
>0 >0
>0 >0
>0 >0
CErr CErr
1 1
1 1
1 1
0 0
0 0
0 0
Halted Halted
1 1
1 1
0 0
1 1
0 0
0 0
XactErr XactErr
>=0 >=0
>0 >0
>0 >0
>= 0 >= 0
>0 >0
0 0
Bytes2Xfer Bytes2Xfer
Three consecutive bus transactions errors Three consecutive bus transactions errors
(any of bad (any of bad pid pid, timeout, data , timeout, data crc crc, etc.) , etc.)
STALL response (same assumption) during STALL response (same assumption) during
some bus transaction during the buffer a some bus transaction during the buffer a
timeout, etc. was encountered timeout, etc. was encountered
Assuming no other status bits are set, this Assuming no other status bits are set, this
was a STALL response. was a STALL response.
( (nc nc or sp) with one or more retries for or sp) with one or more retries for
XactErrors XactErrors detected detected
Short packet (sp) Short packet (sp)
Normal ( Normal (nc nc) )
Explanation Explanation
June 12, 2002 31
Top 5 HW Developer FAQs
Top 5 HW Developer FAQs
!
!
What does Caching of data structures mean?
What does Caching of data structures mean?
Ans Ans: the model is more of a : the model is more of a prefetch prefetch buffer, with no implied buffer, with no implied
coherency mechanisms coherency mechanisms
!
!
Is the
Is the
Typ
Typ
field in a Queue Head Horizontal Pointer used in the
field in a Queue Head Horizontal Pointer used in the
Asynchronous Schedule?
Asynchronous Schedule?
Ans Ans: NO : NO
!
!
Where is the counter for immediate retries on split
Where is the counter for immediate retries on split
isochronous kept?
isochronous kept?
Ans Ans: internal to HC, no room in : internal to HC, no room in siTD siTD
!
!
When does the HC set/clear the
When does the HC set/clear the
Asynch
Asynch
& Periodic
& Periodic
Sched
Sched
.
.
Status bits?
Status bits?
Ans Ans: They are essentially a hardware : They are essentially a hardware ack ack that the HC has seen the enable at that the HC has seen the enable at
a 1, or has seen the enable at a 0 a 1, or has seen the enable at a 0
!
!
Must the Debug Port work on only one port?
Must the Debug Port work on only one port?
Ans Ans: It may optionally work on any port, but it MUST work on the : It may optionally work on any port, but it MUST work on the
port indicated port indicated
June 12, 2002 32
Agenda
Agenda
!
!
EHCI Development Overview
EHCI Development Overview
!
!
EHCI Architecture/Key Features
EHCI Architecture/Key Features
!
!
Top 10 Developer
Top 10 Developer
FAQs
FAQs
!
!
USB2 Host Controller Compliance Program
USB2 Host Controller Compliance Program
!
!
Top Issues Identified with Compliance Tests
Top Issues Identified with Compliance Tests
!
!
Summary
Summary
June 12, 2002 33
EHCI Compliance Program
EHCI Compliance Program
!
!
Goal is to ensure uniform HC
Goal is to ensure uniform HC
functional behavior
functional behavior
!
!
Eliminate need for
Eliminate need for
Implementation
Implementation
-
-
specific
specific
HC Driver Software
HC Driver Software
!
!
Provide tools to help HC
Provide tools to help HC
implementers get it right
implementers get it right
!
!
Not a performance test
Not a performance test
!
!
Self
Self
-
-
Test for EHCI
Test for EHCI
Functional Testing
Functional Testing
(not 3 (not 3
rd rd
Party Test Houses)** Party Test Houses)**
USB USB- -IF IF
Host/Systems Host/Systems
Testing Testing
USB USB- -IF IF
2.0 Hub (TT) 2.0 Hub (TT)
Testing Testing
EHCI Functional EHCI Functional
Testing Testing
Enhanced Host Controller Interface
Enhanced Host Controller Interface
Compliance
Compliance
June 12, 2002 34
EHCI Compliance Prog.
EHCI Compliance Prog.
!
!
Self
Self
-
-
Test for EHCI Compliance Test Suite for Functional Testing is
Test for EHCI Compliance Test Suite for Functional Testing is
not yet released, so
not yet released, so
!
!
Intel Labs is providing EHCI Functional Testing, as a convenienc
Intel Labs is providing EHCI Functional Testing, as a convenienc
e
e
to the USB2 industry until the Self
to the USB2 industry until the Self
-
-
Test Program is in place
Test Program is in place
Must be an an Adopter of the EHCI Specification (e.g. a License Must be an an Adopter of the EHCI Specification (e.g. a Licensee) e)
A Corporate Non Disclosure Agreement (CNDA) must be in place A Corporate Non Disclosure Agreement (CNDA) must be in place
To submit products for testing at Intel Labs, must sign an EHCI To submit products for testing at Intel Labs, must sign an EHCI Testing Testing
Services Agreement Services Agreement
Prior to release, EHCI software is being made available via Rest Prior to release, EHCI software is being made available via Restricted Use ricted Use
License. License.
Details, contacts and forms on these requirements available on: Details, contacts and forms on these requirements available on:
http://developer.intel.com/technology/usb http://developer.intel.com/technology/usb
Continued
Continued
June 12, 2002 35
EHCI Test Methodology
EHCI Test Methodology
!
!
Test Specification derived from EHCI Specification
Test Specification derived from EHCI Specification
Test Assertions Test Assertions
" " Short, Short, concise concise, unambiguous statement. Derived from specification , unambiguous statement. Derived from specification
Test Descriptions Test Descriptions
" " Outlines test, pass/fail criteria and which assertions are exerc Outlines test, pass/fail criteria and which assertions are exercised ised
!
!
Test Software
Test Software
!
!
Special purpose test peripherals for the compliance tests
Special purpose test peripherals for the compliance tests
Test
Assertions
Test Test
Assertions Assertions
Test
Descriptions
Test Test
Descriptions Descriptions
EHCI
Specification
EHCI EHCI
Specification Specification
EHCI Test
Specification
EHCI Test EHCI Test
Specification Specification E
H
C
I

C
o
m
p
l
i
a
n
c
e

E
H
C
I

C
o
m
p
l
i
a
n
c
e

T
e
s
t
s
T
e
s
t
s
June 12, 2002 36
EHCI Compliance Software
EHCI Compliance Software
!
!
Test Executive
Test Executive

Console App w/Popup Menus

Console App w/Popup Menus
!
!
Test DLLs
Test DLLs

1:1 correspondence to tests

1:1 correspondence to tests
defined in EHCI Test
defined in EHCI Test
Specification
Specification
!
!
Testing Services DLL
Testing Services DLL

Simplifies details of
Simplifies details of
developing/maintaining tests
developing/maintaining tests
!
!
Special
Special
-
-
purpose host
purpose host
controller driver
controller driver
EHCI Under Test
EHCI Under Test EHCI Under Test
Compliance HCD
Compliance HCD
Test Services
Test Services Test Services
Test Executive Test Executive
EHCI Tests EHCI Tests
Results
Logs
Results Results
Logs Logs
June 12, 2002 37
Compliance Peripherals
Compliance Peripherals
!
!
Special purpose test stack requires dedicated,
Special purpose test stack requires dedicated,
special purpose compliance peripherals
special purpose compliance peripherals
!
!
USB2 Compliance Device Specification
USB2 Compliance Device Specification
!
!
Defines the interface and operational model for
Defines the interface and operational model for
special purpose peripheral used with the EHCI and
special purpose peripheral used with the EHCI and
USB
USB
-
-
IF TT test software.
IF TT test software.
!
!
Implementations of compliance devices for all
Implementations of compliance devices for all
speeds have been provided by Cypress
speeds have been provided by Cypress

LS, FS Available from USB

LS, FS Available from USB
-
-
IF
IF
June 12, 2002 38
Peripheral Interface
Peripheral Interface
!
!
Device exports list of endpoint capabilities and implements a
Device exports list of endpoint capabilities and implements a
simple set of commands
simple set of commands
!
!
Host can reconfigure individual endpoint characteristics to matc
Host can reconfigure individual endpoint characteristics to matc
h
h
current test requirements
current test requirements
All transfer types (** for enumerated speed) All transfer types (** for enumerated speed)
High High- -bandwidth (high bandwidth (high- -speed only devices) speed only devices)
One or more Data loop back endpoints One or more Data loop back endpoints
" " For all transfer types supported, incl. For all transfer types supported, incl. hbw hbw (not concurrently) (not concurrently)
Data streaming with no Data streaming with no Naks Naks
" " Infinite sink, source, or loop back Infinite sink, source, or loop back
" " Min to Max packet Min to Max packet
Always: Always: Nak Nak, Stall, Timeout and/or generate CRC , Stall, Timeout and/or generate CRC
!
!
Host can command device to Disconnect, Delay, Reconnect
Host can command device to Disconnect, Delay, Reconnect
!
!
Host can command device to issue Remote
Host can command device to issue Remote
-
-
wakeup with a specific
wakeup with a specific
delay (after it observes Suspend)
delay (after it observes Suspend)
June 12, 2002 39
Focused Testing Areas
Focused Testing Areas
! ! Register Operation Register Operation
! ! Transfer Streaming Tests Transfer Streaming Tests
Debug Port Debug Port
! ! Test all event masks and correct operation with Test all event masks and correct operation with PMEStatus PMEStatus
PCI Power Mgt. PCI Power Mgt.
! ! Short Packet Short Packet
! ! Error Interrupt sources ( Error Interrupt sources (siTD siTD, , iTD iTD, Queue Head) , Queue Head)
! ! Interop Interop w/Multiple Data Streams w/Multiple Data Streams
Transfers Transfers
! ! Scatter/Gather across ALL byte boundaries ( Scatter/Gather across ALL byte boundaries (siTD siTD, , iTD iTD, Queue Head) , Queue Head)
! ! Split transaction normal, ALL Micro Split transaction normal, ALL Micro- -Frame boundaries and H Frame boundaries and H- -frame/B frame/B- -Frame Frame
boundary conditions ( boundary conditions (siTD siTD, Queue Head) , Queue Head)
! ! Nak Nak Counter, I Counter, I- -bit, Data Toggle, PID sequencing bit, Data Toggle, PID sequencing
! ! FSTN Traversal, Asynchronous Schedule Service Order & Park Mode FSTN Traversal, Asynchronous Schedule Service Order & Park Mode
! ! PING, High Bandwidth (Interrupt & Isochronous) PING, High Bandwidth (Interrupt & Isochronous)
Data Structures Data Structures
! ! Enumeration (HS, FS, LS), (Interaction with Status Register) Enumeration (HS, FS, LS), (Interaction with Status Register)
! ! Suspend, Resume, Ownership hand Suspend, Resume, Ownership hand- -off off
Port Operations Port Operations
! ! Validate Capability Registers Validate Capability Registers
! ! Control/Status Registers for proper operation Control/Status Registers for proper operation
! ! FRINDEX (Host FRINDEX (Host- -frame to Bus frame to Bus- -Frame) Frame)
Registers Registers
June 12, 2002 40
Agenda
Agenda
!
!
EHCI Development Overview
EHCI Development Overview
!
!
EHCI Architecture/Key Features
EHCI Architecture/Key Features
!
!
Top 10 Developer
Top 10 Developer
FAQs
FAQs
!
!
USB2 Host Controller Compliance Program
USB2 Host Controller Compliance Program
!
!
Top Issues Identified with Compliance Tests
Top Issues Identified with Compliance Tests
!
!
Summary
Summary
June 12, 2002 41
Top Errors Identified
Top Errors Identified
!
!
The Asynchronous schedule bus transaction execution is not fair
The Asynchronous schedule bus transaction execution is not fair
(I.e. not Round
(I.e. not Round
-
-
Robin)
Robin)
Working hard to fit transactions at end of micro Working hard to fit transactions at end of micro- -frame frame
!
!
Setting multiple change bits in the port status and control regi
Setting multiple change bits in the port status and control regi
sters
sters
!
!
FS Isochronous (
FS Isochronous (
siTD
siTD
)
)
Incorrect traversal of Incorrect traversal of siTD siTD back pointers back pointers
" " Additional overhead and/or incorrect operation Additional overhead and/or incorrect operation
Incorrect optimizations for Incorrect optimizations for siTD siTD.Back Pointer traversal .Back Pointer traversal
" " Conflicts with dynamic reprogramming of S Conflicts with dynamic reprogramming of S- -/C /C- -Masks Masks
!
!
Incorrect
Incorrect
Nak
Nak
Counter implementation
Counter implementation
!
!
Using Reserved bits in interface data structures for Vendor
Using Reserved bits in interface data structures for Vendor
-
-
specific intermediate State
specific intermediate State
!
!
High
High
-
-
bandwidth
bandwidth
mult
mult
sequencing incorrect
sequencing incorrect
!
!
IN Data not landing in Assigned Buffer
IN Data not landing in Assigned Buffer
June 12, 2002 42
Summary
Summary
!
!
EHCI Specification, Rev 1.0 released March, 2002
EHCI Specification, Rev 1.0 released March, 2002

Over 30 Licensees
Over 30 Licensees
!
!
Compliance program up and running
Compliance program up and running

More than 4 Implementations have completed

More than 4 Implementations have completed
Compliance Testing
Compliance Testing

Finding problems in time to get them fixed

Finding problems in time to get them fixed

Compliance Testing available @ Intel Labs until

Compliance Testing available @ Intel Labs until
Self
Self
-
-
test is in place
test is in place

Alpha Release of Self

Alpha Release of Self
-
-
test tools available early Q3, 2002
test tools available early Q3, 2002
Note: all dates provided are for planning purposes only and are Note: all dates provided are for planning purposes only and are subject to change subject to change
June 12, 2002 43
Summary
Summary
!
!
Contacts/URLs
Contacts/URLs

Questions on Specification and/or Licensing:

Questions on Specification and/or Licensing:
" "
ehcisupport
ehcisupport
@
@
intel
intel
.com
.com

Specification, Documentation, Compliance

Specification, Documentation, Compliance
Program, etc.
Program, etc.
" "
http://developer.
http://developer.
intel
intel
.com/technology/
.com/technology/
usb
usb
Continued
Continued