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Abstract—The deterioration of operating margin and increasing Moreover, there is a large increase in the leakage current
leakage current in SRAM are becoming critical problems with the of transistors. The leakage current is now a critical problem
advance of process scaling. To solve these problems, we propose
to achieve a low-power SoC, especially in the SRAM mod-
a low-power SRAM circuit using thin buried-oxide fully depleted
silicon-on-insulator transistors. The back-gate bias is introduced to ules, which need to retain their data while the other modules
the SRAM circuits and acquires high operating margin and high- are standing by. Therefore, SRAM supports the stand-by state
speed operation under low supply voltage. The leakage current in where it must retain its data with very little power consumption.
stand-by state is reduced. This SRAM achieves 30% faster writing In this paper, we describe a SRAM circuit composed of thin
time under low-voltage operation and 90% less stand-by power.
buried-oxide (BOX) fully depleted (FD) silicon-on-insulator
Index Terms—Back-gate bias, low-leakage current, operating (SOI) transistor [4]. The of the thin-BOX FD-SOI tran-
margin, SRAM, thin buried-oxide fully depleted silicon-on-insu-
sistor can be controlled by changing its well-node (back-gate)
lator (thin-BOX FD-SOI) transistor.
voltage, like the back-gate bias used in bulk transistors, without
an increase in extra current. We effectively use this back-gate
I. INTRODUCTION bias effect and improve the operating margins and the operating
speed [7]. Moreover, its stand-by power is also reduced by
about 90%.
T ODAY, mobile devices are widely used, and they process
various applications, for example, dealing with a video
phone, playing TV programs or DVDs, and processing office
This paper is organized as follows. Section II presents a
back-gate controllable transistor, a thin-BOX FD-SOI tran-
files. One of the key devices in these mobile devices is the sistor. Section III shows the high-operating margin SRAM,
in which the back-gate bias of memory cells in same column
system-on-a-chip (SoC). The SoC embeds many modules, such
is commonly controlled. Section IV describes the method to
as the processor cores, hardware accelerators, various embedded
reduce the SRAM cell leakage current for low stand-by power.
memories, and so on. Therefore, the SoC is required to have both
Section V shows the measurement results of the thin-BOX
higher operating performance to process various applications
FD-SOI transistor and the results of circuit simulation of newly
and lower power consumption to prolong the battery life. To ac-
developed high-operating margin and low-leakage SRAM
quire the best performance, voltage scaling along with process
circuits. Section VI concludes this paper.
scaling is effective.
However, to continue the voltage scaling is now very difficult II. THIN-BOX FD-SOI TRANSISTOR
because of the difficulty of the SRAM operation. The SRAM Fig. 1 shows a cross-sectional view of a thin-BOX FD-SOI
cell is composed of the smallest size MOS transistors, which transistor. This transistor has an ultrathin SOI thickness
are heavily influenced by the growing manufacturing-process nm and an ultra-thin BOX thickness nm .
fluctuations [1]. Therefore, SRAM has many obstacles to over- This transistor is expected to be a low- variation device.
come to achieve low-voltage operation, such as reductions in The FD-SOI structure controls the local component of
the static-noise margin (SNM) [2], writing margin [3], and op- variation by almost completely eliminating the variation due
erating speed. The reduction in the operating margins is caused to channel-dopant distribution. A Ni-silicide gate (mid-gap
by the threshold-voltage mismatch between the transis- work-function metallic gate) and deep impurity doped under
tors in one memory cell. The deterioration in the SRAM oper- channel are used to give the device a suitable value for
ating speed is caused by the reduction in the SRAM-cell current, use in low-power circuits. The substrate is doped by means of
which is imposed by the reduction in the supply voltage and the implantation through ultrathin SOI and BOX are used. The
increase in the random variations with the advance of the is mainly determined by the work function of the metal gate;
process scaling. this reduces the effects of fluctuation in , , and and
thus controls the global component of the variation.
The other important feature of this thin-BOX FD-SOI tran-
Manuscript received February 18, 2006; revised June 23, 2006. sistor is the back-gate-bias controllability. Because the BOX
The authors are with the Central Research Laboratory, Hitachi Ltd., Tokyo
185-8601, Japan (e-mail: yamaokam@crl.hitachi.co.jp). layer is very thin, can be controlled by changing the voltage
Digital Object Identifier 10.1109/JSSC.2006.882891 of the well layer (back gate) under the BOX layer. This effect
0018-9200/$20.00 © 2006 IEEE
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YAMAOKA et al.: SRAM CIRCUIT USING THIN-BOX FD-SOI TRANSISTORS 2367
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2368 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006
accessed columns are forward-biased, and the of TrMOS improvement of the read and write margins. On the write cycle,
and DrMOS is lowered. Moreover, the back-gate bias of the at first the clock signal (CLK) arises, the word line (WL), the
LdMOS returns to the no-bias state, and its is raised. column-select signal (y[0]) and the bit-write signal (bwen) are
These states are suitable for write operation, because the activated, and a new data information is put to the bit-line pair
write current from the memory-cell storage node to the bit (BLT, BLB). The bwen signal is activated when a new piece of
line (BLT, BLB) is large, and the data keeping current flowing data is written to the column. The back gates of the memory
through the LdMOS is small. Therefore, the write operating cells in the accessed columns are controlled by the y[0] and
margin is improved. Moreover, the cell current flowing through the bwen, and then the condition of the memory cells changed
the TrMOS is large, and the operating speed increases. On to the state to which a new data is easily written. The back
the other hand, in the nonaccessed column, the back-gate bias gates in the memory cells of the other (nonaccessed) columns
of the transistors is the same as that during read operations. are not controlled and the SNM (read margin) keeps high, and
Therefore, the data retention characteristics are good and are the condition of the memory cells are keeping the state that the
protected from being destroyed in the nonaccessed column. data-retention characteristics are good. On the read cycle, the
Fig. 7 illustrates the timing diagram. The ys[n] is the column- back gates in the memory cells are controlled to the state to
select signal, and the bwen is the signal that indicates that new keep the SNM high, and the data-retention characteristics are
data are written to the column. Thus, these structures enable the good.
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YAMAOKA et al.: SRAM CIRCUIT USING THIN-BOX FD-SOI TRANSISTORS 2369
Fig. 6. Voltage of the power-source node in each operating state. V. MEASUREMENT AND SIMULATION RESULTS
Fig. 8 shows a cross-sectional SEM micrograph of a fabri-
cated thin-BOX FD-SOI transistor. The thickness of BOX layer
IV. STAND-BY LOW-LEAKAGE MEMORY ARRAY is 10 nm and the thickness of SOI layer is 20 nm. The Ni-sili-
Reducing the leakage current during the stand-by state is a cide metal gate is properly produced.
very important issue for achieving a low-power SoC. In partic- Fig. 9 shows the measured of a fabricated nMOS device
ular, large memory modules that can be accessed from many as the back-gate bias is changed. The reverse back-gate bias
SoC functional blocks are required to retain their data during the raises the value, and the leakage current can be reduced. The
stand-by state. Raising the voltage of the source line of DrMOS forward back-gate bias lowers the value, and the on current
( in Fig. 4) can reduce the leakage current through the can be increased.
memory cells [6]. The higher voltages of than (ground Fig. 10 shows the simulated butterfly curves. The curves are
level) apply the back-gate bias to the nMOS transistors, and simulated by using a device-and-circuit mixed-mode simulator.
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2370 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006
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YAMAOKA et al.: SRAM CIRCUIT USING THIN-BOX FD-SOI TRANSISTORS 2371
VI. CONCLUSION
ACKNOWLEDGMENT
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memory cell size is assumed as about 0.6 m . This back-gate mada, K. Yanagisawa, and K. Osada, “A 300 MHz 25A/Mb leakage
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2372 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006
Masanao Yamaoka (M’01) was born in Fukuyama, Takayuki Kawahara (M’91–SM’98) received
Japan, in 1973. He received the B.E. and M.E. de- the B.S. and M.S. degrees in physics and the
grees in electronics and communication engineering Ph.D. degree in electronics from Kyusyu Univer-
from Kyoto University, Kyoto, Japan, in 1996 and sity, Fukuoka, Japan, in 1983, 1985, and 1993,
1998, respectively. respectively.
In 1998, he joined the Central Research Labo- In 1985, he joined Central Research Laboratory,
ratory, Hitachi Ltd., Tokyo, Japan, where he has Hitachi Ltd., Tokyo, Japan. Since then, he has made
been engaged in the research and development of fundamental contributions in many areas in the field
low-power embedded SRAM and CMOS circuits. of low-power high-speed memories. In the field
His current research interests include handling V of DRAM circuits, from 1985 to 1993, his major
variation in circuit design. contributions concerned low-power, low-voltage
circuits including subthreshold-current reduction by gate-source self-reverse
biasing technique and an over-drive sense-amplifier scheme coupled with
direct sensing. He also pioneered the charge-recycling scheme, which concept
Ryuta Tsuchiya received the B.S., M.S., and Ph.D. is now widely applied to various circuits. In the field of Flash memory,
degrees in material science from the Tokyo Institute from 1994 to 1998, he and his team developed a bit-line clamped sensing
of Technology, Tokyo, Japan, in 1993, 1995, and scheme for fast sensing, a high-voltage generator scheme under a low voltage
1998, respectively. supply, and a pioneering high-speed programming method. In addition, he
He joined the Central Research Laboratory, headed the ultralow-power system LSI project in the laboratory from 1999 to
Hitachi Ltd., Tokyo, Japan, in 1998, where he 2002. Currently, his mission is exploring a new concept memory. He was a
has been engaged in research on fabrication and Visiting Researcher with the Electronics Laboratory, Swiss Federal Institute of
characterization of high-performance and low-power Technology Lausanne, Lausanne, Switzerland, from 1997 to 1998. He was a
MOSFETs including thin-film SOI and BOX Guest Editor of the Memory section of a special issue of the IEEE JOURNAL
transistors. OF SOLID-STATE CIRCUITS in November 2002. He has been a member of
Dr. Tsuchiya is a member of the Japan Society of the ISSCC program committee since 2000 (also a member of the executive
Applied Physics. committee since 2004), and a program committee member of the Symposium
on VLSI Circuits since 2003 and Secretary of Publicity of the 2006 JFE Circuits
Symposium Committee.
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