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PARKING SYSTEM
CONTROLLER
EN2532: Digital System Design
100403N
Prathibha B.K.M
10/11/2013
Abstract: Parking spaces in Sri Lanka are mostly unorganized. When you enter such parking slot you will have
to hover around looking for a free slot. This process is troublesome and time consuming. This is This system will
give you the best parking slot promptly and since the parking space is partitioned accordingly to accommodate
this system, it will be almost hassle-free to park you vehicle.

Problem Statement
Parking slots in Sri Lanka are unorganized and finding a free slot is troublesome. This is mainly because,
The parking space management doesnt have an organized system to give available free slots.
The parking space in unordered (parking slots are not numbered).

Solution
This system suggests the management to number the parking slots.
Lower numbers should be given to parking slots which are near the exit.
This system will give an existing parking slot to the user at the entrance.

Basic Operation

The parking system management or the operator at the entrance has to give
the input1 as a vehicle enters the premises.
The vehicle will be given a token of the slot number and he will have to park
at the designated slot.
When a vehicle leaves the parking space he will have to produce the token
and that slot will be released.

Design Details

Figure1: Parking Space
Figure2: Block Diagram of the System

Inputs
Input1 This push button is the main triggering mechanism used to change the 4 bit register value.
The register is where the parking slots will be stores. The register value is 1 when there is a vehicle
in that position and 0 when that slot is free.
Input2 & Input3-These will be used to select the slot number when a vehicle leaves the parking space.
The number selected by using these two switches is displayed on the seven segment display. After
selecting the number Input1 button will be pushed to free up that slot.
Input4 This switched is up (1) when the system is used at the entrance (Vehicle entering mode).It
will be in down mode 0 when the system is used at the exit (Vehicle exiting mode).
Reset-This switch is used to reset the whole system.

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Figure3: How to give inputs to the Basys Board
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FPGA Implementation & Simulation results
The code is too lengthy so that a test bench couldnt be implemented. The modules are shown below
and the FPGA implementation is in working condition.

Modules used,
main module
main_reg module
disp_hex_mux module
debouncer module

Conclusion
This project was successful in giving a solution to the parking management in unorganized parking spaces in
Sri Lanka. Apart from that this project was very helpful in gaining the insight to the digital system design
using Verilog HDL and familiarization with Basys2 board.

References
http://www.utdallas.edu/~zhoud/EE%203120/Xilinx_tutorial_Spartan3_home_PC.pdf

Figure4: Screen shot of the Xilinx working space
1. main module

APPENDIX I: Verilog Code

module main(
input wire clk,
input wire enter,
input wire [1:0] next_out_pos,
input wire reset,
input wire set,
output wire [3:0] an,
output wire [7:0] sseg
);
wire [3:0] display_out;
wire enter_out;

main_reg main_instance
(.clk(clk) ,.enter(enter_out) ,.next_out_pos(next_out_pos), .reset(reset) ,
.set(set), .display_out(display_out) );

disp_hex_mux displayer
(.clk(clk) ,.an(an) , .sseg(sseg) , .hex0(display_out) , .hex1(4'b0) ,
.hex2(4'b0) , .hex3(4'b0), .reset(1'b0), .dp_in(4'b0) );

debouncer debouncer0
(.clk_1KHz(clk),.noisy(enter), .debounced(enter_out));

endmodule
2. main_reg module
module main_reg(
input wire clk,
input wire enter,
input wire [1:0] next_out_pos,
input wire reset,
input wire set,
output wire [3:0] display_out
);

reg [3:0] display;
reg [3:0] current_main_reg, next_main_reg;

always @(posedge enter)
current_main_reg = next_main_reg;

always @*
begin
if(set == 0)
case (next_out_pos)
2'b00 : display = 4'b0001;
2'b01 : display = 4'b0010;
2'b10 : display = 4'b0011;
2'b11 : display = 4'b0100;
endcase

case(current_main_reg)
4'b0000:
if( reset == 1)
next_main_reg = 0;
else if(set == 1)
begin
next_main_reg = 4'b0001;
display = 4'b0001;
end
else if(set == 0)
case (next_out_pos)
2'b00 : next_main_reg = 4'b0000;
endcase

4'b0001:
if( reset == 1)
next_main_reg = 0;
else if(set == 1)
begin
display = 4'b0010;
end
else if(set == 0)
case (next_out_pos)
endcase
4'b0010:
if( reset == 1)
next_main_reg = 0;
else if(set == 1)
begin
display = 4'b0001;
end
else if(set == 0)
case (next_out_pos)
endcase

4'b0011:
if( reset == 1)
next_main_reg = 0;
else if(set == 1)
begin
display = 4'b0011;
end
else if(set == 0)
case (next_out_pos)
endcase

4'b0100:
if( reset == 1)
next_main_reg = 0;
else if(set == 1)
begin
display = 4'b0001;
end
else if(set == 0)
case (next_out_pos)
endcase
4'b0101:
if( reset == 1)
next_main_reg = 0;
else if(set == 1)
begin
display = 4'b0010;
end
else if(set == 0)
case (next_out_pos)
endcase

4'b0110:
if( reset == 1)
next_main_reg = 0;
else if(set == 1)
begin
display = 4'b0001;
end
else if(set == 0)
case (next_out_pos)
endcase
4'b0111:
if( reset == 1)
next_main_reg = 0;
else if(set == 1)
begin
display = 4'b0100;
end
else if(set == 0)
case (next_out_pos)
endcase

4'b1000:
if( reset == 1)
next_main_reg = 0;
else if(set == 1)
begin
display = 4'b0001;
end
else if(set == 0)
case (next_out_pos)
endcase

4'b1001:
if( reset == 1)
next_main_reg = 0;
else if(set == 1)
begin
display = 4'b0010;
end
else if(set == 0)
case (next_out_pos)
endcase

4'b1010:
if( reset == 1)
next_main_reg = 0;
else if(set == 1)
begin
display = 4'b0001;
end
else if(set == 0)
case (next_out_pos)
endcase
4'b1011:
if( reset == 1)
next_main_reg = 0;
else if(set == 1)
begin
display = 4'b0011;
end
else if(set == 0)
case (next_out_pos)
endcase

4'b1100:
if( reset == 1)
next_main_reg = 0;
else if(set == 1)
begin
display = 4'b0001;
end
else if(set == 0)
case (next_out_pos)
endcase
4'b1101:
if( reset == 1)
next_main_reg = 0;
else if(set == 1)
begin
display = 4'b0010;
end
else if(set == 0)
case (next_out_pos)
endcase

4'b1110:
if( reset == 1)
next_main_reg = 0;
else if(set == 1)
begin
display = 4'b0001;
end
else if(set == 0)
case (next_out_pos)
endcase
4'b1111:
if( reset == 1)
next_main_reg = 0;
else if(set == 1)
begin
display = 4'b1111;
end
else if(set == 0)
case (next_out_pos)
endcase
endcase
end
assign display_out = display;

endmodule

3. disp_hex_mux module
module disp_hex_mux
(
input wire clk, reset,
input wire [3:0] hex3, hex2, hex1 , hex0,
input wire [3:0] dp_in,
output reg [3:0] an ,
output reg [7:0] sseg
);

localparam N = 18 ;

reg [N-1:0] q_reg;
wire [N-1:0] q_next;
reg [3:0] hex_in ;
reg dp;

always @(posedge clk, posedge reset )
if (reset)
q_reg <= 0;
else
q_reg <= q_next;

assign q_next = q_reg + 1;

always @*
case (q_reg [N-1: N-2])
2'b00:
begin
an = 4'b1110;
hex_in = hex0;
dp = dp_in[0] ;
end
2'b01:
begin
an = 4'b1101;
hex_in = hex1;
dp = dp_in[1] ;
end
2'b10:
begin
an = 4'b1011;
hex_in = hex2;
dp = dp_in[2];
end
default:
begin
an = 4'b0111;
hex_in = hex3;
dp = dp_in[3];
end
endcase

always @*
begin
case(hex_in)
4'h0: sseg [6:0] = 7'b0000001;
4'h1: sseg[6:0] = 7'b1001111;
4'h2: sseg [6:0] = 7'b0010010;
4'h3: sseg [6:0] = 7'b0000110;
4'h4: sseg[6:0] = 7'b1001100;
4'h5: sseg[6:0] = 7'b0100100;
4'h6: sseg [6:0] = 7'b0100000;
4'h7: sseg[6:0] = 7'b0001111;
4'h8 : sseg [6:0] = 7'b0000000;
4'h9: sseg [6:0] = 7'b0000100;
4'ha: sseg [6:0] = 7'b0001000;
4'hb: sseg [6:0] = 7'b1100000;
4 'hc: sseg [6:0] = 7'b0110001;
4'hd: sseg [6:0] = 7'b1000010;
4'he: sseg [6:0] = 7'b0110000;
default : sseg[6:0] = 7'b0111000;
endcase
sseg[7] = 1'b1;
end
endmodule

4. debouncer module

module debouncer (noisy,clk_1KHz,debounced);

input wire clk_1KHz, noisy;
output reg debounced;

reg [7:0] abc;

//reg: wait for stable
always @ (posedge clk_1KHz)
begin
abc[7:0] <= {abc[6:0],noisy}; //shift register
if(abc[7:0] == 8'b00000000)
debounced <= 1'b0;
else if(abc[7:0] == 8'b11111111)
debounced <= 1'b1;
else debounced <= debounced;
end

endmodule

APPENDIX III: Verilog ucf File

NET "an[3]" LOC = K14;
NET "an[2]" LOC = M13;
NET "an[1]" LOC = J12;
NET "an[0]" LOC = F12;
NET "sseg[7]" LOC = N13;
NET "sseg[6]" LOC = L14;
NET "sseg[5]" LOC = H12;
NET "sseg[2]" LOC = P12;
NET "sseg[1]" LOC = L13;
NET "sseg[0]" LOC = M12;
NET "next_out_pos[1]" LOC = L3;
NET "next_out_pos[0]" LOC = P11;
NET "clk" LOC = B8;
NET "enter" LOC = A7;
NET "reset" LOC = E2;
NET "set" LOC = N3;
NET "set" CLOCK_DEDICATED_ROUTE = FALSE;
NET "reset" CLOCK_DEDICATED_ROUTE = FALSE;
NET "next_out_pos[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "next_out_pos[0]" CLOCK_DEDICATED_ROUTE = FALSE;

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