Test and

Verification
Solutions
asureVIP from TVS
TVS PCIE EP VIP

Test and Verification Solutions offers a PCIE VIP as part of its
asureVIP series of offerings. This is a highly flexible and
configurable verification IP, which can be easily, integrated into
any IP Subsystem verification environment, SOC verification
environment and Emulation platforms. The TVS PCIE VIP
supports End Point mode.

The VIP comes with a Bus Monitor for performing all protocol
checks. The monitor performs protocol checks and reports
errors for non compliance with PCIE Specification reference.


FEATURES

Independently controlled egress,
ingress traffic, and support for all
types of packets.
PCIe and legacy interrupt support.
Gen1 and Gen2 support with
optional top speed as Gen1.
Support for Multiple VCs and
Multiple TCs.
RAL model for all configuration
space registers with back door
access.
Flow Control checks and ordering
rule monitors.
Full set DLLP Support.
DL Control and Management state
machine with FC initialization.
Configurable ACK frequency, FC
update frequency and update timer.
Independent LTSSM Monitor.
Auto speed negotiations.
ASPM and PCIEPM support.
Complete Ordered Set support.
Compliance and Loopback mode
support.

OVERVIEW


BLOCK DIAGRAM


SETsquared Business Acceleration
Centre,
University Gate East,
Park Row,
Bristol BS1 5UB

Tel: +44 (0)117 903 1100
Mob: +44 (0)7796 307958

sales@testandverification.com
www.testandverification.com


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SV Behavioral Model (End point)
Transaction layer agent

Link layer agent
PCIE TL
Sequencer

PCIE DL
Sequencer

PCIE Config Space Reg
TL- TLM
PCIE TL monitor
and scoreboard
Sequence
PCIE DL driver
PCIE DL monitor
and scoreboard
PIPE Interface
Physical Layer
TX RX
SerDes: Clock recovery,
PLLs and Clock gen
PCIE RC Device (DUT)
PCIE Serial
Sequence



BENEFITS

Highly Flexible, Independent
and Configurable PCIE VIP in
EP mode.
Some layers if the VIP are
synthesizable.
Can be used on Emulation
platform as well.

DELIVERABLES


VIP user Guide
PCIE VIP EP Mode
Interface to software above
transaction layer.
Traffic generator functions for
SoC level verification
Sample Testbench Integrated
with VIP
Sample Virtual Sequencer


TECHNICAL SPECIFICATION


Part Number
Description
Provider
Languages Supported
Methodology
Simulators

Compliance
Availability

asureVIP_PCIe_EP
PCIe VIP Upstream Port
Test and Verification Solutions
System Verilog, C or C++
UVM 1.1
Cadence Incisive, Mentor Questa,
Aldec Riviera-PRO
PCI Express Base Specification 2.1
September 2013

TVS delivers an independent verification service that not only
reduces your costs and time-to-market, but also improves
product quality.

TVS combines skills and experience in software testing,
hardware verification and outsourcing to provide customers with
an efficient, well-managed, quality assurance service.

TVS provides both consultancy and execution services using
experienced engineering resources in several locations around
the world. TVS removes the pain and risk from outsourcing
leaving you with just the benefits.

To learn more about our offerings, write to us at
sales@testandverification.com

ABOUT US





Test and Verification Solutions reserves the right to change this document without
prior notice and disclaim all warranties. It is the recipients duty to confirm with Test
and Verification Solutions Engineering Department specifications before proceeding
with a product design. This document is confidential and should not be reproduced
without Test and Verification Solutions approval.

asureVIP and the TVS logo are trademarks of Test and Verification Solutions.

2013 Test and Verification Solutions, Bristol, UK. All rights reserved.

April 2013 Version 1.0


asureVIP from TVS
TVS PCIE EP VIP

SETsquared Business Acceleration
Centre,
University Gate East,
Park Row,
Bristol BS1 5UB

Tel: +44 (0)117 903 1100
Mob: +44 (0)7796 307958

sales@testandverification.com
www.testandverification.com

Test and
Verification
Solutions

T

V

S