Layout Effects on Design Optimization of CMOS LNA and Mixer

Wen Wu and Mansun Chan

Department of Electrical and Electronic Engineering, Hong Kong University of Science and Technology,
Clear Water Bay, Kowloon, Hong Kong

Abstract A study on the comparison of different layout
methods on the performance of RF CMOS integrated circuits is
presented in this paper. Multi-finger and compact waffle layout
strategies are investigated in detail. Vital layout parameters,
including unit cell configuration and the conflict between finger
length and the number of fingers, are analyzed in view of the
noise figure and gate RC delay. Layout effects on CMOS LNA
and Mixer are verified through circuit simulation and fabrication
using a 0.35-m standard CMOS process.
Index Terms CMOS integrated circuits, layout, low noise
amplifier, mixer.
I. INTRODUCTION
The continuous scaling of silicon MOSFETs has
encouraged the development of RF CMOS integrated circuits
(ICs) by improving the operating speed of devices [1].
However, one drawback of the devices of very small
dimensions is the presence of relatively large parasitic RC
elements intrinsic to device structures. In the design of analog
transistors with large W/L ratio, a compact polysilicon gate
structure is usually necessary to reduce the gate resistance Rg
in order to enhance the overall performance. The most
commonly used configuration in the design of RF ICs is the
multi-finger (MF) layout. However, the tradeoff between
finger length and the number of fingers sacrifices the
optimality of this layout design. In addition, we studied
MOSFETs designed with a more compact but less traditional
waffle (WF) layout method. Besides the area saving and the
small drain/source to bulk capacitance, significant RF
performance improvement such as higher maximum
oscillation frequency (f
max
) and unity-gain frequency (f
T
) can be
achieved through careful optimization.
In this paper, the optimization and utilization of WF layout
in deep submicron technology for RF ICs are studied based
on the RF parameters of different layout strategies. We
optimize the transistors layout for low noise operation of a
single-ended LNA in which the layout parasitic effects are
also considered. A resistive RF mixer implemented with WF
MOSFETs also shows better conversion gain and higher
intermediate frequency than a similar mixer with MF layout.
II. LAYOUT OPTIMIZATION
To study different layout methodologies on RF noise
performance, two kinds of layout configuration (MF and WF
layouts) are investigated. All the small-signal parameters in
the following discussion are based on measurement extraction.
Details can be found in [2]. In this work, the polysilicon
connection type for both MF and WF layouts is one-side
contact configuration.
A. Multi-finger Layout Optimization
Conventionally, MF MOSFETs divide a device into small
parallel parts to reduce the gate resistance, resulting in an
overall gate resistance [3]:
L N
W
R
f
poly
g
2
3

= (1)
where W is the width of the device and L is the channel
length. Nf is the number of the parallel fingers. (1) indicates
that the gate resistance can be reduced by increasing Nf.
However, increasing Nf will lead to the increase of extrinsic
gate-bulk parasitic capacitance Cgb [4], which is induced by
the gate pads outside of the active area. Also, more gate-
source and gate-drain overpasses are required.

10 100
14.5
15.0
15.5
16.0
16.5
17.0
17.5
18.0
18.5
Device Width
W = 150 (m)
W = 200 (m)
W = 250 (m)
W = 300 (m)
W = 350 (m)
W = 400 (m)
f
T



(
G
H
z
)
The number of fingers
Fig. 1. Cut-off frequency for MF devices of different device width.

As shown in (2) and (3), two critical parameters f
T
and f
max

can be expressed as functions of the small-signal device
parameters, where Cgs and Cgd are the gate-source and gate-
drain capacitance, RS and Rch are the source and the channel
resistance components, respectively. Fig. 1 plots f
T
as a
function of the number of fingers. f
T
decreases with the
increasing number of fingers. As a result, there exists a peak
value of f
max
due to the tradeoff between f
T
and the gate
resistance as shown in Fig. 2. f
max
is the important figure of
0-7803-8846-1/05/$20.00 (C) 2005 IEEE 2067

(a)
(c)
(b)
(d)
expansion direction
m = 1
Source
PolySi Gate
m = 1
Drain
w
w
L
*
min. metal 1
spacing and
width
(micron rule)
clipped corner
w
w
w
w
L
*

w
S
*

w
S
*

merit (FoM) for the RF circuit design. Therefore, the number
of fingers at the peak f
max
can be treated as the optimal value.

( )
gb gd gs
m
T
C C C
g
f
+ +

2
(2)
( ) ( )
ch s g ds gd ch g T
T
R R R g C R R f
f
f
+ + + +
=
2 2
max
(3)
( )( ) ( )
ch gb gs m s g
R f C C g R R NF
2 2
min
2 / 5 . 1 2 1 + + + + =
(4)

0.1 1 10 100
0.70
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
f
m
a
x


(
G
H
z
)
freq = 2GHz
N
F
m
i
n


(
d
B
)
150 m
200 m
250 m
300 m
350 m
400 m
Finger Length (m)
18
20
22
24
26
28
30
32
34

Fig. 2. Minimum noise figure and maximum oscillation frequency
vs. finger length for MF devices of different device width.

From the noise perspective, the degradation of f
T
affects the
minimum noise figure (NF
min
). In other words, the MOS
devices are unable to suppress the input-referred noise at the
reduced f
T
and may cause the malfunction of some noise
sensitive components such as CMOS LNA in the RF
transceivers. The Noise Figure (NF) is an important indicator
of low noise applications. The NF
min
of MOSFETs can be
quantitated as (4) in which the influence of the device parasitic
resistances is considered [4]. As shown in Fig. 2, we found
that the optimal finger length (the width of the device divided
by the optimal Nf) for minimizing NF
min
at the 0.35-m
technology is around 7 m and it is independent of the total
device width. When the finger length exceeds 7 m, NF
min
is
dominated by the gate resistance regardless of the device size.
When the finger length is below 7 m, substrate effects
influence the NF
min
and NF
min
increases with the increase of Nf.
However, the finger length that maximizes f
max
is around 2.2
m. Therefore, there is a tradeoff between NF
min
minimization
and f
max
maximization in determining the optimal finger length.
B. Waffle Layout Optimization
A more compact layout structure, the WF layout, is
introduced to solve the conflict between NF
min
minimization
and f
max
maximization in choosing the finger length in the MF
layout and to improve the overall performance of RF circuits.
Two topologies of WF design are given in Fig. 3, which we
referred to as 3-by-3 Manhattan Gate (MG) (Fig. 3(a), 3(c))
and Manhattan Metal Interconnect (MI) (Fig. 3(b), 3(d)).
Other n-by-n (n>3) unit structures can also be used, depending
on the device total width of the transistor.























Fig. 3. The layout design of the compact WF MOSFET (a) MG
type; (b) MI type; (c) and (d) are zoomed center parts of (a) and (b),
respectively.

All WF MOSFETs have the same characteristic that source
and drain diffusion regions are shared by neighboring gates.
The waffle layout minimizes both the source and drain
diffusion areas. Thus, the total area of the transistor is
reduced. Compared with the MI structure, the MG layout
provides better area saving but worse design compatibility
when diagonal routing is prohibited. In this paper, we mainly
focus on the MG WF MOSFETs. For the MG type of WF
MOSFETs, the gate and the current flow direction are aligned
to the design grid while the metal lines are rotated by 45
degrees. Also, the corners of the metal square which overlaps
the contact holes are clipped to achieve the minimum line
spacing possible, as shown in Fig. 3(c). Therefore, the design
of compact WF MOSFETs is subject to the design rules of
different technologies and the compactness of WF MOSFETs
is actually limited by the metal line spacing.
One drawback of using WF MOSFETs is that the width of
the MOSFETs is restricted to some discrete values. However,
this limitation can be overcome by proper circuit design.
The method used to analyze WF MOSFETs is similar to
that used in the study of MF MOSFETs. The structure with n-
2068

by-n (n > 3) unit cell configuration consists of fewer unit cells
than 3-by-3 MG WF MOSFETs of the same width in
constituting a MOS device. The n-by-n (n > 3) structure is
similar to the MF case with long fingers. Similarly, a WF
MOSFET of n-by-n (n > 3) feature causes a smaller influence
of the gate parasitic components on f
T
. However, WF
MOSFETs with n > 3 become less compact and Rg also
increases. As shown in (3), f
max
is correlated with Rg.
Therefore, the 3-by-3 structure offers the largest f
max
among
all n-by-n configurations. Also, the estimation of NF
min
for the
WF MOSFETs is based on (4). With the increase of n, Rg
increases and Cgb decreases at the same device width, and
therefore the NF
min
for all WF MOSFETs are nearly the same
for different n. As a result, the MG WF MOSFETs of 3-by-3
configuration are the optimal WF layout structure.
III. COMPARISON BETWEEN MF AND WF MOSFETS
To compare the RF characteristics of MF and WF
MOSFETs, the device dimensions of both MOSFETs are
chosen to give the same minimum noise figure. For the device
width around 200 m, the WF MOSFET with 3-by-3 structure
provides the optimal overall performance. In the MF layout
case, the optimal finger length for NF
min
is corresponding to
24 fingers.
Table I summarizes the values of NF
min
, f
T
and f
max
for the
MF and WF MOSFETs. All the device structures are
optimized for the minimum noise performance. Compared
with the 24-finger MF device, the 3-by-3 WF MOSFET gives
a higher f
max
by about 18 % and also a slightly higher f
T
.

TABLE I
SUMMARY OF DEVICE PERFORMANCE COMPARISON
Parameters for Comparison
Device
topology
MF
3-by-3
WF
4-by-4
WF
5-by-5
WF
NF
min
(dB) 0.779 0.753 0.760 0.770
f
T
(GHz) 17.9 18.21 18.22 18.25
f
max
(GHz) 27.2 32.1 27.4 23.9

IV. CIRCUIT DEMONSTRATION
To study the performance of WF and MF MOSFETs in
actual circuit applications, a single-ended CMOS LNA and a
RF passive mixer consisting of four NMOSFET switches in a
bridge configuration were implemented.
The low Q factors of on-chip passive components make the
noise reduction extremely important for the noise sensitive
circuits. Fig. 4(a) shows the schematic of an inductively
degenerated single-ended LNA. Comparison of the impacts of
different layout methods on the LNA is made through the
simulation in Cadence SpectreRF based on the physically
extracted device parameters [2]. The device widths of M
1
and
M
2
in the schematic of LNA are both 200 m. The width of
M
3
is set to 3.6 m for low-power consideration. The channel
length of all MOSFETs is 0.35 m. All the parasitic
resistances induced by on-chip inductors are taken into
account and the influence of the gate resistance Rg is also
considered during simulation.


(a)

4.6 4.8 5.0 5.2 5.4 5.6 5.8
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
4.4
S
1
1


(
d
B
)
LNA with WF MOSFETs
LNA with MF MOSFETs
N
o
i
s
e

F
i
g
u
r
e


(
d
B
)
Frequency (GHz)
-40
-35
-30
-25
-20
-15
-10
-5


(b)

Fig. 4. Inductively degenerated single-ended LNA (a) Schematic;
(b) Comparison of noise figure and S
11
for MF and WF LNAs.

The simulation results are shown in Fig. 4(b). The LNA
consisting of MF devices (M
1
, M
2
and M
3
) suffers a larger
noise figure at the desirable frequency 5.2 GHz, although the
optimal device structure for minimum noise performance is
chosen. For the LNA in Fig. 4(a), the derived noise factor is:
2
2 0
1
3
2
1
m S
m
S
g
G Z
g
Z
R R R
F +
+ +
+ = (5)
M
1

M
2

M
3

L
2

L
0

L
1

R
2

R
1

R
3

R
0

V
DD

Out
In
R
4

C
0
2069

( )
in S
Cgs
m m
Z Z
Z
g G
+
= (6)
F NF log 10 = (7)

where G
m
is the transconductance of LNA R-L-C network at
resonance [5]. Z
S
is 50 Ohm and Z
in
is equal to Z
S
when input
power matching is achieved. Compared with the amplifier
constructed by the WF MOSFETs, large Rg of MF MOSFETs
introduces more thermal noise into the LNA when both of
them achieve good power matching in the input port. In
addition, the larger f
T
of the WF MOSFET helps to suppress
the undesirable noise with the same power gain. As a result, at
least 0.3 dB reduction in the noise figure has been obtained
when applying the WF layout method instead of the MF
counterpart in the LNA design.










(a) (b)

Fig. 5. The RF passive mixer implemented with WF MOSFETs.
(a) Layout; (b) Schematic. (The size of the four n-type MOSFETs in
the mixer is W/L = 430m/0.35m).


TABLE II
MEASUREMENT RESULTS OF THE RF MIXER

A RF passive mixer was fabricated with the 0.35 m CMOS
standard technology to further verify the advantage of the WF
layout applied in RF circuits. Fig. 5 shows the layout of the
mixer and its schematic. The width of all MOSFETs in the
mixer is 430 m with the minimum channel length of 0.35
m. The measurement results of this resistive mixer are listed
in Table II. Compared with a similar Mixer [6] implemented
with MF MOSFETs, the mixer consisting of WF MOSFETs
achieves a better conversion gain at a higher IF bandwidth,
higher linearity and better isolation.

V. CONCLUSION
This paper studies the effects of different layout methods in
the device design and the influence on the performance of RF
ICs. A multi-finger (MF) structure and a more compact WF
layout strategy were investigated in detail. The advantages of
WF layout devices have been revealed especially in low-noise
optimization when applied in circuits. A passive RF mixer was
implemented with 0.35-m technology and demonstrates an
improvement in performance due to the layout optimization.
The accurate simulation further exhibits that at least 0.3 dB
reduction in the noise figure can be achieved when the WF
layout, instead of MF layout, is applied in the CMOS LNAs.
ACKNOWLEDGEMENT
This work is sponsored by a Competitive Earmarked
Research Grant HKUST6189/01E from the Research Grant
Council of Hong Kong.
REFERENCES
[1] P. H. Woerlee, M. J. Knitel, R. V. Langevelde, D. B. M.
Klaassen, L. F. Tiemeijer, A. J. Scholten, and A. T. A.
Duijnhoven, RF-CMOS performance trends, IEEE Trans.
Electron Devices, vol. 48, no. 8, pp. 1776, August 2001.
[2] W. Wu, S. Lam, P. K. Ko and M. Chan, High frequency
characteristics of MOSFETs with compact waffle layout, 34
th

ESSDERC, pp. 381, September 2004.
[3] X. Jin, J. Ou, C. Chen, W. Liu, Deen M.J, Gray P.R, and C. Hu,
An effective gate resistance model for CMOS RF and noise
modeling, IEDM '98 Technical Digest., pp. 961, December
1998.
[4] E. Morifuji, H. S. Momose, T. Ohguro, T. yoshitomi, H.
Kimijima, F. Matsuoka, M. Kinugawa, Y.Katsumata, and H.
Iwai, Future perspective and scaling down roadmap for RF
CMOS, IEEE VLSI Symposium, pp. 165, 1999.
[5] D. K. Shaeffer and T. H. Lee, A 1.5V, 1.5-GHz CMOS low
noise amplifier, IEEE J. of Solid-state Circuits, vol. 31, pp.
745, May 1997.
[6] A. R. Shahani, D. K. Shaeffer and T. H. Lee, A 12-mW wide
dynamic range CMOS front-end for a portable GPS receiver,
IEEE J. of Solid-state Circuits, vol. 32, pp. 2061, December
1997.

RF Frequency 1.6GHz
LO Frequency 1.4GHz
IF Bandwidth 200MHz
LO Power 2.5dBm
LO DC Bias 0.37V
Voltage Conversion Gain -0.1dB
IP3 (Input) 9dBm
1-dB Compression (Input) -7dBm
LO-IF Isolation -29.4dB
RF-IF Isolation -16.2dB
LO-RF Isolation -21.2dB
LO
-
RF
+
RF
-
LO
+
IF
+

IF
-

LO
+
IF
+
RF
+

LO
-

IF
-
RF
-

Gnd Gnd
2070