DESIGN OF A FULLY DIFFERENTIAL HIGH-SPEED

HIGH-PRECISION AMPLIFIER


Mayank Gupta N. V. Girish
mayank@ee.ucla.edu envy@ee.ucla.edu

Design I. Design II.

University of California, Los Angeles

EE215A Term Project Report
Professor B. Razavi, Fall 2001





Abstract: We have designed a fully differential high-speed high-precision amplifier with a fixed gain of 8. Our
two design criterion were that of (a) using a power budget of 20mW minimizing the settling time and (b) to
target a 0.5% large-signal settling time of 20ns, with the aim to minimize the power consumption. Our Circuit
achieves a differential output swing of 2Volts, with a power supply of 3V. Internally the amplifier is a folded-
cascode stage and uses common mode feedback, to stabilize the output. Simulation with Cadence Spectre
have been included in the term report.












I. Design Description and Overview
The design required that two versions of a fully differential high-precision amplifier be made with the aim of
minimizing the power consumption and minimizing the settling time. The specifications that both versions had
to satisfy are given below:

Supply (V
dd
) 3V
Gain 8
Differential Output Swing 2V
Load Capacitance 1pF
Gain Error 1%
Settling Accuracy 0.5%
Power Dissipation 20mW
Settling time Minimum
Table 1: Design Specifications 1

Supply (V
dd
)

3V
Gain 8
Differential Output Swing 2V
Load Capacitance 1pF
Gain Error 1%
Settling Accuracy 0.5%
Power Dissipation Minimum
Settling time 20ns
Table 2: Design Specification 2
In order to get a gain of 8, a capacitive feedback network has been used. This configuration is shown below:


Figure 1: Amplifier with feedback network


II. Topology Selection
The first step in designing the amplifier is to choose a stage that could provide the appropriate gain. Since the
gain error was specified as 1%, we calculate the open loop gain of the amplifier as follows:

+
+ =
Gain Openloop
Gain
Gain
Vin
Vout
_
1
1 =8

This implies that the open loop gain should be roughly 900, which is of the order of (g
m
r
o
)
2
. Keeping this in
mind we can get this level of gain from a single Cascode or Telescopic stage. The voltage swing in a Telescopic
stage is limited to 2[V
DD
- (2*PMOS Overdrives + 3*NMOS Overdrives)] and as the design constraints specify
a output differential swing of 2 Volts, we chose a Folded Cascode topology. In order to make the output
common mode level more stable to voltage fluctuations, common mode feedback was used to fix the input and
output common mode voltage to V
DD
/2. The circuit topology used in the design is shown in the next page and
the various design tradeoffs will be discussed in the succeeding sections.
III. Design Trade-Offs

In both the design approaches the following tradeoffs were observed:
(a) The CM feedback transistors M12 and M13 always introduced some parasitic capacitances, reducing the
gain and bandwidth of the op-amp.
(b) Since the CM voltage was set to 1.5Volts, the overdrive of the transistors M5, M6, M1, M2, M11, M12 and
M13 was constrained. This precondition forced these transistors to have relatively higher widths than the rest of
the transistors in the circuit. This problem was very exaggerated for the case of M12 and M13 since they had to
be operated in deep triode region, with low over drives and their widths could not be increased beyond a certain
limit since it lowered the output impedance of the Op-Amp.


Figure 2: Amplifier Topology with common mode feedback

Figure 3. Biasing Circuit with parasitics

Both the design approaches used the above circuit-biasing network. This circuit also includes the various
parasitics associated with the feedback , load and input capacitors.

IV. Realization of Design Target 1:
Maximum Power Usage (20mw) with aim to Minimize the Settling Time.

With a total allowed current of 6.6mAmp, the circuit was designed to have the least settling time possible.
The circuit had an Open Loop gain of 1.385K and a Bandwidth of 2.893Mhz. The device sizes and the other
related values for our final design are as given below.

Differential Amplifier Description:

Device Description Type W/L(m/m) Current(A) g
m
(mS)
r
o

M0
Reference for Common
Mode Feedback
N 10.88/0.5 100 0.15 605.4
M1,M2
Input Differential pair
N 449/1 1457 11.38 1524.8
M3,M4
PMOS Cascode Devices
P 415.2/1 1500 7.04 710.3
M5,M6
Current Sources for the
folded cascode
P 452/0.5 2957 16.91 146.5
M7,M8
NMOS Upper Cascode
Loads
N 126.36/1 1500 5.88 746
M9,M10
NMOS Lower Cascode
Loads
N 88.43/0.5 1500 8.01 254.8
M11
Tail Current Source for
Input Differential Pair
N 298.68/0.5 2914 20.32 98.3
M12,M13
Common Mode
Feedback Pair
N 163/0.5 1457 2.16 40.2
Mb1
Bias reference & mirror
for M11
N 8.96/0.5 100 0.70 11032
Mb2
Bias reference & mirror
for M5, M6
P 40.6/0.5 100 0.57 11996
Mb3
Bias reference & mirror
for M9, M10
N 5.1/0.5 100 0.53 11743


The values of the various capacitances and resistors used for this configuration where as follows
Feedback Circuit:
Device Description Values
C1, C2 Input Capacitance 7.2pF
C3, C4 Feedback Capacitance 0.9pF
C
par1
, C
par2
Parasitic Capacitance 1.44pF
C
par3
, C
par4
Parasitic Capacitance 180f F
C
load
Load Capacitance 1pF
R1, R2 Feedback resistors
1G

Under these device values the circuit had the following specifications for DC bias
V
reference
=1.5V
V
out1
=V
out2
=1.501V
Vb1=1.8V
Vb2=1.15V
Differential Output Swing =2V
Gain Error= 0.97%
Settling time =7.26nS
Power consumed = 19mW

V. Realization of Design Target 2:
0.5% Settling time (20ns) with Minimum Power Dissipation

The folded cascode differential amplifier topology (Figure 2) was used to achieve this design to minimize the
power dissipation and limit the settling time to 20ns. The device dimensions, currents and bias voltages were
chosen to give a high open loop ac gain so as to achieve the gain error specification (Gain Error<1%). The
differential amplifier was then embedded in a closed loop feedback circuit as shown in Figure 3 and the
differential output was simulated to achieve the settling time specification for maximum output swing (2V).

Differential Amplifier Description:
Device Description Type W/L(m/m) Current(A) g
m
(mS)
r
o

M0
Reference for Common
Mode Feedback
N 5.86/0.5 100 0.156 1.16K
M1,M2
Input Differential pair
N 117.54/0.5 303.45 each 4.75 6.42K
M3,M4
PMOS Cascode Devices
P 127.61/0.5 332 each 3.17 2.70K
M5,M6
Current Sources for the
folded cascode
P 111.6/1 635.4 each 2.32 0.948K
M7,M8
NMOS Upper Cascode
Loads
N 10/0.5 332 each 1.35 3.32K
M9,M10
NMOS Lower Cascode
Loads
N 81.6/1 332 each 2.2 1.19K
M11
Tail Current Source for
Input Differential Pair
N 65.3/0.5 606.9 4.36 0.55K
M12,M13
Common Mode
Feedback Pair
N 17.77/0.5 303.45 each 0.47 0.38K
Mb1
Bias reference & mirror
for M11
N 9.32/0.5 100 0.72 11.14K
Mb2
Bias reference & mirror
for M5, M6
P 16.34/1 100 0.36 13.96K
Mb3
Bias reference & mirror
for M9, M10
N 23.3/1 100 0.65 11.06K
Additional Design Tradeoffs:

In the process of the design to achieve the required specifications, the following tradeoffs were observed in
addition to the ones discussed above:
Power Dissipation vs. Device Dimensions: As the power dissipation was increased, the settling time
correspondingly decreased, but at the expense of introduction of device capacitances which arose
because of the need to increase the gain in order to decrease the gain error.
Settling Time vs. Device Dimensions vs. Gain: To increase the gain, device dimensions of input
differential pair (M1, M2), cascode current sources (M5, M6) and the loads (M7, M8, M9, M10) were
increased. This increased the gain but also increased the settling time due to introduction of device
capacitances at the output.
Gain vs. Input Impedance: Increase in the device dimensions of the input differential pair devices
increased the gain and also the input capacitance, thus reducing the input impedance.

Figure 6 shows the open loop ac gain magnitude and phase response of the differential amplifier.
Figure 7 shows the 0.5% settling time of 20ns with minimum power dissipation.

Feedback Circuit:
Figure 3 shows the feedback topology used for the design. The component values are given in the following
table.
Device Description Values
C1, C2
Input Capacitance
2.4pF
C3, C4
Feedback Capacitance
0.3pF
C
par1
, C
par2

Parasitic Capacitance
0.48pF
C
par3
, C
par4

Parasitic Capacitance
60fF
C
load

Load Capacitance
1pF
R1, R2
Feedback resistors
1G
For the differential amplifier and the feedback circuit, the DC bias conditions are as follows:
V
reference
=1.5V
V
out1
=V
out2
=1.5V
Vb1=1.8V
Vb2=1.15V
Differential Output Swing =2V
Gain Error= 0.995%
Settling time =20.1nS
Minimum Power Dissipation achieved = 4.71mW

VI. Simulation Procedure used for both designs:
Open Loop AC response: The input to the differential pair was given as a combination of a DC source
with a CM level of 1.5V in addition to a sinusoid of amplitude 1V. The sinusoids applied to the 2 inputs
were 180 degrees out of phase.
Settling time: Two pulses of amplitude 0.125 and 0.125 volts (with rise time=fall time=0.1ns, pulse
width=1s, period=2s) were applied to the non-inverting and inverting terminal of the feedback circuit
respectively with the initial condition at Vout1=2V and Vout2=1V. The difference Vout2-Vout1 was
then plotted versus time to observe the settling time.

References
[1] B.Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill 2001
[2] S.Rabii and B.A. Wooley, A 1.8V Digital-Audio Sigma-Delta Modulator in 0.8-m CMOS, IEEE J. of
Solid-State Circuits,vol .32 ,pp. 783-796,June 1997.

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