Vedic Mathematics is the name given to the ancient system of Indian

Mathematics which was rediscovered from the Vedas between 1911 and 1918
by Sri Bharati Krsna Tirthaji (1884-1960). According to his research all of
mathematics is based on sixteen Sutras, or word-formulae. For example,
'Vertically and Crosswise` is one of these Sutras. These formulae describe the
way the mind naturally works and are therefore a great help in directing the
student to the appropriate method of solution.
This unifying quality is very satisfying, it makes mathematics easy and
enjoyable and encourages innovation.
Vedic mathematics sutras (principles) 16
1.By one more than the one before.
2.All from 9 and the last from 10
3.Vertically and Cross-wise
4.Transpose and Apply
5.If the Samccaya is the same it is !ero
6.If one is in "atio the other is #ero
7.By addition and by Sbstraction
8.By the completion or $on-completion
9.%i&erential Calcls.
10. By the %e'ciency
11. Speci'c and (eneral
12. The remainders by the last di)it
13. The ltimate and Twice the *enltimate
14. By one less than the one before
15. The prodct of the sm
16. All the mltipliers.
The system is based on 16 sutras or aphorisms, such as: "by one more than the one
before" and "all from nine and the last from 10". These describe natural processes in the
mind and ways of solving a whole range of mathematical problems. For eample, if we
wished to subtract !6" from 1,000 we simply apply the sutra "all from nine and the last
from 10". #ach figure in !6" is subtracted from nine and the last figure is subtracted
from 10, yielding "$6.
The sutra "vertically and crosswise" has many uses. %ne very useful application is
helping children who are having trouble with their tables above !!. For eample &'. &
is $ below the base of 10, and ' is ( below the base of 10.
The sutra "vertically and crosswise" is often used in long multiplication. )uppose we
wish to multiply
$( by "". *e multiply vertically ("+'.
Then we multiply crosswise and add the two results: $","(+(0, so put down 0 and
carry (.
Finally we multiply vertically $"+1( and add the carried ( +1". -esult: 1,"0'.
Books:
.#/01 23T4#23T01)
%r )iteen )imple 2athematical Formulae from the .edas The original introduction to
.edic 2athematics.
3uthor: 5agadguru )wami )ri 6harati 7rsna Tirtha8i 2ahara8a,
196! :various reprints;.
<aperbac=, $6& pages, 3! in si>e.
0)6? '1 (0' 016$ 6 :cloth;
0)6? '( (0' 016$ " :paper;@p
23T4) %- 23A01B
This is a popular boo= giving a brief outline of some of the .edic 2athematics methods.
3uthor: 5oseph 4owse. 19&6
0)6? 0&(("01"$"
1urrently out of print.@p
.#/01 23T4#23T01)
2aster 2ultiplication tables, division and lots moreC
*e recommed you chec= out this eboo=, itDs pac=ed with tips,
tric=s and tutorials that will boost your math ability, guaranteedC
www.vedicEmathsEeboo=.com
3 <##< 0?T% .#/01 23T4#23T01)
2ainly on recurring decimals.
3uthor: 6 - 6aliga, 19&9.
<amphlet.@p
0?T-%/F1T%-G H#1TF-#) %? .#/01 23T4#23T01)
Following various lecture courses in Hondon an interest arose for printed material
containing the course material. This boo= of 1( chapters was the result covering a
range topics from elementary arithmetic to cubic eIuations.
3uthors: 3. <. ?icholas, 5. <ic=les, 7. *illiams, 19'(.
<aperbac=, 166 pages, 3" si>e.@p
/0)1%.#- .#/01 23T4#23T01)
This has siteen chapters each of which focuses on one of the .edic )utras or subE
)utras and shows many applications of each. 3lso contains .edic 2aths solutions to
A1)# and D3D level eamination Iuestions.
3uthor: 7. *illiams, 19'", 1omb bound, 1'0 pages, 3".
0)6? 1 '699$( 01 $.@p
.#-T013HHG 3?/ 1-%))*0)#
This is an advanced boo= of siteen chapters on one )utra ranging from elementary
multiplication etc. to the solution of nonElinear partial differential eIuations. 0t deals with
:i; calculation of common functions and their series epansions, and :ii; the solution of
eIuations, starting with simultaneous eIuations and moving on to algebraic,
transcendental and differential eIuations.
3uthors: 3. <. ?icholas, 7. *illiams, 5. <ic=les
first published 19'";, new edition 1999. 1omb bound, (00 pages, 3".
0)6? 1 90(!1& 0$ (.@p
ONE MORE THAN THE ONE BEFORE
3 Iuic= way to sIuare numbers that end in ! using
the formula 6G %?# 2%-# T43? T4# %?# 6#F%-#.
75
2
= 5625
&!J means &! &!.
The answer is in two parts: !6 and (!.
The last part is always 25.
The first part is the first number, &, multiplied
by the number "one more", which is ':
so & ' + 56
)imilarly 85
2
= 7225 because ' 9 + &(.
#ercise 1 Tutorial "
Try these:
1) "!
(
+
2) 6!
(
+
3) 9!
(
+
4) $!
(
+
/oes " divide evenly into 1($"B
For 4 to divide into an n!"#er $e %ave
to "a&e '!re t%at t%e (a't n!"#er i' even
0f it is an odd number, there is no way it will go in evenly.
)o, for eample, " will not go evenly into 1($$ or 1($!
?ow we =now that for " to divide evenly into any
number the number has to end with an even number.
6ac= to the Iuestion...
" into 1($", the solution:
Ta&e t%e (a't n!"#er and add it to 2 ti"e' t%e 'e)ond (a't n!"#er
0f " goes evenly into this number then you =now
that " will go evenly into the whole number.
)o
" , :( K $; + 10
" goes into 10 two times with a remainder of ( so it does not go in evenly.
Therefore " into 1($" does not go in completely.
HetLs try " into $"$6!"6
)o, from our eample, ta=e the last number, 6 and add it to
two times the penultimate number, "
6 , :( K "; + 1"
" goes into 1" three times with two remainder.
)o it doesnDt go in evenly.
HetDs try one more.
" into (1($$""$6
6 , :( K $; + 1(
" goes into 1( three times with 0 remainder.
Therefore " goes into ($""$6 evenly.
Vedic Mathematics is a super fast way of
calculation whereby you can do
supposedly complex calculations like 998
x 997 in less than fve seconds at! "t is
hi#hly benefcial for school and colle#e
students and students who are appearin#
for their entrance examinations!
Vedic Mathematics is far more
systematic$ simplifed and unifed than
the conventional system! "t is a mental
tool for calculation that encoura#es the
development and use of intuition and
innovation$ while #ivin# the student a lot
of exibility$ fun and satisfaction ! %or
your child$ it means #ivin# them a
competitive ed#e$ a way to optimi&e their
performance and #ives them an ed#e in
mathematics and lo#ic that will help them
to shine in the classroom and beyond!
'herefore it(s direct and easy to
implement in schools ) a reason behind
its enormous popularity amon#
academicians and students!
"t complements the Mathematics
curriculum conventionally tau#ht in
schools by actin# as a powerful checkin#
tool and #oes to save precious time in
examinations!'he methods * techni+ues
are based on the pioneerin# work of late
,wami ,hri Bharati -rishna 'irtha.i$
,ankracharya of /uri$ who established the
system from the study of ancient Vedic
texts coupled with a profound insi#ht into
the natural process of mathematical
reasonin#!
'here are .ust 01 ,utras or %ormulae which
solve all known mathematical problems in
the branches of 2rithmetic$ 2l#ebra$
3eometry and 4alculus! 'hey are easy to
understand$ easy to apply and easy to
remember!
Vedic Mathematics is the
worlds fastest way of making all
your maths calculations easy.


It is an ancient system of mathematics which was rediscovered
from the Vedas between 1911 & 1918 by Shri Bharti Kishna
Tirthaji (188!19"#$. %ccording to his research& all of Mathematics
is based on 1" 'utras or (ord )ormulae.
Benefits of Vedic Maths
Eliminates math-phobia.
Increases speed and accuracy.
More systematic, simplified, unified & faster than the conventional system.
*ives the student flexibility, fun and
immense satisfaction
% powerful checking tool.
a!es precious time in e+aminations.
*ives the student a competiti!e edge.
,evelo-s .eft & /ight 'ides of the brains
by increasing !isuali"ation and
concentration abilities.
V567
"ntroduction
Verilo# is a 5286928: 6:,48"/'";< 72<3=23: >567?! 2
hardware description lan#ua#e is a lan#ua#e used to describe
a di#ital system: for example$ a network switch$ a
microprocessor or a memory or a simple ip@op! 'his .ust
means that$ by usin# a 567$ one can describe any >di#ital?
hardware at any level!
0 AA 6 ip@op 4ode
B module dCD > d$ clk$ +$ +Cbar?E
F input d $clkE
G output +$ +CbarE
H wire d $clkE
1 re# +$ +CbarE
7
8 always I >posed#e clk?
9 be#in
0J + KL dE
00 +Cbar KL M dE
0B end
0F
0G endmodule
;ne can describe a simple %lip op as that in the above f#ure$ as
well as a complicated desi#n havin# 0 million #ates! Verilo# is one of
the 567 lan#ua#es available in the industry for hardware desi#nin#!
"t allows us to desi#n a 6i#ital desi#n at Behavior 7evel$ 8e#ister
'ransfer 7evel >8'7?$ 3ate level and at switch level! Verilo# allows
hardware desi#ners to express their desi#ns with behavioral
constructs$ deferrin# the details of implementation to a later sta#e
in the fnal desi#n!
The Verilog Hardware Description Language, usually just called Verilog, was designed and first
implemented by Phil Moorby at Gateway Design utomation in !"#$ and !"#%& 't was first used
beginning in !"#% and was e(tended substantially through !"#)& The implementation was the
Verilog*+L simulator sold by Gateway
Hi'tor O* +eri(o,
.erilog was started initially as
a proprietary hardware
modeling language by
Aateway /esign 3utomation
0nc. around 19'". 0t is
rumored that the original
language was designed by
ta=ing features from the most
popular 4/H language of the
time, called 4iHo, as well as
from traditional computer
languages such as 1. 3t that
time, .erilog was not
standardi>ed and the
language modified itself in
almost all the revisions that
came out within 19'" to
1990.

.erilog simulator was first
used beginning in 19'! and
was etended substantially
through 19'&. The
implementation was the
.erilog simulator sold by
Aateway. The first ma8or
etension was .erilogEKH,
which added a few features
and implemented the
infamous "KH algorithm"
which was a very efficient
method for doing gateElevel
simulation.

The time was late 1990.
1adence /esign )ystem,
whose primary product at
that time included Thin film
process simulator, decided to
acIuire Aateway 3utomation
)ystem. 3long with other
Aateway products, 1adence
now became the owner of the
.erilog language, and
continued to mar=et .erilog
as both a language and a
simulator. 3t the same time,
)ynopsys was mar=eting the
topEdown design
methodology, using .erilog.
This was a powerful
combination.

0n 1990, 1adence recogni>ed
that if .erilog remained a
closed language, the
pressures of standardi>ation
would eventually cause the
industry to shift to .4/H.
1onseIuently, 1adence
organi>ed the %pen .erilog
0nternational :%.0;, and in
1991 gave it the
documentation for the .erilog
4ardware /escription
Hanguage. This was the
event which "opened" the
language.

%.0 did a considerable
amount of wor= to improve
the Hanguage -eference
2anual :H-2;, clarifying
things and ma=ing the
language specification as
vendorEindependent as
possible.

)oon it was reali>ed that if
there were too many
companies in the mar=et for
.erilog, potentially everybody
would li=e to do what
Aateway had done so far E
changing the language for
their own benefit. This would
defeat the main purpose of
releasing the language to
public domain. 3s a result in
199", the 0### 1$6" wor=ing
group was formed to turn the
%.0 H-2 into an 0###
standard. This effort was
concluded with a successful
ballot in 199!, and .erilog
became an 0### standard in
/ecember 199!.

*hen 1adence gave %.0 the
H-2, several companies
began wor=ing on .erilog
simulators. 0n 199(, the first
of these were announced,
and by 199$ there were
several .erilog simulators
available from companies
other than 1adence. The
most successful of these was
.1), the .erilog 1ompiled
)imulator, from 1hronologic
)imulation. This was a true
compiler as opposed to an
interpreter, which is what
.erilogEKH was. 3s a result,
compile time was substantial,
but simulation eecution
speed was much faster.

0n the meantime, the
popularity of .erilog and <H0
was rising eponentially.
.erilog as a 4/H found more
admirers than wellEformed
and federally funded .4/H. 0t
was only a matter of time
before people in %.0 reali>ed
the need of a more
universally accepted
standard. 3ccordingly, the
board of directors of %.0
reIuested 0### to form a
wor=ing committee for
establishing .erilog as an
0### standard. The wor=ing
committee 1$6" was formed
in mid 199$ and on %ctober
1", 199$, it had its first
meeting.

The standard, which
combined both the .erilog
language synta and the <H0
in a single volume, was
passed in 2ay 199! and now
=nown as 0### )td. 1$6"E
199!.

3fter many years, new
features have been added to
.erilog, and the new version
is called .erilog (001. This
version seems to have fied
a lot of problems that .erilog
199! had. This version is
called 1$6"E(001.
"ntroduction to 5ello 9orld example
0f you refer to any boo=
on programming
languages, it starts
with an "4ello *orld"
programM once you
have written it, you can
be sure that you can
do something in that
language .

*ell 0 am also going to show how to write a -%e((o
$or(d- program, followed by a -)o!nter- design, in .erilog.

He((o .or(d /ro,ra"

1 0011111111111111111111111111111111111111111111111111111
2 00 T%i' i' " *ir't +eri(o, /ro,ra"
3 00 2e'i,n Na"e 3 %e((o4$or(d
4 00 Fi(e Na"e 3 %e((o4$or(d.v
5 00 F!n)tion 3 T%i' 5ro,ra" $i(( 5rint 6%e((o $or(d6
6 00 7oder 3 2ee5a&
7 0011111111111111111111111111111111111111111111111111111
8 "od!(e hello_world ;
9
10 initia( #e,in
11 8di'5(a (-He((o .or(d # 2ee5a&-);
12 91: 8*ini'%;
13 end
14
15 end"od!(e 00 End o* Mod!(e %e((o4$or(d
Gou could download file helloNworld.v here

*ords in green are comments, blue are reserved words.
3ny program in .erilog starts with reserved word DmoduleD
OmoduleNnameP. 0n the above eample line ' contains
module helloNworld. :?ote: *e can have compiler preE
processor statements li=e QincludeD, QdefineD before module
declaration;

Hine 10 contains the initial bloc=: this bloc= gets eecuted
only once after the simulation starts, at time+0 :0ns;. This
bloc= contains two statements which are enclosed within
begin, at line 10, and end, at line 1$. 0n .erilog, if you have
multiple lines within a bloc=, you need to use begin and end.
2odule ends with DendmoduleD reserved word, in this case at
line 1!.

He((o .or(d /ro,ra" O!t5!t

4ello *orld by /eepa=


7o!nter 2e'i,n B(o)&


7o!nter 2e'i,n ;5e)'

"Ebit synchronous up counter.
active high, synchronous reset.
3ctive high enable.

7o!nter 2e'i,n

1 0011111111111111111111111111111111111111111111111111111
2 00 T%i' i' " 'e)ond +eri(o, 2e'i,n
3 00 2e'i,n Na"e 3 *ir't4)o!nter
4 00 Fi(e Na"e 3 *ir't4)o!nter.v
5 00 F!n)tion 3 T%i' i' a 4 #it !51)o!nter $it%
6 00 ;n)%rono!' a)tive %i,% re'et and
7 00 $it% a)tive %i,% ena#(e 'i,na(
8 0011111111111111111111111111111111111111111111111111111
9 "od!(e first_counter (
10 clock , 00 7(o)& in5!t o* t%e de'i,n
11 reset , 00 a)tive %i,%< 'n)%rono!' Re'et in5!t
12 en!le , 00 A)tive %i,% ena#(e 'i,na( *or )o!nter
13 counter_out 00 4 #it ve)tor o!t5!t o* t%e )o!nter
14 ); 00 End o* 5ort (i't
15 001111111111111=n5!t /ort'11111111111111111111111111111
16 in5!t clock ;
17 in5!t reset ;
18 in5!t en!le ;
19 001111111111111O!t5!t /ort'1111111111111111111111111111
20 o!t5!t "3#0$ counter_out ;
21 001111111111111=n5!t 5ort' 2ata T5e1111111111111111111
22 00 B r!(e a(( t%e in5!t 5ort' '%o!(d #e $ire'
23 $ire clock ;
24 $ire reset ;
25 $ire en!le ;
26 001111111111111O!t5!t /ort' 2ata T5e111111111111111111
27 00 O!t5!t 5ort )an #e a 'tora,e e(e"ent >re,) or a $ire
28 re, "3#0$ counter_out ;
29
30 001111111111117ode ;tart' Here1111111111111111111111111
31 00 ;in)e t%i' )o!nter i' a 5o'itive ed,e tri,,ed one<
32 00 .e tri,,er t%e #e(o$ #(o)& $it% re'5e)t to 5o'itive
33 00 ed,e o* t%e )(o)&.
34 a($a' ? (5o'ed,e clock)
35 #e,in 3 %&'()*+ 00 B(o)& Na"e
36 00 At ever ri'in, ed,e o* )(o)& $e )%e)& i* re'et i' a)tive
37 00 =* a)tive< $e (oad t%e )o!nter o!t5!t $it% 46#::::
38 i* (reset == 1,!1) #e,in
39 counter_out @= 91 4,!0000;
40 end
41 00 =* ena#(e i' a)tive< t%en $e in)re"ent t%e )o!nter
42 e('e i* (en!le == 1,!1) #e,in
43 counter_out @= 91 counter_out A 1;
44 end
45 end 00 End o* B(o)& 7OBNTER
46
47 end"od!(e 00 End o* Mod!(e )o!nter
Gou could download file firstNcounter.v here

7o!nter Te't Ben)%
3ny digital circuit, no matter how comple, needs to be
tested. For the counter logic, we need to provide cloc= and
reset logic. %nce the counter is out of reset, we toggle the
enable input to the counter, and chec= the waveform to see
if the counter is counting correctly. This is done in .erilog.


The counter testbench consists of cloc= generator, reset
control, enable control and monitor@chec=er logic. 6elow is
the simple code of testbench without the monitor@chec=er
logic.

1 Cin)(!de -*ir't4)o!nter.v-
2 "od!(e first_counter_t!();
3 00 2e)(are in5!t' a' re,' and o!t5!t' a' $ire'
4 re, clock, reset, en!le;
5 $ire "3#0$ counter_out;
6
7 00 =nitia(iDe a(( varia#(e'
8 initia( #e,in
9 8di'5(a (-ti"eEt )(& re'et ena#(e )o!nter-);
10 8"onitor (-F,Et F# F# F# F#-,
11 8ti"e, clock, reset, en!le, counter_out);
12 clock = 1; 00 initia( va(!e o* )(o)&
13 reset = 0; 00 initia( va(!e o* re'et
14 en!le = 0; 00 initia( va(!e o* ena#(e
15 95 reset = 1; 00 A''ert t%e re'et
16 91: reset = 0; 00 2e1a''ert t%e re'et
17 91: en!le = 1; 00 A''ert ena#(e
18 91:: en!le = 0; 00 2e1a''ert ena#(e
19 95 8*ini'%; 00 Ter"inate 'i"!(ation
20 end
21
22 00 7(o)& ,enerator
23 a($a' #e,in
24 95 clock = Gclock; 00 To,,(e )(o)& ever 5 ti)&'
25 end
26
27 00 7onne)t 2BT to te't #en)%
28 first_counter '_counter (
29 clock,
30 reset,
31 en!le,
32 counter_out
33 );
34
35 end"od!(e
Gou could download file firstNcounterNtb.v here

time cl= reset enable counter
0 1 0 0
! 0 1 0
10 1 1 0
11 1 1 0 0000
1! 0 0 0 0000
(0 1 0 0 0000
(! 0 0 1 0000
$0 1 0 1 0000
$1 1 0 1 0001
$! 0 0 1 0001
"0 1 0 1 0001
"1 1 0 1 0010
"! 0 0 1 0010
!0 1 0 1 0010
!1 1 0 1 0011
!! 0 0 1 0011
60 1 0 1 0011
61 1 0 1 0100
6! 0 0 1 0100
&0 1 0 1 0100
&1 1 0 1 0101
&! 0 0 1 0101
'0 1 0 1 0101
'1 1 0 1 0110
'! 0 0 1 0110
90 1 0 1 0110
91 1 0 1 0111
9! 0 0 1 0111
100 1 0 1 0111
101 1 0 1 1000
10! 0 0 1 1000
110 1 0 1 1000
111 1 0 1 1001
11! 0 0 1 1001
1(0 1 0 1 1001
1(1 1 0 1 1010
1(! 0 0 0 1010

7o!nter .ave*or"

Mod!(e'

2odules are the
building bloc=s of
.erilog designs
Gou create the design
hierarchy by
instantiating modules
in other modules.
/ort'

<orts allow
communication
between a module and
its environment.
3ll but the topElevel
modules in a hierarchy
have ports.
<orts can be
associated by order or
by name.

Gou declare ports to be input,
output or inout. The port
declaration synta is :
input RrangeNval:rangeNvarS
listNofNidentifiersM
output RrangeNval:rangeNvarS
listNofNidentifiersM
inout RrangeNval:rangeNvarS
listNofNidentifiersM