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1
Day In the Life of an
Ethernet Over SONET/SDH Packet
SPI-4.2
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Framer
SPI-4.2
SPI-4.2
FIFO Processor SDH
GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
Inter VCAT Mapper
Packet
Gap
Ethernet Frames Extracted From
Preamble
the Line Interface
SFD
8B/10B Decoding For SerDes Interfaces
Inter Packet Gap, Preamble and Start of
Ethernet Ethernet
Packet Packet
Frame Delimiter are Stripped
At Completion of Packet
Ethernet Ethernet
FCS FCS Reception, Error Conditions are
Inter Checked and Statistics Updated
Packet
Gap Packet Length Check
FCS Check
Incoming Ethernet Extracted Ethernet
Packet Stream Packet Packet and Byte Counters Updated
Copyright©2004 Vitesse Semiconductor Corporation 3
Ingress FIFO Buffers Packet
Tx Tx
Ingress Tx Tx VC
Payload SONET/
Buffer Mapper
SPI-4.2
SPI-4.2
FIFO Processor SDH
GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper
SPI-4.2
SPI-4.2
FIFO Processor SDH
GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper
SPI-4.2
SPI-4.2
FIFO Processor SDH
GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper
Ctrl Word
Begin
Previous
Ethernet
Packet
Packet
Ctrl Word Packet Bursts Reassembled into Packets
Another Ethernet in the Tx Buffer
Channel’s Packet
Ethernet
Data
Ctrl Word Ethernet
Remainder FCS
Of Ethernet
Packet
With FCS
Ctrl Word
SPI-4.2
SPI-4.2
FIFO Processor SDH
GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper
PLI 2 Bytes
cHEC
Generic Framing Procedure (GFP) is One of Two
2 Bytes
Type Ethernet Encapsulation Choices
2 Bytes
tHEC 2 Bytes PDU Length Indicator (PLI) Along with the Core
Extension
Header 2 Bytes Header Error Check (cHEC) form the Core Header
eHEC 2 Bytes PLI is the number of Bytes in the Entire Encapsulated Packet
Excluding the Core Header Itself
Ethernet Ethernet
Type Field describes encapsulated packet
Packet Packet Control or Data Packet
FCS Present Indicator
Extension Header Indicator
Ethernet Ethernet
FCS FCS Extension Header is Optionally Inserted
GFP FCS 4 Bytes
GFP FCS
Incoming Resulting GFP Optionally Inserted CRC
Ethernet Encapsulated
Packet Packet
Copyright©2004 Vitesse Semiconductor Corporation 7
Packet Encapsulation –
Link Access Procedure - SDH (LAPS)
Tx Tx
Ingress Tx Tx VC
Payload SONET/
Buffer Mapper
SPI-4.2
SPI-4.2
FIFO Processor SDH
GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper
SPI-4.2
SPI-4.2
FIFO Processor SDH
GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper
SPI-4.2
SPI-4.2
FIFO Processor SDH
GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper
SPI-4.2
SPI-4.2
FIFO Processor SDH
GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper
H4 STS-1 #32
Path Overhead Processing
H4 H4 Virtual Concatenation Byte and Payload
Extraction
SPI-4.2
SPI-4.2
FIFO Processor SDH
GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper
SPI-4.2
SPI-4.2
FIFO Processor SDH
GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper
PLI 2 Bytes
cHEC 2 Bytes
Generic Framing Procedure (GFP) is One of Two
Type 2 Bytes Ethernet Encapsulation Choices
tHEC 2 Bytes
Extension Core Header is Processed to Delineate Frames
Header 2 Bytes
eHEC 2 Bytes Type and Extension Headers are Optionally
Checked and Stripped
Ethernet Ethernet
Packet Packet GFP FCS is Optionally Checked and Stripped
Ethernet Ethernet
FCS FCS
GFP FCS 4 Bytes
Incoming GFP Resulting
Encapsulated Ethernet
Packet Packet
Copyright©2004 Vitesse Semiconductor Corporation 13
Packet Extraction –
Link Access Procedure - SDH (LAPS)
Tx Tx
Ingress Tx Tx VC
Payload SONET/
Buffer Mapper
SPI-4.2
SPI-4.2
FIFO Processor SDH
GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper
Flag
Link Access Procedure –SDH (LAPS) is
1 Byte
Address 1 Byte
One of Two Ethernet Encapsulation
Control 1 Byte Choices
SAPI 2 Bytes
Flag Character is Used to Delineate
Ethernet Ethernet
Frames
Packet Packet
All Fields are Optionally Checked and
Ethernet Ethernet
Stripped
FCS FCS
LAPS
FCS 4 Bytes
SPI-4.2
SPI-4.2
FIFO Processor SDH
GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper
Previous
Packet
Extracted Ethernet Packets Placed in the
Rx FIFO for that Group
Ethernet Ethernet
Packet Packet
Ethernet Ethernet
FCS FCS
SPI-4.2
SPI-4.2
FIFO Processor SDH
GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper
SPI-4.2
SPI-4.2
FIFO Processor SDH
GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper
Ctrl Word
Begin
Previous
Ethernet
Packet
Packet
Ctrl Word Packet Bursts Reassembled into Packets
Another Ethernet in the Egress FIFO
Channel’s Packet
Ethernet
Data
Ctrl Word Ethernet
Remainder FCS
Of Ethernet
Packet
With FCS
Ctrl Word
SPI-4.2
SPI-4.2
FIFO Processor SDH
GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper
Inter
Ethernet Frame Pulled from the Egress
Packet FIFO
Gap