NMOS and PMOS Characteristics

Step 1:
Connect the NMOS and PMOS. Simulate the Ids Vgs characteristics curve.

These are the SPICE codes for both NMOS
and PMOS connections. As it is observed,
NMOS and PMOS has length of 18u and
3.68u, respectively. Both has the same
width of 0.58u.

For MOSFETS, before the chip is being
named, m must be put before hand. For
in this activity, chips are named mjelord.

For SPICE syntax:
mjelord vd vg gnd gnd nch l=18u
w=0.58u, declares mjelord.
Vd vd gnd 1.8, assigns a voltage source,
Vd=1.8V, on the drain of mjelord.
.lib <filepath>filename entryname,
library call; filepath, path to a file;
filename, name of a file to include in the
data file; entryname, entry name for the
section of the library file to include.
TT, NMOS typical, PMOS typical; the
speed of the transistor.
.dc vd 0 1.8 0.01, performs DC analysis
of vd from 0V to 1.8V, sampling every
0.01V.
.probe i1(mjelord), drawn Ids of
mjelord for plotting.
.op, calculates the small signal model
parameters of a MOS for a given
operation point; it will list the following
information: id, vgs, vds, beta, gm and
vth.

The graph shows that an NMOS has Vgs that must be greater that Vth so that the Id can
flow (the flat line shows that the Vgs did not exceed the Vth). It has a threshold voltage of
approximately 431mV as it appears in the .lis file of the simulation. The threshold voltage is
reached where drain current elevates. For Vgs, between 0V and 0.7V, Ids is nearly zero indicating
that equivalent resistance between the drain and source terminals is extremely high. Once Vgs
reaches 0.7V, the current increases rapidly with Vgs indicating that the equivalent resistance at
the drain decreases with increasing gate-source voltage. As it operates, Ids Vgs curve rises
quadratically, it occurs in the saturation region. Typically, Vds is fixed when Ids is plotted as
function of Vgs.



This is the .lis file of the NMOS through
the simulation. As procured, the
component is in saturation with Id which
is equal to 6.6uA.
|Vtn|
Vout=1.20
V

The graph shows that a PMOS has Vgs that must be less that Vth so that the Id can flow
(the flat line shows that the Vgs did not exceed the Vth). It has a threshold voltage of
approximately -381mV as it appears in the .lis file of the simulation. The PMOS transistor
input characteristic is analogous to the NMOS transistor except Ids and Vgs polarities are
reversed. Vds is negative and approximately -0.1V. Additionally, the gate is at a voltage lower
than the source terminal voltage to attract holes to the channel surface.



This is the .lis file of the PMOS through
the simulation. As obtained, the
component is in saturation with Id which
is approximately equal to -6.6uA.

|Vtp|
Vout=1.20
V
Step 2:
Disconnect the gate and the drain of the MOS. Then, assign the different values of Vgs to
its gate terminal. Simulate the Ids Vgs characteristic curve.

These are the SPICE codes for both NMOS
and PMOS connections. As it is observed,
NMOS and PMOS has length of 10.29u and
1.86u, respectively. Both has the same
width of 0.58u.

For MOSFETS, before the chip is being
named, m must be put before hand. For in
this activity, chips are named mjelord.

For SPICE syntax:
mjelord vd vg gnd gnd nch l=10.29u
w=0.58u, declares mjelord.
Vd vd gnd 1.8, assigns a voltage source,
Vd=1.8V, on the drain of mjelord.
Vg Vg gnd 1.4, assign a voltage source,
Vg=1.4, on the gate of mjelord.
.lib <filepath>filename entryname,
library call; filepath, path to a file; filename,
name of a file to include in the data file;
entryname, entry name for the section of
the library file to include.
.option post probe, graph nodal voltages,
elements currents, circuit response,
algebraic expressions from the transient
analysis, DC sweeps and AC analysis; it
enables only selective probing done in
.probe statements.
TT, NMOS typical, PMOS typical; the
speed of the transistor.
.alter, is used to re-run the simulation
with a modified netlist; here, Vgs is altered
with chosen values.







The graph above displays the NMOS transistor output characteristic plot Ids Vds with
several values of Vgs. The linear region, saturation region and the break-down are also
distinguished when the device is on. In the linear region (when Vgs < Vds + Vtn), as the drain
current increases, Vds increases. Somehow, the MOSFET acts sort of like a resistor. In the
saturation region (When Vgs > Vds + Vtn), the Ids lines are flat because the current does not
increase as any more Vds increases. To obtain the saturation, is to supply enough voltage until
eventually the rise in the current will make no difference to the current. Break-down means the
input voltage level is higher than the highest allowable power supply level. When the transistor
is off (Vgs < Vtn), Ids is zero for any Vds value.



This is the .lis file of the NMOS
transistor through the simulation. As a
result, the component is in saturation
with Id that is approximately equal to
6.6uA.




Vgs=1.4V
Vout=1.20
V
Vgs=1.2V
Vout=1.20
V
Vgs=0.8V
Vout=1.20
V
Break Down
Vout=1.20V
Vgs=0V
Vout=1.20
V
Saturation Region
Vout=1.20V
Linear Region
Vout=1.20V

The graph above shows the PMOS transistor output characteristic plot Ids Vds with
several values of Vgs. The linear region, saturation region and the break-down are also
distinguished when the device is on. The drain current in saturation is virtually independent of
Vds and the transistor acs as current source. This is because there is no carrier inversion at the
drain region of the channel. Carriers are pulled into the high electric field of the
drain/substance pn junction and ejected out of the drain terminal. A near constant current is
driven from transistor no matter the drain-to-source voltage. The PMOS transistor Ids versus Vds
curves has similar shape to that in NMOS, but the voltage and current polarities are negative to
account for hole inversion and drain current that enters the transistor.



This is the .lis file of the PMOS transistor
through the simulation. As procured, the
component is in saturation with Id that is
equal to -6.6uA.

Break Down
Vout=1.20V
Saturation Region
Vout=1.20V
Linear Region
Vout=1.20V
Vgs=-1.4V
Vout=1.20
V
Vgs=-0.8V
Vout=1.20
V
Vgs=-0.8V
Vout=1.20
V
Vgs=0V
Vout=1.20
V
Step 3:
Follow Step 2, change the channel length. Simulate the Ids-Vgs characteristic curve.

These are the SPICE codes for both NMOS
and PMOS connections. As it is observed,
NMOS and PMOS has length of 10.29u and
1.86u, respectively. Both has the same
width of 0.58u.

For MOSFETS, before the chip is being
named, m must be put before hand. For in
this activity, chips are named mjelord.

For SPICE syntax:
mjelord vd vg gnd gnd nch l=10.29u
w=0.58u, declares mjelord.
Vd vd gnd 1.8, assigns a voltage source,
Vd=1.8V, on the drain of mjelord.
Vg Vg gnd 1.4, assign a voltage source,
Vg=1.4, on the gate of mjelord.
.lib <filepath>filename entryname,
library call; filepath, path to a file; filename,
name of a file to include in the data file;
entryname, entry name for the section of
the library file to include.
TT, NMOS typical, PMOS typical; the
speed of the transistor.
.option post probe, graph nodal voltages,
elements currents, circuit response,
algebraic expressions from the transient
analysis, DC sweeps and AC analysis; it
enables only selective probing done in
.probe statements.
.dc vd 0 5 0.01, performs DC analysis of
vd from 0V to 5V, sampling every 0.01V.
.probe i1(mjelord), drawn Ids of mjelord
for plotting.
.alter, is used to re-run the simulation
with a modified netlist; here, Vgs is altered
with chosen values.



The graph above shows the NMOS transistor output characteristic plot Ids Vgs. The
channel is set to width=0.58u, Vgs=1.4, and change in the channel length. As observed, the
channel length modulation affects the current of the NMOS in the saturation region while its
channel length is changed. The amount of the increment can be reduced by increasing the
channel length. It means that, if MOSFET will be used as a constant source, a larger channel
length can produce a current which is more constant and less sensitive to process variations.



This is the .lis file of the NMOS transistor
through the simulation. As acquired, the
component is in saturation with Id that is
equal to 6.6uA.

L=7
L=9
L=4
L=10.29

The graph above displays the PMOS transistor output characteristic plot Ids Vgs. The
channel is set to width=0.58u, Vgs=-1.4, and change in the channel length. As perceived, the
channel length modulation affects the current of the NMOS in the saturation region while its
channel length is changed. Channel length modulation (or CLM), is one of the several short-
channel effects in MOSFET scaling. It is a shortening of the length of the inverted channel region
with increase in drain bias for large drain biases. The result of CLM is an increase in current with
drain bias and a reduction output resistance. The effect is pronounced the shorter the source-
to-drain separation, the deeper the drain junction, and the thicker the oxide insulator.



This is the .lis file of the PMOS transistor
through the simulation. As obtained, the
component is in saturation with Id that is
approximately equal to -6.6uA.

L=7
L=4
L=9
L=1.79
Step 4:
Set |Vgs| to a value smaller than |Vt| to operate the MOS in subthreshold region.
Simulate the Ids-Vgs characteristic curve.

These are the SPICE codes for both NMOS
and PMOS connections. As it is observed,
NMOS and PMOS has length of 10.29u and
1.86u, respectively. Both has the same
width of 0.58u.

For MOSFETS, before the chip is being
named, m must be put before hand. For
in this activity, chips are named mjelord.

For SPICE syntax:
.lib <filepath>filename entryname,
library call; filepath, path to a file;
filename, name of a file to include in the
data file; entryname, entry name for the
section of the library file to include.
TT, NMOS typical, PMOS typical; the
speed of the transistor.
.option post probe, graph nodal voltages,
elements currents, circuit response,
algebraic expressions from the transient
analysis, DC sweeps and AC analysis; it
enables only selective probing done in
.probe statements.
.dc vd 0 5 0.01, performs DC analysis of
vd from 0V to 5V, sampling every 0.01V.
.probe i1(mjelord), drawn Ids of
mjelord for plotting.
.alter, is used to re-run the simulation
with a modified netlist; here, Vgs is altered
with chosen values.





The graph illustrates the IdsVgs characteristic curves of an NMOS transistor. In the
gradual channel approximation modeling of MOSFET terminal characteristics, as it stated
earlier, that the drain current is identically zero when the gate voltage is less than the threshold
voltage. The population of mobile electrons under the gate provides a mechanism for charge
flow between the drain and source even |Vgs| < |Vt|, and thus there is in fact a small, non-zero
drain current through a MOSFET biased below threshold. This is significant because on an
integrated chip with millions of transistors which are supposed to be off and therefore not
dissipating any power, a little current flowing through each transistor can easily add up to be a
significant power drain, and be a source of heating. Furthermore, MOSFET is operated in
subthreshold region.



This is the .lis file of the NMOS transistor
through the simulation. As a result, the
component is cut-off with Id which is
approximately equal to 1.56nA.



Vgs=0.6V
Vgs=0.5V
Vgs=1.8V
Vds=1.8V
Vds=1.3V
Vds=0.8V

The graph illustrates the IdsVgs characteristic curves of an NMOS transistor. It is not
totally correct that when Vgs value of a MOSFET is smaller than Vt, it will turn off and Ids will be
equal to zero, as stated earlier. In fact, when Vgs is slightly smaller than Vt, there is still a small
current flowing from the drain to source, thus the MOSFET is operated in the subthreshold
region. One thing that all of these circuits have in common is that they operate in the
subthreshold region of the MOSFET. That is, they use the MOSFETs characteristics with the
gate biased below the transistor's threshold voltage. This is rare for MOSFET circuits, in which
the fact that they have a sharp transition from cutoff to conducting is the most useful of the
transistor's properties. However, subthreshold operation also has its benefits. In this region, the
currents through the transistor are extremely low, orders of magnitude lower than in normal
operation. Subthreshold circuits consume extremely small amounts of power, which is
important when you are trying to cram many thousands of these circuits onto a single
integrated circuit.



This is the .lis file of the PMOS transistor
through the simulation. As procured, the
component is cut-off with Id which is
approximately equal to -1.14nA.
Vds=1.8V Vds=1.3V
Vds=0.8V
QUESTIONS:

1. If we increase W/L of the device in Step 1, what changes will occur to the curve?

Increasing the W/L of the NMOS and PMOS will result to an increase in the curves slope
with respect to the y-axis. This is due to a decrease in threshold voltage. There is a need to
reduce the threshold voltage in order to maintain performance. When it is being reduced, the
transistor cannot be switched from complete turn-off to complete turn-on with the limited
swing available.

2. When the dimensions Wn/Ln equal Wp/Lp, does |Idsp|/Idsn equal p/n?

Solution:

(Wn/Ln = Wp/Lp)

using,

ID =
1
2
(Vgs Vtn)
2
when = cox

.
IN =
1
2
n (Vgs Vtn)
2
=
p
n

IN
IP =
1
2
p (Vgs Vtn)
2
=
p
n

IN

equating the 2 equations,

=
p
n


3. What relationship between the channel length and the slope of Ids Vds Characteristic
Curve of NMOS and PMOS?

The current increased as the L is decreased (p =p cox

, ID =

(Vgs Vtn)
2
).

4. When the MOSFET operates in sub-threshold region, what is the relationship between
Vgs and the slope of the Ids Vgs Characteristic Curve? What device, either PMOS or NMOS, has
the larger slope? Why?

The sub-threshold region is determined by the voltage in the gate-source voltage and
thus proportional to the current (though minimal), and since NMOS has a larger current than
PMOS, that is why the NMOS has a larger slope in the Ids-Vgs curve.